reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

Declarations

   54 class MachineInstr;

   24 class MachineInstr;

   43 class MachineInstr;

   22 class MachineInstr;

   27 class MachineInstr;

   34 class MachineInstr;

   47 class MachineInstr;

   43 class MachineInstr;

   28 class MachineInstr;

   21 class MachineInstr;

   20 class MachineInstr;

   20 class MachineInstr;

   45 class MachineInstr;

   35 class MachineInstr;

   37 class MachineInstr;

   31 class MachineInstr;

   29 class MachineInstr;

   26 class MachineInstr;

   32 class MachineInstr;

   48 class MachineInstr;

   41 class MachineInstr;

   38 class MachineInstr;

   26 class MachineInstr;

   31 class MachineInstr;

   24 class MachineInstr;

   20 class MachineInstr;

  108 class MachineInstr;

   62 class MachineInstr;

   22 class MachineInstr;

   73 class MachineInstr;

   32 class MachineInstr;

   35 class MachineInstr;

   29 class MachineInstr;

   41   class MachineInstr;

   19 class MachineInstr;

   32 class MachineInstr;

   32   class MachineInstr;

   30 class MachineInstr;

   82 class MachineInstr;

   39 class MachineInstr;

   27 class MachineInstr;

   36 class MachineInstr;

   31 class MachineInstr;

   21 class MachineInstr;

   24 class MachineInstr;

   28 class MachineInstr;

   47 class MachineInstr;

   19 class MachineInstr;

   22 class MachineInstr;

   28 class MachineInstr;

   26 class MachineInstr;

   37 class MachineInstr;

   25 class MachineInstr;

   23 class MachineInstr;

   35 class MachineInstr;

   20 class MachineInstr;

   34 class MachineInstr;

   23 class MachineInstr;

   45 class MachineInstr;

   17 class MachineInstr;

   20 class MachineInstr;

   24 class MachineInstr;

   22 class MachineInstr;

   24 class MachineInstr;

   26 class MachineInstr;

   34 class MachineInstr;

   36 class MachineInstr;

   23 class MachineInstr;

   23 class MachineInstr;

  252 class MachineInstr;

   20 class MachineInstr;

   20   class MachineInstr;

   34 class MachineInstr;

   49 class MachineInstr;

   35 class MachineInstr;

   19 class MachineInstr;

   23 class MachineInstr;

   26   class MachineInstr;

   29 class MachineInstr;

   27   class MachineInstr;

   21 class MachineInstr;

   19 class MachineInstr;

   22 class MachineInstr;

   26 class MachineInstr;

   18   class MachineInstr;

References

   27     MachineInstr &MI,
   98     MachineInstr &MI,

   25   bool testMIPredicate_MI(unsigned PredicateID, const MachineInstr &MI) const override;
  883 bool AArch64InstructionSelector::testMIPredicate_MI(unsigned PredicateID, const MachineInstr & MI) const {
 1019 bool AArch64InstructionSelector::selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const {

17985 static bool isExynosArithFast(const MachineInstr &MI);
17986 static bool isExynosCheapAsMove(const MachineInstr &MI);
17987 static bool isExynosLogicExFast(const MachineInstr &MI);
17988 static bool isExynosLogicFast(const MachineInstr &MI);
17989 static bool isExynosResetFast(const MachineInstr &MI);
17990 static bool isExynosScaledAddr(const MachineInstr &MI);
17991 static bool isCopyIdiom(const MachineInstr &MI);
17992 static bool isZeroFPIdiom(const MachineInstr &MI);
17993 static bool isZeroIdiom(const MachineInstr &MI);
17994 static bool hasExtendedReg(const MachineInstr &MI);
17995 static bool hasShiftedReg(const MachineInstr &MI);
17996 static bool isScaledAddr(const MachineInstr &MI);
18003 bool AArch64InstrInfo::isExynosArithFast(const MachineInstr &MI) {
18064 bool AArch64InstrInfo::isExynosCheapAsMove(const MachineInstr &MI) {
18090 bool AArch64InstrInfo::isExynosLogicExFast(const MachineInstr &MI) {
18147 bool AArch64InstrInfo::isExynosLogicFast(const MachineInstr &MI) {
18198 bool AArch64InstrInfo::isExynosResetFast(const MachineInstr &MI) {
18224 bool AArch64InstrInfo::isExynosScaledAddr(const MachineInstr &MI) {
18280 bool AArch64InstrInfo::isCopyIdiom(const MachineInstr &MI) {
18311 bool AArch64InstrInfo::isZeroFPIdiom(const MachineInstr &MI) {
18331 bool AArch64InstrInfo::isZeroIdiom(const MachineInstr &MI) {
18348 bool AArch64InstrInfo::hasExtendedReg(const MachineInstr &MI) {
18368 bool AArch64InstrInfo::hasShiftedReg(const MachineInstr &MI) {
18400 bool AArch64InstrInfo::isScaledAddr(const MachineInstr &MI) {

   11                             const MachineInstr *MI) {

17972   unsigned resolveSchedClass(unsigned SchedClass,  const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const override;
17998 ::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {

   25   bool testMIPredicate_MI(unsigned PredicateID, const MachineInstr &MI) const override;
  376 bool AMDGPUInstructionSelector::testMIPredicate_MI(unsigned PredicateID, const MachineInstr & MI) const {
  438 bool AMDGPUInstructionSelector::selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const {

   11                             const MachineInstr *MI) {

  786   unsigned resolveSchedClass(unsigned SchedClass,  const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const override;
  812 ::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {

  310   unsigned resolveSchedClass(unsigned SchedClass,  const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const override;
  339 ::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {

  136   unsigned resolveSchedClass(unsigned SchedClass,  const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const override;
  162 ::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {

   25   bool testMIPredicate_MI(unsigned PredicateID, const MachineInstr &MI) const override;
  745 bool ARMInstructionSelector::testMIPredicate_MI(unsigned PredicateID, const MachineInstr & MI) const {
  807 bool ARMInstructionSelector::selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const {

   11                             const MachineInstr *MI) {

19572   unsigned resolveSchedClass(unsigned SchedClass,  const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const override;
19601 ::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {

  537   unsigned resolveSchedClass(unsigned SchedClass,  const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const override;
  563 ::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {

  159   unsigned resolveSchedClass(unsigned SchedClass,  const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const override;
  185 ::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {

 4683   unsigned resolveSchedClass(unsigned SchedClass,  const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const override;
 4713 ::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {

  217   unsigned resolveSchedClass(unsigned SchedClass,  const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const override;
  246 ::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {

  160   unsigned resolveSchedClass(unsigned SchedClass,  const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const override;
  186 ::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {

   25   bool testMIPredicate_MI(unsigned PredicateID, const MachineInstr &MI) const override;
  610 bool MipsInstructionSelector::testMIPredicate_MI(unsigned PredicateID, const MachineInstr & MI) const {
  632 bool MipsInstructionSelector::selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const {

   11                             const MachineInstr *MI) {

 3863   unsigned resolveSchedClass(unsigned SchedClass,  const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const override;
 3889 ::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {

  235   unsigned resolveSchedClass(unsigned SchedClass,  const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const override;
  261 ::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {

 8212   unsigned resolveSchedClass(unsigned SchedClass,  const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const override;
 8241 ::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {

   25   bool testMIPredicate_MI(unsigned PredicateID, const MachineInstr &MI) const override;
  256 bool RISCVInstructionSelector::testMIPredicate_MI(unsigned PredicateID, const MachineInstr & MI) const {
  278 bool RISCVInstructionSelector::selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const {

   11                             const MachineInstr *MI) {

  273   unsigned resolveSchedClass(unsigned SchedClass,  const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const override;
  300 ::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {

  529   unsigned resolveSchedClass(unsigned SchedClass,  const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const override;
  558 ::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {

 5174   unsigned resolveSchedClass(unsigned SchedClass,  const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const override;
 5200 ::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {

  178   unsigned resolveSchedClass(unsigned SchedClass,  const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const override;
  204 ::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {

   25   bool testMIPredicate_MI(unsigned PredicateID, const MachineInstr &MI) const override;
  749 bool X86InstructionSelector::testMIPredicate_MI(unsigned PredicateID, const MachineInstr & MI) const {
  771 bool X86InstructionSelector::selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const {

49336 static bool isThreeOperandsLEA(const MachineInstr &MI);
49343 bool X86InstrInfo::isThreeOperandsLEA(const MachineInstr &MI) {

21497   unsigned resolveSchedClass(unsigned SchedClass,  const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const override;
21500   bool isZeroIdiom(const MachineInstr *MI, APInt &Mask) const override;
21501   bool isDependencyBreaking(const MachineInstr *MI, APInt &Mask) const override;
21502   bool isOptimizableRegisterMove(const MachineInstr *MI) const override;
21526 ::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {
22917 bool X86GenSubtargetInfo::isZeroIdiom(const MachineInstr *MI, APInt &Mask) const {
23005 bool X86GenSubtargetInfo::isDependencyBreaking(const MachineInstr *MI, APInt &Mask) const {
23050 bool X86GenSubtargetInfo::isOptimizableRegisterMove(const MachineInstr *MI) const {

  137   unsigned resolveSchedClass(unsigned SchedClass,  const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const override;
  163 ::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {

  108         const ArrayRef<U *> &A,
  110            std::is_convertible<U *const *, T const *>::value>::type * = nullptr)
  118       const SmallVectorTemplateCommon<U *, DummyT> &Vec,
  120           std::is_convertible<U *const *, T const *>::value>::type * = nullptr)
  127     ArrayRef(const std::vector<U *, A> &Vec,
  129                  std::is_convertible<U *const *, T const *>::value>::type* = 0)

   39   static inline T* getEmptyKey() {
   41     Val <<= PointerLikeTypeTraits<T*>::NumLowBitsAvailable;
   45   static inline T* getTombstoneKey() {
   47     Val <<= PointerLikeTypeTraits<T*>::NumLowBitsAvailable;
   51   static unsigned getHashValue(const T *PtrVal) {
   56   static bool isEqual(const T *LHS, const T *RHS) { return LHS == RHS; }
   56   static bool isEqual(const T *LHS, const T *RHS) { return LHS == RHS; }

  249 class SmallSet<PointeeType*, N> : public SmallPtrSet<PointeeType*, N> {};

   96 template <class T> T &make();
  106   static Yes &test(U *I, decltype(I->getNext(&make<NodeT>())) * = 0);
  136   static Yes &test(U *I, decltype(I->createNode(make<NodeT>())) * = 0);
  144   static const bool value = HasGetNext<TraitsT, NodeT>::value ||
  146                             HasCreateNode<TraitsT, NodeT>::value;
  389     : public iplist_impl<simple_ilist<T, Options...>, ilist_traits<T>> {

  150           typename ilist_detail::compute_node_options<T, Options...>::type> {
  256 class ilist_node_with_parent : public ilist_node<NodeTy, Options...> {
  274   NodeTy *getPrevNode() {
  283   const NodeTy *getPrevNode() const {
  288   NodeTy *getNextNode() {
  297   const NodeTy *getNextNode() const {

  108   typedef T value_type;
  109   typedef T *pointer;
  110   typedef T &reference;
  111   typedef const T *const_pointer;
  112   typedef const T &const_reference;
  122   typedef node_options<T, extract_sentinel_tracking<Options...>::value,

   38   iterator_range(Container &&c)

   79     : ilist_detail::compute_node_options<T, Options...>::type::list_base_type,
   81           typename ilist_detail::compute_node_options<T, Options...>::type> {
   85       typename ilist_detail::compute_node_options<T, Options...>::type;

  131   template <class InstT> bool contains(const InstT *Inst) const {

  278   void recordSled(MCSymbol *Sled, const MachineInstr &MI, SledKind Kind,
  317   void emitCFIInstruction(const MachineInstr &MI);
  319   void emitFrameAlloc(const MachineInstr &MI);
  413   virtual void EmitInstruction(const MachineInstr *) {
  442   virtual void emitImplicitDef(const MachineInstr *MI) const;
  604   virtual void PrintSpecial(const MachineInstr *MI, raw_ostream &OS,
  614   virtual bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
  621   virtual bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo,
  653   mutable const MachineInstr *LastMI = nullptr;
  669   void EmitInlineAsm(const MachineInstr *MI) const;

   66   virtual void beginInstruction(const MachineInstr *MI) = 0;

  118   bool canReserveResources(MachineInstr &MI);
  122   void reserveResources(MachineInstr &MI);
  152   std::vector<MachineInstr*> CurrentPacketMIs;
  156   std::map<MachineInstr*, SUnit*> MIToSUnit;
  191   virtual bool ignorePseudoInstruction(const MachineInstr &I,
  198   virtual bool isSoloInstruction(const MachineInstr &MI) { return true; }
  206   virtual bool shouldAddToPacket(const MachineInstr &MI) { return true; }
  221   bool alias(const MachineInstr &MI1, const MachineInstr &MI2,
  221   bool alias(const MachineInstr &MI1, const MachineInstr &MI2,

   57     Entry(const MachineInstr *Instr, EntryKind Kind)
   60     const MachineInstr *getInstr() const { return Instr.getPointer(); }
   71     PointerIntPair<const MachineInstr *, 1, EntryKind> Instr;
   82   bool startDbgValue(InlinedEntity Var, const MachineInstr &MI,
   84   EntryIndex startClobber(InlinedEntity Var, const MachineInstr &MI);
  107   using InstrMap = MapVector<InlinedEntity, const MachineInstr *>;
  113   void  addInstr(InlinedEntity Label, const MachineInstr &MI);

   48   extractFromMachineInstruction(const MachineInstr &Instruction);
   76   const MachineInstr *CurMI = nullptr;
   90   DenseMap<const MachineInstr *, MCSymbol *> LabelsBeforeInsn;
   93   DenseMap<const MachineInstr *, MCSymbol *> LabelsAfterInsn;
  100   void requestLabelBeforeInsn(const MachineInstr *MI) {
  105   void requestLabelAfterInsn(const MachineInstr *MI) {
  115   void beginInstruction(const MachineInstr *MI) override;
  122   MCSymbol *getLabelBeforeInsn(const MachineInstr *MI);
  125   MCSymbol *getLabelAfterInsn(const MachineInstr *MI);
  129   const MCExpr *getFunctionLocalOffsetAfterInsn(const MachineInstr *MI);

   67   SmallVector<MachineInstr *, 8> Instrs;
  196   bool visitInstr(MachineInstr *);
  200   void processDefs(MachineInstr *, bool Kill);
  203   void visitSoftInstr(MachineInstr *, unsigned mask);
  207   void visitHardInstr(MachineInstr *, unsigned domain);

   90     MachineInstr *Call = nullptr;
  221   MachineInstr *LastLocalValue;
  226   MachineInstr *EmitStartPt;
  237   MachineInstr *getLastLocalValue() { return LastLocalValue; }
  241   void setLastLocalValue(MachineInstr *I) {
  304   virtual bool tryToFoldLoadIntoMI(MachineInstr * /*MI*/, unsigned /*OpNo*/,
  568   void removeDeadLocalValueCode(MachineInstr *SavedLastLocalValue);
  571     DenseMap<MachineInstr *, unsigned> Orders;
  572     MachineInstr *FirstTerminator = nullptr;
  581   void sinkLocalValueMaterialization(MachineInstr &LocalMI, unsigned DefReg,

  135   SmallVector<MachineInstr*, 8> ArgDbgValues;
  178   std::vector<std::pair<MachineInstr*, unsigned> > PHINodesToUpdate;

   33   const MachineInstr *MI;
   34   explicit UniqueMachineInstr(const MachineInstr *MI) : MI(MI) {}
   84   DenseMap<const MachineInstr *, UniqueMachineInstr *> InstrMapping;
  102   UniqueMachineInstr *getUniqueInstrForMI(const MachineInstr *MI);
  108   MachineInstr *getMachineInstrIfExists(FoldingSetNodeID &ID,
  114   void insertInstr(MachineInstr *MI, void *InsertPos = nullptr);
  128   void recordNewInstruction(MachineInstr *MI);
  131   void handleRecordedInst(MachineInstr *MI);
  140   void handleRemoveInst(MachineInstr *MI);
  157   void erasingInstr(MachineInstr &MI) override;
  158   void createdInstr(MachineInstr &MI) override;
  159   void changingInstr(MachineInstr &MI) override;
  160   void changedInstr(MachineInstr &MI) override;
  193   const GISelInstProfileBuilder &addNodeID(const MachineInstr *MI) const;

   36   MachineInstr *MI;
   62   bool tryCombineCopy(MachineInstr &MI);
   63   bool matchCombineCopy(MachineInstr &MI);
   64   void applyCombineCopy(MachineInstr &MI);
   68   bool isPredecessor(MachineInstr &DefMI, MachineInstr &UseMI);
   68   bool isPredecessor(MachineInstr &DefMI, MachineInstr &UseMI);
   76   bool dominates(MachineInstr &DefMI, MachineInstr &UseMI);
   76   bool dominates(MachineInstr &DefMI, MachineInstr &UseMI);
   80   bool tryCombineExtendingLoads(MachineInstr &MI);
   81   bool matchCombineExtendingLoads(MachineInstr &MI, PreferredTuple &MatchInfo);
   82   void applyCombineExtendingLoads(MachineInstr &MI, PreferredTuple &MatchInfo);
   86   bool tryCombineIndexedLoadStore(MachineInstr &MI);
   88   bool matchElideBrByInvertingCond(MachineInstr &MI);
   89   void applyElideBrByInvertingCond(MachineInstr &MI);
   90   bool tryElideBrByInvertingCond(MachineInstr &MI);
  100   bool tryCombineConcatVectors(MachineInstr &MI);
  108   bool matchCombineConcatVectors(MachineInstr &MI, bool &IsUndef,
  112   void applyCombineConcatVectors(MachineInstr &MI, bool IsUndef,
  119   bool tryCombineShuffleVector(MachineInstr &MI);
  126   bool matchCombineShuffleVector(MachineInstr &MI,
  129   void applyCombineShuffleVector(MachineInstr &MI,
  162   bool tryCombineMemCpyFamily(MachineInstr &MI, unsigned MaxLen = 0);
  166   bool tryCombine(MachineInstr &MI);
  170   bool optimizeMemcpy(MachineInstr &MI, Register Dst, Register Src,
  173   bool optimizeMemmove(MachineInstr &MI, Register Dst, Register Src,
  176   bool optimizeMemset(MachineInstr &MI, Register Dst, Register Val,
  183   bool findPostIndexCandidate(MachineInstr &MI, Register &Addr, Register &Base,
  190   bool findPreIndexCandidate(MachineInstr &MI, Register &Addr, Register &Base,

   67   virtual bool combine(GISelChangeObserver &Observer, MachineInstr &MI,

   29   SmallPtrSet<MachineInstr *, 4> ChangingAllUsesOfReg;
   35   virtual void erasingInstr(MachineInstr &MI) = 0;
   42   virtual void createdInstr(MachineInstr &MI) = 0;
   45   virtual void changingInstr(MachineInstr &MI) = 0;
   48   virtual void changedInstr(MachineInstr &MI) = 0;
   83   void erasingInstr(MachineInstr &MI) override {
   87   void createdInstr(MachineInstr &MI) override {
   91   void changingInstr(MachineInstr &MI) override {
   95   void changedInstr(MachineInstr &MI) override {
  100   void MF_HandleInsertion(MachineInstr &MI) override { createdInstr(MI); }
  101   void MF_HandleRemoval(MachineInstr &MI) override { erasingInstr(MI); }

   46   KnownBits getKnownBits(MachineInstr &MI);
   72   static MaybeAlign inferPtrAlignment(const MachineInstr &MI);
   75   void erasingInstr(MachineInstr &MI) override{};
   76   void createdInstr(MachineInstr &MI) override{};
   77   void changingInstr(MachineInstr &MI) override{};
   78   void changedInstr(MachineInstr &MI) override{};

   32   SmallVector<MachineInstr *, N> Worklist;
   33   DenseMap<MachineInstr *, unsigned> WorklistMap;
   54   void deferred_insert(MachineInstr *I) {
   78   void insert(MachineInstr *I) {
   85   void remove(const MachineInstr *I) {
  102   MachineInstr *pop_back_val() {
  104     MachineInstr *I;

  162   SmallVector<std::pair<const PHINode *, SmallVector<MachineInstr *, 1>>, 4>

  387   virtual bool select(MachineInstr &I) = 0;
  405   using RecordedMIVector = SmallVector<MachineInstr *, 4>;
  472   virtual bool testMIPredicate_MI(unsigned, const MachineInstr &) const {
  481   bool constrainOperandRegToRegClass(MachineInstr &I, unsigned OpIdx,
  499   bool isObviouslySafeToFold(MachineInstr &MI, MachineInstr &IntoMI) const;
  499   bool isObviouslySafeToFold(MachineInstr &MI, MachineInstr &IntoMI) const;

  109       MachineInstr *NewMI = MRI.getVRegDef(MO.getReg());

   48   bool tryCombineAnyExt(MachineInstr &MI,
   49                         SmallVectorImpl<MachineInstr *> &DeadInsts) {
   67     MachineInstr *ExtMI;
   79     auto *SrcMI = MRI.getVRegDef(SrcReg);
   93   bool tryCombineZExt(MachineInstr &MI,
   94                       SmallVectorImpl<MachineInstr *> &DeadInsts) {
  120     auto *SrcMI = MRI.getVRegDef(SrcReg);
  134   bool tryCombineSExt(MachineInstr &MI,
  135                       SmallVectorImpl<MachineInstr *> &DeadInsts) {
  160   bool tryCombineTrunc(MachineInstr &MI,
  161                        SmallVectorImpl<MachineInstr *> &DeadInsts) {
  170     auto *SrcMI = MRI.getVRegDef(SrcReg);
  187   bool tryFoldImplicitDef(MachineInstr &MI,
  188                           SmallVectorImpl<MachineInstr *> &DeadInsts) {
  193     if (MachineInstr *DefMI = getOpcodeDef(TargetOpcode::G_IMPLICIT_DEF,
  249   bool tryCombineMerges(MachineInstr &MI,
  250                         SmallVectorImpl<MachineInstr *> &DeadInsts) {
  254     MachineInstr *SrcDef =
  261     MachineInstr *MergeI = SrcDef;
  375   bool tryCombineExtract(MachineInstr &MI,
  376                          SmallVectorImpl<MachineInstr *> &DeadInsts) {
  392     MachineInstr *MergeI = MRI.getVRegDef(Src);
  427   bool tryCombineInstruction(MachineInstr &MI,
  428                              SmallVectorImpl<MachineInstr *> &DeadInsts,
  453       for (auto &Use : MRI.use_instructions(MI.getOperand(0).getReg()))
  462   static unsigned getArtifactSrcReg(const MachineInstr &MI) {
  483   void markInstAndDefDead(MachineInstr &MI, MachineInstr &DefMI,
  483   void markInstAndDefDead(MachineInstr &MI, MachineInstr &DefMI,
  484                           SmallVectorImpl<MachineInstr *> &DeadInsts) {
  496     MachineInstr *PrevMI = &MI;
  500       MachineInstr *TmpDef = MRI.getVRegDef(PrevRegSrc);
  523   void deleteMarkedDeadInsts(SmallVectorImpl<MachineInstr *> &DeadInsts,
  525     for (auto *DeadMI : DeadInsts) {

   62   bool combineExtracts(MachineInstr &MI, MachineRegisterInfo &MRI,

   63   LegalizeResult legalizeInstrStep(MachineInstr &MI);
   66   LegalizeResult libcall(MachineInstr &MI);
   70   LegalizeResult narrowScalar(MachineInstr &MI, unsigned TypeIdx, LLT NarrowTy);
   75   LegalizeResult widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy);
   79   LegalizeResult lower(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
   83   LegalizeResult fewerElementsVector(MachineInstr &MI, unsigned TypeIdx,
   88   LegalizeResult moreElementsVector(MachineInstr &MI, unsigned TypeIdx,
  103   void widenScalarSrc(MachineInstr &MI, LLT WideTy, unsigned OpIdx,
  109   void narrowScalarSrc(MachineInstr &MI, LLT NarrowTy, unsigned OpIdx);
  114   void widenScalarDst(MachineInstr &MI, LLT WideTy, unsigned OpIdx = 0,
  120   void narrowScalarDst(MachineInstr &MI, LLT NarrowTy, unsigned OpIdx,
  125   void moreElementsVectorDst(MachineInstr &MI, LLT MoreTy, unsigned OpIdx);
  130   void moreElementsVectorSrc(MachineInstr &MI, LLT MoreTy, unsigned OpIdx);
  133   widenScalarMergeValues(MachineInstr &MI, unsigned TypeIdx, LLT WideTy);
  135   widenScalarUnmergeValues(MachineInstr &MI, unsigned TypeIdx, LLT WideTy);
  137   widenScalarExtract(MachineInstr &MI, unsigned TypeIdx, LLT WideTy);
  139   widenScalarInsert(MachineInstr &MI, unsigned TypeIdx, LLT WideTy);
  174   LegalizeResult fewerElementsVectorImplicitDef(MachineInstr &MI,
  179   LegalizeResult fewerElementsVectorBasic(MachineInstr &MI, unsigned TypeIdx,
  185   LegalizeResult fewerElementsVectorMultiEltType(MachineInstr &MI,
  188   LegalizeResult fewerElementsVectorCasts(MachineInstr &MI, unsigned TypeIdx,
  192   fewerElementsVectorCmp(MachineInstr &MI, unsigned TypeIdx, LLT NarrowTy);
  195   fewerElementsVectorSelect(MachineInstr &MI, unsigned TypeIdx, LLT NarrowTy);
  197   LegalizeResult fewerElementsVectorPhi(MachineInstr &MI,
  200   LegalizeResult moreElementsVectorPhi(MachineInstr &MI, unsigned TypeIdx,
  203   LegalizeResult fewerElementsVectorUnmergeValues(MachineInstr &MI,
  206   LegalizeResult fewerElementsVectorBuildVector(MachineInstr &MI,
  211   reduceLoadStoreWidth(MachineInstr &MI, unsigned TypeIdx, LLT NarrowTy);
  213   LegalizeResult narrowScalarShiftByConstant(MachineInstr &MI, const APInt &Amt,
  216   LegalizeResult narrowScalarShift(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
  217   LegalizeResult narrowScalarMul(MachineInstr &MI, LLT Ty);
  218   LegalizeResult narrowScalarExtract(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
  219   LegalizeResult narrowScalarInsert(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
  221   LegalizeResult narrowScalarBasic(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
  222   LegalizeResult narrowScalarSelect(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
  224   LegalizeResult lowerBitCount(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
  226   LegalizeResult lowerU64ToF32BitOps(MachineInstr &MI);
  227   LegalizeResult lowerUITOFP(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
  228   LegalizeResult lowerSITOFP(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
  229   LegalizeResult lowerFPTOUI(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
  230   LegalizeResult lowerMinMax(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
  231   LegalizeResult lowerFCopySign(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
  232   LegalizeResult lowerFMinNumMaxNum(MachineInstr &MI);
  233   LegalizeResult lowerFMad(MachineInstr &MI);
  234   LegalizeResult lowerUnmergeValues(MachineInstr &MI);
  235   LegalizeResult lowerShuffleVector(MachineInstr &MI);
  236   LegalizeResult lowerDynStackAlloc(MachineInstr &MI);
  237   LegalizeResult lowerExtract(MachineInstr &MI);
  238   LegalizeResult lowerInsert(MachineInstr &MI);
  239   LegalizeResult lowerSADDO_SSUBO(MachineInstr &MI);
  257                                                  MachineInstr &MI);

 1140   LegalizeActionStep getAction(const MachineInstr &MI,
 1146   bool isLegal(const MachineInstr &MI, const MachineRegisterInfo &MRI) const;
 1147   bool isLegalOrCustom(const MachineInstr &MI,
 1150   virtual bool legalizeCustom(MachineInstr &MI, MachineRegisterInfo &MRI,
 1156   virtual bool legalizeIntrinsic(MachineInstr &MI, MachineRegisterInfo &MRI,
 1350 const MachineInstr *machineFunctionIsIllegal(const MachineFunction &MF);

   52   bool shouldLocalize(const MachineInstr &MI);
   58   static bool isLocalUse(MachineOperand &MOUse, const MachineInstr &Def,
   64   typedef SmallSetVector<MachineInstr *, 32> LocalizedSetVecT;

  125   static bool bind(const MachineRegisterInfo &MRI, MachineInstr *&MI,
  164 inline bind_ty<MachineInstr *> m_MInstr(MachineInstr *&MI) { return MI; }
  164 inline bind_ty<MachineInstr *> m_MInstr(MachineInstr *&MI) { return MI; }
  180     MachineInstr *TmpMI;
  248     MachineInstr *TmpMI;

  233   void recordInsertion(MachineInstr *MI) const;
  239   MachineIRBuilder(MachineInstr &MI) : MachineIRBuilder(*MI.getMF()) {
  313   void setInstr(MachineInstr &MI);

  206     MachineInstr &Instr;
  226     InstrInsertPoint(MachineInstr &Instr, bool Before = true);
  355     RepairingPlacement(MachineInstr &MI, unsigned OpIdx,
  372     void addInsertPoint(MachineInstr &MI, bool Before);
  517   bool assignInstr(MachineInstr &MI);
  580   findBestMapping(MachineInstr &MI,
  592   computeMapping(MachineInstr &MI,
  613   bool applyMapping(MachineInstr &MI,

  262     bool verify(const MachineInstr &MI) const;
  291     MachineInstr &MI;
  321     OperandsMapper(MachineInstr &MI, const InstructionMapping &InstrMapping,
  327     MachineInstr &getMI() const { return MI; }
  457   const InstructionMapping &getInstrMappingImpl(const MachineInstr &MI) const;
  544   getRegBankFromConstraints(const MachineInstr &MI, unsigned OpIdx,
  680   getInstrMapping(const MachineInstr &MI) const;
  685   getInstrAlternativeMappings(const MachineInstr &MI) const;
  703   InstructionMappings getInstrPossibleMappings(const MachineInstr &MI) const;

   62                                   MachineInstr &InsertPt,
   80                                   MachineInstr &InsertPt, const MCInstrDesc &II,
   92 bool constrainSelectedInstRegOperands(MachineInstr &I,
   98 bool isTriviallyDead(const MachineInstr &MI, const MachineRegisterInfo &MRI);
  109                         const MachineInstr &MI);
  138 MachineInstr *getOpcodeDef(unsigned Opcode, Register Reg,
  144 MachineInstr *getDefIgnoringCopies(Register Reg,

   39 using InsnRange = std::pair<const MachineInstr *, const MachineInstr *>;
   39 using InsnRange = std::pair<const MachineInstr *, const MachineInstr *>;
   72   void openInsnRange(const MachineInstr *MI) {
   82   void extendInsnRange(const MachineInstr *MI) {
  131   const MachineInstr *LastInsn = nullptr;  // Last instruction of this scope.
  132   const MachineInstr *FirstInsn = nullptr; // First instruction of this scope.
  223                             DenseMap<const MachineInstr *, LexicalScope *> &M);
  227                           DenseMap<const MachineInstr *, LexicalScope *> &M);

  107                                 const MachineInstr &MI);
  153                                                  MachineInstr &startInst);
  162                       SmallVectorImpl<MachineInstr*> *dead = nullptr);
  221     bool isNotInMIMap(const MachineInstr &Instr) const {
  226     SlotIndex getInstructionIndex(const MachineInstr &Instr) const {
  231     MachineInstr* getInstructionFromIndex(SlotIndex index) const {
  266     SlotIndex InsertMachineInstrInMaps(MachineInstr &MI) {
  276     void RemoveMachineInstrFromMaps(MachineInstr &MI) {
  280     SlotIndex ReplaceMachineInstrInMaps(MachineInstr &MI, MachineInstr &NewMI) {
  280     SlotIndex ReplaceMachineInstrInMaps(MachineInstr &MI, MachineInstr &NewMI) {
  311     void handleMove(MachineInstr &MI, bool UpdateFlags = false);
  321     void handleMoveIntoBundle(MachineInstr &MI, MachineInstr &BundleStart,
  321     void handleMoveIntoBundle(MachineInstr &MI, MachineInstr &BundleStart,
  463                            SmallVectorImpl<MachineInstr*> *dead);

  112   void removeDefs(const MachineInstr &MI);
  115   void addUses(const MachineInstr &MI);
  120   void stepBackward(const MachineInstr &MI);
  128   void stepForward(const MachineInstr &MI,

   55     virtual void LRE_WillEraseInstruction(MachineInstr *MI) {}
   86   SmallPtrSet<MachineInstr *, 32> *DeadRemats;
  101   bool allUsesAvailableAt(const MachineInstr *OrigMI, SlotIndex OrigIdx,
  106   bool foldAsLoad(LiveInterval *LI, SmallVectorImpl<MachineInstr *> &Dead);
  112   void eliminateDeadDef(MachineInstr *MI, ToShrinkSet &ToShrink,
  141                 SmallPtrSet<MachineInstr *, 32> *deadRemats = nullptr)
  197   bool checkRematerializable(VNInfo *VNI, const MachineInstr *DefMI,
  203     MachineInstr *OrigMI = nullptr; // Instruction defining OrigVNI. It contains
  245   void eliminateDeadDefs(SmallVectorImpl<MachineInstr *> &Dead,

   47   static void accumulateUsedDefed(const MachineInstr &MI,
  128   void stepBackward(const MachineInstr &MI);
  133   void accumulate(const MachineInstr &MI);

   88     std::vector<MachineInstr*> Kills;
   93     bool removeKill(MachineInstr &MI) {
   94       std::vector<MachineInstr *>::iterator I = find(Kills, &MI);
  102     MachineInstr *findKill(const MachineBasicBlock *MBB) const;
  135   std::vector<MachineInstr *> PhysRegDef;
  140   std::vector<MachineInstr *> PhysRegUse;
  146   DenseMap<MachineInstr*, unsigned> DistanceMap;
  151   bool HandlePhysRegKill(unsigned Reg, MachineInstr *MI);
  156   void HandlePhysRegUse(unsigned Reg, MachineInstr &MI);
  157   void HandlePhysRegDef(unsigned Reg, MachineInstr *MI,
  159   void UpdatePhysRegDefs(MachineInstr &MI, SmallVectorImpl<unsigned> &Defs);
  163   MachineInstr *FindLastRefOrPartRef(unsigned Reg);
  168   MachineInstr *FindLastPartialDef(unsigned Reg,
  177   void runOnInstr(MachineInstr &MI, SmallVectorImpl<unsigned> &Defs);
  186   bool RegisterDefIsDead(MachineInstr &MI, unsigned Reg) const;
  193   void replaceKillInstruction(unsigned Reg, MachineInstr &OldMI,
  194                               MachineInstr &NewMI);
  200   void addVirtualRegisterKilled(unsigned IncomingReg, MachineInstr &MI,
  210   bool removeVirtualRegisterKilled(unsigned reg, MachineInstr &MI) {
  231   void removeVirtualRegistersKilled(MachineInstr &MI);
  236   void addVirtualRegisterDead(unsigned IncomingReg, MachineInstr &MI,
  246   bool removeVirtualRegisterDead(unsigned reg, MachineInstr &MI) {
  279   void HandleVirtRegDef(unsigned reg, MachineInstr &MI);
  280   void HandleVirtRegUse(unsigned reg, MachineBasicBlock *MBB, MachineInstr &MI);

   55       simple_ilist<MachineInstr, ilist_sentinel_tracking<true>>::iterator;
   58   void addNodeToList(MachineInstr *N);
   59   void removeNodeFromList(MachineInstr *N);
   62   void deleteNode(MachineInstr *MI);
   81   using Instructions = ilist<MachineInstr, ilist_sentinel_tracking<true>>;
  181   using iterator = MachineInstrBundleIterator<MachineInstr>;
  182   using const_iterator = MachineInstrBundleIterator<const MachineInstr>;
  183   using reverse_iterator = MachineInstrBundleIterator<MachineInstr, true>;
  185       MachineInstrBundleIterator<const MachineInstr, true>;
  190   MachineInstr       &instr_front()       { return Insts.front(); }
  191   MachineInstr       &instr_back()        { return Insts.back();  }
  192   const MachineInstr &instr_front() const { return Insts.front(); }
  193   const MachineInstr &instr_back()  const { return Insts.back();  }
  195   MachineInstr       &front()             { return Insts.front(); }
  196   MachineInstr       &back()              { return *--end();      }
  197   const MachineInstr &front()       const { return Insts.front(); }
  198   const MachineInstr &back()        const { return *--end();      }
  601   void push_back(MachineInstr *MI) { Insts.push_back(MI); }
  620   iterator insert(iterator I, MachineInstr *MI) {
  629   iterator insertAfter(iterator I, MachineInstr *MI) {
  679   iterator erase(MachineInstr *I) {
  688   MachineInstr *remove(MachineInstr *I) {
  688   MachineInstr *remove(MachineInstr *I) {
  698   MachineInstr *remove_instr(MachineInstr *I);
  698   MachineInstr *remove_instr(MachineInstr *I);

  132   bool dominates(const MachineInstr *A, const MachineInstr *B) const {
  132   bool dominates(const MachineInstr *A, const MachineInstr *B) const {

  263   Recycler<MachineInstr> InstructionRecycler;
  377     virtual void MF_HandleInsertion(MachineInstr &MI) = 0;
  379     virtual void MF_HandleRemoval(MachineInstr &MI) = 0;
  400   using CallSiteInfoMap = DenseMap<const MachineInstr *, CallSiteInfo>;
  416   void handleInsertion(MachineInstr &MI);
  417   void handleRemoval(MachineInstr &MI);
  721   MachineInstr *CreateMachineInstr(const MCInstrDesc &MCID, const DebugLoc &DL,
  731   MachineInstr *CloneMachineInstr(const MachineInstr *Orig);
  731   MachineInstr *CloneMachineInstr(const MachineInstr *Orig);
  738   MachineInstr &CloneMachineInstrBundle(MachineBasicBlock &MBB,
  739       MachineBasicBlock::iterator InsertBefore, const MachineInstr &Orig);
  742   void DeleteMachineInstr(MachineInstr *MI);
  803   MachineInstr::ExtraInfo *createMIExtraInfo(
  984   void addCallArgsForwardingRegs(const MachineInstr *CallI,
 1000   void moveCallSiteInfo(const MachineInstr *Old,
 1001                         const MachineInstr *New);
 1005   void eraseCallSiteInfo(const MachineInstr *MI);
 1010   void copyCallSiteInfo(const MachineInstr *Old,
 1011                         const MachineInstr *New);

   64     : public ilist_node_with_parent<MachineInstr, MachineBasicBlock,
  254   MachineInstr(MachineFunction &, const MachineInstr &);
  266   MachineInstr(const MachineInstr &) = delete;
  267   MachineInstr &operator=(const MachineInstr &) = delete;
  267   MachineInstr &operator=(const MachineInstr &) = delete;
  891            getFlag(MachineInstr::MIFlag::FPExcept);
 1003   bool isIdenticalTo(const MachineInstr &Other,
 1011   MachineInstr *removeFromParent();
 1018   MachineInstr *removeFromBundle();
 1452   bool mayAlias(AAResults *AA, const MachineInstr &Other, bool UseTBAA) const;
 1503   void copyImplicitOps(MachineFunction &MF, const MachineInstr &MI);
 1596   void cloneMemRefs(MachineFunction &MF, const MachineInstr &MI);
 1606                           ArrayRef<const MachineInstr *> MIs);
 1624   void cloneInstrSymbols(MachineFunction &MF, const MachineInstr &MI);
 1635   uint16_t mergeFlagsWith(const MachineInstr& Other) const;
 1655   void collectDebugValues(SmallVectorImpl<MachineInstr *> &DbgValues);
 1704 struct MachineInstrExpressionTrait : DenseMapInfo<MachineInstr*> {
 1705   static inline MachineInstr *getEmptyKey() {
 1709   static inline MachineInstr *getTombstoneKey() {
 1713   static unsigned getHashValue(const MachineInstr* const &MI);
 1715   static bool isEqual(const MachineInstr* const &LHS,
 1716                       const MachineInstr* const &RHS) {
 1720     return LHS->isIdenticalTo(*RHS, MachineInstr::IgnoreVRegDefs);
 1727 inline raw_ostream& operator<<(raw_ostream &OS, const MachineInstr &MI) {

   62   MachineInstr *MI = nullptr;
   69   MachineInstrBuilder(MachineFunction &F, MachineInstr *I) : MF(&F), MI(I) {}
   74   operator MachineInstr*() const { return MI; }
   75   MachineInstr *operator->() const { return MI; }
   80   MachineInstr *getInstr() const { return MI; }
  204   const MachineInstrBuilder &cloneMemRefs(const MachineInstr &OtherMI) const {
  210   cloneMergedMemRefs(ArrayRef<const MachineInstr *> OtherMIs) const {
  269   const MachineInstrBuilder &setMIFlag(MachineInstr::MIFlag Flag) const {
  303   copyImplicitOps(const MachineInstr &OtherMI) const {
  337   MachineInstr *MI = MF.CreateMachineInstr(MCID, DL);
  353   MachineInstr *MI = MF.CreateMachineInstr(MCID, DL);
  358 inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, MachineInstr &I,
  368 inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, MachineInstr *I,
  382   MachineInstr *MI = MF.CreateMachineInstr(MCID, DL);
  392   MachineInstr *MI = MF.CreateMachineInstr(MCID, DL);
  397 inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, MachineInstr &I,
  407 inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, MachineInstr *I,
  462 MachineInstr *buildDbgValueForSpill(MachineBasicBlock &BB,
  464                                     const MachineInstr &Orig, int FrameIndex);
  468 void updateDbgValueForSpill(MachineInstr &Orig, int FrameIndex);
  530       MachineInstr &MI = *B;
  538   explicit MIBundleBuilder(MachineInstr *MI)
  572     MI->setFlag(MachineInstr::BundledPred);
  573     MI->setFlag(MachineInstr::BundledSucc);
  579   MIBundleBuilder &prepend(MachineInstr *MI) {
  585   MIBundleBuilder &append(MachineInstr *MI) {

   95   MachineInstr::mop_iterator OpI, OpE;
  116   explicit MachineOperandIteratorBase(MachineInstr &MI, bool WholeBundle) {
  209            SmallVectorImpl<std::pair<MachineInstr*, unsigned> > *Ops = nullptr);
  224   MIOperands(MachineInstr &MI) : MachineOperandIteratorBase(MI, false) {}
  233   ConstMIOperands(const MachineInstr &MI)
  244   MIBundleOperands(MachineInstr &MI) : MachineOperandIteratorBase(MI, true) {}
  254   ConstMIBundleOperands(const MachineInstr &MI)

   26   using list_type = simple_ilist<T, ilist_sentinel_tracking<true>>;
   32   using list_type = simple_ilist<T, ilist_sentinel_tracking<true>>;
   38   using list_type = simple_ilist<T, ilist_sentinel_tracking<true>>;
   44   using list_type = simple_ilist<T, ilist_sentinel_tracking<true>>;
  109   using Traits = MachineInstrBundleIteratorTraits<Ty, IsReverse>;
  129   using reverse_iterator = MachineInstrBundleIterator<Ty, !IsReverse>;
  154       const MachineInstrBundleIterator<OtherTy, IsReverse> &I,
  155       typename std::enable_if<std::is_convertible<OtherTy *, Ty *>::value,
  155       typename std::enable_if<std::is_convertible<OtherTy *, Ty *>::value,
  170       const MachineInstrBundleIterator<Ty, !IsReverse> &I)

  163   MachineInstr *ParentMI;
  235   MachineInstr *getParent() { return ParentMI; }
  236   const MachineInstr *getParent() const { return ParentMI; }

   41     MachineArgument(StringRef Key, const MachineInstr &MI);

   79     MachineInstr *LoopInductionVar = nullptr;
   80     MachineInstr *LoopCompare = nullptr;
  146   using InstrMapTy = DenseMap<MachineInstr *, MachineInstr *>;
  146   using InstrMapTy = DenseMap<MachineInstr *, MachineInstr *>;
  153   DenseMap<MachineInstr*, MachineInstr *> NewMIs;
  153   DenseMap<MachineInstr*, MachineInstr *> NewMIs;
  263   void applyInstrChange(MachineInstr *MI, SMSchedule &Schedule);
  302   bool computeDelta(MachineInstr &MI, unsigned &Delta);
  303   MachineInstr *findDefInLoop(unsigned Reg);
  304   bool canUseLastOffsetValue(MachineInstr *MI, unsigned &BasePos,
  463   bool canReserveResources(const MachineInstr &MI) const;
  467   void reserveResources(const MachineInstr &MI);
  582   bool isLoopCarried(SwingSchedulerDAG *SSD, MachineInstr &Phi);
  583   bool isLoopCarriedDefOfUse(SwingSchedulerDAG *SSD, MachineInstr *Def,

   40   using InstT = MachineInstr;

  596   MachineInstr *getVRegDef(unsigned Reg) const;
  601   MachineInstr *getUniqueVRegDef(unsigned Reg) const;
  824                            ArrayRef<MachineInstr*> Users) const {
  825     for (MachineInstr *MI : Users) {
  971     : public std::iterator<std::forward_iterator_tag, MachineInstr, ptrdiff_t> {
 1009                                     MachineInstr, ptrdiff_t>::reference;
 1011                                   MachineInstr, ptrdiff_t>::pointer;
 1031         MachineInstr *P = Op->getParent();
 1077     : public std::iterator<std::forward_iterator_tag, MachineInstr, ptrdiff_t> {
 1115                                     MachineInstr, ptrdiff_t>::reference;
 1117                                   MachineInstr, ptrdiff_t>::pointer;
 1137         MachineInstr *P = Op->getParent();
 1156     MachineInstr &operator*() const {
 1163     MachineInstr *operator->() const { return &operator*(); }

   49   SmallVectorImpl<MachineInstr*> *InsertedPHIs;
   58                         SmallVectorImpl<MachineInstr*> *NewPHI = nullptr);

  339   void moveInstruction(MachineInstr *MI, MachineBasicBlock::iterator InsertPos);

   78   const MachineInstr *MI = nullptr;
  298     InstrCycles getInstrCycles(const MachineInstr &MI) const {
  305     unsigned getInstrSlack(const MachineInstr &MI) const;
  309     unsigned getPHIDepth(const MachineInstr &PHI) const;
  314     bool isDepInTrace(const MachineInstr &DefMI,
  315                       const MachineInstr &UseMI) const;
  325     DenseMap<const MachineInstr*, InstrCycles> Cycles;
  335     void addLiveIns(const MachineInstr *DefMI, unsigned DefOp,
  364     void updateDepth(TraceBlockInfo &TBI, const MachineInstr&,
  366     void updateDepth(const MachineBasicBlock *, const MachineInstr&,

   32                                                 const MachineInstr *FirstMI,
   33                                                 const MachineInstr &SecondMI)>;

   86   std::vector<MachineInstr *> ScheduledInstrs;
   89   DenseMap<MachineInstr *, int> Cycle;
   92   DenseMap<MachineInstr *, int> Stage;
  106                  std::vector<MachineInstr *> ScheduledInstrs,
  107                  DenseMap<MachineInstr *, int> Cycle,
  108                  DenseMap<MachineInstr *, int> Stage)
  133   int getStage(MachineInstr *MI) {
  139   int getCycle(MachineInstr *MI) {
  145   ArrayRef<MachineInstr *> getInstructions() { return ScheduledInstrs; }
  155   using InstrChangesTy = DenseMap<MachineInstr *, std::pair<unsigned, int64_t>>;
  160   using InstrMapTy = DenseMap<MachineInstr *, MachineInstr *>;
  160   using InstrMapTy = DenseMap<MachineInstr *, MachineInstr *>;
  204   bool computeDelta(MachineInstr &MI, unsigned &Delta);
  205   void updateMemOperands(MachineInstr &NewMI, MachineInstr &OldMI,
  205   void updateMemOperands(MachineInstr &NewMI, MachineInstr &OldMI,
  207   MachineInstr *cloneInstr(MachineInstr *OldMI, unsigned CurStageNum,
  207   MachineInstr *cloneInstr(MachineInstr *OldMI, unsigned CurStageNum,
  209   MachineInstr *cloneAndChangeInstr(MachineInstr *OldMI, unsigned CurStageNum,
  209   MachineInstr *cloneAndChangeInstr(MachineInstr *OldMI, unsigned CurStageNum,
  211   void updateInstruction(MachineInstr *NewMI, bool LastDef,
  214   MachineInstr *findDefInLoop(unsigned Reg);
  222                              MachineInstr *Phi, unsigned OldReg,
  224   bool isLoopCarried(MachineInstr &Phi);
  296   DenseMap<MachineInstr *, MachineInstr *> CanonicalMIs;
  296   DenseMap<MachineInstr *, MachineInstr *> CanonicalMIs;
  297   DenseMap<std::pair<MachineBasicBlock *, MachineInstr *>, MachineInstr *>
  297   DenseMap<std::pair<MachineBasicBlock *, MachineInstr *>, MachineInstr *>
  332   void rewriteUsesOf(MachineInstr *MI);
  340   unsigned getStage(MachineInstr *MI) {

   59   DenseMap<MachineInstr *, int> InstIds;
   94   int getReachingDef(MachineInstr *MI, int PhysReg);
   98   int getClearance(MachineInstr *MI, MCPhysReg PhysReg);
  112   void processDefs(MachineInstr *);

  180   void collect(const MachineInstr &MI, const TargetRegisterInfo &TRI,
  186   void detectDeadDefs(const MachineInstr &MI, const LiveIntervals &LIS);
  194                           MachineInstr *AddFlagsMI = nullptr);
  478   void getMaxUpwardPressureDelta(const MachineInstr *MI,
  484   void getUpwardPressureDelta(const MachineInstr *MI,
  494   void getMaxDownwardPressureDelta(const MachineInstr *MI,
  502   void getMaxPressureDelta(const MachineInstr *MI,
  516   void getUpwardPressure(const MachineInstr *MI,
  521   void getDownwardPressure(const MachineInstr *MI,
  525   void getPressureAfterInst(const MachineInstr *MI,
  558   void bumpUpwardPressure(const MachineInstr *MI);
  559   void bumpDownwardPressure(const MachineInstr *MI);

   57     const MachineInstr *Restore = nullptr;

  247     MachineInstr *Instr = nullptr; ///< Alternatively, a MachineInstr.
  319     SUnit(MachineInstr *instr, unsigned nodenum)
  366     void setInstr(MachineInstr *MI) {
  373     MachineInstr *getInstr() const {

  158     DenseMap<MachineInstr*, SUnit*> MISUnitMap;
  244         std::vector<std::pair<MachineInstr *, MachineInstr *>>;
  244         std::vector<std::pair<MachineInstr *, MachineInstr *>>;
  249     MachineInstr *FirstDbgValue = nullptr;
  278     SUnit *newSUnit(MachineInstr *MI);
  281     SUnit *getSUnit(MachineInstr *MI) const;
  373     void toggleKillFlag(MachineInstr &MI, MachineOperand &MO);
  384   inline SUnit *ScheduleDAGInstrs::newSUnit(MachineInstr *MI) {
  395   inline SUnit *ScheduleDAGInstrs::getSUnit(MachineInstr *MI) const {
  396     DenseMap<MachineInstr*, SUnit*>::const_iterator I = MISUnitMap.find(MI);

   75   virtual void EmitInstruction(MachineInstr *) {}
   88   virtual unsigned PreEmitNoops(MachineInstr *) {

   47     MachineInstr *mi;
   51     IndexListEntry(MachineInstr *mi, unsigned index) : mi(mi), index(index) {}
   53     MachineInstr* getInstr() const { return mi; }
   54     void setInstr(MachineInstr *mi) {
  324     using Mi2IndexMap = DenseMap<const MachineInstr *, SlotIndex>;
  334     IndexListEntry* createEntry(MachineInstr *mi, unsigned index) {
  385     bool hasIndex(const MachineInstr &instr) const {
  390     SlotIndex getInstructionIndex(const MachineInstr &MI) const {
  395       const MachineInstr &BundleNonDebug =
  406     MachineInstr* getInstructionFromIndex(SlotIndex index) const {
  425     SlotIndex getIndexBefore(const MachineInstr &MI) const {
  442     SlotIndex getIndexAfter(const MachineInstr &MI) const {
  518       if (MachineInstr *MI = getInstructionFromIndex(index))
  538     SlotIndex insertMachineInstrInMaps(MachineInstr &MI, bool Late = false) {
  581     void removeMachineInstrFromMaps(MachineInstr &MI);
  586     void removeSingleMachineInstrFromMaps(MachineInstr &MI);
  591     SlotIndex replaceMachineInstrInMaps(MachineInstr &MI, MachineInstr &NewMI) {
  591     SlotIndex replaceMachineInstrInMaps(MachineInstr &MI, MachineInstr &NewMI) {

   41   const MachineInstr* MI;
   44   explicit StackMapOpers(const MachineInstr *MI);
   82   const MachineInstr *MI;
   95   explicit PatchPointOpers(const MachineInstr *MI);
  168   explicit StatepointOpers(const MachineInstr *MI) : MI(MI) {}
  190   const MachineInstr *MI;
  269   void recordStackMap(const MachineInstr &MI);
  272   void recordPatchPoint(const MachineInstr &MI);
  275   void recordStatepoint(const MachineInstr &MI);
  296   MachineInstr::const_mop_iterator
  297   parseOperand(MachineInstr::const_mop_iterator MOI,
  298                MachineInstr::const_mop_iterator MOE, LocationVec &Locs,
  314   void recordStackMapOpers(const MachineInstr &MI, uint64_t ID,
  315                            MachineInstr::const_mop_iterator MOI,
  316                            MachineInstr::const_mop_iterator MOE,

   94   void processPHI(MachineInstr *MI, MachineBasicBlock *TailBB,
   99   void duplicateInstruction(MachineInstr *MI, MachineBasicBlock *TailBB,
  110                          SmallVectorImpl<MachineInstr *> &Copies);
  115                      SmallVectorImpl<MachineInstr *> &Copies);
  118                  SmallVectorImpl<MachineInstr *> &Copies);

   98   bool isTriviallyReMaterializable(const MachineInstr &MI,
  114   virtual bool isReallyTriviallyReMaterializable(const MachineInstr &MI,
  134   virtual MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
  134   virtual MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
  157   bool isReallyTriviallyReMaterializableGeneric(const MachineInstr &MI,
  170   bool isFrameInstr(const MachineInstr &I) const {
  176   bool isFrameSetup(const MachineInstr &I) const {
  188   int64_t getFrameSize(const MachineInstr &I) const {
  197   int64_t getFrameTotalSize(const MachineInstr &I) const {
  213   virtual int getSPAdjust(const MachineInstr &MI) const;
  220   virtual bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg,
  230   virtual unsigned isLoadFromStackSlot(const MachineInstr &MI,
  239   virtual unsigned isLoadFromStackSlot(const MachineInstr &MI,
  248   virtual unsigned isLoadFromStackSlotPostFE(const MachineInstr &MI,
  260       const MachineInstr &MI,
  268   virtual unsigned isStoreToStackSlot(const MachineInstr &MI,
  277   virtual unsigned isStoreToStackSlot(const MachineInstr &MI,
  286   virtual unsigned isStoreToStackSlotPostFE(const MachineInstr &MI,
  298       const MachineInstr &MI,
  304   virtual bool isStackSlotCopy(const MachineInstr &MI, int &DestFrameIndex,
  328   virtual unsigned getInstSizeInBytes(const MachineInstr &MI) const {
  336   virtual bool isAsCheapAsAMove(const MachineInstr &MI) const {
  345   virtual bool shouldSink(const MachineInstr &MI) const { return true; }
  362   virtual MachineInstr &duplicate(MachineBasicBlock &MBB,
  376   virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
  404   MachineInstr *
  405   commuteInstruction(MachineInstr &MI, bool NewMI = false,
  426   virtual bool findCommutedOpIndices(const MachineInstr &MI,
  477   getRegSequenceInputs(const MachineInstr &MI, unsigned DefIdx,
  495   bool getExtractSubregInputs(const MachineInstr &MI, unsigned DefIdx,
  515   bool getInsertSubregInputs(const MachineInstr &MI, unsigned DefIdx,
  524   virtual bool produceSameValue(const MachineInstr &MI0,
  525                                 const MachineInstr &MI1,
  536   virtual MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const {
  605     MachineInstr *ConditionDef = nullptr;
  676     virtual bool shouldIgnoreForPipelining(const MachineInstr *MI) const = 0;
  714   virtual bool analyzeLoop(MachineLoop &L, MachineInstr *&IndVarInst,
  715                            MachineInstr *&CmpInst) const {
  725                                    MachineInstr *IndVar, MachineInstr &Cmp,
  725                                    MachineInstr *IndVar, MachineInstr &Cmp,
  727                                    SmallVectorImpl<MachineInstr *> &PrevInsts,
  791   virtual unsigned predictBranchSizeForIfCvt(MachineInstr &MI) const {
  875   virtual bool analyzeSelect(const MachineInstr &MI,
  898   virtual MachineInstr *optimizeSelect(MachineInstr &MI,
  898   virtual MachineInstr *optimizeSelect(MachineInstr &MI,
  899                                        SmallPtrSetImpl<MachineInstr *> &NewMIs,
  925   virtual bool isCopyInstrImpl(const MachineInstr &MI,
  937   bool isCopyInstr(const MachineInstr &MI, const MachineOperand *&Source,
  978   virtual bool expandPostRAPseudo(MachineInstr &MI) const { return false; }
 1002   MachineInstr *foldMemoryOperand(MachineInstr &MI, ArrayRef<unsigned> Ops,
 1002   MachineInstr *foldMemoryOperand(MachineInstr &MI, ArrayRef<unsigned> Ops,
 1009   MachineInstr *foldMemoryOperand(MachineInstr &MI, ArrayRef<unsigned> Ops,
 1009   MachineInstr *foldMemoryOperand(MachineInstr &MI, ArrayRef<unsigned> Ops,
 1010                                   MachineInstr &LoadMI,
 1021       MachineInstr &Root,
 1034   bool isReassociationCandidate(const MachineInstr &Inst, bool &Commuted) const;
 1037   virtual bool isAssociativeAndCommutative(const MachineInstr &Inst) const {
 1042   virtual bool hasReassociableOperands(const MachineInstr &Inst,
 1046   bool hasReassociableSibling(const MachineInstr &Inst, bool &Commuted) const;
 1059       MachineInstr &Root, MachineCombinerPattern Pattern,
 1060       SmallVectorImpl<MachineInstr *> &InsInstrs,
 1061       SmallVectorImpl<MachineInstr *> &DelInstrs,
 1066   void reassociateOps(MachineInstr &Root, MachineInstr &Prev,
 1066   void reassociateOps(MachineInstr &Root, MachineInstr &Prev,
 1068                       SmallVectorImpl<MachineInstr *> &InsInstrs,
 1069                       SmallVectorImpl<MachineInstr *> &DelInstrs,
 1074   virtual void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2,
 1074   virtual void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2,
 1075                                      MachineInstr &NewMI1,
 1076                                      MachineInstr &NewMI2) const {}
 1091   virtual MachineInstr *
 1092   foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI,
 1105   virtual MachineInstr *foldMemoryOperandImpl(
 1106       MachineFunction &MF, MachineInstr &MI, ArrayRef<unsigned> Ops,
 1121       const MachineInstr &MI, unsigned DefIdx,
 1134   virtual bool getExtractSubregLikeInputs(const MachineInstr &MI,
 1149   getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
 1167   unfoldMemoryOperand(MachineFunction &MF, MachineInstr &MI, unsigned Reg,
 1169                       SmallVectorImpl<MachineInstr *> &NewMIs) const {
 1216   virtual bool getMemOperandWithOffset(const MachineInstr &MI,
 1226   virtual bool getBaseAndOffsetPosition(const MachineInstr &MI,
 1233   virtual bool getIncrementValue(const MachineInstr &MI, int &Value) const {
 1264   virtual bool isPostIncrement(const MachineInstr &MI) const { return false; }
 1267   virtual bool isPredicated(const MachineInstr &MI) const { return false; }
 1271   virtual bool isUnpredicatedTerminator(const MachineInstr &MI) const;
 1274   virtual bool isUnconditionalTailCall(const MachineInstr &MI) const {
 1280                                           const MachineInstr &TailCall) const {
 1287                                          const MachineInstr &TailCall) const {
 1293   virtual bool PredicateInstruction(MachineInstr &MI,
 1306   virtual bool DefinesPredicate(MachineInstr &MI,
 1314   virtual bool isPredicable(const MachineInstr &MI) const {
 1326   virtual bool isSchedulingBoundary(const MachineInstr &MI,
 1369   virtual bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
 1377   virtual bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
 1382   virtual bool optimizeCondBranch(MachineInstr &MI) const { return false; }
 1391   virtual MachineInstr *optimizeLoadInstr(MachineInstr &MI,
 1391   virtual MachineInstr *optimizeLoadInstr(MachineInstr &MI,
 1394                                           MachineInstr *&DefMI) const {
 1404   virtual bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI,
 1404   virtual bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI,
 1414                                   const MachineInstr &MI) const;
 1437                                 const MachineInstr &DefMI, unsigned DefIdx,
 1438                                 const MachineInstr &UseMI,
 1445                                    const MachineInstr &MI,
 1448   virtual unsigned getPredicationCost(const MachineInstr &MI) const;
 1455                              const MachineInstr &DefMI) const;
 1458                                const MachineInstr &DefMI) const;
 1470                                      const MachineInstr &DefMI, unsigned DefIdx,
 1471                                      const MachineInstr &UseMI,
 1479                                 const MachineInstr &DefMI,
 1483   virtual bool verifyInstruction(const MachineInstr &MI,
 1508   getExecutionDomain(const MachineInstr &MI) const {
 1516   virtual void setExecutionDomain(MachineInstr &MI, unsigned Domain) const {}
 1558   getPartialRegUpdateClearance(const MachineInstr &MI, unsigned OpNum,
 1578   virtual unsigned getUndefRegClearance(const MachineInstr &MI, unsigned &OpNum,
 1601   virtual void breakPartialRegDependency(MachineInstr &MI, unsigned OpNum,
 1622   areMemAccessesTriviallyDisjoint(const MachineInstr &MIa,
 1623                                   const MachineInstr &MIb) const {
 1689   virtual bool isTailCall(const MachineInstr &Inst) const {
 1696   virtual bool isBasicBlockPrologue(const MachineInstr &MI) const {
 1703   virtual MachineInstr *createPHIDestinationCopy(
 1713   virtual MachineInstr *createPHISourceCopy(MachineBasicBlock &MBB,
 1780   describeLoadedValue(const MachineInstr &MI) const;

 2924   MachineBasicBlock *emitPatchPoint(MachineInstr &MI,
 2929   MachineBasicBlock *emitXRayCustomEvent(MachineInstr &MI,
 2934   MachineBasicBlock *emitXRayTypedEvent(MachineInstr &MI,
 2990   virtual bool isIndexingLegal(MachineInstr &MI, Register Base, Register Offset,
 4204   EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const;
 4210   virtual void AdjustInstrPostInstrSelection(MachineInstr &MI,

  872   virtual int64_t getFrameIndexInstrOffset(const MachineInstr *MI,
  881   virtual bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const {
  896   virtual void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
  903   virtual bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg,
  946   virtual bool shouldCoalesce(MachineInstr *MI,

   56   const MCSchedClassDesc *resolveSchedClass(const MachineInstr *MI) const;
   98   bool mustBeginGroup(const MachineInstr *MI,
  101   bool mustEndGroup(const MachineInstr *MI,
  105   unsigned getNumMicroOps(const MachineInstr *MI,
  170   unsigned computeOperandLatency(const MachineInstr *DefMI, unsigned DefOperIdx,
  171                                  const MachineInstr *UseMI, unsigned UseOperIdx)
  185   unsigned computeInstrLatency(const MachineInstr *MI,
  194   unsigned computeOutputLatency(const MachineInstr *DefMI, unsigned DefOperIdx,
  195                                 const MachineInstr *DepMI) const;
  198   double computeReciprocalThroughput(const MachineInstr *MI) const;

  140                                      const MachineInstr *MI,
  154   virtual bool isZeroIdiom(const MachineInstr *MI, APInt &Mask) const {
  165   virtual bool isDependencyBreaking(const MachineInstr *MI, APInt &Mask) const {
  178   virtual bool isOptimizableRegisterMove(const MachineInstr *MI) const {

   56   static inline void *getAsVoidPointer(T *P) { return P; }
   57   static inline T *getFromVoidPointer(void *P) { return static_cast<T *>(P); }
   59   enum { NumLowBitsAvailable = detail::ConstantLog2<alignof(T)>::value };
   91   typedef PointerLikeTypeTraits<T *> NonConst;
   93   static inline const void *getAsVoidPointer(const T *P) {
   96   static inline const T *getFromVoidPointer(const void *P) {

   83   SubClass *Allocate(AllocatorType &Allocator) {
   84     static_assert(alignof(SubClass) <= Align,
   86     static_assert(sizeof(SubClass) <= Size,
   93   T *Allocate(AllocatorType &Allocator) {
   93   T *Allocate(AllocatorType &Allocator) {
   98   void Deallocate(AllocatorType & /*Allocator*/, SubClass* Element) {

  390     for (auto &SomePHI : BB->phis()) {

  196 void AggressiveAntiDepBreaker::Observe(MachineInstr &MI, unsigned Count,
  230 bool AggressiveAntiDepBreaker::IsImplicitDefUse(MachineInstr &MI,
  249     MachineInstr &MI, std::set<unsigned> &PassthruRegs) {
  355     MachineInstr &MI, unsigned Count, std::set<unsigned> &PassthruRegs) {
  443 void AggressiveAntiDepBreaker::ScanInstruction(MachineInstr &MI,
  705         MachineInstr *UseMI = Q.second.Operand->getParent();
  723         MachineInstr *DefMI = Q.second.Operand->getParent();
  772   std::map<MachineInstr *, const SUnit *> MISUnitMap;
  783   MachineInstr *CriticalPathMI = nullptr;
  816     MachineInstr &MI = *--I;

  150     void Observe(MachineInstr &MI, unsigned Count,
  162     bool IsImplicitDefUse(MachineInstr &MI, MachineOperand &MO);
  166     void GetPassthruRegs(MachineInstr &MI, std::set<unsigned> &PassthruRegs);
  172     void PrescanInstruction(MachineInstr &MI, unsigned Count,
  174     void ScanInstruction(MachineInstr &MI, unsigned Count);

   34       std::vector<std::pair<MachineInstr *, MachineInstr *>>;
   34       std::vector<std::pair<MachineInstr *, MachineInstr *>>;
   51   virtual void Observe(MachineInstr &MI, unsigned Count,
   59   void UpdateDbgValue(MachineInstr &MI, unsigned OldReg, unsigned NewReg) {
   67   void UpdateDbgValues(const DbgValueVector &DbgValues, MachineInstr *ParentMI,
   71     MachineInstr *PrevDbgMI = nullptr;
   73       MachineInstr *PrevMI = DV.second;
   75         MachineInstr *DbgMI = DV.first;

  764 static void emitComments(const MachineInstr &MI, raw_ostream &CommentOS) {
  786   if (MI.getAsmPrinterFlag(MachineInstr::ReloadReuse))
  792 void AsmPrinter::emitImplicitDef(const MachineInstr *MI) const {
  804 static void emitKill(const MachineInstr *MI, AsmPrinter &AP) {
  821 static bool emitDebugValueComment(const MachineInstr *MI, AsmPrinter &AP) {
  911 static bool emitDebugLabelComment(const MachineInstr *MI, AsmPrinter &AP) {
  948 void AsmPrinter::emitCFIInstruction(const MachineInstr &MI) {
  973 void AsmPrinter::emitFrameAlloc(const MachineInstr &MI) {
 1055     for (auto &MI : MBB) {
 3034   for (const auto &MI : Pred->terminators()) {
 3179 void AsmPrinter::recordSled(MCSymbol *Sled, const MachineInstr &MI,

  171 static void EmitMSInlineAsmStr(const char *AsmStr, const MachineInstr *MI,
  283 static void EmitGCCInlineAsmStr(const char *AsmStr, const MachineInstr *MI,
  468 void AsmPrinter::EmitInlineAsm(const MachineInstr *MI) const {
  576 void AsmPrinter::PrintSpecial(const MachineInstr *MI, raw_ostream &OS,
  613 bool AsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
  655 bool AsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo,

 1218     const MachineInstr *DVInst = Entry.getInstr();
 1408     for (const auto &MI : MBB) {
 1409       if (!MI.isMetaInstruction() && !MI.getFlag(MachineInstr::FrameSetup) &&
 1427     for (const auto &MI : MBB) {
 2859     for (const auto &MI : MBB) {
 2883 void CodeViewDebug::beginInstruction(const MachineInstr *MI) {
 2888       MI->getFlag(MachineInstr::FrameSetup))
 2895     for (const auto &NextMI : *MI->getParent()) {

  464   void beginInstruction(const MachineInstr *MI) override;

   41 static Register isDescribedByReg(const MachineInstr &MI) {
   54                                        const MachineInstr &MI,
   74                                             const MachineInstr &MI) {
   92 void DbgLabelInstrMap::addInstr(InlinedEntity Label, const MachineInstr &MI) {
  137                               const MachineInstr &ClobberingInstr,
  159 static void handleNewDebugValue(InlinedEntity Var, const MachineInstr &DV,
  174       const MachineInstr &DV = *Entry.getInstr();
  241     for (const auto &MI : MBB) {
  286                    (!MI.getFlag(MachineInstr::FrameDestroy) &&
  287                    !MI.getFlag(MachineInstr::FrameSetup))) {

   31     const MachineInstr &Instruction) {
  116 MCSymbol *DebugHandlerBase::getLabelBeforeInsn(const MachineInstr *MI) {
  123 MCSymbol *DebugHandlerBase::getLabelAfterInsn(const MachineInstr *MI) {
  129 DebugHandlerBase::getFunctionLocalOffsetAfterInsn(const MachineInstr *MI) {
  270     const MachineInstr *MI = I.second;
  279 void DebugHandlerBase::beginInstruction(const MachineInstr *MI) {
  287   DenseMap<const MachineInstr *, MCSymbol *>::iterator I =
  317   DenseMap<const MachineInstr *, MCSymbol *>::iterator I =

  160   const MachineInstr &MI;
  165               DbgVariable &V, const MachineInstr &MI)

  232 static DbgValueLoc getDebugLocValue(const MachineInstr *MI) {
  254 void DbgVariable::initializeDbgValue(const MachineInstr *DbgValue) {
  540 static void collectCallSiteParameters(const MachineInstr *CallMI,
  709     for (const MachineInstr &MI : MBB.instrs()) {
 1299                             const MachineInstr *DbgValue,
 1300                             const MachineInstr *RangeEnd) {
 1313   const MachineInstr *LScopeBegin = LSRange.front().first;
 1319     if (Pred->getFlag(MachineInstr::FrameSetup))
 1338   const MachineInstr *LScopeEnd = LSRange.back().second;
 1391   const MachineInstr *StartDebugMI = nullptr;
 1392   const MachineInstr *EndMI = nullptr;
 1395     const MachineInstr *Instr = EI->getInstr();
 1538     const MachineInstr *MInsn = HistoryMapEntries.front().getInstr();
 1548       const auto *End =
 1590     const MachineInstr *MI = I.second;
 1633 void DwarfDebug::beginInstruction(const MachineInstr *MI) {
 1644   if (MI->isMetaInstruction() || MI->getFlag(MachineInstr::FrameSetup))
 1730     for (const auto &MI : MBB)
 1731       if (!MI.isMetaInstruction() && !MI.getFlag(MachineInstr::FrameSetup) &&

  163   void initializeDbgValue(const MachineInstr *DbgValue);
  613   void beginInstruction(const MachineInstr *MI) override;

  168 bool EHStreamer::callToNoUnwindFunction(const MachineInstr *MI) {
  244     for (const auto &MI : MBB) {

  130   void beginInstruction(const MachineInstr *MI) override {}
  135   static bool callToNoUnwindFunction(const MachineInstr *MI);

   48   void beginInstruction(const MachineInstr *MI) override {}

  457       const MachineInstr &MI = *MBBI;

  167     if (MI.isCall(MachineInstr::IgnoreBundle))
  231     for (const MachineInstr &I : BB)
  256 static unsigned HashMachineInstr(const MachineInstr &MI) {
  305 static bool countsAsInstruction(const MachineInstr &MI) {
  903   for (auto &MI : *MBB) {
 1347   for (MachineInstr &MI : MBB.instrs())
 1359   for (MachineInstr &MI : MBB.instrs())
 1491           MachineInstr &DuplicateDbg = *MBBIter;
 1587     MachineInstr &TailCall = *MBB->getFirstNonDebugInstr();
 2005     if (!TIB->isIdenticalTo(*FIB, MachineInstr::CheckKillDead))

   95   MachineBasicBlock *splitBlockBeforeInstr(MachineInstr &MI,
   98   bool isBlockInRange(const MachineInstr &MI, const MachineBasicBlock &BB) const;
  100   bool fixupConditionalBranch(MachineInstr &MI);
  101   bool fixupUnconditionalBranch(MachineInstr &MI);
  103   unsigned getInstrOffset(const MachineInstr &MI) const;
  170   for (const MachineInstr &MI : MBB)
  178 unsigned BranchRelaxation::getInstrOffset(const MachineInstr &MI) const {
  225 MachineBasicBlock *BranchRelaxation::splitBlockBeforeInstr(MachineInstr &MI,
  281   const MachineInstr &MI, const MachineBasicBlock &DestBB) const {
  300 bool BranchRelaxation::fixupConditionalBranch(MachineInstr &MI) {
  438 bool BranchRelaxation::fixupUnconditionalBranch(MachineInstr &MI) {
  513       MachineInstr &MI = *J;

   41   std::vector<std::pair<MachineInstr *, unsigned>> UndefReads;
   74   void processDefs(MachineInstr *MI);
   81   bool pickBestRegisterForUndef(MachineInstr *MI, unsigned OpIdx,
   86   bool shouldBreakDependence(MachineInstr *, unsigned OpIdx, unsigned Pref);
  107 bool BreakFalseDeps::pickBestRegisterForUndef(MachineInstr *MI, unsigned OpIdx,
  163 bool BreakFalseDeps::shouldBreakDependence(MachineInstr *MI, unsigned OpIdx,
  177 void BreakFalseDeps::processDefs(MachineInstr *MI) {
  229   MachineInstr *UndefMI = UndefReads.back().first;
  232   for (MachineInstr &I : make_range(MBB->rbegin(), MBB->rend())) {
  256   for (MachineInstr &MI : *MBB) {

   70   SmallVector<MachineInstr *, 8> SetjmpCalls;
   75     for (MachineInstr &MI : MBB) {
  108   for (MachineInstr *Setjmp : SetjmpCalls) {

  166   for (MachineInstr &MI : *MBBInfo.MBB) {

   51 static Register copyHint(const MachineInstr *mi, unsigned reg,
   99     MachineInstr *MI = LIS.getInstructionFromIndex(VNI->def);
  160   SmallPtrSet<MachineInstr*, 8> visited;
  209     MachineInstr *mi = &*(I++);

  106 void CriticalAntiDepBreaker::Observe(MachineInstr &MI, unsigned Count,
  165 void CriticalAntiDepBreaker::PrescanInstruction(MachineInstr &MI) {
  252 void CriticalAntiDepBreaker::ScanInstruction(MachineInstr &MI, unsigned Count) {
  360     MachineInstr *MI = RefOper->getParent();
  450   DenseMap<MachineInstr *, const SUnit *> MISUnitMap;
  478   MachineInstr *CriticalPathMI = CriticalPathSU->getInstr();
  529     MachineInstr &MI = *--I;

   90     void Observe(MachineInstr &MI, unsigned Count,
   97     void PrescanInstruction(MachineInstr &MI);
   98     void ScanInstruction(MachineInstr &MI, unsigned Count);

  121 bool DFAPacketizer::canReserveResources(MachineInstr &MI) {
  128 void DFAPacketizer::reserveResources(MachineInstr &MI) {
  221     MachineInstr &MIFirst = *CurrentPacketMIs.front();
  260     MachineInstr &MI = *BeginItr;
  347 bool VLIWPacketizerList::alias(const MachineInstr &MI1,
  348                                const MachineInstr &MI2,

   49     bool isDead(const MachineInstr *MI) const;
   58 bool DeadMachineInstructionElim::isDead(const MachineInstr *MI) const {
   84         for (const MachineInstr &Use : MRI->use_nodbg_instructions(Reg)) {
  125       MachineInstr *MI = &*MII++;

   80   void transferUsedLanesStep(const MachineInstr &MI, LaneBitmask UsedLanes);
   96   LaneBitmask transferUsedLanes(const MachineInstr &MI, LaneBitmask UsedLanes,
  137 static bool lowersToCopies(const MachineInstr &MI) {
  153                         const MachineInstr &MI,
  219 void DetectDeadLanes::transferUsedLanesStep(const MachineInstr &MI,
  229 LaneBitmask DetectDeadLanes::transferUsedLanes(const MachineInstr &MI,
  280   const MachineInstr &MI = *Use.getParent();
  312   const MachineInstr &MI = *Def.getParent();
  359   const MachineInstr &DefMI = *Def.getParent();
  393           const MachineInstr &MODefMI = *MODef.getParent();
  423     const MachineInstr &UseMI = *MO.getParent();
  469   const MachineInstr &MI = *MO.getParent();
  515     const MachineInstr &MI = *Def.getParent();
  535     for (MachineInstr &MI : MBB) {

  111     MachineInstr *PHI;
  116     PHIInfo(MachineInstr *phi)
  128   SmallPtrSet<MachineInstr*, 8> InsertAfter;
  150   bool InstrDependenciesAllowIfConv(MachineInstr *I);
  254 bool SSAIfConv::InstrDependenciesAllowIfConv(MachineInstr *I) {
  271     MachineInstr *DefMI = MRI->getVRegDef(Reg);
  987     for (MachineInstr &I : IfBlock) {
 1001   for (MachineInstr &I : *IfConv.TBB) {
 1007   for (MachineInstr &I : *IfConv.FBB) {

  222 bool ExecutionDomainFix::visitInstr(MachineInstr *MI) {
  235 void ExecutionDomainFix::processDefs(MachineInstr *MI, bool Kill) {
  257 void ExecutionDomainFix::visitHardInstr(MachineInstr *mi, unsigned domain) {
  282 void ExecutionDomainFix::visitSoftInstr(MachineInstr *mi, unsigned mask) {
  402   for (MachineInstr &MI : *TraversedMBB.MBB) {

   50   bool LowerSubregToReg(MachineInstr *MI);
   51   bool LowerCopy(MachineInstr *MI);
   53   void TransferImplicitOperands(MachineInstr *MI);
   66 void ExpandPostRA::TransferImplicitOperands(MachineInstr *MI) {
   75 bool ExpandPostRA::LowerSubregToReg(MachineInstr *MI) {
  134 bool ExpandPostRA::LowerCopy(MachineInstr *MI) {
  194       MachineInstr &MI = *mi;

   56       MachineInstr &MI = *MBBI++;

  134 UniqueMachineInstr *GISelCSEInfo::getUniqueInstrForMI(const MachineInstr *MI) {
  140 void GISelCSEInfo::insertInstr(MachineInstr *MI, void *InsertPos) {
  148 MachineInstr *GISelCSEInfo::getMachineInstrIfExists(FoldingSetNodeID &ID,
  169 void GISelCSEInfo::recordNewInstruction(MachineInstr *MI) {
  176 void GISelCSEInfo::handleRecordedInst(MachineInstr *MI) {
  198 void GISelCSEInfo::handleRemoveInst(MachineInstr *MI) {
  208     auto *MI = TemporaryInsts.pop_back_val();
  221 void GISelCSEInfo::erasingInstr(MachineInstr &MI) { handleRemoveInst(&MI); }
  222 void GISelCSEInfo::createdInstr(MachineInstr &MI) { recordNewInstruction(&MI); }
  223 void GISelCSEInfo::changingInstr(MachineInstr &MI) {
  228 void GISelCSEInfo::changedInstr(MachineInstr &MI) { changingInstr(MI); }
  235     for (MachineInstr &MI : MBB) {
  268 GISelInstProfileBuilder::addNodeID(const MachineInstr *MI) const {

   39   MachineInstr *MI =
  109   MachineInstr *MIBInstr = MIB;

   56   SmallPtrSet<const MachineInstr *, 4> CreatedInstrs;
   64   void erasingInstr(MachineInstr &MI) override {
   68   void createdInstr(MachineInstr &MI) override {
   73   void changingInstr(MachineInstr &MI) override {
   77   void changedInstr(MachineInstr &MI) override {
  136         MachineInstr *CurMI = &*MII;
  150       MachineInstr *CurrInst = WorkList.pop_back_val();

   65 bool CombinerHelper::tryCombineCopy(MachineInstr &MI) {
   72 bool CombinerHelper::matchCombineCopy(MachineInstr &MI) {
   85 void CombinerHelper::applyCombineCopy(MachineInstr &MI) {
   92 bool CombinerHelper::tryCombineConcatVectors(MachineInstr &MI) {
  102 bool CombinerHelper::matchCombineConcatVectors(MachineInstr &MI, bool &IsUndef,
  107   MachineInstr *Undef = nullptr;
  117     MachineInstr *Def = MRI.getVRegDef(Reg);
  155     MachineInstr &MI, bool IsUndef, const ArrayRef<Register> Ops) {
  176 bool CombinerHelper::tryCombineShuffleVector(MachineInstr &MI) {
  185 bool CombinerHelper::matchCombineShuffleVector(MachineInstr &MI,
  251 void CombinerHelper::applyCombineShuffleVector(MachineInstr &MI,
  270                                   MachineInstr *MIForCandidate) {
  321     MachineIRBuilder &Builder, MachineInstr &DefMI, MachineOperand &UseMO,
  325   MachineInstr &UseMI = *UseMO.getParent();
  348 bool CombinerHelper::tryCombineExtendingLoads(MachineInstr &MI) {
  357 bool CombinerHelper::matchCombineExtendingLoads(MachineInstr &MI,
  402   for (auto &UseMI : MRI.use_instructions(LoadValue.getReg())) {
  423 void CombinerHelper::applyCombineExtendingLoads(MachineInstr &MI,
  430   DenseMap<MachineBasicBlock *, MachineInstr *> EmittedInsns;
  434     MachineInstr *PreviouslyEmitted = EmittedInsns.lookup(InsertIntoBB);
  444     MachineInstr *NewMI = Builder.buildTrunc(NewDstReg, ChosenDstReg);
  464     MachineInstr *UseMI = UseMO->getParent();
  533 bool CombinerHelper::isPredecessor(MachineInstr &DefMI, MachineInstr &UseMI) {
  533 bool CombinerHelper::isPredecessor(MachineInstr &DefMI, MachineInstr &UseMI) {
  546 bool CombinerHelper::dominates(MachineInstr &DefMI, MachineInstr &UseMI) {
  546 bool CombinerHelper::dominates(MachineInstr &DefMI, MachineInstr &UseMI) {
  555 bool CombinerHelper::findPostIndexCandidate(MachineInstr &MI, Register &Addr,
  567   MachineInstr *BaseDef = MRI.getUniqueVRegDef(Base);
  573   for (auto &Use : MRI.use_instructions(Base)) {
  588     MachineInstr *OffsetDef = MRI.getUniqueVRegDef(Offset);
  600     for (auto &GEPUse : MRI.use_instructions(Use.getOperand(0).getReg())) {
  622 bool CombinerHelper::findPreIndexCandidate(MachineInstr &MI, Register &Addr,
  634   MachineInstr *AddrDef = getOpcodeDef(TargetOpcode::G_GEP, Addr, MRI);
  649   MachineInstr *BaseDef = getDefIgnoringCopies(Base, MRI);
  673   for (auto &UseMI : MRI.use_instructions(Addr)) {
  683 bool CombinerHelper::tryCombineIndexedLoadStore(MachineInstr &MI) {
  714   MachineInstr &AddrDef = *MRI.getUniqueVRegDef(Addr);
  735 bool CombinerHelper::matchElideBrByInvertingCond(MachineInstr &MI) {
  760   MachineInstr *BrCond = &*std::prev(BrIt);
  768   MachineInstr *CmpMI = MRI.getVRegDef(BrCond->getOperand(0).getReg());
  775 bool CombinerHelper::tryElideBrByInvertingCond(MachineInstr &MI) {
  782 void CombinerHelper::applyElideBrByInvertingCond(MachineInstr &MI) {
  785   MachineInstr *BrCond = &*std::prev(BrIt);
  786   MachineInstr *CmpMI = MRI.getVRegDef(BrCond->getOperand(0).getReg());
  919 bool CombinerHelper::optimizeMemset(MachineInstr &MI, Register Dst, Register Val,
  933   MachineInstr *FIDef = getOpcodeDef(TargetOpcode::G_FRAME_INDEX, Dst, MRI);
 1032 bool CombinerHelper::optimizeMemcpy(MachineInstr &MI, Register Dst,
 1048   MachineInstr *FIDef = getOpcodeDef(TargetOpcode::G_FRAME_INDEX, Dst, MRI);
 1140 bool CombinerHelper::optimizeMemmove(MachineInstr &MI, Register Dst,
 1156   MachineInstr *FIDef = getOpcodeDef(TargetOpcode::G_FRAME_INDEX, Dst, MRI);
 1247 bool CombinerHelper::tryCombineMemCpyFamily(MachineInstr &MI, unsigned MaxLen) {
 1298 bool CombinerHelper::tryCombine(MachineInstr &MI) {

   20   for (auto &ChangingMI : MRI.use_instructions(Reg)) {
   27   for (auto *ChangedMI : ChangingAllUsesOfReg)

   43 MaybeAlign GISelKnownBits::inferPtrAlignment(const MachineInstr &MI) {
   54   const MachineInstr &MI = *MRI.getVRegDef(R);
   65 KnownBits GISelKnownBits::getKnownBits(MachineInstr &MI) {
   93   MachineInstr &MI = *MRI.getVRegDef(R);

  128   void erasingInstr(MachineInstr &MI) override {}
  129   void changingInstr(MachineInstr &MI) override {}
  130   void changedInstr(MachineInstr &MI) override {}
  132   void createdInstr(MachineInstr &MI) override {
  299     Flags = MachineInstr::copyFlagsFromInstruction(I);
  315       Flags = MachineInstr::copyFlagsFromInstruction(I);
  330     Flags = MachineInstr::copyFlagsFromInstruction(I);
  356                           MachineInstr::copyFlagsFromInstruction(*CI));
 1011     Flags = MachineInstr::copyFlagsFromInstruction(*Cmp);
 1274                         MachineInstr::copyFlagsFromInstruction(CI));
 1419                             MachineInstr::copyFlagsFromInstruction(CI));
 1423                                         MachineInstr::copyFlagsFromInstruction(CI));
 1425                             MachineInstr::copyFlagsFromInstruction(CI));
 1832                                       MachineInstr::NoUWrap);
 1930   SmallVector<MachineInstr *, 4> Insts;
 2055     ArrayRef<MachineInstr *> ComponentPHIs = Phi.second;

   93     if (const MachineInstr *MI = machineFunctionIsIllegal(MF)) {
  117       MachineInstr &MI = *MII;
  161       MachineInstr &MI = *MII;
  192     MachineInstr *MI = nullptr;
  235     for (const auto &MI : MBB) {

   37     MachineInstr &I, unsigned OpIdx, const TargetRegisterClass &RC,
   62   MachineInstr *RootI = MRI.getVRegDef(Root.getReg());
   67   MachineInstr *RHSI = MRI.getVRegDef(RHS.getReg());
   74 bool InstructionSelector::isObviouslySafeToFold(MachineInstr &MI,
   75                                                 MachineInstr &IntoMI) const {

   66 static bool isArtifact(const MachineInstr &MI) {
   90   SmallVector<MachineInstr *, 4> NewMIs;
   97   void createdOrChangedInstr(MachineInstr &MI) {
  109   void createdInstr(MachineInstr &MI) override {
  123   void erasingInstr(MachineInstr &MI) override {
  129   void changingInstr(MachineInstr &MI) override {
  133   void changedInstr(MachineInstr &MI) override {
  167     for (MachineInstr &MI : *MBB) {
  215   SmallVector<MachineInstr *, 128> RetryList;
  220       MachineInstr &MI = *InstList.pop_back_val();
  253         MachineInstr *MI = *RetryList.begin();
  259       MachineInstr &MI = *ArtifactList.pop_back_val();
  267       SmallVector<MachineInstr *, 4> DeadInstructions;
  271         for (auto *DeadMI : DeadInstructions) {

   83 LegalizerHelper::legalizeInstrStep(MachineInstr &MI) {
  332 static bool isLibCallInTailPosition(MachineInstr &MI) {
  352   MachineInstr *Next = MI.getNextNode();
  380 simpleLibcall(MachineInstr &MI, MachineIRBuilder &MIRBuilder, unsigned Size,
  393                        MachineInstr &MI) {
  482 conversionLibcall(MachineInstr &MI, MachineIRBuilder &MIRBuilder, Type *ToType,
  490 LegalizerHelper::libcall(MachineInstr &MI) {
  597 LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI,
 1081 void LegalizerHelper::widenScalarSrc(MachineInstr &MI, LLT WideTy,
 1088 void LegalizerHelper::narrowScalarSrc(MachineInstr &MI, LLT NarrowTy,
 1096 void LegalizerHelper::widenScalarDst(MachineInstr &MI, LLT WideTy,
 1105 void LegalizerHelper::narrowScalarDst(MachineInstr &MI, LLT NarrowTy,
 1114 void LegalizerHelper::moreElementsVectorDst(MachineInstr &MI, LLT WideTy,
 1123 void LegalizerHelper::moreElementsVectorSrc(MachineInstr &MI, LLT MoreTy,
 1154 LegalizerHelper::widenScalarMergeValues(MachineInstr &MI, unsigned TypeIdx,
 1276 LegalizerHelper::widenScalarUnmergeValues(MachineInstr &MI, unsigned TypeIdx,
 1316 LegalizerHelper::widenScalarExtract(MachineInstr &MI, unsigned TypeIdx,
 1395 LegalizerHelper::widenScalarInsert(MachineInstr &MI, unsigned TypeIdx,
 1407 LegalizerHelper::widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy) {
 1909 LegalizerHelper::lower(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
 2286     MachineInstr &MI, unsigned TypeIdx, LLT NarrowTy) {
 2314 LegalizerHelper::fewerElementsVectorBasic(MachineInstr &MI, unsigned TypeIdx,
 2420   MachineInstr &MI, unsigned TypeIdx, LLT NarrowTyArg) {
 2503 LegalizerHelper::fewerElementsVectorCasts(MachineInstr &MI, unsigned TypeIdx,
 2534     MachineInstr *NewInst = MIRBuilder.buildInstr(MI.getOpcode())
 2552 LegalizerHelper::fewerElementsVectorCmp(MachineInstr &MI, unsigned TypeIdx,
 2603       MachineInstr *NewCmp
 2619 LegalizerHelper::fewerElementsVectorSelect(MachineInstr &MI, unsigned TypeIdx,
 2691 LegalizerHelper::fewerElementsVectorPhi(MachineInstr &MI, unsigned TypeIdx,
 2758 LegalizerHelper::fewerElementsVectorUnmergeValues(MachineInstr &MI,
 2798 LegalizerHelper::fewerElementsVectorBuildVector(MachineInstr &MI,
 2857 LegalizerHelper::reduceLoadStoreWidth(MachineInstr &MI, unsigned TypeIdx,
 2944 LegalizerHelper::fewerElementsVector(MachineInstr &MI, unsigned TypeIdx,
 3042 LegalizerHelper::narrowScalarShiftByConstant(MachineInstr &MI, const APInt &Amt,
 3131 LegalizerHelper::narrowScalarShift(MachineInstr &MI, unsigned TypeIdx,
 3158   if (const MachineInstr *KShiftAmt =
 3241 LegalizerHelper::moreElementsVectorPhi(MachineInstr &MI, unsigned TypeIdx,
 3260 LegalizerHelper::moreElementsVector(MachineInstr &MI, unsigned TypeIdx,
 3413 LegalizerHelper::narrowScalarMul(MachineInstr &MI, LLT NarrowTy) {
 3448 LegalizerHelper::narrowScalarExtract(MachineInstr &MI, unsigned TypeIdx,
 3513 LegalizerHelper::narrowScalarInsert(MachineInstr &MI, unsigned TypeIdx,
 3588 LegalizerHelper::narrowScalarBasic(MachineInstr &MI, unsigned TypeIdx,
 3629 LegalizerHelper::narrowScalarSelect(MachineInstr &MI, unsigned TypeIdx,
 3675 LegalizerHelper::lowerBitCount(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
 3790 LegalizerHelper::lowerU64ToF32BitOps(MachineInstr &MI) {
 3846 LegalizerHelper::lowerUITOFP(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
 3867 LegalizerHelper::lowerSITOFP(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
 3905 LegalizerHelper::lowerFPTOUI(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
 3962 LegalizerHelper::lowerMinMax(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
 3978 LegalizerHelper::lowerFCopySign(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
 3996   MachineInstr *Or;
 4026 LegalizerHelper::lowerFMinNumMaxNum(MachineInstr &MI) {
 4035   if (!MI.getFlag(MachineInstr::FmNoNans)) {
 4056 LegalizerHelper::LegalizeResult LegalizerHelper::lowerFMad(MachineInstr &MI) {
 4070 LegalizerHelper::lowerUnmergeValues(MachineInstr &MI) {
 4103 LegalizerHelper::lowerShuffleVector(MachineInstr &MI) {
 4162 LegalizerHelper::lowerDynStackAlloc(MachineInstr &MI) {
 4197 LegalizerHelper::lowerExtract(MachineInstr &MI) {
 4229 LegalizerHelper::LegalizeResult LegalizerHelper::lowerInsert(MachineInstr &MI) {
 4269 LegalizerHelper::lowerSADDO_SSUBO(MachineInstr &MI) {

  390 static LLT getTypeFromTypeIdx(const MachineInstr &MI,
  476 LegalizerInfo::getAction(const MachineInstr &MI,
  507 bool LegalizerInfo::isLegal(const MachineInstr &MI,
  512 bool LegalizerInfo::isLegalOrCustom(const MachineInstr &MI,
  520 bool LegalizerInfo::legalizeCustom(MachineInstr &MI, MachineRegisterInfo &MRI,
  682 bool LegalizerInfo::legalizeIntrinsic(MachineInstr &MI,
  737 const MachineInstr *llvm::machineFunctionIsIllegal(const MachineFunction &MF) {
  741       for (const MachineInstr &MI : MBB)

   38 bool Localizer::shouldLocalize(const MachineInstr &MI) {
   98 bool Localizer::isLocalUse(MachineOperand &MOUse, const MachineInstr &Def,
  100   MachineInstr &MIUse = *MOUse.getParent();
  118     MachineInstr &MI = *RI;
  144         MachineInstr *LocalizedMI = MF.CloneMachineInstr(&MI);
  146         MachineInstr &UseMI = *MOUse.getParent();
  179   for (MachineInstr *MI : LocalizedInstrs) {
  183     SmallPtrSet<MachineInstr *, 32> Users;
  184     for (MachineInstr &UseMI : MRI->use_nodbg_instructions(Reg)) {

   43 void MachineIRBuilder::setInstr(MachineInstr &MI) {
   59 void MachineIRBuilder::recordInsertion(MachineInstr *InsertedInstr) const {

  144   MachineInstr *MI;
  217   std::unique_ptr<MachineInstr *[]> NewInstrs(
  218       new MachineInstr *[RepairPt.getNumInsertPoints()]);
  222     MachineInstr *CurMI;
  289     MachineInstr &MI, RegisterBankInfo::InstructionMappings &PossibleMappings,
  325   const MachineInstr &MI = *MO.getParent();
  415     const MachineInstr *Next = MI.getNextNode();
  442     MachineInstr &MI, const RegisterBankInfo::InstructionMapping &InstrMapping,
  581     MachineInstr &MI, const RegisterBankInfo::InstructionMapping &InstrMapping,
  622 bool RegBankSelect::assignInstr(MachineInstr &MI) {
  669     if (const MachineInstr *MI = machineFunctionIsIllegal(MF)) {
  688       MachineInstr &MI = *MII++;
  723     MachineInstr &MI, unsigned OpIdx, const TargetRegisterInfo &TRI, Pass &P,
  816 void RegBankSelect::RepairingPlacement::addInsertPoint(MachineInstr &MI,
  838 RegBankSelect::InstrInsertPoint::InstrInsertPoint(MachineInstr &Instr,

  110     const MachineInstr &MI, unsigned OpIdx, const TargetInstrInfo &TII,
  150 static bool isCopyLike(const MachineInstr &MI) {
  156 RegisterBankInfo::getInstrMappingImpl(const MachineInstr &MI) const {
  400 RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
  434   MachineInstr &MI = OpdMapper.getMI();
  591     const MachineInstr &MI) const {
  647     MachineInstr &MI, const InstructionMapping &InstrMapping,

   43     const RegisterBankInfo &RBI, MachineInstr &InsertPt,
   73     const RegisterBankInfo &RBI, MachineInstr &InsertPt, const MCInstrDesc &II,
  111 bool llvm::constrainSelectedInstRegOperands(MachineInstr &I,
  158 bool llvm::isTriviallyDead(const MachineInstr &MI,
  197                               const MachineInstr &MI) {
  222   MachineInstr *MI;
  297   MachineInstr *MI = MRI.getVRegDef(VReg);
  303 llvm::MachineInstr *llvm::getDefIgnoringCopies(Register Reg,
  305   auto *DefMI = MRI.getVRegDef(Reg);
  319 llvm::MachineInstr *llvm::getOpcodeDef(unsigned Opcode, Register Reg,
  321   MachineInstr *DefMI = getDefIgnoringCopies(Reg, MRI);
  391   const MachineInstr *DefMI = MRI.getVRegDef(Val);
  395   if (DefMI->getFlag(MachineInstr::FmNoNans))

  308         for (auto &I : make_range(TBBInfo.BB->begin(), TIB)) {
  312         for (auto &I : make_range(FBBInfo.BB->begin(), FIB)) {
  321         for (auto &I : make_range(TIE, TBBInfo.BB->end())) {
  330         for (auto &I : make_range(FIE, FBBInfo.BB->end())) {
  339         for (auto &I : CommBB.terminators()) {
  352         for (auto &I : make_range(TIB, TIE)) {
  358         for (auto &I : make_range(FIB, FIE)) {
 1066   for (MachineInstr &MI : make_range(Begin, End)) {
 1474 static void UpdatePredRedefs(MachineInstr &MI, LivePhysRegs &Redefs) {
 1494     MachineInstr *OpMI = Op.getParent();
 1847     if (DI2->isCall(MachineInstr::IgnoreBundle))
 1858     for (const MachineInstr &MI : make_range(MBB1.begin(), DI1)) {
 1896     if (DI1->isCall(MachineInstr::IgnoreBundle))
 1941     for (const MachineInstr &FI : make_range(MBB2.begin(), DI2)) {
 2107 static bool MaySpeculate(const MachineInstr &MI,
 2134   for (MachineInstr &I : make_range(BBI.BB->begin(), E)) {
 2177   for (MachineInstr &I : FromMBB) {
 2182     MachineInstr *MI = MF.CloneMachineInstr(&I);
 2184     if (MI->isCall(MachineInstr::IgnoreBundle))

   82   static bool canHandle(const MachineInstr *MI);
   87   bool canReorder(const MachineInstr *A, const MachineInstr *B);
   87   bool canReorder(const MachineInstr *A, const MachineInstr *B);
  100     Optional<ArrayRef<MachineInstr *>::iterator> PotentialDependence;
  104         Optional<ArrayRef<MachineInstr *>::iterator> PotentialDependence)
  116   DependenceResult computeDependence(const MachineInstr *MI,
  117                                      ArrayRef<MachineInstr *> Block);
  122     MachineInstr *MemOperation;
  125     MachineInstr *CheckOperation;
  138     MachineInstr *OnlyDependency;
  141     explicit NullCheck(MachineInstr *memOperation, MachineInstr *checkOperation,
  141     explicit NullCheck(MachineInstr *memOperation, MachineInstr *checkOperation,
  145                        MachineInstr *onlyDependency)
  150     MachineInstr *getMemOperation() const { return MemOperation; }
  152     MachineInstr *getCheckOperation() const { return CheckOperation; }
  160     MachineInstr *getOnlyDependency() const { return OnlyDependency; }
  170   MachineInstr *insertFaultingInstr(MachineInstr *MI, MachineBasicBlock *MBB,
  170   MachineInstr *insertFaultingInstr(MachineInstr *MI, MachineBasicBlock *MBB,
  183   AliasResult areMemoryOpsAliased(const MachineInstr &MI,
  184                                   const MachineInstr *PrevMI) const;
  198   SuitabilityResult isSuitableMemoryOp(const MachineInstr &MI,
  200                                        ArrayRef<MachineInstr *> PrevInsts);
  205   bool canHoistInst(MachineInstr *FaultingMI, unsigned PointerReg,
  206                     ArrayRef<MachineInstr *> InstsSeenSoFar,
  207                     MachineBasicBlock *NullSucc, MachineInstr *&Dependence);
  231 bool ImplicitNullChecks::canHandle(const MachineInstr *MI) {
  246 ImplicitNullChecks::computeDependence(const MachineInstr *MI,
  247                                       ArrayRef<MachineInstr *> Block) {
  251   Optional<ArrayRef<MachineInstr *>::iterator> Dep;
  269 bool ImplicitNullChecks::canReorder(const MachineInstr *A,
  270                                     const MachineInstr *B) {
  324 ImplicitNullChecks::areMemoryOpsAliased(const MachineInstr &MI,
  325                                         const MachineInstr *PrevMI) const {
  362 ImplicitNullChecks::isSuitableMemoryOp(const MachineInstr &MI,
  364                                        ArrayRef<MachineInstr *> PrevInsts) {
  379   for (auto *PrevMI : PrevInsts) {
  389 bool ImplicitNullChecks::canHoistInst(MachineInstr *FaultingMI,
  391                                       ArrayRef<MachineInstr *> InstsSeenSoFar,
  393                                       MachineInstr *&Dependence) {
  404   auto *DependenceMI = *DependenceItr;
  582   SmallVector<MachineInstr *, 8> InstsSeenSoFar;
  584   for (auto &MI : *NotNullSucc) {
  588     MachineInstr *Dependence;
  615 MachineInstr *ImplicitNullChecks::insertFaultingInstr(
  616     MachineInstr *MI, MachineBasicBlock *MBB, MachineBasicBlock *HandlerMBB) {
  673     if (auto *DepMI = NC.getOnlyDependency()) {
  682     MachineInstr *FaultingInstr = insertFaultingInstr(
  698     if (auto *DepMI = NC.getOnlyDependency()) {

  110       MapVector<std::pair<int, VNInfo *>, SmallPtrSet<MachineInstr *, 16>>;
  122       SmallPtrSet<MachineInstr *, 16> &Spills,
  127       MachineBasicBlock *Root, SmallPtrSet<MachineInstr *, 16> &Spills,
  134                       SmallPtrSet<MachineInstr *, 16> &Spills,
  151   void addToMergeableSpills(MachineInstr &Spill, int StackSlot,
  153   bool rmFromMergeableSpills(MachineInstr &Spill, int StackSlot);
  182   SmallPtrSet<MachineInstr*, 8> SnippetCopies;
  188   SmallVector<MachineInstr*, 8> DeadDefs;
  217   bool hoistSpillInsideBB(LiveInterval &SpillLI, MachineInstr &CopyMI);
  221   bool canGuaranteeAssignmentAfterRemat(unsigned VReg, MachineInstr &MI);
  222   bool reMaterializeFor(LiveInterval &, MachineInstr &MI);
  225   bool coalesceStackAccess(MachineInstr *MI, unsigned Reg);
  226   bool foldMemoryOperand(ArrayRef<std::pair<MachineInstr *, unsigned>>,
  227                          MachineInstr *LoadMI = nullptr);
  261 static unsigned isFullCopyOf(const MachineInstr &MI, unsigned Reg) {
  287   MachineInstr *UseMI = nullptr;
  293     MachineInstr &MI = *RI++;
  332     MachineInstr &MI = *RI++;
  372                                        MachineInstr &CopyMI) {
  406     MachineInstr *DefMI = LIS.getInstructionFromIndex(SrcVNI->def);
  450       MachineInstr &MI = *UI++;
  509     MachineInstr *MI = LIS.getInstructionFromIndex(VNI->def);
  521                                                      MachineInstr &MI) {
  543 bool InlineSpiller::reMaterializeFor(LiveInterval &VirtReg, MachineInstr &MI) {
  545   SmallVector<std::pair<MachineInstr *, unsigned>, 8> Ops;
  614   auto *NewMI = LIS.getInstructionFromIndex(DefIdx);
  650       MachineInstr &MI = *RegI++;
  673       MachineInstr *MI = LIS.getInstructionFromIndex(VNI->def);
  718 bool InlineSpiller::coalesceStackAccess(MachineInstr *MI, unsigned Reg) {
  789 foldMemoryOperand(ArrayRef<std::pair<MachineInstr *, unsigned>> Ops,
  790                   MachineInstr *LoadMI) {
  794   MachineInstr *MI = Ops.front().first;
  837   MachineInstr *FoldMI =
  875   for (MachineInstr &MI : MIS)
  922 static bool isFullUndefDef(const MachineInstr &Def) {
  970     MachineInstr *MI = &*(RegI++);
  994     SmallVector<std::pair<MachineInstr*, unsigned>, 8> Ops;
 1096       MachineInstr &MI = *(RI++);
 1141 void HoistSpillHelper::addToMergeableSpills(MachineInstr &Spill, int StackSlot,
 1160 bool HoistSpillHelper::rmFromMergeableSpills(MachineInstr &Spill,
 1199     SmallPtrSet<MachineInstr *, 16> &Spills,
 1208     MachineInstr *PrevSpill = SpillBBToSpill[Node];
 1212       MachineInstr *SpillToRm = (CIdx > PIdx) ? CurrentSpill : PrevSpill;
 1213       MachineInstr *SpillToKeep = (CIdx > PIdx) ? PrevSpill : CurrentSpill;
 1231     MachineBasicBlock *Root, SmallPtrSet<MachineInstr *, 16> &Spills,
 1257     MachineInstr *SpillToRm = nullptr;
 1319     SmallPtrSet<MachineInstr *, 16> &Spills,
 1331   DenseMap<MachineDomTreeNode *, MachineInstr *> SpillBBToSpill;
 1410           MachineInstr *SpillToRm = SpillBBToSpill[SpillBB];
 1471     SmallPtrSet<MachineInstr *, 16> &EqValSpills = Ent.second;
 1484     SmallVector<MachineInstr *, 16> SpillsToRm;

   58   DenseMap<const MachineInstr *, LexicalScope *> MI2ScopeMap;
   70     DenseMap<const MachineInstr *, LexicalScope *> &MI2ScopeMap) {
   73     const MachineInstr *RangeBeginMI = nullptr;
   74     const MachineInstr *PrevMI = nullptr;
   76     for (const auto &MInsn : MBB) {
  260     DenseMap<const MachineInstr *, LexicalScope *> &MI2ScopeMap) {
  312   for (auto &I : *MBB) {

   84 static Register isDbgValueDescribedByReg(const MachineInstr &MI) {
  150     DebugVariable(const MachineInstr &MI)
  200     const MachineInstr &MI;
  222     VarLoc(const MachineInstr &MI, LexicalScopes &LS)
  248     static VarLoc CreateEntryLoc(const MachineInstr &MI, LexicalScopes &LS,
  258     static VarLoc CreateCopyLoc(const MachineInstr &MI, LexicalScopes &LS,
  268     static VarLoc CreateSpillLoc(const MachineInstr &MI, unsigned SpillBase,
  281     MachineInstr *BuildDbgValue(MachineFunction &MF) const {
  372   using DebugParamMap = SmallDenseMap<const DILocalVariable *, MachineInstr *>;
  377     MachineInstr *TransferInst; /// Instruction where this transfer occurs.
  448   bool isSpillInstruction(const MachineInstr &MI, MachineFunction *MF);
  456   bool isLocationSpill(const MachineInstr &MI, MachineFunction *MF,
  461   Optional<VarLoc::SpillLoc> isRestoreInstruction(const MachineInstr &MI,
  466   VarLoc::SpillLoc extractSpillBaseRegAndOffset(const MachineInstr &MI);
  467   void insertTransferDebugPair(MachineInstr &MI, OpenRangesSet &OpenRanges,
  472   void transferDebugValue(const MachineInstr &MI, OpenRangesSet &OpenRanges,
  474   void transferSpillOrRestoreInst(MachineInstr &MI, OpenRangesSet &OpenRanges,
  476   void emitEntryValues(MachineInstr &MI, OpenRangesSet &OpenRanges,
  480   void transferRegisterCopy(MachineInstr &MI, OpenRangesSet &OpenRanges,
  482   void transferRegisterDef(MachineInstr &MI, OpenRangesSet &OpenRanges,
  488   void process(MachineInstr &MI, OpenRangesSet &OpenRanges,
  492   void accumulateFragmentMap(MachineInstr &MI, VarToFragments &SeenFragments,
  653 LiveDebugValues::extractSpillBaseRegAndOffset(const MachineInstr &MI) {
  669 void LiveDebugValues::transferDebugValue(const MachineInstr &MI,
  702 void LiveDebugValues::emitEntryValues(MachineInstr &MI,
  712     const MachineInstr *CurrDebugInstr = &VarLocIDs[ID].MI;
  737     MachineInstr &MI, OpenRangesSet &OpenRanges, TransferMap &Transfers,
  740   const MachineInstr *DebugInstr = &VarLocIDs[OldVarID].MI;
  805     MachineInstr &MI, OpenRangesSet &OpenRanges, VarLocMap &VarLocIDs,
  845 bool LiveDebugValues::isSpillInstruction(const MachineInstr &MI,
  858 bool LiveDebugValues::isLocationSpill(const MachineInstr &MI,
  899 LiveDebugValues::isRestoreInstruction(const MachineInstr &MI,
  920 void LiveDebugValues::transferSpillOrRestoreInst(MachineInstr &MI,
  996 void LiveDebugValues::transferRegisterCopy(MachineInstr &MI,
 1066 void LiveDebugValues::accumulateFragmentMap(MachineInstr &MI,
 1117 void LiveDebugValues::process(MachineInstr &MI, OpenRangesSet &OpenRanges,
 1243       MachineInstr *MI = DiffIt.BuildDbgValue(*MBB.getParent());
 1318   for (auto &MI : First_MBB)
 1329     for (auto &MI : MBB) {
 1380         for (auto &MI : *MBB)
 1408     MachineInstr *MI = VL.BuildDbgValue(MF);

  425   bool handleDebugValue(MachineInstr &MI, SlotIndex Idx);
  433   bool handleDebugLabel(MachineInstr &MI, SlotIndex Idx);
  599 bool LDVImpl::handleDebugValue(MachineInstr &MI, SlotIndex Idx) {
  658 bool LDVImpl::handleDebugLabel(MachineInstr &MI, SlotIndex Idx) {
  774     MachineInstr *MI = MO.getParent();
  822       MachineInstr *CopyMI = LIS.getInstructionFromIndex(DstVNI->def);
 1244   MachineInstr *MI;

  900     const MachineInstr *MI = Indexes.getInstructionFromIndex(VNI->def);
  983       const MachineInstr &MI = *MO.getParent();
 1358     MachineInstr *MI = RI->getParent();

  225     for (const MachineInstr &MI : MBB) {
  442                                  SmallVectorImpl<MachineInstr*> *dead) {
  462   for (MachineInstr &UseMI : MRI->reg_instructions(Reg)) {
  501                                       SmallVectorImpl<MachineInstr*> *dead) {
  515         MachineInstr *MI = getInstructionFromIndex(Def);
  530       MachineInstr *MI = getInstructionFromIndex(Def);
  563     MachineInstr *UseMI = MO.getParent();
  723       MachineInstr *MI = getInstructionFromIndex(RI->end);
  855                                     const MachineInstr &MI) {
  868 LiveIntervals::addSegmentToEndOfBlock(unsigned reg, MachineInstr &startInst) {
  972   void updateAllRanges(MachineInstr *MI) {
 1063       if (MachineInstr *KillMI = LIS.getInstructionFromIndex(OldIdxIn->end))
 1364         if (MachineInstr *KillMI = LIS.getInstructionFromIndex(NewIdx))
 1412         const MachineInstr &MI = *MO.getParent();
 1429     if (MachineInstr *MI = Indexes->getInstructionFromIndex(
 1456 void LiveIntervals::handleMove(MachineInstr &MI, bool UpdateFlags) {
 1472 void LiveIntervals::handleMoveIntoBundle(MachineInstr &MI,
 1473                                          MachineInstr &BundleStart,
 1500     MachineInstr &MI = *I;
 1510     for (MachineInstr::mop_iterator OI = MI.operands_begin(),
 1597     MachineInstr &MI = *I;
 1600     for (MachineInstr::const_mop_iterator MOI = MI.operands_begin(),

   44 void LivePhysRegs::removeDefs(const MachineInstr &MI) {
   59 void LivePhysRegs::addUses(const MachineInstr &MI) {
   72 void LivePhysRegs::stepBackward(const MachineInstr &MI) {
   84 void LivePhysRegs::stepForward(const MachineInstr &MI,
  253   for (const MachineInstr &MI : make_range(MBB.rbegin(), MBB.rend()))
  289   for (MachineInstr &MI : make_range(MBB.rbegin(), MBB.rend())) {

   66   const MachineInstr &MI = *MO.getParent();
  188     const MachineInstr *MI = MO.getParent();
  369       const MachineInstr *MI = Indexes->getInstructionFromIndex(Use);

   71                                           const MachineInstr *DefMI,
   90     MachineInstr *DefMI = LIS.getInstructionFromIndex(OrigVNI->def);
  106 bool LiveRangeEdit::allUsesAvailableAt(const MachineInstr *OrigMI,
  186                                SmallVectorImpl<MachineInstr*> &Dead) {
  187   MachineInstr *DefMI = nullptr, *UseMI = nullptr;
  191     MachineInstr *MI = MO.getParent();
  229   MachineInstr *FoldMI = TII.foldMemoryOperand(*UseMI, Ops, *DefMI, &LIS);
  245   const MachineInstr &MI = *MO.getParent();
  260 void LiveRangeEdit::eliminateDeadDef(MachineInstr *MI, ToShrinkSet &ToShrink,
  307   for (MachineInstr::mop_iterator MOI = MI->operands_begin(),
  392 void LiveRangeEdit::eliminateDeadDefs(SmallVectorImpl<MachineInstr *> &Dead,

   69 using InstOrderMap = DenseMap<MachineInstr *, unsigned>;
   76 static MachineInstr *FindDominatedInstruction(MachineInstr &New,
   76 static MachineInstr *FindDominatedInstruction(MachineInstr &New,
   77                                               MachineInstr *Old,
   90   for (MachineInstr *I = Old->getNextNode(); M.find(I)->second == OrderNew;
  103   for (MachineInstr &I : make_range(Start, Start->getParent()->end()))
  120   DenseMap<unsigned, std::pair<unsigned, MachineInstr *>> UseMap;
  130       MachineInstr &MI = *Next;
  139       MachineInstr *BarrierMI = nullptr;
  166       MachineInstr *Insert = nullptr;
  198           MachineInstr &DefInstr = *MRI.def_instr_begin(Reg);
  210       for (MachineInstr *I = Insert; I && IOM[I] == Barrier;

   44 void LiveRegUnits::stepBackward(const MachineInstr &MI) {
   69 void LiveRegUnits::accumulate(const MachineInstr &MI) {

   59 MachineInstr *
  132                                      MachineInstr &MI) {
  182 void LiveVariables::HandleVirtRegDef(unsigned Reg, MachineInstr &MI) {
  192 MachineInstr *LiveVariables::FindLastPartialDef(unsigned Reg,
  196   MachineInstr *LastDef = nullptr;
  199     MachineInstr *Def = PhysRegDef[SubReg];
  231 void LiveVariables::HandlePhysRegUse(unsigned Reg, MachineInstr &MI) {
  232   MachineInstr *LastDef = PhysRegDef[Reg];
  244     MachineInstr *LastPartialDef = FindLastPartialDef(Reg, PartDefRegs);
  281 MachineInstr *LiveVariables::FindLastRefOrPartRef(unsigned Reg) {
  282   MachineInstr *LastDef = PhysRegDef[Reg];
  283   MachineInstr *LastUse = PhysRegUse[Reg];
  287   MachineInstr *LastRefOrPartRef = LastUse ? LastUse : LastDef;
  292     MachineInstr *Def = PhysRegDef[SubReg];
  299     } else if (MachineInstr *Use = PhysRegUse[SubReg]) {
  311 bool LiveVariables::HandlePhysRegKill(unsigned Reg, MachineInstr *MI) {
  312   MachineInstr *LastDef = PhysRegDef[Reg];
  313   MachineInstr *LastUse = PhysRegUse[Reg];
  317   MachineInstr *LastRefOrPartRef = LastUse ? LastUse : LastDef;
  336   MachineInstr *LastPartDef = nullptr;
  341     MachineInstr *Def = PhysRegDef[SubReg];
  352     if (MachineInstr *Use = PhysRegUse[SubReg]) {
  385       MachineInstr *LastSubRef = FindLastRefOrPartRef(SubReg);
  443 void LiveVariables::HandlePhysRegDef(unsigned Reg, MachineInstr *MI,
  486 void LiveVariables::UpdatePhysRegDefs(MachineInstr &MI,
  500 void LiveVariables::runOnInstr(MachineInstr &MI,
  576   for (MachineInstr &MI : *MBB) {
  681 void LiveVariables::replaceKillInstruction(unsigned Reg, MachineInstr &OldMI,
  682                                            MachineInstr &NewMI) {
  689 void LiveVariables::removeVirtualRegistersKilled(MachineInstr &MI) {
  710     for (const auto &BBI : MBB) {
  730   const MachineInstr *Def = MRI.getVRegDef(Reg);
  783     for (MachineInstr::mop_iterator I = BBI->operands_begin(),

   61     FrameRef(MachineInstr *I, int64_t Offset, int Idx, unsigned Ord) :
  272                        const MachineInstr &MI,
  304     for (MachineInstr &MI : BB) {
  348     MachineInstr &MI = *FR.getMachineInstr();

   99 rescheduleLexographically(std::vector<MachineInstr *> instructions,
  104   using StringInstrPair = std::pair<std::string, MachineInstr *>;
  107   for (auto *II : instructions) {
  157   std::vector<MachineInstr *> Instructions;
  158   for (auto &MI : *MBB) {
  162   std::map<MachineInstr *, std::vector<MachineInstr *>> MultiUsers;
  162   std::map<MachineInstr *, std::vector<MachineInstr *>> MultiUsers;
  163   std::map<unsigned, MachineInstr *> MultiUserLookup;
  165   std::vector<MachineInstr *> PseudoIdempotentInstructions;
  167   for (auto *II : Instructions) {
  183   for (auto *II : Instructions) {
  221     MachineInstr *Def = II;
  223     MachineInstr *UseToBringDefCloserTo = nullptr;
  226       MachineInstr *UseInst = UO.getParent();
  310   std::vector<MachineInstr *> Copies;
  311   for (MachineInstr &MI : MBB->instrs()) {
  316   for (MachineInstr *MI : Copies) {
  356   for (auto &MI : *MBB) {
  427     MachineInstr &MI = *MII++;

  397   bool parse(MachineInstr *&MI);
  502   bool assignRegisterTies(MachineInstr &MI,
  800   MachineInstr *PrevMI = nullptr;
  812     MachineInstr *MI = nullptr;
  817       PrevMI->setFlag(MachineInstr::BundledSucc);
  818       MI->setFlag(MachineInstr::BundledPred);
  826       MI->setFlag(MachineInstr::BundledSucc);
  884 bool MIParser::parse(MachineInstr *&MI) {
 1144       Flags |= MachineInstr::FrameSetup;
 1146       Flags |= MachineInstr::FrameDestroy;
 1148       Flags |= MachineInstr::FmNoNans;
 1150       Flags |= MachineInstr::FmNoInfs;
 1152       Flags |= MachineInstr::FmNsz;
 1154       Flags |= MachineInstr::FmArcp;
 1156       Flags |= MachineInstr::FmContract;
 1158       Flags |= MachineInstr::FmAfn;
 1160       Flags |= MachineInstr::FmReassoc;
 1162       Flags |= MachineInstr::NoUWrap;
 1164       Flags |= MachineInstr::NoSWrap;
 1166       Flags |= MachineInstr::IsExact;
 1168       Flags |= MachineInstr::FPExcept;
 1356 bool MIParser::assignRegisterTies(MachineInstr &MI,

  322     for (const MachineInstr &MI : MBB) {
  361     if (!CallI->isCall(MachineInstr::IgnoreBundle))
  614     for (const MachineInstr &MI : MBB) {

  162   void print(const MachineInstr &MI);
  164   void print(const MachineInstr &MI, unsigned OpIdx,
  554   for (const MachineInstr &MI : MBB) {
  688     const MachineInstr &MI = *I;
  695     if (!IsInBundle && MI.getFlag(MachineInstr::BundledSucc)) {
  705 void MIPrinter::print(const MachineInstr &MI) {
  731   if (MI.getFlag(MachineInstr::FrameSetup))
  733   if (MI.getFlag(MachineInstr::FrameDestroy))
  735   if (MI.getFlag(MachineInstr::FmNoNans))
  737   if (MI.getFlag(MachineInstr::FmNoInfs))
  739   if (MI.getFlag(MachineInstr::FmNsz))
  741   if (MI.getFlag(MachineInstr::FmArcp))
  743   if (MI.getFlag(MachineInstr::FmContract))
  745   if (MI.getFlag(MachineInstr::FmAfn))
  747   if (MI.getFlag(MachineInstr::FmReassoc))
  749   if (MI.getFlag(MachineInstr::NoUWrap))
  751   if (MI.getFlag(MachineInstr::NoSWrap))
  753   if (MI.getFlag(MachineInstr::IsExact))
  755   if (MI.getFlag(MachineInstr::FPExcept))
  818 void MIPrinter::print(const MachineInstr &MI, unsigned OpIdx,

   51 std::vector<MachineInstr *> populateCandidates(MachineBasicBlock *MBB) {
   52   std::vector<MachineInstr *> Candidates;
   56     MachineInstr *MI = &*II;
   83                      std::vector<MachineInstr *> &VisitedMIs,
  122       MachineInstr *Def = RI->getParent();
  260   std::vector<MachineInstr *> Candidates = populateCandidates(MBB);
  261   std::vector<MachineInstr *> VisitedMIs;

  110 void ilist_traits<MachineInstr>::addNodeToList(MachineInstr *N) {
  123 void ilist_traits<MachineInstr>::removeNodeFromList(MachineInstr *N) {
  155 void ilist_traits<MachineInstr>::deleteNode(MachineInstr *MI) {
  410   for (const MachineInstr &MI : instrs()) {
  426     if (!IsInBundle && MI.getFlag(MachineInstr::BundledSucc)) {
  905       MachineInstr *MI = &*I;
  906       for (MachineInstr::mop_iterator OI = MI->operands_begin(),
  925       MachineInstr *MI = &*I;
  927       for (MachineInstr::mop_iterator OI = MI->operands_begin(),
  943   SmallVector<MachineInstr*, 4> Terminators;
  953     SmallVector<MachineInstr*, 4> NewTerminators;
  958     for (SmallVectorImpl<MachineInstr*>::iterator I = Terminators.begin(),
  973       for (MachineInstr &MI : NMBB->instrs()) {
 1143 static void unbundleSingleMI(MachineInstr *MI) {
 1160 MachineInstr *MachineBasicBlock::remove_instr(MachineInstr *MI) {
 1160 MachineInstr *MachineBasicBlock::remove_instr(MachineInstr *MI) {
 1162   MI->clearFlag(MachineInstr::BundledPred);
 1163   MI->clearFlag(MachineInstr::BundledSucc);
 1173     MI->setFlag(MachineInstr::BundledPred);
 1174     MI->setFlag(MachineInstr::BundledSucc);
 1218   for (MachineInstr &MI : phis())

  100                             ScopedHashTableVal<MachineInstr *, unsigned>>;
  102         ScopedHashTable<MachineInstr *, unsigned, MachineInstrExpressionTrait,
  109     DenseMap<MachineInstr *, MachineBasicBlock *, MachineInstrExpressionTrait>
  112     SmallVector<MachineInstr *, 64> Exps;
  115     bool PerformTrivialCopyPropagation(MachineInstr *MI,
  120     bool hasLivePhysRegDefUses(const MachineInstr *MI,
  124     bool PhysRegDefsReach(MachineInstr *CSMI, MachineInstr *MI,
  124     bool PhysRegDefsReach(MachineInstr *CSMI, MachineInstr *MI,
  127     bool isCSECandidate(MachineInstr *MI);
  129                            MachineBasicBlock *CSBB, MachineInstr *MI);
  137     bool isPRECandidate(MachineInstr *MI);
  164 bool MachineCSE::PerformTrivialCopyPropagation(MachineInstr *MI,
  174     MachineInstr *DefMI = MRI->getVRegDef(Reg);
  276 bool MachineCSE::hasLivePhysRegDefUses(const MachineInstr *MI,
  328 bool MachineCSE::PhysRegDefsReach(MachineInstr *CSMI, MachineInstr *MI,
  328 bool MachineCSE::PhysRegDefsReach(MachineInstr *CSMI, MachineInstr *MI,
  395 bool MachineCSE::isCSECandidate(MachineInstr *MI) {
  432                                    MachineBasicBlock *CSBB, MachineInstr *MI) {
  440     SmallPtrSet<MachineInstr*, 8> CSUses;
  441     for (MachineInstr &MI : MRI->use_nodbg_instructions(CSReg)) {
  444     for (MachineInstr &MI : MRI->use_nodbg_instructions(Reg)) {
  473     for (MachineInstr &MI : MRI->use_nodbg_instructions(Reg)) {
  487   for (MachineInstr &UseMI : MRI->use_nodbg_instructions(CSReg)) {
  517     MachineInstr *MI = &*I;
  541       if (MachineInstr *NewMI = TII->commuteInstruction(*MI)) {
  572         MachineInstr *CSMI = Exps[CSVN];
  586     MachineInstr *CSMI = Exps[CSVN];
  646         MachineInstr *Def = MRI->getUniqueVRegDef(NewReg);
  771 bool MachineCSE::isPRECandidate(MachineInstr *MI) {
  795     MachineInstr *MI = &*I;
  831         MachineInstr &NewMI =

   87   MachineInstr *getOperandDef(const MachineOperand &MO);
   88   unsigned getDepth(SmallVectorImpl<MachineInstr *> &InsInstrs,
   91   unsigned getLatency(MachineInstr *Root, MachineInstr *NewRoot,
   91   unsigned getLatency(MachineInstr *Root, MachineInstr *NewRoot,
   94   improvesCriticalPathLen(MachineBasicBlock *MBB, MachineInstr *Root,
   96                           SmallVectorImpl<MachineInstr *> &InsInstrs,
   97                           SmallVectorImpl<MachineInstr *> &DelInstrs,
  102                             SmallVectorImpl<MachineInstr *> &InsInstrs,
  103                             SmallVectorImpl<MachineInstr *> &DelInstrs);
  104   void instr2instrSC(SmallVectorImpl<MachineInstr *> &Instrs,
  107   getLatenciesForInstrSequences(MachineInstr &MI,
  108                                 SmallVectorImpl<MachineInstr *> &InsInstrs,
  109                                 SmallVectorImpl<MachineInstr *> &DelInstrs,
  112   void verifyPatternOrder(MachineBasicBlock *MBB, MachineInstr &Root,
  137 MachineInstr *MachineCombiner::getOperandDef(const MachineOperand &MO) {
  138   MachineInstr *DefInstr = nullptr;
  157 MachineCombiner::getDepth(SmallVectorImpl<MachineInstr *> &InsInstrs,
  167   for (auto *InstrPtr : InsInstrs) { // for each Use
  182         MachineInstr *DefInstr = InsInstrs[II->second];
  191         MachineInstr *DefInstr = getOperandDef(MO);
  216 unsigned MachineCombiner::getLatency(MachineInstr *Root, MachineInstr *NewRoot,
  216 unsigned MachineCombiner::getLatency(MachineInstr *Root, MachineInstr *NewRoot,
  235     MachineInstr *UseMO = RI->getParent();
  275     MachineInstr &MI, SmallVectorImpl<MachineInstr *> &InsInstrs,
  275     MachineInstr &MI, SmallVectorImpl<MachineInstr *> &InsInstrs,
  276     SmallVectorImpl<MachineInstr *> &DelInstrs,
  281   MachineInstr *NewRoot = InsInstrs.back();
  299     MachineBasicBlock *MBB, MachineInstr *Root,
  301     SmallVectorImpl<MachineInstr *> &InsInstrs,
  302     SmallVectorImpl<MachineInstr *> &DelInstrs,
  358     SmallVectorImpl<MachineInstr *> &Instrs,
  360   for (auto *InstrPtr : Instrs) {
  371     SmallVectorImpl<MachineInstr *> &InsInstrs,
  372     SmallVectorImpl<MachineInstr *> &DelInstrs) {
  430 static void insertDeleteInstructions(MachineBasicBlock *MBB, MachineInstr &MI,
  431                                      SmallVector<MachineInstr *, 16> InsInstrs,
  432                                      SmallVector<MachineInstr *, 16> DelInstrs,
  436   for (auto *InstrPtr : InsInstrs)
  439   for (auto *InstrPtr : DelInstrs) {
  451     for (auto *InstrPtr : InsInstrs)
  462     MachineBasicBlock *MBB, MachineInstr &Root,
  467     SmallVector<MachineInstr *, 16> InsInstrs;
  468     SmallVector<MachineInstr *, 16> DelInstrs;
  511     auto &MI = *BlockIter++;
  547       SmallVector<MachineInstr *, 16> InsInstrs;
  548       SmallVector<MachineInstr *, 16> DelInstrs;
  620         for (auto *InstrPtr : InsInstrs)

   78     MachineInstr *MI;
  110         if (MachineInstr *MI = I->second.MI)
  119   void trackCopy(MachineInstr *MI, const TargetRegisterInfo &TRI) {
  143   MachineInstr *findCopyForUnit(unsigned RegUnit, const TargetRegisterInfo &TRI,
  153   MachineInstr *findAvailCopy(MachineInstr &DestCopy, unsigned Reg,
  153   MachineInstr *findAvailCopy(MachineInstr &DestCopy, unsigned Reg,
  158     MachineInstr *AvailCopy =
  168     for (const MachineInstr &MI :
  211   void ReadRegister(unsigned Reg, MachineInstr &Reader,
  214   bool eraseIfRedundant(MachineInstr &Copy, unsigned Src, unsigned Def);
  215   void forwardUses(MachineInstr &MI);
  216   bool isForwardableRegClassCopy(const MachineInstr &Copy,
  217                                  const MachineInstr &UseI, unsigned UseIdx);
  218   bool hasImplicitOverlap(const MachineInstr &MI, const MachineOperand &Use);
  221   SmallSetVector<MachineInstr *, 8> MaybeDeadCopies;
  224   DenseMap<MachineInstr*, SmallVector<MachineInstr*, 2>> CopyDbgUsers;
  224   DenseMap<MachineInstr*, SmallVector<MachineInstr*, 2>> CopyDbgUsers;
  240 void MachineCopyPropagation::ReadRegister(unsigned Reg, MachineInstr &Reader,
  246     if (MachineInstr *Copy = Tracker.findCopyForUnit(*RUI, *TRI)) {
  263 static bool isNopCopy(const MachineInstr &PreviousCopy, unsigned Src,
  280 bool MachineCopyPropagation::eraseIfRedundant(MachineInstr &Copy, unsigned Src,
  288   MachineInstr *PrevCopy = Tracker.findAvailCopy(Copy, Def, *TRI);
  305   for (MachineInstr &MI :
  318 bool MachineCopyPropagation::isForwardableRegClassCopy(const MachineInstr &Copy,
  319                                                        const MachineInstr &UseI,
  369 bool MachineCopyPropagation::hasImplicitOverlap(const MachineInstr &MI,
  381 void MachineCopyPropagation::forwardUses(MachineInstr &MI) {
  409     MachineInstr *Copy = Tracker.findAvailCopy(MI, MOUse.getReg(), *TRI);
  452     for (MachineInstr &KMI :
  465     MachineInstr *MI = &*I;
  582       for (SmallSetVector<MachineInstr *, 8>::iterator DI =
  585         MachineInstr *MaybeDead = *DI;
  619     for (MachineInstr *MaybeDead : MaybeDeadCopies) {

  198     for (const MachineInstr &MI : MBB) {

  143 void MachineFunction::handleInsertion(MachineInstr &MI) {
  148 void MachineFunction::handleRemoval(MachineInstr &MI) {
  326 MachineInstr *MachineFunction::CreateMachineInstr(const MCInstrDesc &MCID,
  329   return new (InstructionRecycler.Allocate<MachineInstr>(Allocator))
  330     MachineInstr(*this, MCID, DL, NoImp);
  335 MachineInstr *
  336 MachineFunction::CloneMachineInstr(const MachineInstr *Orig) {
  337   return new (InstructionRecycler.Allocate<MachineInstr>(Allocator))
  338              MachineInstr(*this, *Orig);
  341 MachineInstr &MachineFunction::CloneMachineInstrBundle(MachineBasicBlock &MBB,
  343   MachineInstr *FirstClone = nullptr;
  346     MachineInstr *Cloned = CloneMachineInstr(&*I);
  366 MachineFunction::DeleteMachineInstr(MachineInstr *MI) {
  450 MachineInstr::ExtraInfo *MachineFunction::createMIExtraInfo(
  453   return MachineInstr::ExtraInfo::create(Allocator, MMOs, PreInstrSymbol,
  826 void MachineFunction::moveCallSiteInfo(const MachineInstr *Old,
  827                                        const MachineInstr *New) {
  839 void MachineFunction::eraseCallSiteInfo(const MachineInstr *MI) {
  846 void MachineFunction::copyCallSiteInfo(const MachineInstr *Old,
  847                                        const MachineInstr *New) {

   79 static const MachineFunction *getMFIfAvailable(const MachineInstr &MI) {
   88 static void tryToGetTargetInfo(const MachineInstr &MI,
  134 MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI)
  382 void MachineInstr::cloneMemRefs(MachineFunction &MF, const MachineInstr &MI) {
  417                                       ArrayRef<const MachineInstr *> MIs) {
  442   for (const MachineInstr &MI : make_pointee_range(MIs.slice(1))) {
  507                                      const MachineInstr &MI) {
  520 uint16_t MachineInstr::mergeFlagsWith(const MachineInstr &Other) const {
  532       MIFlags |= MachineInstr::MIFlag::NoSWrap;
  534       MIFlags |= MachineInstr::MIFlag::NoUWrap;
  540       MIFlags |= MachineInstr::MIFlag::IsExact;
  546       MIFlags |= MachineInstr::MIFlag::FmNoNans;
  548       MIFlags |= MachineInstr::MIFlag::FmNoInfs;
  550       MIFlags |= MachineInstr::MIFlag::FmNsz;
  552       MIFlags |= MachineInstr::MIFlag::FmArcp;
  554       MIFlags |= MachineInstr::MIFlag::FmContract;
  556       MIFlags |= MachineInstr::MIFlag::FmAfn;
  558       MIFlags |= MachineInstr::MIFlag::FmReassoc;
  584 bool MachineInstr::isIdenticalTo(const MachineInstr &Other,
  659 MachineInstr *MachineInstr::removeFromParent() {
  664 MachineInstr *MachineInstr::removeFromBundle() {
  680   MachineInstr *MI = (MachineInstr *)this;
 1191 bool MachineInstr::mayAlias(AAResults *AA, const MachineInstr &Other,
 1399                                    const MachineInstr &MI) {
 1517   if (getFlag(MachineInstr::FrameSetup))
 1519   if (getFlag(MachineInstr::FrameDestroy))
 1521   if (getFlag(MachineInstr::FmNoNans))
 1523   if (getFlag(MachineInstr::FmNoInfs))
 1525   if (getFlag(MachineInstr::FmNsz))
 1527   if (getFlag(MachineInstr::FmArcp))
 1529   if (getFlag(MachineInstr::FmContract))
 1531   if (getFlag(MachineInstr::FmAfn))
 1533   if (getFlag(MachineInstr::FmReassoc))
 1535   if (getFlag(MachineInstr::NoUWrap))
 1537   if (getFlag(MachineInstr::NoSWrap))
 1539   if (getFlag(MachineInstr::IsExact))
 1541   if (getFlag(MachineInstr::FPExcept))
 1977 MachineInstrExpressionTrait::getHashValue(const MachineInstr* const &MI) {
 2054   MachineInstr *MI = BuildMI(MF, DL, MCID, IsIndirect, Reg, Variable, Expr);
 2065   MachineInstr *MI = BuildMI(MF, DL, MCID, IsIndirect, MO, Variable, Expr);
 2072 static const DIExpression *computeExprForSpill(const MachineInstr &MI) {
 2085 MachineInstr *llvm::buildDbgValueForSpill(MachineBasicBlock &BB,
 2097 void llvm::updateDbgValueForSpill(MachineInstr &Orig, int FrameIndex) {
 2105                                 SmallVectorImpl<MachineInstr *> &DbgValues) {
 2106   MachineInstr &MI = *this;
 2123   SmallVector<MachineInstr *, 2> DbgValues;
 2131     auto *DI = MO.getParent();
 2141   for (auto *DBI : DbgValues)

   54       MachineInstr *MI = &*MII;
  231     if (MII->getFlag(MachineInstr::FrameSetup))
  232       MIB.setMIFlag(MachineInstr::FrameSetup);
  233     if (MII->getFlag(MachineInstr::FrameDestroy))
  234       MIB.setMIFlag(MachineInstr::FrameDestroy);
  286                     SmallVectorImpl<std::pair<MachineInstr*, unsigned> > *Ops) {

  132     DenseMap<unsigned, std::vector<const MachineInstr *>> CSEMap;
  170       MachineInstr *MI;
  174       CandidateInfo(MachineInstr *mi, unsigned def, int fi)
  180     void HoistPostRA(MachineInstr *MI, unsigned Def);
  182     void ProcessMI(MachineInstr *MI, BitVector &PhysRegDefs,
  188     bool IsLICMCandidate(MachineInstr &I);
  190     bool IsLoopInvariantInst(MachineInstr &I);
  192     bool HasLoopPHIUse(const MachineInstr *MI) const;
  194     bool HasHighOperandLatency(MachineInstr &MI, unsigned DefIdx,
  197     bool IsCheapInstruction(MachineInstr &MI) const;
  202     void UpdateBackTraceRegPressure(const MachineInstr *MI);
  204     bool IsProfitableToHoist(MachineInstr &MI);
  225     DenseMap<unsigned, int> calcRegisterCost(const MachineInstr *MI,
  229     void UpdateRegPressure(const MachineInstr *MI,
  232     MachineInstr *ExtractHoistableLoad(MachineInstr *MI);
  232     MachineInstr *ExtractHoistableLoad(MachineInstr *MI);
  234     const MachineInstr *
  235     LookForDuplicate(const MachineInstr *MI,
  236                      std::vector<const MachineInstr *> &PrevMIs);
  239         MachineInstr *MI,
  240         DenseMap<unsigned, std::vector<const MachineInstr *>>::iterator &CI);
  242     bool MayCSE(MachineInstr *MI);
  244     bool Hoist(MachineInstr *MI, MachineBasicBlock *Preheader);
  374 static bool InstructionStoresToFI(const MachineInstr *MI, int FI) {
  397 void MachineLICMBase::ProcessMI(MachineInstr *MI,
  517     for (MachineInstr &MI : *BB)
  552       MachineInstr *MI = Candidate.MI;
  577     for (MachineInstr &MI : *BB) {
  589 void MachineLICMBase::HoistPostRA(MachineInstr *MI, unsigned Def) {
  737       MachineInstr *MI = &*MII;
  758   SmallVector<MachineInstr *, 8> Candidates;
  767   for (MachineInstr *I : Candidates) {
  775     for (MachineInstr &MI : MRI->use_instructions(MO.getReg())) {
  821   for (const MachineInstr &MI : *BB)
  826 void MachineLICMBase::UpdateRegPressure(const MachineInstr *MI,
  845 MachineLICMBase::calcRegisterCost(const MachineInstr *MI, bool ConsiderSeen,
  889 static bool mayLoadFromGOTOrConstantPool(MachineInstr &MI) {
  912 static bool isInvariantStore(const MachineInstr &MI,
  946 static bool isCopyFeedingInvariantStore(const MachineInstr &MI,
  969   for (MachineInstr &UseMI : MRI->use_instructions(CopyDstReg)) {
  978 bool MachineLICMBase::IsLICMCandidate(MachineInstr &I) {
 1003 bool MachineLICMBase::IsLoopInvariantInst(MachineInstr &I) {
 1056 bool MachineLICMBase::HasLoopPHIUse(const MachineInstr *MI) const {
 1057   SmallVector<const MachineInstr*, 8> Work(1, MI);
 1066       for (MachineInstr &UseMI : MRI->use_instructions(Reg)) {
 1091 bool MachineLICMBase::HasHighOperandLatency(MachineInstr &MI,
 1097   for (MachineInstr &UseMI : MRI->use_nodbg_instructions(Reg)) {
 1123 bool MachineLICMBase::IsCheapInstruction(MachineInstr &MI) const {
 1174 void MachineLICMBase::UpdateBackTraceRegPressure(const MachineInstr *MI) {
 1188 bool MachineLICMBase::IsProfitableToHoist(MachineInstr &MI) {
 1283 MachineInstr *MachineLICMBase::ExtractHoistableLoad(MachineInstr *MI) {
 1283 MachineInstr *MachineLICMBase::ExtractHoistableLoad(MachineInstr *MI) {
 1308   SmallVector<MachineInstr *, 2> NewMIs;
 1342   for (MachineInstr &MI : *BB)
 1348 const MachineInstr*
 1349 MachineLICMBase::LookForDuplicate(const MachineInstr *MI,
 1350                                   std::vector<const MachineInstr*> &PrevMIs) {
 1351   for (const MachineInstr *PrevMI : PrevMIs)
 1362 bool MachineLICMBase::EliminateCSE(MachineInstr *MI,
 1363     DenseMap<unsigned, std::vector<const MachineInstr *>>::iterator &CI) {
 1369   if (const MachineInstr *Dup = LookForDuplicate(MI, CI->second)) {
 1420 bool MachineLICMBase::MayCSE(MachineInstr *MI) {
 1422   DenseMap<unsigned, std::vector<const MachineInstr *>>::iterator
 1435 bool MachineLICMBase::Hoist(MachineInstr *MI, MachineBasicBlock *Preheader) {
 1468   DenseMap<unsigned, std::vector<const MachineInstr *>>::iterator

   18 MachineInstr &findEquivalentInstruction(MachineInstr &MI,
   18 MachineInstr &findEquivalentInstruction(MachineInstr &MI,
   47   for (MachineInstr &MI : *Loop) {
   48     MachineInstr *NewMI = MF.CloneMachineInstr(&MI);
   80     MachineInstr &MI = *I;
   84     MachineInstr &OrigPhi = findEquivalentInstruction(MI, Loop);

   41   if (const MachineInstr *MI = MO.getParent())
  122   const MachineInstr *MI = getParent();
  127     return !MI->hasExtraDefRegAllocReq(MachineInstr::IgnoreBundle);
  130   return !MI->hasExtraSrcRegAllocReq(MachineInstr::IgnoreBundle);

   24     StringRef MKey, const MachineInstr &MI)

  617   DenseMap<MachineInstr *, unsigned, MachineInstrExpressionTrait>
  663     MachineInstr &MI = *It;
  665     DenseMap<MachineInstr *, unsigned, MachineInstrExpressionTrait>::iterator
 1140     MachineInstr *NewMI = MF.CloneMachineInstr(&*I);

  352   for (MachineInstr &PI : make_range(B.begin(), B.getFirstNonPHI())) {
  531   DenseMap<MachineInstr *, int> Cycles, Stages;
  532   std::vector<MachineInstr *> OrderedInsts;
  541   DenseMap<MachineInstr *, std::pair<unsigned, int64_t>> NewInstrChanges;
  581 static void getPhiRegs(MachineInstr &Phi, MachineBasicBlock *Loop,
  597 static unsigned getLoopPhiReg(MachineInstr &Phi, MachineBasicBlock *LoopBB) {
  628 static bool isDependenceBarrier(MachineInstr &MI, AliasAnalysis *AA) {
  638 static void getUnderlyingObjects(const MachineInstr *MI,
  665     MachineInstr &MI = *SU.getInstr();
  690           MachineInstr &LdMI = *Load->getInstr();
  765     MachineInstr *MI = I.getInstr();
  767     for (MachineInstr::mop_iterator MOI = MI->operands_begin(),
  779           MachineInstr *UseMI = &*UI;
  797         MachineInstr *DefMI = MRI.getUniqueVRegDef(Reg);
  821       MachineInstr *PMI = PI.getSUnit()->getInstr();
  852     MachineInstr *DefMI = MRI.getUniqueVRegDef(OrigBase);
  859     MachineInstr *LastMI = MRI.getUniqueVRegDef(NewBase);
  916   unsigned minFuncUnits(const MachineInstr *Inst, unsigned &F) const {
  963   void calcCriticalResources(MachineInstr &MI) {
  996   bool operator()(const MachineInstr *IS1, const MachineInstr *IS2) const {
  996   bool operator()(const MachineInstr *IS1, const MachineInstr *IS2) const {
 1028   PriorityQueue<MachineInstr *, std::vector<MachineInstr *>, FuncUnitSorter>
 1028   PriorityQueue<MachineInstr *, std::vector<MachineInstr *>, FuncUnitSorter>
 1037     MachineInstr *MI = FuncUnitOrder.top();
 1300       MachineInstr *TmpMI = TmpSU->getInstr();
 1323         MachineInstr *TmpMI = TmpSU->getInstr();
 1551     const MachineInstr *MI = SU->getInstr();
 2056 bool SwingSchedulerDAG::computeDelta(MachineInstr &MI, unsigned &Delta) {
 2070   MachineInstr *BaseDef = MRI.getVRegDef(BaseReg);
 2093 bool SwingSchedulerDAG::canUseLastOffsetValue(MachineInstr *MI,
 2108   MachineInstr *Phi = MRI.getVRegDef(BaseReg);
 2117   MachineInstr *PrevDef = MRI.getVRegDef(PrevReg);
 2132   MachineInstr *NewMI = MF.CloneMachineInstr(MI);
 2149 void SwingSchedulerDAG::applyInstrChange(MachineInstr *MI,
 2160     MachineInstr *LoopDef = findDefInLoop(BaseReg);
 2166       MachineInstr *NewMI = MF.CloneMachineInstr(MI);
 2186 MachineInstr *SwingSchedulerDAG::findDefInLoop(unsigned Reg) {
 2187   SmallPtrSet<MachineInstr *, 8> Visited;
 2188   MachineInstr *Def = MRI.getVRegDef(Reg);
 2216   MachineInstr *SI = Source->getInstr();
 2217   MachineInstr *DI = Dep.getSUnit()->getInstr();
 2248   MachineInstr *Def = MRI.getVRegDef(BaseOpS->getReg());
 2254   MachineInstr *LoopDef = MRI.getVRegDef(LoopVal);
 2461   MachineInstr *MI = SU->getInstr();
 2588 bool SMSchedule::isLoopCarried(SwingSchedulerDAG *SSD, MachineInstr &Phi) {
 2617                                        MachineInstr *Def, MachineOperand &MO) {
 2622   MachineInstr *Phi = MRI.getVRegDef(MO.getReg());
 2764     MachineInstr *MI = SU->getInstr();
 2778             MachineInstr *NewMI = MF.CloneMachineInstr(MI);
 3013 bool ResourceManager::canReserveResources(const MachineInstr &MI) const {
 3017 void ResourceManager::reserveResources(const MachineInstr &MI) {

  135     MachineInstr *MI = MO.getParent();
  222     MachineInstr *MI = MO->getParent();
  400 MachineInstr *MachineRegisterInfo::getVRegDef(unsigned Reg) const {
  411 MachineInstr *MachineRegisterInfo::getUniqueVRegDef(unsigned Reg) const {
  508   for (MachineInstr &I : use_instructions(Reg))
  551     MachineInstr *UseMI = &*I;
  557 static const Function *getCalledFunction(const MachineInstr &MI) {
  570   const MachineInstr &MI = *MO.getParent();

   44                                      SmallVectorImpl<MachineInstr*> *NewPHI)
  152     MachineInstr *NewDef = InsertNewDef(TargetOpcode::IMPLICIT_DEF,
  211 MachineBasicBlock *findCorrespondingPred(const MachineInstr *MI,
  224   MachineInstr *UseMI = U.getParent();
  245   using PhiT = MachineInstr;
  254     MachineInstr *PHI;
  258     explicit PHI_iterator(MachineInstr *P) // begin iterator
  260     PHI_iterator(MachineInstr *P, bool) // end iterator
  294     MachineInstr *NewDef = InsertNewDef(TargetOpcode::IMPLICIT_DEF,
  306     MachineInstr *PHI = InsertNewDef(TargetOpcode::PHI, BB, Loc,
  314   static void AddPHIOperand(MachineInstr *PHI, unsigned Val,
  320   static MachineInstr *InstrIsPHI(MachineInstr *I) {
  320   static MachineInstr *InstrIsPHI(MachineInstr *I) {
  328   static MachineInstr *ValueIsPHI(unsigned Val, MachineSSAUpdater *Updater) {
  334   static MachineInstr *ValueIsNewPHI(unsigned Val, MachineSSAUpdater *Updater) {
  335     MachineInstr *PHI = ValueIsPHI(Val, Updater);
  343   static unsigned GetPHIValue(MachineInstr *PHI) {

  488       MachineInstr &MI = *std::prev(I);
  714   MachineInstr *MI, MachineBasicBlock::iterator InsertPos) {
  779     MachineInstr *MI = SU->getInstr();
  893   for (std::vector<std::pair<MachineInstr *, MachineInstr *>>::iterator
  893   for (std::vector<std::pair<MachineInstr *, MachineInstr *>>::iterator
  895     std::pair<MachineInstr *, MachineInstr *> P = *std::prev(DI);
  895     std::pair<MachineInstr *, MachineInstr *> P = *std::prev(DI);
  896     MachineInstr *DbgValue = P.first;
  929   const MachineInstr &MI = *SU.getInstr();
 1331     MachineInstr *DefMI = LIS->getInstructionFromIndex(DefVNI->def);
 1388   MachineInstr *MI = SU->getInstr();
 1688   MachineInstr *Copy = CopySU->getInstr();
 1756   MachineInstr *GlobalDef = LIS->getInstructionFromIndex(GlobalSegment->start);
 1768   MachineInstr *LastLocalDef = LIS->getInstructionFromIndex(LastLocalVN->def);
 1782   MachineInstr *FirstLocalDef =
 2912   const MachineInstr *MI = SU->getInstr();
 3268     MachineInstr *Copy = DepSU->getInstr();

  109     DenseMap<unsigned, TinyPtrVector<MachineInstr *>> SeenDbgUsers;
  138     void ProcessDbgInst(MachineInstr &MI);
  139     bool isWorthBreakingCriticalEdge(MachineInstr &MI,
  155     bool PostponeSplitCriticalEdge(MachineInstr &MI,
  159     bool SinkInstruction(MachineInstr &MI, bool &SawStore,
  166     void SalvageUnsunkDebugUsersOfCopy(MachineInstr &,
  171     MachineBasicBlock *FindSuccToSinkTo(MachineInstr &MI, MachineBasicBlock *MBB,
  173     bool isProfitableToSinkTo(unsigned Reg, MachineInstr &MI,
  178     bool PerformTrivialForwardCoalescing(MachineInstr &MI,
  201 bool MachineSinking::PerformTrivialForwardCoalescing(MachineInstr &MI,
  217   MachineInstr *DefMI = MRI->getVRegDef(SrcReg);
  266     MachineInstr *UseInst = MO.getParent();
  280     MachineInstr *UseInst = MO.getParent();
  372     MachineInstr &MI = *I;  // The instruction to sink.
  405 void MachineSinking::ProcessDbgInst(MachineInstr &MI) {
  417 bool MachineSinking::isWorthBreakingCriticalEdge(MachineInstr &MI,
  459       MachineInstr *DefMI = MRI->getVRegDef(Reg);
  468 bool MachineSinking::PostponeSplitCriticalEdge(MachineInstr &MI,
  539 bool MachineSinking::isProfitableToSinkTo(unsigned Reg, MachineInstr &MI,
  559   for (MachineInstr &UseInst : MRI->use_nodbg_instructions(Reg)) {
  626 MachineSinking::FindSuccToSinkTo(MachineInstr &MI, MachineBasicBlock *MBB,
  721 static bool SinkingPreventsImplicitNullCheck(MachineInstr &MI,
  762 static void performSink(MachineInstr &MI, MachineBasicBlock &SuccToSinkTo,
  789   for (SmallVectorImpl<MachineInstr *>::iterator DBI = DbgValuesToSink.begin(),
  792     MachineInstr *DbgMI = *DBI;
  793     MachineInstr *NewDbgMI = DbgMI->getMF()->CloneMachineInstr(*DBI);
  838 bool MachineSinking::SinkInstruction(MachineInstr &MI, bool &SawStore,
  951   SmallVector<MachineInstr *, 4> DbgUsersToSink;
  984     MachineInstr &MI, MachineBasicBlock *TargetBlock) {
  991   SmallVector<MachineInstr *, 4> DbgDefUsers;
  996     for (auto &User : MRI.use_instructions(MO.getReg())) {
 1012   for (auto *User : DbgDefUsers) {
 1078   DenseMap<unsigned, TinyPtrVector<MachineInstr *>> SeenDbgInstrs;
 1143 static void clearKillFlags(MachineInstr *MI, MachineBasicBlock &CurBB,
 1152       for (MachineInstr &UI : make_range(NI, CurBB.end())) {
 1163 static void updateLiveIn(MachineInstr *MI, MachineBasicBlock *SuccBB,
 1178 static bool hasRegisterDependency(MachineInstr *MI,
 1245     MachineInstr *MI = &*I;
 1309     SetVector<MachineInstr *> DbgValsToSinkSet;
 1310     SmallVector<MachineInstr *, 4> DbgValsToSink;
 1317         for (auto *MI : SeenDbgInstrs.lookup(Reg))

  111   for (const auto &MI : *MBB) {
  581   for (const auto &I : *BadMBB)
  627   const MachineInstr *DefMI;
  631   DataDep(const MachineInstr *DefMI, unsigned DefOp, unsigned UseOp)
  650 static bool getDataDeps(const MachineInstr &UseMI,
  658   for (MachineInstr::const_mop_iterator I = UseMI.operands_begin(),
  680 static void getPHIDeps(const MachineInstr &UseMI,
  699 static void updatePhysDepsDownwards(const MachineInstr *UseMI,
  706   for (MachineInstr::const_mop_iterator MI = UseMI->operands_begin(),
  770     const MachineInstr *DefMI = MTM.MRI->getVRegDef(LIR.Reg);
  782 updateDepth(MachineTraceMetrics::TraceBlockInfo &TBI, const MachineInstr &UseMI,
  821 updateDepth(const MachineBasicBlock *MBB, const MachineInstr &UseMI,
  883     for (const auto &UseMI : *MBB) {
  892 static unsigned updatePhysDepsUpwards(const MachineInstr &MI, unsigned Height,
  899   for (MachineInstr::const_mop_iterator MOI = MI.operands_begin(),
  948 using MIHeightMap = DenseMap<const MachineInstr *, unsigned>;
  952 static bool pushDepHeight(const DataDep &Dep, const MachineInstr &UseMI,
  978 addLiveIns(const MachineInstr *DefMI, unsigned DefOp,
 1074       for (const auto &PHI : *Succ) {
 1093       const MachineInstr &MI = *--BI;
 1135       const MachineInstr *DefMI = MTM.MRI->getVRegDef(LIR.Reg);
 1173 MachineTraceMetrics::Trace::getInstrSlack(const MachineInstr &MI) const {
 1181 MachineTraceMetrics::Trace::getPHIDepth(const MachineInstr &PHI) const {
 1277 bool MachineTraceMetrics::Trace::isDepInTrace(const MachineInstr &DefMI,
 1278                                               const MachineInstr &UseMI) const {

  108     using RegMap = DenseMap<unsigned, const MachineInstr *>;
  111     const MachineInstr *FirstNonPHI;
  112     const MachineInstr *FirstTerminator;
  232     void visitMachineBundleBefore(const MachineInstr *MI);
  234     bool verifyVectorElementMatch(LLT Ty0, LLT Ty1, const MachineInstr *MI);
  235     void verifyPreISelGenericInstruction(const MachineInstr *MI);
  236     void visitMachineInstrBefore(const MachineInstr *MI);
  238     void visitMachineInstrAfter(const MachineInstr *MI);
  239     void visitMachineBundleAfter(const MachineInstr *MI);
  245     void report(const char *msg, const MachineInstr *MI);
  261     void verifyInlineAsm(const MachineInstr *MI);
  407     const MachineInstr *CurBundle = nullptr;
  439         const MachineInstr &MI = *MBBI;
  500 void MachineVerifier::report(const char *msg, const MachineInstr *MI) {
  827 void MachineVerifier::visitMachineBundleBefore(const MachineInstr *MI) {
  851 void MachineVerifier::verifyInlineAsm(const MachineInstr *MI) {
  898                                                const MachineInstr *MI) {
  917 void MachineVerifier::verifyPreISelGenericInstruction(const MachineInstr *MI) {
 1480 void MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI) {
 1503   for (MachineInstr::mmo_iterator I = MI->memoperands_begin(),
 1594   const MachineInstr *MI = MO->getParent();
 1940   const MachineInstr *MI = MO->getParent();
 2096 void MachineVerifier::visitMachineInstrAfter(const MachineInstr *MI) {}
 2102 void MachineVerifier::visitMachineBundleAfter(const MachineInstr *MI) {
 2209   for (const MachineInstr &Phi : MBB) {
 2404   const MachineInstr *MI = LiveInts->getInstructionFromIndex(VNI->def);
 2510   const MachineInstr *MI =
 2779     for (const auto &I : *MBB) {

  146   const MachineInstr &AnchorMI = *AnchorSU.getInstr();
  164     const MachineInstr *DepMI = DepSU.getInstr();

   25   for (MachineInstr *MI : ScheduledInstrs)
   35 static void getPhiRegs(MachineInstr &Phi, MachineBasicBlock *Loop,
   51 static unsigned getInitPhiReg(MachineInstr &Phi, MachineBasicBlock *LoopBB) {
   59 static unsigned getLoopPhiReg(MachineInstr &Phi, MachineBasicBlock *LoopBB) {
   74   for (MachineInstr *MI : Schedule.getInstructions()) {
   88         MachineInstr *UseMI = UseOp.getParent();
  132   for (MachineInstr *CI : Schedule.getInstructions()) {
  136     MachineInstr *NewMI = cloneInstr(CI, MaxStageCount, StageNum);
  147     MachineInstr *NewMI = MF.CloneMachineInstr(&*I);
  183   for (auto &I : *BB)
  219           MachineInstr *NewMI =
  290       for (auto &BBI : *BB) {
  293         MachineInstr *In = &BBI;
  297           MachineInstr *NewMI = cloneInstr(In, UINT_MAX, 0);
  450         MachineInstr *InstOp1 = MRI.getVRegDef(PhiOp1);
  472       if (MachineInstr *InstOp1 = MRI.getVRegDef(PhiOp1))
  476       MachineInstr *PhiInst = MRI.getVRegDef(LoopVal);
  643       if (MachineInstr *InstOp2 = MRI.getVRegDef(PhiOp2))
  654         if (MachineInstr *InstOp1 = MRI.getVRegDef(PhiOp1)) {
  724       for (MachineInstr::mop_iterator MOI = MI->operands_begin(),
  765     MachineInstr *MI = &*BBI;
  788   for (auto &PHI : KernelBB->phis()) {
  800         MachineInstr *MI = MRI.getVRegDef(LCDef);
  806         for (auto &BBJ : make_range(MachineBasicBlock::instr_iterator(MI),
  822           for (auto &I : *Epilog)
  833   for (MachineInstr &MI : *BB) {
  859   SmallVector<MachineInstr *, 4> PrevInsts;
  911 bool ModuloScheduleExpander::computeDelta(MachineInstr &MI, unsigned &Delta) {
  925   MachineInstr *BaseDef = MRI.getVRegDef(BaseReg);
  944 void ModuloScheduleExpander::updateMemOperands(MachineInstr &NewMI,
  945                                                MachineInstr &OldMI,
  977 MachineInstr *ModuloScheduleExpander::cloneInstr(MachineInstr *OldMI,
  977 MachineInstr *ModuloScheduleExpander::cloneInstr(MachineInstr *OldMI,
  980   MachineInstr *NewMI = MF.CloneMachineInstr(OldMI);
  999 MachineInstr *ModuloScheduleExpander::cloneAndChangeInstr(
 1000     MachineInstr *OldMI, unsigned CurStageNum, unsigned InstStageNum) {
 1001   MachineInstr *NewMI = MF.CloneMachineInstr(OldMI);
 1009     MachineInstr *LoopDef = findDefInLoop(RegAndOffset.first);
 1020 void ModuloScheduleExpander::updateInstruction(MachineInstr *NewMI,
 1039       MachineInstr *Def = MRI.getVRegDef(reg);
 1058 MachineInstr *ModuloScheduleExpander::findDefInLoop(unsigned Reg) {
 1059   SmallPtrSet<MachineInstr *, 8> Visited;
 1060   MachineInstr *Def = MRI.getVRegDef(Reg);
 1079     MachineInstr *LoopInst = MRI.getVRegDef(LoopVal);
 1110   for (auto &PHI : BB->phis()) {
 1137     unsigned PhiNum, MachineInstr *Phi, unsigned OldReg, unsigned NewReg,
 1147     MachineInstr *UseMI = UseOp.getParent();
 1159     MachineInstr *OrigMI = OrigInstr->second;
 1189 bool ModuloScheduleExpander::isLoopCarried(MachineInstr &Phi) {
 1198   MachineInstr *Use = MRI.getVRegDef(LoopVal);
 1222       MachineInstr &MI = *I++;
 1263   Register remapUse(Register Reg, MachineInstr &MI);
 1295   MachineInstr *FirstMI = nullptr;
 1296   for (MachineInstr *MI : S.getInstructions()) {
 1316   for (MachineInstr &MI : *BB) {
 1340       for (MachineInstr &MI : MRI.use_instructions(Def.getReg())) {
 1350 Register KernelRewriter::remapUse(Register Reg, MachineInstr &MI) {
 1351   MachineInstr *Producer = MRI.getUniqueVRegDef(Reg);
 1472     MachineInstr *MI = MRI.getVRegDef(R);
 1525                     const SmallPtrSetImpl<MachineInstr *> &IllegalPhis)
 1530       MachineInstr *MI = MRI.getVRegDef(MO->getReg());
 1638     for (MachineInstr &MI : (*EI)->phis()) {
 1640       MachineInstr *Use = MRI.getUniqueVRegDef(Reg);
 1658       MachineInstr *MI = &*I++;
 1678   for (MachineInstr &MI : BB->phis()) {
 1682     SmallVector<MachineInstr *, 4> Uses;
 1683     for (MachineInstr &Use : MRI.use_instructions(OldR))
 1686     for (MachineInstr *Use : Uses)
 1689     MachineInstr *NI = BuildMI(NewBB, DebugLoc(), TII->get(TargetOpcode::PHI), R)
 1714   MachineInstr *MI = MRI.getUniqueVRegDef(Reg);
 1719 void PeelingModuloScheduleExpander::rewriteUsesOf(MachineInstr *MI) {
 1743     SmallVector<std::pair<MachineInstr *, Register>, 4> Subs;
 1744     for (MachineInstr &UseMI : MRI.use_instructions(DefMO.getReg())) {
 1787       for (MachineInstr &P : Fallthrough->phis()) {
 1797       for (MachineInstr &P : Epilog->phis()) {
 1860   SmallPtrSet<MachineInstr *, 4> IllegalPhis;
 1990   DenseMap<MachineInstr *, int> Cycle, Stage;
 1991   std::vector<MachineInstr *> Instrs;
 1992   for (MachineInstr &MI : *BB) {
 2015   for (MachineInstr *MI : S.getInstructions()) {

   55     using InstrSet = SmallPtrSet<MachineInstr *, 16>;
   56     using InstrSetIterator = SmallPtrSetIterator<MachineInstr *>;
   58     bool IsSingleValuePHICycle(MachineInstr *MI, unsigned &SingleValReg,
   60     bool IsDeadPHICycle(MachineInstr *MI, InstrSet &PHIsInCycle);
   96 bool OptimizePHIs::IsSingleValuePHICycle(MachineInstr *MI,
  115     MachineInstr *SrcMI = MRI->getVRegDef(SrcReg);
  142 bool OptimizePHIs::IsDeadPHICycle(MachineInstr *MI, InstrSet &PHIsInCycle) {
  156   for (MachineInstr &UseMI : MRI->use_nodbg_instructions(DstReg)) {
  170     MachineInstr *MI = &*MII++;
  199         MachineInstr *PhiMI = *PI;

  112     SmallPtrSet<MachineInstr*, 4> ImpDefs;
  116         DenseMap<MachineInstr*, unsigned, MachineInstrExpressionTrait>;
  172   for (MachineInstr *DefMI : ImpDefs) {
  223   for (MachineInstr &DI : MRI.def_instructions(VirtReg))
  230 static bool allPhiOperandsUndefined(const MachineInstr &MPhi,
  247   MachineInstr *MPhi = MBB.remove(&*MBB.begin());
  262   MachineInstr *PHICopy = nullptr;
  301         if (MachineInstr *OldKill = VI.findKill(&MBB)) {
  399     MachineInstr *NewSrcInstr = nullptr;
  410         if (MachineInstr *DefMI = MRI->getVRegDef(SrcReg))
  553     for (const auto &BBI : MBB) {

   34   SmallPtrSet<MachineInstr*, 8> DefUsesInMBB;
   36   for (MachineInstr &RI : MRI.reg_instructions(SrcReg)) {

   41 static bool doesNotGeneratecode(const MachineInstr &MI) {

  187     bool optimizeCmpInstr(MachineInstr &MI);
  188     bool optimizeExtInstr(MachineInstr &MI, MachineBasicBlock &MBB,
  189                           SmallPtrSetImpl<MachineInstr*> &LocalMIs);
  190     bool optimizeSelect(MachineInstr &MI,
  191                         SmallPtrSetImpl<MachineInstr *> &LocalMIs);
  192     bool optimizeCondBranch(MachineInstr &MI);
  193     bool optimizeCoalescableCopy(MachineInstr &MI);
  194     bool optimizeUncoalescableCopy(MachineInstr &MI,
  195                                    SmallPtrSetImpl<MachineInstr *> &LocalMIs);
  196     bool optimizeRecurrence(MachineInstr &PHI);
  198     bool isMoveImmediate(MachineInstr &MI,
  200                          DenseMap<unsigned, MachineInstr*> &ImmDefMIs);
  201     bool foldImmediate(MachineInstr &MI, SmallSet<unsigned, 4> &ImmDefRegs,
  202                        DenseMap<unsigned, MachineInstr*> &ImmDefMIs);
  216     bool foldRedundantCopy(MachineInstr &MI,
  218                            DenseMap<unsigned, MachineInstr *> &CopyMIs);
  228     bool foldRedundantNAPhysCopy(MachineInstr &MI,
  229         DenseMap<unsigned, MachineInstr *> &NAPhysToVirtMIs);
  231     bool isLoadFoldable(MachineInstr &MI,
  236     bool isCoalescableCopy(const MachineInstr &MI) {
  246     bool isUncoalescableCopy(const MachineInstr &MI) {
  253     MachineInstr &rewriteSource(MachineInstr &CopyLike,
  253     MachineInstr &rewriteSource(MachineInstr &CopyLike,
  267     RecurrenceInstr(MachineInstr *MI) : MI(MI) {}
  268     RecurrenceInstr(MachineInstr *MI, unsigned Idx1, unsigned Idx2)
  271     MachineInstr *getMI() const { return MI; }
  275     MachineInstr *MI;
  288     const MachineInstr *Inst = nullptr;
  299     void setInst(const MachineInstr *I) { Inst = I; }
  300     const MachineInstr *getInst() const { return Inst; }
  366     const MachineInstr *Def = nullptr;
  457 optimizeExtInstr(MachineInstr &MI, MachineBasicBlock &MBB,
  458                  SmallPtrSetImpl<MachineInstr*> &LocalMIs) {
  489   for (MachineInstr &UI : MRI->use_nodbg_instructions(DstReg))
  500     MachineInstr *UseMI = UseMO.getParent();
  566     for (MachineInstr &UI : MRI->use_nodbg_instructions(DstReg))
  573       MachineInstr *UseMI = UseMO->getParent();
  585       MachineInstr *Copy = BuildMI(*UseMBB, UseMI, UseMI->getDebugLoc(),
  606 bool PeepholeOptimizer::optimizeCmpInstr(MachineInstr &MI) {
  626 bool PeepholeOptimizer::optimizeSelect(MachineInstr &MI,
  627                             SmallPtrSetImpl<MachineInstr *> &LocalMIs) {
  644 bool PeepholeOptimizer::optimizeCondBranch(MachineInstr &MI) {
  754 static MachineInstr &
  757           MachineInstr &OrigPHI) {
  788   MachineInstr &CopyLike;
  791   Rewriter(MachineInstr &CopyLike) : CopyLike(CopyLike) {}
  830   CopyRewriter(MachineInstr &MI) : Rewriter(MI) {
  868   UncoalescableRewriter(MachineInstr &MI) : Rewriter(MI) {
  905   InsertSubregRewriter(MachineInstr &MI) : Rewriter(MI) {
  957   ExtractSubregRewriter(MachineInstr &MI, const TargetInstrInfo &TII)
 1017   RegSequenceRewriter(MachineInstr &MI) : Rewriter(MI) {
 1084 static Rewriter *getCopyRewriter(MachineInstr &MI, const TargetInstrInfo &TII) {
 1144     MachineInstr &OrigPHI = const_cast<MachineInstr &>(*Res.getInst());
 1145     MachineInstr &NewPHI = insertPHI(*MRI, *TII, NewPHISrcs, OrigPHI);
 1167 bool PeepholeOptimizer::optimizeCoalescableCopy(MachineInstr &MI) {
 1221 MachineInstr &
 1222 PeepholeOptimizer::rewriteSource(MachineInstr &CopyLike,
 1234   MachineInstr *NewCopy =
 1269     MachineInstr &MI, SmallPtrSetImpl<MachineInstr *> &LocalMIs) {
 1269     MachineInstr &MI, SmallPtrSetImpl<MachineInstr *> &LocalMIs) {
 1297     MachineInstr &NewCopy = rewriteSource(MI, Def, RewriteMap);
 1311     MachineInstr &MI, SmallSet<unsigned, 16> &FoldAsLoadDefCandidates) {
 1331     MachineInstr &MI, SmallSet<unsigned, 4> &ImmDefRegs,
 1332     DenseMap<unsigned, MachineInstr *> &ImmDefMIs) {
 1351 bool PeepholeOptimizer::foldImmediate(MachineInstr &MI,
 1353     DenseMap<unsigned, MachineInstr *> &ImmDefMIs) {
 1366     DenseMap<unsigned, MachineInstr*>::iterator II = ImmDefMIs.find(Reg);
 1390 bool PeepholeOptimizer::foldRedundantCopy(MachineInstr &MI,
 1392     DenseMap<unsigned, MachineInstr *> &CopyMIs) {
 1409   MachineInstr *PrevCopy = CopyMIs.find(SrcReg)->second;
 1439     MachineInstr &MI, DenseMap<unsigned, MachineInstr *> &NAPhysToVirtMIs) {
 1439     MachineInstr &MI, DenseMap<unsigned, MachineInstr *> &NAPhysToVirtMIs) {
 1512   MachineInstr &MI = *(MRI->use_instr_nodbg_begin(Reg));
 1564 bool PeepholeOptimizer::optimizeRecurrence(MachineInstr &PHI) {
 1620     SmallPtrSet<MachineInstr*, 16> LocalMIs;
 1622     DenseMap<unsigned, MachineInstr*> ImmDefMIs;
 1630     DenseMap<unsigned, MachineInstr *> NAPhysToVirtMIs;
 1634     DenseMap<unsigned, MachineInstr *> CopySrcMIs;
 1640       MachineInstr *MI = &*MII;
 1768             MachineInstr *DefMI = nullptr;
 1769             if (MachineInstr *FoldMI =
 1867   for (const MachineInstr &UseMI : MRI.use_nodbg_instructions(DefOp.getReg())) {

   81     for (MachineInstr &MI : MBB) {

  180     void Observe(MachineInstr &MI, unsigned Count);
  337       MachineInstr &MI = *std::prev(I);
  426 void SchedulePostRATDList::Observe(MachineInstr &MI, unsigned Count) {
  693   for (std::vector<std::pair<MachineInstr *, MachineInstr *> >::iterator
  693   for (std::vector<std::pair<MachineInstr *, MachineInstr *> >::iterator
  695     std::pair<MachineInstr *, MachineInstr *> P = *std::prev(DI);
  695     std::pair<MachineInstr *, MachineInstr *> P = *std::prev(DI);
  696     MachineInstr *DbgValue = P.first;

   32   SmallSetVector<MachineInstr*, 16> WorkList;
   34   void processImplicitDef(MachineInstr *MI);
   35   bool canTurnIntoImplicitDef(MachineInstr *MI);
   62 bool ProcessImplicitDefs::canTurnIntoImplicitDef(MachineInstr *MI) {
   74 void ProcessImplicitDefs::processImplicitDef(MachineInstr *MI) {
   83       MachineInstr *UserMI = MO.getParent();

  173     SmallDenseMap<MachineBasicBlock *, SmallVector<MachineInstr *, 4>, 4>;
  180   SmallVector<const MachineInstr *, 4> FrameIndexValues;
  182   for (auto &MI : MBB) {
  208     for (auto *MI : EntryDbgValues[&MBB])
 1195     MachineInstr &MI = *I;

   95 void ReachingDefAnalysis::processDefs(MachineInstr *MI) {
  127   for (MachineInstr &MI : *TraversedMBB.MBB) {
  173 int ReachingDefAnalysis::getReachingDef(MachineInstr *MI, int PhysReg) {
  192 int ReachingDefAnalysis::getClearance(MachineInstr *MI, MCPhysReg PhysReg) {

  118       MachineInstr *MI = nullptr;

   75   SmallPtrSet<MachineInstr *, 32> DeadRemats;

   84       MachineInstr *LastUse = nullptr; ///< Last instr to use reg.
  102     DenseMap<unsigned, SmallVector<MachineInstr *, 2>> LiveDbgValueMap;
  132     SmallVector<MachineInstr *, 32> Coalesced;
  184     void allocateInstruction(MachineInstr &MI);
  185     void handleDebugValue(MachineInstr &MI);
  186     void handleThroughOperands(MachineInstr &MI,
  210     void allocVirtReg(MachineInstr &MI, LiveReg &LR, unsigned Hint);
  212     MCPhysReg defineVirtReg(MachineInstr &MI, unsigned OpNum, unsigned VirtReg,
  214     LiveReg &reloadVirtReg(MachineInstr &MI, unsigned OpNum, unsigned VirtReg,
  217     bool setPhysReg(MachineInstr &MI, MachineOperand &MO, MCPhysReg PhysReg);
  283   for (const MachineInstr &UseInst : MRI->reg_nodbg_instructions(VirtReg)) {
  302   for (const MachineInstr &DefInst : MRI->def_instructions(VirtReg)) {
  328   SmallVectorImpl<MachineInstr *> &LRIDbgValues = LiveDbgValueMap[VirtReg];
  329   for (MachineInstr *DBG : LRIDbgValues) {
  330     MachineInstr *NewDV = buildDbgValueForSpill(*MBB, Before, *DBG, FI);
  620 static bool isCoalescable(const MachineInstr &MI) {
  632     MachineInstr *VRegDef = MRI->getUniqueVRegDef(Reg);
  646   for (const MachineInstr &MI : MRI->def_instructions(VirtReg)) {
  661 void RegAllocFast::allocVirtReg(MachineInstr &MI, LiveReg &LR, unsigned Hint0) {
  777 MCPhysReg RegAllocFast::defineVirtReg(MachineInstr &MI, unsigned OpNum,
  787       const MachineInstr &UseMI = *MRI->use_instr_nodbg_begin(VirtReg);
  808 RegAllocFast::LiveReg &RegAllocFast::reloadVirtReg(MachineInstr &MI,
  855 bool RegAllocFast::setPhysReg(MachineInstr &MI, MachineOperand &MO,
  886 void RegAllocFast::handleThroughOperands(MachineInstr &MI,
 1012 void RegAllocFast::allocateInstruction(MachineInstr &MI) {
 1210 void RegAllocFast::handleDebugValue(MachineInstr &MI) {
 1263   for (MachineInstr &MI : MBB) {
 1285   for (MachineInstr *MI : Coalesced)

 1822   MachineInstr *MI = MRI->getUniqueVRegDef(VirtReg.reg);
 2065     const MachineInstr *MI, unsigned Reg, const TargetRegisterClass *SuperRC,
 2113     if (const MachineInstr *MI = Indexes->getInstructionFromIndex(Uses[i]))
 2873   for (const MachineInstr &Instr : MRI->reg_nodbg_instructions(Reg)) {
 3169       for (MachineInstr &MI : *MBB) {

  160   SmallPtrSet<MachineInstr *, 32> DeadRemats;
  446       for (const auto &MI : MBB) {

   64   static void setRegMask(MachineInstr &MI, ArrayRef<uint32_t> RegMask) {
   89                                           const MachineInstr &MI) {
  116     for (MachineInstr &MI : MBB) {

  150     SmallVector<MachineInstr*, 8> WorkList;
  151     SmallVector<MachineInstr*, 8> LocalWorkList;
  155     SmallPtrSet<MachineInstr*, 8> ErasedInstrs;
  158     SmallVector<MachineInstr*, 8> DeadDefs;
  176     void LRE_WillEraseInstruction(MachineInstr *MI) override;
  190     bool copyCoalesceWorkList(MutableArrayRef<MachineInstr*> CurrList);
  204     bool joinCopy(MachineInstr *CopyMI, bool &Again);
  239     bool adjustCopiesBackFrom(const CoalescerPair &CP, MachineInstr *CopyMI);
  255                                                   MachineInstr *CopyMI);
  258     bool removePartialRedundancy(const CoalescerPair &CP, MachineInstr &CopyMI);
  262     bool reMaterializeTrivialDef(const CoalescerPair &CP, MachineInstr *CopyMI,
  288     MachineInstr *eliminateUndefCopy(MachineInstr *CopyMI);
  288     MachineInstr *eliminateUndefCopy(MachineInstr *CopyMI);
  302     bool applyTerminalRule(const MachineInstr &Copy) const;
  308                       SmallVectorImpl<MachineInstr * > *Dead = nullptr) {
  322     void deleteInstr(MachineInstr* MI) {
  362                                        const MachineInstr *MI, unsigned &Src,
  390   for (const auto &MI : *MBB) {
  397 bool CoalescerPair::setRegisters(const MachineInstr *MI) {
  494 bool CoalescerPair::isCoalescable(const MachineInstr *MI) const {
  550 void RegisterCoalescer::LRE_WillEraseInstruction(MachineInstr *MI) {
  556                                              MachineInstr *CopyMI) {
  600   MachineInstr *ACopyMI = LIS->getInstructionFromIndex(AValNo->def);
  613   MachineInstr *ValSEndInst =
  739                                             MachineInstr *CopyMI) {
  778   MachineInstr *DefMI = LIS->getInstructionFromIndex(AValNo->def);
  817     MachineInstr *UseMI = MO.getParent();
  834   MachineInstr *NewMI =
  866     MachineInstr *UseMI = UseMO.getParent();
 1026                                                 MachineInstr &CopyMI) {
 1060     MachineInstr *DefMI = LIS->getInstructionFromIndex(PVal->def);
 1123     MachineInstr *NewCopyMI = BuildMI(*CopyLeftBB, InsPos, CopyMI.getDebugLoc(),
 1190 static bool definesFullReg(const MachineInstr &MI, unsigned Reg) {
 1205                                                 MachineInstr *CopyMI,
 1222   MachineInstr *DefMI = LIS->getInstructionFromIndex(ValNo->def);
 1282   MachineInstr &NewMI = *std::prev(MII);
 1481       MachineInstr *UseMI = UseMO.getParent();
 1514 MachineInstr *RegisterCoalescer::eliminateUndefCopy(MachineInstr *CopyMI) {
 1514 MachineInstr *RegisterCoalescer::eliminateUndefCopy(MachineInstr *CopyMI) {
 1590     const MachineInstr &MI = *MO.getParent();
 1662       MachineInstr &MI = *MO.getParent();
 1670   SmallPtrSet<MachineInstr*, 8> Visited;
 1674     MachineInstr *UseMI = &*(I++);
 1751 bool RegisterCoalescer::joinCopy(MachineInstr *CopyMI, bool &Again) {
 1790     if (MachineInstr *UndefMI = eliminateUndefCopy(CopyMI)) {
 2024   MachineInstr *CopyMI;
 2052     MachineInstr &DestMI = *MRI->getVRegDef(SrcReg);
 2064         MachineInstr *MI = LIS->getInstructionFromIndex(SI);
 2283   LaneBitmask computeWriteLanes(const MachineInstr *DefMI, bool &Redef) const;
 2325   bool usesLanes(const MachineInstr &MI, unsigned, unsigned, LaneBitmask) const;
 2377   void eraseInstrs(SmallPtrSetImpl<MachineInstr*> &ErasedInstrs,
 2390 LaneBitmask JoinVals::computeWriteLanes(const MachineInstr *DefMI, bool &Redef)
 2410     MachineInstr *MI = Indexes->getInstructionFromIndex(Def);
 2492   const MachineInstr *DefMI = nullptr;
 2823 bool JoinVals::usesLanes(const MachineInstr &MI, unsigned Reg, unsigned SubIdx,
 2876     MachineInstr *LastMI =
 3113 void JoinVals::eraseInstrs(SmallPtrSetImpl<MachineInstr*> &ErasedInstrs,
 3189       MachineInstr *MI = Indexes->getInstructionFromIndex(Def);
 3459 static bool isLocalCopy(MachineInstr *Copy, const LiveIntervals *LIS) {
 3489 copyCoalesceWorkList(MutableArrayRef<MachineInstr*> CurrList) {
 3511 static bool isTerminalReg(unsigned DstReg, const MachineInstr &Copy,
 3515   for (const MachineInstr &MI : MRI->reg_nodbg_instructions(DstReg))
 3521 bool RegisterCoalescer::applyTerminalRule(const MachineInstr &Copy) const {
 3540   for (const MachineInstr &MI : MRI->reg_nodbg_instructions(SrcReg)) {
 3577     SmallVector<MachineInstr*, 2> LocalTerminals;
 3578     SmallVector<MachineInstr*, 2> GlobalTerminals;
 3605     SmallVector<MachineInstr*, 2> Terminals;
 3606     for (MachineInstr &MII : *MBB)
 3619   MutableArrayRef<MachineInstr*>

   68     bool setRegisters(const MachineInstr*);
   76     bool isCoalescable(const MachineInstr*) const;

  480   void collectInstr(const MachineInstr &MI) const {
  489   void collectInstrLanes(const MachineInstr &MI) const {
  568 void RegisterOperands::collect(const MachineInstr &MI,
  579 void RegisterOperands::detectDeadDefs(const MachineInstr &MI,
  602                                           MachineInstr *AddFlagsMI) {
  881   const MachineInstr &MI = *CurrPos;
  947   const MachineInstr &MI = *CurrPos;
 1041 void RegPressureTracker::bumpUpwardPressure(const MachineInstr *MI) {
 1093 getMaxUpwardPressureDelta(const MachineInstr *MI, PressureDiff *PDiff,
 1161 getUpwardPressureDelta(const MachineInstr *MI, /*const*/ PressureDiff &PDiff,
 1230     const MachineInstr *MI = MO.getParent();
 1282 void RegPressureTracker::bumpDownwardPressure(const MachineInstr *MI) {
 1342 getMaxDownwardPressureDelta(const MachineInstr *MI, RegPressureDelta &Delta,
 1365 getUpwardPressure(const MachineInstr *MI,
 1381 getDownwardPressure(const MachineInstr *MI,

  112   MachineInstr &MI = *MBBI;
  159   MachineInstr &MI = *MBBI;
  186   MachineInstr &MI = *MBBI;
  263   const MachineInstr &MI = *MBBI;
  392     const MachineInstr &MI = *I;
  450 static unsigned getFrameIndexOperandNum(MachineInstr &MI) {
  537   MachineInstr &MI = *I;
  630   const MachineInstr *RealDef = nullptr;
  637       const MachineInstr &MI = *MO.getParent();
  661   MachineInstr &DefMI = *FirstDef->getParent();
  693       const MachineInstr &NMI = *N;
  715     const MachineInstr &MI = *I;

  221     auto *MI = MO.getParent();

  127 static bool getUnderlyingObjectsForInstr(const MachineInstr *MI,
  201   MachineInstr *ExitMI = RegionEnd != BB->end() ? &*RegionEnd : nullptr;
  253       MachineInstr *RegUse = nullptr;
  285   MachineInstr *MI = SU->getInstr();
  389   MachineInstr *MI = SU->getInstr();
  438         MachineInstr *Use = UseSU->getInstr();
  509   const MachineInstr *MI = SU->getInstr();
  534 static inline bool isGlobalMemoryObject(AAResults *AA, MachineInstr *MI) {
  565   for (MachineInstr &MI : make_range(RegionBegin, RegionEnd)) {
  792   MachineInstr *DbgMI = nullptr;
  795     MachineInstr &MI = *std::prev(MII);
 1087                         MachineInstr &MI, bool addToLiveRegs) {
 1110   for (MachineInstr &MI : make_range(MBB.rbegin(), MBB.rend())) {