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| /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|* *|
|* Subtarget Enumeration Source Fragment *|
|* *|
|* Automatically generated file, do not edit! *|
|* *|
\*===----------------------------------------------------------------------===*/
#ifdef GET_SUBTARGETINFO_ENUM
#undef GET_SUBTARGETINFO_ENUM
namespace llvm {
namespace RISCV {
enum {
Feature64Bit = 0,
FeatureRV32E = 1,
FeatureRVCHints = 2,
FeatureRelax = 3,
FeatureReserveX1 = 4,
FeatureReserveX2 = 5,
FeatureReserveX3 = 6,
FeatureReserveX4 = 7,
FeatureReserveX5 = 8,
FeatureReserveX6 = 9,
FeatureReserveX7 = 10,
FeatureReserveX8 = 11,
FeatureReserveX9 = 12,
FeatureReserveX10 = 13,
FeatureReserveX11 = 14,
FeatureReserveX12 = 15,
FeatureReserveX13 = 16,
FeatureReserveX14 = 17,
FeatureReserveX15 = 18,
FeatureReserveX16 = 19,
FeatureReserveX17 = 20,
FeatureReserveX18 = 21,
FeatureReserveX19 = 22,
FeatureReserveX20 = 23,
FeatureReserveX21 = 24,
FeatureReserveX22 = 25,
FeatureReserveX23 = 26,
FeatureReserveX24 = 27,
FeatureReserveX25 = 28,
FeatureReserveX26 = 29,
FeatureReserveX27 = 30,
FeatureReserveX28 = 31,
FeatureReserveX29 = 32,
FeatureReserveX30 = 33,
FeatureReserveX31 = 34,
FeatureStdExtA = 35,
FeatureStdExtC = 36,
FeatureStdExtD = 37,
FeatureStdExtF = 38,
FeatureStdExtM = 39,
NumSubtargetFeatures = 40
};
} // end namespace RISCV
} // end namespace llvm
#endif // GET_SUBTARGETINFO_ENUM
#ifdef GET_SUBTARGETINFO_MC_DESC
#undef GET_SUBTARGETINFO_MC_DESC
namespace llvm {
// Sorted (by key) array of values for CPU features.
extern const llvm::SubtargetFeatureKV RISCVFeatureKV[] = {
{ "64bit", "Implements RV64", RISCV::Feature64Bit, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } },
{ "a", "'A' (Atomic Instructions)", RISCV::FeatureStdExtA, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } },
{ "c", "'C' (Compressed Instructions)", RISCV::FeatureStdExtC, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } },
{ "d", "'D' (Double-Precision Floating-Point)", RISCV::FeatureStdExtD, { { { 0x4000000000ULL, 0x0ULL, 0x0ULL, } } } },
{ "e", "Implements RV32E (provides 16 rather than 32 GPRs)", RISCV::FeatureRV32E, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } },
{ "f", "'F' (Single-Precision Floating-Point)", RISCV::FeatureStdExtF, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } },
{ "m", "'M' (Integer Multiplication and Division)", RISCV::FeatureStdExtM, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } },
{ "relax", "Enable Linker relaxation.", RISCV::FeatureRelax, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } },
{ "reserve-x1", "Reserve X1", RISCV::FeatureReserveX1, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } },
{ "reserve-x10", "Reserve X10", RISCV::FeatureReserveX10, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } },
{ "reserve-x11", "Reserve X11", RISCV::FeatureReserveX11, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } },
{ "reserve-x12", "Reserve X12", RISCV::FeatureReserveX12, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } },
{ "reserve-x13", "Reserve X13", RISCV::FeatureReserveX13, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } },
{ "reserve-x14", "Reserve X14", RISCV::FeatureReserveX14, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } },
{ "reserve-x15", "Reserve X15", RISCV::FeatureReserveX15, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } },
{ "reserve-x16", "Reserve X16", RISCV::FeatureReserveX16, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } },
{ "reserve-x17", "Reserve X17", RISCV::FeatureReserveX17, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } },
{ "reserve-x18", "Reserve X18", RISCV::FeatureReserveX18, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } },
{ "reserve-x19", "Reserve X19", RISCV::FeatureReserveX19, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } },
{ "reserve-x2", "Reserve X2", RISCV::FeatureReserveX2, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } },
{ "reserve-x20", "Reserve X20", RISCV::FeatureReserveX20, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } },
{ "reserve-x21", "Reserve X21", RISCV::FeatureReserveX21, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } },
{ "reserve-x22", "Reserve X22", RISCV::FeatureReserveX22, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } },
{ "reserve-x23", "Reserve X23", RISCV::FeatureReserveX23, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } },
{ "reserve-x24", "Reserve X24", RISCV::FeatureReserveX24, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } },
{ "reserve-x25", "Reserve X25", RISCV::FeatureReserveX25, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } },
{ "reserve-x26", "Reserve X26", RISCV::FeatureReserveX26, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } },
{ "reserve-x27", "Reserve X27", RISCV::FeatureReserveX27, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } },
{ "reserve-x28", "Reserve X28", RISCV::FeatureReserveX28, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } },
{ "reserve-x29", "Reserve X29", RISCV::FeatureReserveX29, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } },
{ "reserve-x3", "Reserve X3", RISCV::FeatureReserveX3, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } },
{ "reserve-x30", "Reserve X30", RISCV::FeatureReserveX30, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } },
{ "reserve-x31", "Reserve X31", RISCV::FeatureReserveX31, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } },
{ "reserve-x4", "Reserve X4", RISCV::FeatureReserveX4, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } },
{ "reserve-x5", "Reserve X5", RISCV::FeatureReserveX5, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } },
{ "reserve-x6", "Reserve X6", RISCV::FeatureReserveX6, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } },
{ "reserve-x7", "Reserve X7", RISCV::FeatureReserveX7, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } },
{ "reserve-x8", "Reserve X8", RISCV::FeatureReserveX8, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } },
{ "reserve-x9", "Reserve X9", RISCV::FeatureReserveX9, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } },
{ "rvc-hints", "Enable RVC Hint Instructions.", RISCV::FeatureRVCHints, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } },
};
#ifdef DBGFIELD
#error "<target>GenSubtargetInfo.inc requires a DBGFIELD macro"
#endif
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
#define DBGFIELD(x) x,
#else
#define DBGFIELD(x)
#endif
// ===============================================================
// Data tables for the new per-operand machine model.
// {ProcResourceIdx, Cycles}
extern const llvm::MCWriteProcResEntry RISCVWriteProcResTable[] = {
{ 0, 0}, // Invalid
}; // RISCVWriteProcResTable
// {Cycles, WriteResourceID}
extern const llvm::MCWriteLatencyEntry RISCVWriteLatencyTable[] = {
{ 0, 0}, // Invalid
}; // RISCVWriteLatencyTable
// {UseIdx, WriteResourceID, Cycles}
extern const llvm::MCReadAdvanceEntry RISCVReadAdvanceTable[] = {
{0, 0, 0}, // Invalid
}; // RISCVReadAdvanceTable
#undef DBGFIELD
static const llvm::MCSchedModel NoSchedModel = {
MCSchedModel::DefaultIssueWidth,
MCSchedModel::DefaultMicroOpBufferSize,
MCSchedModel::DefaultLoopMicroOpBufferSize,
MCSchedModel::DefaultLoadLatency,
MCSchedModel::DefaultHighLatency,
MCSchedModel::DefaultMispredictPenalty,
false, // PostRAScheduler
false, // CompleteModel
0, // Processor ID
nullptr, nullptr, 0, 0, // No instruction-level machine model.
nullptr, // No Itinerary
nullptr // No extra processor descriptor
};
// Sorted (by key) array of values for CPU subtype.
extern const llvm::SubtargetSubTypeKV RISCVSubTypeKV[] = {
{ "generic-rv32", { { { 0x4ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
{ "generic-rv64", { { { 0x5ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
};
namespace RISCV_MC {
unsigned resolveVariantSchedClassImpl(unsigned SchedClass,
const MCInst *MI, unsigned CPUID) {
// Don't know how to resolve this scheduling class.
return 0;
}
} // end namespace RISCV_MC
struct RISCVGenMCSubtargetInfo : public MCSubtargetInfo {
RISCVGenMCSubtargetInfo(const Triple &TT,
StringRef CPU, StringRef FS, ArrayRef<SubtargetFeatureKV> PF,
ArrayRef<SubtargetSubTypeKV> PD,
const MCWriteProcResEntry *WPR,
const MCWriteLatencyEntry *WL,
const MCReadAdvanceEntry *RA, const InstrStage *IS,
const unsigned *OC, const unsigned *FP) :
MCSubtargetInfo(TT, CPU, FS, PF, PD,
WPR, WL, RA, IS, OC, FP) { }
unsigned resolveVariantSchedClass(unsigned SchedClass,
const MCInst *MI, unsigned CPUID) const override {
return RISCV_MC::resolveVariantSchedClassImpl(SchedClass, MI, CPUID);
}
unsigned getHwMode() const override;
};
unsigned RISCVGenMCSubtargetInfo::getHwMode() const {
if (checkFeatures("-64bit")) return 1;
if (checkFeatures("+64bit")) return 2;
return 0;
}
static inline MCSubtargetInfo *createRISCVMCSubtargetInfoImpl(const Triple &TT, StringRef CPU, StringRef FS) {
return new RISCVGenMCSubtargetInfo(TT, CPU, FS, RISCVFeatureKV, RISCVSubTypeKV,
RISCVWriteProcResTable, RISCVWriteLatencyTable, RISCVReadAdvanceTable,
nullptr, nullptr, nullptr);
}
} // end namespace llvm
#endif // GET_SUBTARGETINFO_MC_DESC
#ifdef GET_SUBTARGETINFO_TARGET_DESC
#undef GET_SUBTARGETINFO_TARGET_DESC
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
// ParseSubtargetFeatures - Parses features string setting specified
// subtarget options.
void llvm::RISCVSubtarget::ParseSubtargetFeatures(StringRef CPU, StringRef FS) {
LLVM_DEBUG(dbgs() << "\nFeatures:" << FS);
LLVM_DEBUG(dbgs() << "\nCPU:" << CPU << "\n\n");
InitMCProcessorInfo(CPU, FS);
const FeatureBitset& Bits = getFeatureBits();
if (Bits[RISCV::Feature64Bit]) HasRV64 = true;
if (Bits[RISCV::FeatureRV32E]) IsRV32E = true;
if (Bits[RISCV::FeatureRVCHints]) EnableRVCHintInstrs = true;
if (Bits[RISCV::FeatureRelax]) EnableLinkerRelax = true;
if (Bits[RISCV::FeatureReserveX1]) UserReservedRegister[RISCV::X1] = true;
if (Bits[RISCV::FeatureReserveX2]) UserReservedRegister[RISCV::X2] = true;
if (Bits[RISCV::FeatureReserveX3]) UserReservedRegister[RISCV::X3] = true;
if (Bits[RISCV::FeatureReserveX4]) UserReservedRegister[RISCV::X4] = true;
if (Bits[RISCV::FeatureReserveX5]) UserReservedRegister[RISCV::X5] = true;
if (Bits[RISCV::FeatureReserveX6]) UserReservedRegister[RISCV::X6] = true;
if (Bits[RISCV::FeatureReserveX7]) UserReservedRegister[RISCV::X7] = true;
if (Bits[RISCV::FeatureReserveX8]) UserReservedRegister[RISCV::X8] = true;
if (Bits[RISCV::FeatureReserveX9]) UserReservedRegister[RISCV::X9] = true;
if (Bits[RISCV::FeatureReserveX10]) UserReservedRegister[RISCV::X10] = true;
if (Bits[RISCV::FeatureReserveX11]) UserReservedRegister[RISCV::X11] = true;
if (Bits[RISCV::FeatureReserveX12]) UserReservedRegister[RISCV::X12] = true;
if (Bits[RISCV::FeatureReserveX13]) UserReservedRegister[RISCV::X13] = true;
if (Bits[RISCV::FeatureReserveX14]) UserReservedRegister[RISCV::X14] = true;
if (Bits[RISCV::FeatureReserveX15]) UserReservedRegister[RISCV::X15] = true;
if (Bits[RISCV::FeatureReserveX16]) UserReservedRegister[RISCV::X16] = true;
if (Bits[RISCV::FeatureReserveX17]) UserReservedRegister[RISCV::X17] = true;
if (Bits[RISCV::FeatureReserveX18]) UserReservedRegister[RISCV::X18] = true;
if (Bits[RISCV::FeatureReserveX19]) UserReservedRegister[RISCV::X19] = true;
if (Bits[RISCV::FeatureReserveX20]) UserReservedRegister[RISCV::X20] = true;
if (Bits[RISCV::FeatureReserveX21]) UserReservedRegister[RISCV::X21] = true;
if (Bits[RISCV::FeatureReserveX22]) UserReservedRegister[RISCV::X22] = true;
if (Bits[RISCV::FeatureReserveX23]) UserReservedRegister[RISCV::X23] = true;
if (Bits[RISCV::FeatureReserveX24]) UserReservedRegister[RISCV::X24] = true;
if (Bits[RISCV::FeatureReserveX25]) UserReservedRegister[RISCV::X25] = true;
if (Bits[RISCV::FeatureReserveX26]) UserReservedRegister[RISCV::X26] = true;
if (Bits[RISCV::FeatureReserveX27]) UserReservedRegister[RISCV::X27] = true;
if (Bits[RISCV::FeatureReserveX28]) UserReservedRegister[RISCV::X28] = true;
if (Bits[RISCV::FeatureReserveX29]) UserReservedRegister[RISCV::X29] = true;
if (Bits[RISCV::FeatureReserveX30]) UserReservedRegister[RISCV::X30] = true;
if (Bits[RISCV::FeatureReserveX31]) UserReservedRegister[RISCV::X31] = true;
if (Bits[RISCV::FeatureStdExtA]) HasStdExtA = true;
if (Bits[RISCV::FeatureStdExtC]) HasStdExtC = true;
if (Bits[RISCV::FeatureStdExtD]) HasStdExtD = true;
if (Bits[RISCV::FeatureStdExtF]) HasStdExtF = true;
if (Bits[RISCV::FeatureStdExtM]) HasStdExtM = true;
}
#endif // GET_SUBTARGETINFO_TARGET_DESC
#ifdef GET_SUBTARGETINFO_HEADER
#undef GET_SUBTARGETINFO_HEADER
namespace llvm {
class DFAPacketizer;
namespace RISCV_MC {
unsigned resolveVariantSchedClassImpl(unsigned SchedClass, const MCInst *MI, unsigned CPUID);
} // end namespace RISCV_MC
struct RISCVGenSubtargetInfo : public TargetSubtargetInfo {
explicit RISCVGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS);
public:
unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const override;
unsigned resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, unsigned CPUID) const override;
DFAPacketizer *createDFAPacketizer(const InstrItineraryData *IID) const;
unsigned getHwMode() const override;
};
} // end namespace llvm
#endif // GET_SUBTARGETINFO_HEADER
#ifdef GET_SUBTARGETINFO_CTOR
#undef GET_SUBTARGETINFO_CTOR
#include "llvm/CodeGen/TargetSchedule.h"
namespace llvm {
extern const llvm::SubtargetFeatureKV RISCVFeatureKV[];
extern const llvm::SubtargetSubTypeKV RISCVSubTypeKV[];
extern const llvm::MCWriteProcResEntry RISCVWriteProcResTable[];
extern const llvm::MCWriteLatencyEntry RISCVWriteLatencyTable[];
extern const llvm::MCReadAdvanceEntry RISCVReadAdvanceTable[];
RISCVGenSubtargetInfo::RISCVGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS)
: TargetSubtargetInfo(TT, CPU, FS, makeArrayRef(RISCVFeatureKV, 40), makeArrayRef(RISCVSubTypeKV, 2),
RISCVWriteProcResTable, RISCVWriteLatencyTable, RISCVReadAdvanceTable,
nullptr, nullptr, nullptr) {}
unsigned RISCVGenSubtargetInfo
::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {
report_fatal_error("Expected a variant SchedClass");
} // RISCVGenSubtargetInfo::resolveSchedClass
unsigned RISCVGenSubtargetInfo
::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, unsigned CPUID) const {
return RISCV_MC::resolveVariantSchedClassImpl(SchedClass, MI, CPUID);
} // RISCVGenSubtargetInfo::resolveVariantSchedClass
unsigned RISCVGenSubtargetInfo::getHwMode() const {
if (checkFeatures("-64bit")) return 1;
if (checkFeatures("+64bit")) return 2;
return 0;
}
} // end namespace llvm
#endif // GET_SUBTARGETINFO_CTOR
#ifdef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
#undef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
#endif // GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
#ifdef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
#undef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
#endif // GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
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