/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|* *|
|* Global Instruction Selector for the AMDGPU target *|
|* *|
|* Automatically generated file, do not edit! *|
|* *|
\*===----------------------------------------------------------------------===*/
#ifdef GET_GLOBALISEL_PREDICATE_BITSET
const unsigned MAX_SUBTARGET_PREDICATES = 44;
using PredicateBitset = llvm::PredicateBitsetImpl<MAX_SUBTARGET_PREDICATES>;
#endif // ifdef GET_GLOBALISEL_PREDICATE_BITSET
#ifdef GET_GLOBALISEL_TEMPORARIES_DECL
mutable MatcherState State;
typedef ComplexRendererFns(AMDGPUInstructionSelector::*ComplexMatcherMemFn)(MachineOperand &) const;
typedef void(AMDGPUInstructionSelector::*CustomRendererFn)(MachineInstrBuilder &, const MachineInstr&) const;
const ISelInfoTy<PredicateBitset, ComplexMatcherMemFn, CustomRendererFn> ISelInfo;
static AMDGPUInstructionSelector::ComplexMatcherMemFn ComplexPredicateFns[];
static AMDGPUInstructionSelector::CustomRendererFn CustomRenderers[];
bool testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const override;
bool testImmPredicate_APInt(unsigned PredicateID, const APInt &Imm) const override;
bool testImmPredicate_APFloat(unsigned PredicateID, const APFloat &Imm) const override;
const int64_t *getMatchTable() const override;
bool testMIPredicate_MI(unsigned PredicateID, const MachineInstr &MI) const override;
#endif // ifdef GET_GLOBALISEL_TEMPORARIES_DECL
#ifdef GET_GLOBALISEL_TEMPORARIES_INIT
, State(3),
ISelInfo(TypeObjects, NumTypeObjects, FeatureBitsets, ComplexPredicateFns, CustomRenderers)
#endif // ifdef GET_GLOBALISEL_TEMPORARIES_INIT
#ifdef GET_GLOBALISEL_IMPL
// Bits for subtarget features that participate in instruction matching.
enum SubtargetFeatureBits : uint8_t {
Feature_isGFX6Bit = 13,
Feature_isGFX6GFX7Bit = 2,
Feature_isGFX6GFX7GFX10Bit = 5,
Feature_isGFX7OnlyBit = 28,
Feature_isGFX7GFX8GFX9Bit = 9,
Feature_isGFX6GFX7GFX8GFX9Bit = 19,
Feature_isGFX7PlusBit = 4,
Feature_isGFX8PlusBit = 0,
Feature_isGFX8OnlyBit = 6,
Feature_isGFX9PlusBit = 7,
Feature_isGFX10PlusBit = 1,
Feature_HasFlatAddressSpaceBit = 11,
Feature_HasFlatGlobalInstsBit = 12,
Feature_HasUnpackedD16VMemBit = 30,
Feature_HasPackedD16VMemBit = 31,
Feature_D16PreservesUnusedBitsBit = 29,
Feature_LDSRequiresM0InitBit = 42,
Feature_NotLDSRequiresM0InitBit = 43,
Feature_HasAddNoCarryInstsBit = 18,
Feature_Has16BitInstsBit = 3,
Feature_HasVOP3PInstsBit = 34,
Feature_HasMadMixInstsBit = 24,
Feature_HasScalarStoresBit = 10,
Feature_has16BankLDSBit = 15,
Feature_has32BankLDSBit = 14,
Feature_HasFmaMixInstsBit = 25,
Feature_HasDLInstsBit = 41,
Feature_HasDot1InstsBit = 27,
Feature_HasDot2InstsBit = 26,
Feature_HasDot3InstsBit = 23,
Feature_HasDot4InstsBit = 22,
Feature_HasDot5InstsBit = 20,
Feature_HasDot6InstsBit = 21,
Feature_HasMAIInstsBit = 8,
Feature_EnableLateCFGStructurizeBit = 16,
Feature_FP16DenormalsBit = 36,
Feature_FP32DenormalsBit = 38,
Feature_FP64DenormalsBit = 40,
Feature_NoFP16DenormalsBit = 35,
Feature_NoFP32DenormalsBit = 37,
Feature_NoFP64DenormalsBit = 39,
Feature_UnsafeFPMathBit = 33,
Feature_isWave32Bit = 32,
Feature_isWave64Bit = 17,
};
PredicateBitset AMDGPUInstructionSelector::
computeAvailableModuleFeatures(const AMDGPUSubtarget *Subtarget) const {
PredicateBitset Features;
if (Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS)
Features.set(Feature_isGFX6Bit);
if (Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS)
Features.set(Feature_isGFX6GFX7Bit);
if (Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||Subtarget->getGeneration() == AMDGPUSubtarget::GFX10)
Features.set(Feature_isGFX6GFX7GFX10Bit);
if (Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS)
Features.set(Feature_isGFX7OnlyBit);
if (Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||Subtarget->getGeneration() == AMDGPUSubtarget::GFX9)
Features.set(Feature_isGFX7GFX8GFX9Bit);
if (Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||Subtarget->getGeneration() == AMDGPUSubtarget::GFX9)
Features.set(Feature_isGFX6GFX7GFX8GFX9Bit);
if (Subtarget->getGeneration() >= AMDGPUSubtarget::SEA_ISLANDS)
Features.set(Feature_isGFX7PlusBit);
if (Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS)
Features.set(Feature_isGFX8PlusBit);
if (Subtarget->getGeneration() ==AMDGPUSubtarget::VOLCANIC_ISLANDS)
Features.set(Feature_isGFX8OnlyBit);
if (Subtarget->getGeneration() >= AMDGPUSubtarget::GFX9)
Features.set(Feature_isGFX9PlusBit);
if (Subtarget->getGeneration() >= AMDGPUSubtarget::GFX10)
Features.set(Feature_isGFX10PlusBit);
if (Subtarget->hasFlatAddressSpace())
Features.set(Feature_HasFlatAddressSpaceBit);
if (Subtarget->hasFlatGlobalInsts())
Features.set(Feature_HasFlatGlobalInstsBit);
if (Subtarget->hasUnpackedD16VMem())
Features.set(Feature_HasUnpackedD16VMemBit);
if (!Subtarget->hasUnpackedD16VMem())
Features.set(Feature_HasPackedD16VMemBit);
if (Subtarget->d16PreservesUnusedBits())
Features.set(Feature_D16PreservesUnusedBitsBit);
if (Subtarget->ldsRequiresM0Init())
Features.set(Feature_LDSRequiresM0InitBit);
if (!Subtarget->ldsRequiresM0Init())
Features.set(Feature_NotLDSRequiresM0InitBit);
if (Subtarget->hasAddNoCarry())
Features.set(Feature_HasAddNoCarryInstsBit);
if (Subtarget->has16BitInsts())
Features.set(Feature_Has16BitInstsBit);
if (Subtarget->hasVOP3PInsts())
Features.set(Feature_HasVOP3PInstsBit);
if (Subtarget->hasMadMixInsts())
Features.set(Feature_HasMadMixInstsBit);
if (Subtarget->hasScalarStores())
Features.set(Feature_HasScalarStoresBit);
if (Subtarget->getLDSBankCount() == 16)
Features.set(Feature_has16BankLDSBit);
if (Subtarget->getLDSBankCount() == 32)
Features.set(Feature_has32BankLDSBit);
if (Subtarget->hasFmaMixInsts())
Features.set(Feature_HasFmaMixInstsBit);
if (Subtarget->hasDLInsts())
Features.set(Feature_HasDLInstsBit);
if (Subtarget->hasDot1Insts())
Features.set(Feature_HasDot1InstsBit);
if (Subtarget->hasDot2Insts())
Features.set(Feature_HasDot2InstsBit);
if (Subtarget->hasDot3Insts())
Features.set(Feature_HasDot3InstsBit);
if (Subtarget->hasDot4Insts())
Features.set(Feature_HasDot4InstsBit);
if (Subtarget->hasDot5Insts())
Features.set(Feature_HasDot5InstsBit);
if (Subtarget->hasDot6Insts())
Features.set(Feature_HasDot6InstsBit);
if (Subtarget->hasMAIInsts())
Features.set(Feature_HasMAIInstsBit);
if (EnableLateStructurizeCFG)
Features.set(Feature_EnableLateCFGStructurizeBit);
if (Subtarget->hasFP16Denormals())
Features.set(Feature_FP16DenormalsBit);
if (Subtarget->hasFP32Denormals())
Features.set(Feature_FP32DenormalsBit);
if (Subtarget->hasFP64Denormals())
Features.set(Feature_FP64DenormalsBit);
if (!Subtarget->hasFP16Denormals())
Features.set(Feature_NoFP16DenormalsBit);
if (!Subtarget->hasFP32Denormals())
Features.set(Feature_NoFP32DenormalsBit);
if (!Subtarget->hasFP64Denormals())
Features.set(Feature_NoFP64DenormalsBit);
if (TM.Options.UnsafeFPMath)
Features.set(Feature_UnsafeFPMathBit);
if (Subtarget->getWavefrontSize() == 32)
Features.set(Feature_isWave32Bit);
if (Subtarget->getWavefrontSize() == 64)
Features.set(Feature_isWave64Bit);
return Features;
}
PredicateBitset AMDGPUInstructionSelector::
computeAvailableFunctionFeatures(const AMDGPUSubtarget *Subtarget, const MachineFunction *MF) const {
PredicateBitset Features;
return Features;
}
// LLT Objects.
enum {
GILLT_p0s64,
GILLT_p1s64,
GILLT_p2s32,
GILLT_p3s32,
GILLT_p4s64,
GILLT_p5s32,
GILLT_p6s32,
GILLT_s1,
GILLT_s16,
GILLT_s32,
GILLT_s64,
GILLT_v2s16,
GILLT_v2s32,
GILLT_v2s64,
GILLT_v3s32,
GILLT_v4s16,
GILLT_v4s32,
GILLT_v5s32,
GILLT_v8s32,
GILLT_v16s32,
GILLT_v32s32,
};
const static size_t NumTypeObjects = 21;
const static LLT TypeObjects[] = {
LLT::pointer(0, 64),
LLT::pointer(1, 64),
LLT::pointer(2, 32),
LLT::pointer(3, 32),
LLT::pointer(4, 64),
LLT::pointer(5, 32),
LLT::pointer(6, 32),
LLT::scalar(1),
LLT::scalar(16),
LLT::scalar(32),
LLT::scalar(64),
LLT::vector(2, 16),
LLT::vector(2, 32),
LLT::vector(2, 64),
LLT::vector(3, 32),
LLT::vector(4, 16),
LLT::vector(4, 32),
LLT::vector(5, 32),
LLT::vector(8, 32),
LLT::vector(16, 32),
LLT::vector(32, 32),
};
// Feature bitsets.
enum {
GIFBS_Invalid,
GIFBS_FP16Denormals,
GIFBS_FP32Denormals,
GIFBS_FP64Denormals,
GIFBS_Has16BitInsts,
GIFBS_HasFlatAddressSpace,
GIFBS_HasFlatGlobalInsts,
GIFBS_HasMAIInsts,
GIFBS_LDSRequiresM0Init,
GIFBS_NoFP16Denormals,
GIFBS_NoFP32Denormals,
GIFBS_NoFP64Denormals,
GIFBS_NotLDSRequiresM0Init,
GIFBS_has16BankLDS,
GIFBS_has32BankLDS,
GIFBS_isGFX10Plus,
GIFBS_isGFX6,
GIFBS_isGFX6GFX7,
GIFBS_isGFX6GFX7GFX10,
GIFBS_isGFX7GFX8GFX9,
GIFBS_isGFX7Only,
GIFBS_isGFX7Plus,
GIFBS_isGFX8Plus,
GIFBS_isGFX9Plus,
GIFBS_isWave64,
GIFBS_Has16BitInsts_isGFX6GFX7GFX8GFX9,
GIFBS_Has16BitInsts_isGFX8Only,
GIFBS_Has16BitInsts_isGFX9Plus,
GIFBS_HasScalarStores_isGFX8Plus,
};
const static PredicateBitset FeatureBitsets[] {
{}, // GIFBS_Invalid
{Feature_FP16DenormalsBit, },
{Feature_FP32DenormalsBit, },
{Feature_FP64DenormalsBit, },
{Feature_Has16BitInstsBit, },
{Feature_HasFlatAddressSpaceBit, },
{Feature_HasFlatGlobalInstsBit, },
{Feature_HasMAIInstsBit, },
{Feature_LDSRequiresM0InitBit, },
{Feature_NoFP16DenormalsBit, },
{Feature_NoFP32DenormalsBit, },
{Feature_NoFP64DenormalsBit, },
{Feature_NotLDSRequiresM0InitBit, },
{Feature_has16BankLDSBit, },
{Feature_has32BankLDSBit, },
{Feature_isGFX10PlusBit, },
{Feature_isGFX6Bit, },
{Feature_isGFX6GFX7Bit, },
{Feature_isGFX6GFX7GFX10Bit, },
{Feature_isGFX7GFX8GFX9Bit, },
{Feature_isGFX7OnlyBit, },
{Feature_isGFX7PlusBit, },
{Feature_isGFX8PlusBit, },
{Feature_isGFX9PlusBit, },
{Feature_isWave64Bit, },
{Feature_Has16BitInstsBit, Feature_isGFX6GFX7GFX8GFX9Bit, },
{Feature_Has16BitInstsBit, Feature_isGFX8OnlyBit, },
{Feature_Has16BitInstsBit, Feature_isGFX9PlusBit, },
{Feature_HasScalarStoresBit, Feature_isGFX8PlusBit, },
};
// ComplexPattern predicates.
enum {
GICP_Invalid,
GICP_gi_ds_1addr_1offset,
GICP_gi_flat_atomic,
GICP_gi_flat_offset,
GICP_gi_flat_offset_signed,
GICP_gi_flat_signed_atomic,
GICP_gi_mubuf_scratch_offen,
GICP_gi_mubuf_scratch_offset,
GICP_gi_smrd_imm,
GICP_gi_smrd_imm32,
GICP_gi_smrd_sgpr,
GICP_gi_vcsrc,
GICP_gi_vop3mods,
GICP_gi_vop3mods0,
GICP_gi_vop3omods,
GICP_gi_vop3omods0clamp0omod,
GICP_gi_vop3opselmods,
GICP_gi_vop3opselmods0,
GICP_gi_vsrc0,
};
// See constructor for table contents
// PatFrag predicates.
enum {
GIPFP_I64_Predicate_NegSubInlineConst16 = GIPFP_I64_Invalid + 1,
GIPFP_I64_Predicate_NegSubInlineConst32,
GIPFP_I64_Predicate_SIMM16bit,
GIPFP_I64_Predicate_UIMM16bit,
GIPFP_I64_Predicate_i64imm_32bit,
};
bool AMDGPUInstructionSelector::testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const {
switch (PredicateID) {
case GIPFP_I64_Predicate_NegSubInlineConst16: {
return Imm < -16 && Imm >= -64;
llvm_unreachable("ImmediateCode should have returned");
return false;
}
case GIPFP_I64_Predicate_NegSubInlineConst32: {
return Imm < -16 && Imm >= -64;
llvm_unreachable("ImmediateCode should have returned");
return false;
}
case GIPFP_I64_Predicate_SIMM16bit: {
return isInt<16>(Imm);
llvm_unreachable("ImmediateCode should have returned");
return false;
}
case GIPFP_I64_Predicate_UIMM16bit: {
return isUInt<16>(Imm);
llvm_unreachable("ImmediateCode should have returned");
return false;
}
case GIPFP_I64_Predicate_i64imm_32bit: {
return (Imm & 0xffffffffULL) == static_cast<uint64_t>(Imm);
llvm_unreachable("ImmediateCode should have returned");
return false;
}
}
llvm_unreachable("Unknown predicate");
return false;
}
bool AMDGPUInstructionSelector::testImmPredicate_APFloat(unsigned PredicateID, const APFloat & Imm) const {
llvm_unreachable("Unknown predicate");
return false;
}
bool AMDGPUInstructionSelector::testImmPredicate_APInt(unsigned PredicateID, const APInt & Imm) const {
llvm_unreachable("Unknown predicate");
return false;
}
// PatFrag predicates.
enum {
GIPFP_MI_Predicate_smrd_load = GIPFP_MI_Invalid + 1,
};
bool AMDGPUInstructionSelector::testMIPredicate_MI(unsigned PredicateID, const MachineInstr & MI) const {
const MachineFunction &MF = *MI.getParent()->getParent();
const MachineRegisterInfo &MRI = MF.getRegInfo();
(void)MRI;
switch (PredicateID) {
case GIPFP_MI_Predicate_smrd_load: {
if (!MI.hasOneMemOperand())
return false;
if (!isInstrUniform(MI))
return false;
// FIXME: We should probably be caching this.
SmallVector<GEPInfo, 4> AddrInfo;
getAddrModeInfo(MI, MRI, AddrInfo);
if (hasVgprParts(AddrInfo))
return false;
return true;
llvm_unreachable("GISelPredicateCode should have returned");
return false;
}
}
llvm_unreachable("Unknown predicate");
return false;
}
AMDGPUInstructionSelector::ComplexMatcherMemFn
AMDGPUInstructionSelector::ComplexPredicateFns[] = {
nullptr, // GICP_Invalid
&AMDGPUInstructionSelector::selectDS1Addr1Offset, // gi_ds_1addr_1offset
&AMDGPUInstructionSelector::selectFlatOffset, // gi_flat_atomic
&AMDGPUInstructionSelector::selectFlatOffset, // gi_flat_offset
&AMDGPUInstructionSelector::selectFlatOffsetSigned, // gi_flat_offset_signed
&AMDGPUInstructionSelector::selectFlatOffsetSigned, // gi_flat_signed_atomic
&AMDGPUInstructionSelector::selectMUBUFScratchOffen, // gi_mubuf_scratch_offen
&AMDGPUInstructionSelector::selectMUBUFScratchOffset, // gi_mubuf_scratch_offset
&AMDGPUInstructionSelector::selectSmrdImm, // gi_smrd_imm
&AMDGPUInstructionSelector::selectSmrdImm32, // gi_smrd_imm32
&AMDGPUInstructionSelector::selectSmrdSgpr, // gi_smrd_sgpr
&AMDGPUInstructionSelector::selectVCSRC, // gi_vcsrc
&AMDGPUInstructionSelector::selectVOP3Mods, // gi_vop3mods
&AMDGPUInstructionSelector::selectVOP3Mods0, // gi_vop3mods0
&AMDGPUInstructionSelector::selectVOP3OMods, // gi_vop3omods
&AMDGPUInstructionSelector::selectVOP3Mods0Clamp0OMod, // gi_vop3omods0clamp0omod
&AMDGPUInstructionSelector::selectVOP3OpSelMods, // gi_vop3opselmods
&AMDGPUInstructionSelector::selectVOP3OpSelMods0, // gi_vop3opselmods0
&AMDGPUInstructionSelector::selectVSRC0, // gi_vsrc0
};
// Custom renderers.
enum {
GICR_Invalid,
GICR_renderTruncImm32,
};
AMDGPUInstructionSelector::CustomRendererFn
AMDGPUInstructionSelector::CustomRenderers[] = {
nullptr, // GICP_Invalid
&AMDGPUInstructionSelector::renderTruncImm32, // gi_as_i32timm
};
bool AMDGPUInstructionSelector::selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const {
MachineFunction &MF = *I.getParent()->getParent();
MachineRegisterInfo &MRI = MF.getRegInfo();
// FIXME: This should be computed on a per-function basis rather than per-insn.
AvailableFunctionFeatures = computeAvailableFunctionFeatures(&STI, &MF);
const PredicateBitset AvailableFeatures = getAvailableFeatures();
NewMIVector OutMIs;
State.MIs.clear();
State.MIs.push_back(&I);
if (executeMatchTable(*this, OutMIs, State, ISelInfo, getMatchTable(), TII, MRI, TRI, RBI, AvailableFeatures, CoverageInfo)) {
return true;
}
return false;
}
const int64_t *AMDGPUInstructionSelector::getMatchTable() const {
constexpr static int64_t MatchTable0[] = {
GIM_SwitchOpcode, /*MI*/0, /*[*/35, 1549, /*)*//*default:*//*Label 68*/ 53645,
/*TargetOpcode::G_ADD*//*Label 0*/ 1519,
/*TargetOpcode::G_SUB*//*Label 1*/ 1814,
/*TargetOpcode::G_MUL*//*Label 2*/ 1876, 0, 0, 0, 0,
/*TargetOpcode::G_AND*//*Label 3*/ 1953,
/*TargetOpcode::G_OR*//*Label 4*/ 2039,
/*TargetOpcode::G_XOR*//*Label 5*/ 3870, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/*TargetOpcode::G_BITCAST*//*Label 6*/ 4020, 0, 0,
/*TargetOpcode::G_LOAD*//*Label 7*/ 6271,
/*TargetOpcode::G_SEXTLOAD*//*Label 8*/ 20016,
/*TargetOpcode::G_ZEXTLOAD*//*Label 9*/ 21070, 0, 0, 0,
/*TargetOpcode::G_STORE*//*Label 10*/ 22068, 0, 0,
/*TargetOpcode::G_ATOMIC_CMPXCHG*//*Label 11*/ 29730,
/*TargetOpcode::G_ATOMICRMW_XCHG*//*Label 12*/ 30125,
/*TargetOpcode::G_ATOMICRMW_ADD*//*Label 13*/ 30726,
/*TargetOpcode::G_ATOMICRMW_SUB*//*Label 14*/ 31327,
/*TargetOpcode::G_ATOMICRMW_AND*//*Label 15*/ 31928, 0,
/*TargetOpcode::G_ATOMICRMW_OR*//*Label 16*/ 32529,
/*TargetOpcode::G_ATOMICRMW_XOR*//*Label 17*/ 33130,
/*TargetOpcode::G_ATOMICRMW_MAX*//*Label 18*/ 33731,
/*TargetOpcode::G_ATOMICRMW_MIN*//*Label 19*/ 34332,
/*TargetOpcode::G_ATOMICRMW_UMAX*//*Label 20*/ 34933,
/*TargetOpcode::G_ATOMICRMW_UMIN*//*Label 21*/ 35534,
/*TargetOpcode::G_ATOMICRMW_FADD*//*Label 22*/ 36135, 0,
/*TargetOpcode::G_FENCE*//*Label 23*/ 36302, 0, 0,
/*TargetOpcode::G_INTRINSIC*//*Label 24*/ 36345,
/*TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS*//*Label 25*/ 41836, 0, 0,
/*TargetOpcode::G_CONSTANT*//*Label 26*/ 42369, 0, 0, 0, 0, 0, 0,
/*TargetOpcode::G_SHL*//*Label 27*/ 42422,
/*TargetOpcode::G_LSHR*//*Label 28*/ 42631,
/*TargetOpcode::G_ASHR*//*Label 29*/ 42840,
/*TargetOpcode::G_ICMP*//*Label 30*/ 43049,
/*TargetOpcode::G_FCMP*//*Label 31*/ 43934, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/*TargetOpcode::G_UMULH*//*Label 32*/ 46031,
/*TargetOpcode::G_SMULH*//*Label 33*/ 46060,
/*TargetOpcode::G_FADD*//*Label 34*/ 46089,
/*TargetOpcode::G_FSUB*//*Label 35*/ 46439,
/*TargetOpcode::G_FMUL*//*Label 36*/ 46572,
/*TargetOpcode::G_FMA*//*Label 37*/ 46922,
/*TargetOpcode::G_FMAD*//*Label 38*/ 47233, 0, 0,
/*TargetOpcode::G_FPOW*//*Label 39*/ 47400, 0,
/*TargetOpcode::G_FEXP2*//*Label 40*/ 47471, 0,
/*TargetOpcode::G_FLOG2*//*Label 41*/ 47570, 0,
/*TargetOpcode::G_FNEG*//*Label 42*/ 47669,
/*TargetOpcode::G_FPEXT*//*Label 43*/ 48515,
/*TargetOpcode::G_FPTRUNC*//*Label 44*/ 48612,
/*TargetOpcode::G_FPTOSI*//*Label 45*/ 48709,
/*TargetOpcode::G_FPTOUI*//*Label 46*/ 48983,
/*TargetOpcode::G_SITOFP*//*Label 47*/ 49257,
/*TargetOpcode::G_UITOFP*//*Label 48*/ 49577,
/*TargetOpcode::G_FABS*//*Label 49*/ 49897, 0,
/*TargetOpcode::G_FCANONICALIZE*//*Label 50*/ 50324,
/*TargetOpcode::G_FMINNUM*//*Label 51*/ 50730,
/*TargetOpcode::G_FMAXNUM*//*Label 52*/ 51080,
/*TargetOpcode::G_FMINNUM_IEEE*//*Label 53*/ 51430,
/*TargetOpcode::G_FMAXNUM_IEEE*//*Label 54*/ 51780, 0, 0, 0, 0,
/*TargetOpcode::G_SMIN*//*Label 55*/ 52130,
/*TargetOpcode::G_SMAX*//*Label 56*/ 52210,
/*TargetOpcode::G_UMIN*//*Label 57*/ 52290,
/*TargetOpcode::G_UMAX*//*Label 58*/ 52370,
/*TargetOpcode::G_BR*//*Label 59*/ 52450, 0, 0, 0, 0, 0, 0, 0, 0,
/*TargetOpcode::G_CTPOP*//*Label 60*/ 52475, 0,
/*TargetOpcode::G_BITREVERSE*//*Label 61*/ 52554,
/*TargetOpcode::G_FCEIL*//*Label 62*/ 52595, 0, 0,
/*TargetOpcode::G_FSQRT*//*Label 63*/ 52741,
/*TargetOpcode::G_FFLOOR*//*Label 64*/ 52885,
/*TargetOpcode::G_FRINT*//*Label 65*/ 53195, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/*AMDGPU::G_AMDGPU_ATOMIC_CMPXCHG*//*Label 66*/ 53341,
/*AMDGPU::G_AMDGPU_FFBH_U32*//*Label 67*/ 53604,
// Label 0: @1519
GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/8, 11, /*)*//*default:*//*Label 72*/ 1813,
/*GILLT_s16*//*Label 69*/ 1528,
/*GILLT_s32*//*Label 70*/ 1702,
/*GILLT_s64*//*Label 71*/ 1788,
// Label 69: @1528
GIM_Try, /*On fail goto*//*Label 73*/ 1701,
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
GIM_Try, /*On fail goto*//*Label 74*/ 1590, // Rule ID 1108 //
GIM_CheckFeatures, GIFBS_Has16BitInsts_isGFX6GFX7GFX8GFX9,
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
GIM_CheckIsSafeToFold, /*InsnID*/1,
// (add:{ *:[i16] } (mul:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1), i16:{ *:[i16] }:$src2) => (V_MAD_U16:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src2, 0:{ *:[i1] })
GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MAD_U16,
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src2
GIR_AddImm, /*InsnID*/0, /*Imm*/0,
GIR_EraseFromParent, /*InsnID*/0,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 1108,
GIR_Done,
// Label 74: @1590
GIM_Try, /*On fail goto*//*Label 75*/ 1638, // Rule ID 1109 //
GIM_CheckFeatures, GIFBS_Has16BitInsts_isGFX6GFX7GFX8GFX9,
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
GIM_CheckIsSafeToFold, /*InsnID*/1,
// (add:{ *:[i16] } (mul:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1), i16:{ *:[i16] }:$src2) => (V_MAD_I16:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src2, 0:{ *:[i1] })
GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MAD_I16,
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src2
GIR_AddImm, /*InsnID*/0, /*Imm*/0,
GIR_EraseFromParent, /*InsnID*/0,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 1109,
GIR_Done,
// Label 75: @1638
GIM_Try, /*On fail goto*//*Label 76*/ 1686, // Rule ID 2886 //
GIM_CheckFeatures, GIFBS_Has16BitInsts_isGFX6GFX7GFX8GFX9,
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
GIM_CheckIsSafeToFold, /*InsnID*/1,
// (add:{ *:[i16] } i16:{ *:[i16] }:$src2, (mul:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)) => (V_MAD_U16:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src2, 0:{ *:[i1] })
GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_MAD_U16,
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src2
GIR_AddImm, /*InsnID*/0, /*Imm*/0,
GIR_EraseFromParent, /*InsnID*/0,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 2886,
GIR_Done,
// Label 76: @1686
GIM_Try, /*On fail goto*//*Label 77*/ 1700, // Rule ID 517 //
GIM_CheckFeatures, GIFBS_Has16BitInsts,
// (add:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1) => (V_ADD_U16_e64:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AMDGPU::V_ADD_U16_e64,
GIR_AddImplicitUse, /*InsnID*/0, AMDGPU::EXEC,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 517,
GIR_Done,
// Label 77: @1700
GIM_Reject,
// Label 73: @1701
GIM_Reject,
// Label 70: @1702
GIM_Try, /*On fail goto*//*Label 78*/ 1787,
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
GIM_Try, /*On fail goto*//*Label 79*/ 1751, // Rule ID 489 //
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CTPOP,
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
GIM_CheckIsSafeToFold, /*InsnID*/1,
// (add:{ *:[i32] } (ctpop:{ *:[i32] } i32:{ *:[i32] }:$src0), i32:{ *:[i32] }:$src1) => (V_BCNT_U32_B32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_BCNT_U32_B32_e64,
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
GIR_EraseFromParent, /*InsnID*/0,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 489,
GIR_Done,
// Label 79: @1751
GIM_Try, /*On fail goto*//*Label 80*/ 1786, // Rule ID 2861 //
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CTPOP,
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
GIM_CheckIsSafeToFold, /*InsnID*/1,
// (add:{ *:[i32] } i32:{ *:[i32] }:$src1, (ctpop:{ *:[i32] } i32:{ *:[i32] }:$src0)) => (V_BCNT_U32_B32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_BCNT_U32_B32_e64,
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
GIR_EraseFromParent, /*InsnID*/0,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 2861,
GIR_Done,
// Label 80: @1786
GIM_Reject,
// Label 78: @1787
GIM_Reject,
// Label 71: @1788
GIM_Try, /*On fail goto*//*Label 81*/ 1812, // Rule ID 759 //
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_64RegClassID,
// (add:{ *:[i64] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1) => (S_ADD_U64_PSEUDO:{ *:[i64] }:{ *:[i1] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AMDGPU::S_ADD_U64_PSEUDO,
GIR_AddImplicitDef, /*InsnID*/0, AMDGPU::SCC,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 759,
GIR_Done,
// Label 81: @1812
GIM_Reject,
// Label 72: @1813
GIM_Reject,
// Label 1: @1814
GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/8, 11, /*)*//*default:*//*Label 84*/ 1875,
/*GILLT_s16*//*Label 82*/ 1823, 0,
/*GILLT_s64*//*Label 83*/ 1850,
// Label 82: @1823
GIM_Try, /*On fail goto*//*Label 85*/ 1849, // Rule ID 518 //
GIM_CheckFeatures, GIFBS_Has16BitInsts,
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
// (sub:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1) => (V_SUB_U16_e64:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AMDGPU::V_SUB_U16_e64,
GIR_AddImplicitUse, /*InsnID*/0, AMDGPU::EXEC,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 518,
GIR_Done,
// Label 85: @1849
GIM_Reject,
// Label 83: @1850
GIM_Try, /*On fail goto*//*Label 86*/ 1874, // Rule ID 760 //
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_64RegClassID,
// (sub:{ *:[i64] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1) => (S_SUB_U64_PSEUDO:{ *:[i64] }:{ *:[i1] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AMDGPU::S_SUB_U64_PSEUDO,
GIR_AddImplicitDef, /*InsnID*/0, AMDGPU::SCC,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 760,
GIR_Done,
// Label 86: @1874
GIM_Reject,
// Label 84: @1875
GIM_Reject,
// Label 2: @1876
GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/8, 10, /*)*//*default:*//*Label 89*/ 1952,
/*GILLT_s16*//*Label 87*/ 1884,
/*GILLT_s32*//*Label 88*/ 1911,
// Label 87: @1884
GIM_Try, /*On fail goto*//*Label 90*/ 1910, // Rule ID 519 //
GIM_CheckFeatures, GIFBS_Has16BitInsts,
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
// (mul:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1) => (V_MUL_LO_U16_e64:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AMDGPU::V_MUL_LO_U16_e64,
GIR_AddImplicitUse, /*InsnID*/0, AMDGPU::EXEC,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 519,
GIR_Done,
// Label 90: @1910
GIM_Reject,
// Label 88: @1911
GIM_Try, /*On fail goto*//*Label 91*/ 1951,
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
GIM_Try, /*On fail goto*//*Label 92*/ 1934, // Rule ID 44 //
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::SReg_32RegClassID,
// (mul:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1) => (S_MUL_I32:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AMDGPU::S_MUL_I32,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 44,
GIR_Done,
// Label 92: @1934
GIM_Try, /*On fail goto*//*Label 93*/ 1950, // Rule ID 538 //
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
// (mul:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1) => (V_MUL_LO_U32:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AMDGPU::V_MUL_LO_U32,
GIR_AddImplicitUse, /*InsnID*/0, AMDGPU::EXEC,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 538,
GIR_Done,
// Label 93: @1950
GIM_Reject,
// Label 91: @1951
GIM_Reject,
// Label 89: @1952
GIM_Reject,
// Label 3: @1953
GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/8, 12, /*)*//*default:*//*Label 97*/ 2038,
/*GILLT_s16*//*Label 94*/ 1963,
/*GILLT_s32*//*Label 95*/ 1988, 0,
/*GILLT_v2s16*//*Label 96*/ 2013,
// Label 94: @1963
GIM_Try, /*On fail goto*//*Label 98*/ 1987, // Rule ID 1080 //
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
// (and:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1) => (V_AND_B32_e64:{ *:[i16] } VSrc_b32:{ *:[i16] }:$src0, VSrc_b32:{ *:[i16] }:$src1)
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AMDGPU::V_AND_B32_e64,
GIR_AddImplicitUse, /*InsnID*/0, AMDGPU::EXEC,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 1080,
GIR_Done,
// Label 98: @1987
GIM_Reject,
// Label 95: @1988
GIM_Try, /*On fail goto*//*Label 99*/ 2012, // Rule ID 482 //
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
// (and:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1) => (V_AND_B32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AMDGPU::V_AND_B32_e64,
GIR_AddImplicitUse, /*InsnID*/0, AMDGPU::EXEC,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 482,
GIR_Done,
// Label 99: @2012
GIM_Reject,
// Label 96: @2013
GIM_Try, /*On fail goto*//*Label 100*/ 2037, // Rule ID 1083 //
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
// (and:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src0, v2i16:{ *:[v2i16] }:$src1) => (V_AND_B32_e64:{ *:[v2i16] } VSrc_b32:{ *:[v2i16] }:$src0, VSrc_b32:{ *:[v2i16] }:$src1)
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AMDGPU::V_AND_B32_e64,
GIR_AddImplicitUse, /*InsnID*/0, AMDGPU::EXEC,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 1083,
GIR_Done,
// Label 100: @2037
GIM_Reject,
// Label 97: @2038
GIM_Reject,
// Label 4: @2039
GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/8, 12, /*)*//*default:*//*Label 104*/ 3869,
/*GILLT_s16*//*Label 101*/ 2049,
/*GILLT_s32*//*Label 102*/ 2074, 0,
/*GILLT_v2s16*//*Label 103*/ 3844,
// Label 101: @2049
GIM_Try, /*On fail goto*//*Label 105*/ 2073, // Rule ID 1081 //
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
// (or:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1) => (V_OR_B32_e64:{ *:[i16] } VSrc_b32:{ *:[i16] }:$src0, VSrc_b32:{ *:[i16] }:$src1)
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AMDGPU::V_OR_B32_e64,
GIR_AddImplicitUse, /*InsnID*/0, AMDGPU::EXEC,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 1081,
GIR_Done,
// Label 105: @2073
GIM_Reject,
// Label 102: @2074
GIM_Try, /*On fail goto*//*Label 106*/ 3843,
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
GIM_Try, /*On fail goto*//*Label 107*/ 2187, // Rule ID 4063 //
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_OR,
GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_AND,
// MIs[3] x
GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
// MIs[3] z
GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
GIM_CheckIsSafeToFold, /*InsnID*/1,
GIM_CheckIsSafeToFold, /*InsnID*/2,
GIM_CheckIsSafeToFold, /*InsnID*/3,
// (or:{ *:[i32] } (and:{ *:[i32] } (or:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z), i32:{ *:[i32] }:$y), (and:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z)) => (V_BFI_B32:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$y), i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$y)
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::V_XOR_B32_e64,
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // x
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // y
GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_BFI_B32,
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // z
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // y
GIR_EraseFromParent, /*InsnID*/0,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 4063,
GIR_Done,
// Label 107: @2187
GIM_Try, /*On fail goto*//*Label 108*/ 2290, // Rule ID 4064 //
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_OR,
GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_AND,
// MIs[3] z
GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
// MIs[3] x
GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
GIM_CheckIsSafeToFold, /*InsnID*/1,
GIM_CheckIsSafeToFold, /*InsnID*/2,
GIM_CheckIsSafeToFold, /*InsnID*/3,
// (or:{ *:[i32] } (and:{ *:[i32] } (or:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z), i32:{ *:[i32] }:$y), (and:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x)) => (V_BFI_B32:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$y), i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$y)
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::V_XOR_B32_e64,
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // x
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // y
GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_BFI_B32,
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // z
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // y
GIR_EraseFromParent, /*InsnID*/0,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 4064,
GIR_Done,
// Label 108: @2290
GIM_Try, /*On fail goto*//*Label 109*/ 2393, // Rule ID 4065 //
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_OR,
GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_AND,
// MIs[3] x
GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
// MIs[3] z
GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
GIM_CheckIsSafeToFold, /*InsnID*/1,
GIM_CheckIsSafeToFold, /*InsnID*/2,
GIM_CheckIsSafeToFold, /*InsnID*/3,
// (or:{ *:[i32] } (and:{ *:[i32] } (or:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x), i32:{ *:[i32] }:$y), (and:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z)) => (V_BFI_B32:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$y), i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$y)
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::V_XOR_B32_e64,
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // x
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // y
GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_BFI_B32,
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // z
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // y
GIR_EraseFromParent, /*InsnID*/0,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 4065,
GIR_Done,
// Label 109: @2393
GIM_Try, /*On fail goto*//*Label 110*/ 2496, // Rule ID 4066 //
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_OR,
GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_AND,
// MIs[3] z
GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
// MIs[3] x
GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
GIM_CheckIsSafeToFold, /*InsnID*/1,
GIM_CheckIsSafeToFold, /*InsnID*/2,
GIM_CheckIsSafeToFold, /*InsnID*/3,
// (or:{ *:[i32] } (and:{ *:[i32] } (or:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x), i32:{ *:[i32] }:$y), (and:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x)) => (V_BFI_B32:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$y), i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$y)
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::V_XOR_B32_e64,
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // x
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // y
GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_BFI_B32,
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // z
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // y
GIR_EraseFromParent, /*InsnID*/0,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 4066,
GIR_Done,
// Label 110: @2496
GIM_Try, /*On fail goto*//*Label 111*/ 2599, // Rule ID 4059 //
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_OR,
GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_AND,
// MIs[3] x
GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
// MIs[3] z
GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
GIM_CheckIsSafeToFold, /*InsnID*/1,
GIM_CheckIsSafeToFold, /*InsnID*/2,
GIM_CheckIsSafeToFold, /*InsnID*/3,
// (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$y, (or:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z)), (and:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z)) => (V_BFI_B32:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$y), i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$y)
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::V_XOR_B32_e64,
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // x
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // y
GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_BFI_B32,
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // z
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // y
GIR_EraseFromParent, /*InsnID*/0,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 4059,
GIR_Done,
// Label 111: @2599
GIM_Try, /*On fail goto*//*Label 112*/ 2702, // Rule ID 4060 //
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_OR,
GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_AND,
// MIs[3] z
GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
// MIs[3] x
GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
GIM_CheckIsSafeToFold, /*InsnID*/1,
GIM_CheckIsSafeToFold, /*InsnID*/2,
GIM_CheckIsSafeToFold, /*InsnID*/3,
// (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$y, (or:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z)), (and:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x)) => (V_BFI_B32:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$y), i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$y)
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::V_XOR_B32_e64,
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // x
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // y
GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_BFI_B32,
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // z
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // y
GIR_EraseFromParent, /*InsnID*/0,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 4060,
GIR_Done,
// Label 112: @2702
GIM_Try, /*On fail goto*//*Label 113*/ 2805, // Rule ID 4061 //
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_OR,
GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_AND,
// MIs[3] x
GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
// MIs[3] z
GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
GIM_CheckIsSafeToFold, /*InsnID*/1,
GIM_CheckIsSafeToFold, /*InsnID*/2,
GIM_CheckIsSafeToFold, /*InsnID*/3,
// (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$y, (or:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x)), (and:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z)) => (V_BFI_B32:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$y), i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$y)
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::V_XOR_B32_e64,
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // x
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // y
GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_BFI_B32,
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // z
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // y
GIR_EraseFromParent, /*InsnID*/0,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 4061,
GIR_Done,
// Label 113: @2805
GIM_Try, /*On fail goto*//*Label 114*/ 2908, // Rule ID 4062 //
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_OR,
GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_AND,
// MIs[3] z
GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
// MIs[3] x
GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
GIM_CheckIsSafeToFold, /*InsnID*/1,
GIM_CheckIsSafeToFold, /*InsnID*/2,
GIM_CheckIsSafeToFold, /*InsnID*/3,
// (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$y, (or:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x)), (and:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x)) => (V_BFI_B32:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$y), i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$y)
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::V_XOR_B32_e64,
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // x
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // y
GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_BFI_B32,
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // z
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // y
GIR_EraseFromParent, /*InsnID*/0,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 4062,
GIR_Done,
// Label 114: @2908
GIM_Try, /*On fail goto*//*Label 115*/ 3011, // Rule ID 4053 //
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND,
GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_OR,
// MIs[3] x
GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
// MIs[3] z
GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
GIM_CheckIsSafeToFold, /*InsnID*/1,
GIM_CheckIsSafeToFold, /*InsnID*/2,
GIM_CheckIsSafeToFold, /*InsnID*/3,
// (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z), (and:{ *:[i32] } (or:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z), i32:{ *:[i32] }:$y)) => (V_BFI_B32:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$y), i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$y)
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::V_XOR_B32_e64,
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // x
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // y
GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_BFI_B32,
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // z
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // y
GIR_EraseFromParent, /*InsnID*/0,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 4053,
GIR_Done,
// Label 115: @3011
GIM_Try, /*On fail goto*//*Label 116*/ 3114, // Rule ID 4054 //
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND,
GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_OR,
// MIs[3] z
GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
// MIs[3] x
GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
GIM_CheckIsSafeToFold, /*InsnID*/1,
GIM_CheckIsSafeToFold, /*InsnID*/2,
GIM_CheckIsSafeToFold, /*InsnID*/3,
// (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z), (and:{ *:[i32] } (or:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x), i32:{ *:[i32] }:$y)) => (V_BFI_B32:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$y), i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$y)
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::V_XOR_B32_e64,
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // x
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // y
GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_BFI_B32,
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // z
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // y
GIR_EraseFromParent, /*InsnID*/0,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 4054,
GIR_Done,
// Label 116: @3114
GIM_Try, /*On fail goto*//*Label 117*/ 3217, // Rule ID 4057 //
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND,
GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_OR,
// MIs[3] x
GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
// MIs[3] z
GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
GIM_CheckIsSafeToFold, /*InsnID*/1,
GIM_CheckIsSafeToFold, /*InsnID*/2,
GIM_CheckIsSafeToFold, /*InsnID*/3,
// (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x), (and:{ *:[i32] } (or:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z), i32:{ *:[i32] }:$y)) => (V_BFI_B32:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$y), i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$y)
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::V_XOR_B32_e64,
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // x
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // y
GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_BFI_B32,
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // z
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // y
GIR_EraseFromParent, /*InsnID*/0,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 4057,
GIR_Done,
// Label 117: @3217
GIM_Try, /*On fail goto*//*Label 118*/ 3320, // Rule ID 4058 //
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND,
GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_OR,
// MIs[3] z
GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
// MIs[3] x
GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
GIM_CheckIsSafeToFold, /*InsnID*/1,
GIM_CheckIsSafeToFold, /*InsnID*/2,
GIM_CheckIsSafeToFold, /*InsnID*/3,
// (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x), (and:{ *:[i32] } (or:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x), i32:{ *:[i32] }:$y)) => (V_BFI_B32:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$y), i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$y)
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::V_XOR_B32_e64,
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // x
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // y
GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_BFI_B32,
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // z
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // y
GIR_EraseFromParent, /*InsnID*/0,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 4058,
GIR_Done,
// Label 118: @3320
GIM_Try, /*On fail goto*//*Label 119*/ 3423, // Rule ID 2638 //
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND,
GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_OR,
// MIs[3] x
GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
// MIs[3] z
GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
GIM_CheckIsSafeToFold, /*InsnID*/1,
GIM_CheckIsSafeToFold, /*InsnID*/2,
GIM_CheckIsSafeToFold, /*InsnID*/3,
// (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z), (and:{ *:[i32] } i32:{ *:[i32] }:$y, (or:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z))) => (V_BFI_B32:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$y), i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$y)
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::V_XOR_B32_e64,
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // x
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // y
GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_BFI_B32,
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // z
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // y
GIR_EraseFromParent, /*InsnID*/0,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 2638,
GIR_Done,
// Label 119: @3423
GIM_Try, /*On fail goto*//*Label 120*/ 3526, // Rule ID 4052 //
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND,
GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_OR,
// MIs[3] z
GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
// MIs[3] x
GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
GIM_CheckIsSafeToFold, /*InsnID*/1,
GIM_CheckIsSafeToFold, /*InsnID*/2,
GIM_CheckIsSafeToFold, /*InsnID*/3,
// (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z), (and:{ *:[i32] } i32:{ *:[i32] }:$y, (or:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x))) => (V_BFI_B32:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$y), i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$y)
GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
GIR_BuildMI, /*InsnID*/1, /*Opcode*/AMDGPU::V_XOR_B32_e64,
GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // x
GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // y
GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
GIR_BuildMI, /*InsnID*/0, /*Opcode*/AMDGPU::V_BFI_B32,
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdst
GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // z
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // y
GIR_EraseFromParent, /*InsnID*/0,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 4052,
GIR_Done,
// Label 120: @3526
GIM_Try, /*On fail goto*//*Label 121*/ 3629, // Rule ID 4055 //
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/AMDGPU::VGPR_32RegClassID,
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
GIM_RecordInsn |