1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
| /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|* *|
|* Pseudo-instruction MC lowering Source Fragment *|
|* *|
|* Automatically generated file, do not edit! *|
|* *|
\*===----------------------------------------------------------------------===*/
bool RISCVAsmPrinter::
emitPseudoExpansionLowering(MCStreamer &OutStreamer,
const MachineInstr *MI) {
switch (MI->getOpcode()) {
default: return false;
case RISCV::PseudoBR: {
MCInst TmpInst;
MCOperand MCOp;
TmpInst.setOpcode(RISCV::JAL);
// Operand: rd
TmpInst.addOperand(MCOperand::createReg(RISCV::X0));
// Operand: imm20
lowerOperand(MI->getOperand(0), MCOp);
TmpInst.addOperand(MCOp);
EmitToStreamer(OutStreamer, TmpInst);
break;
}
case RISCV::PseudoBRIND: {
MCInst TmpInst;
MCOperand MCOp;
TmpInst.setOpcode(RISCV::JALR);
// Operand: rd
TmpInst.addOperand(MCOperand::createReg(RISCV::X0));
// Operand: rs1
lowerOperand(MI->getOperand(0), MCOp);
TmpInst.addOperand(MCOp);
// Operand: imm12
lowerOperand(MI->getOperand(1), MCOp);
TmpInst.addOperand(MCOp);
EmitToStreamer(OutStreamer, TmpInst);
break;
}
case RISCV::PseudoCALLIndirect: {
MCInst TmpInst;
MCOperand MCOp;
TmpInst.setOpcode(RISCV::JALR);
// Operand: rd
TmpInst.addOperand(MCOperand::createReg(RISCV::X1));
// Operand: rs1
lowerOperand(MI->getOperand(0), MCOp);
TmpInst.addOperand(MCOp);
// Operand: imm12
TmpInst.addOperand(MCOperand::createImm(0));
EmitToStreamer(OutStreamer, TmpInst);
break;
}
case RISCV::PseudoRET: {
MCInst TmpInst;
MCOperand MCOp;
TmpInst.setOpcode(RISCV::JALR);
// Operand: rd
TmpInst.addOperand(MCOperand::createReg(RISCV::X0));
// Operand: rs1
TmpInst.addOperand(MCOperand::createReg(RISCV::X1));
// Operand: imm12
TmpInst.addOperand(MCOperand::createImm(0));
EmitToStreamer(OutStreamer, TmpInst);
break;
}
case RISCV::PseudoTAILIndirect: {
MCInst TmpInst;
MCOperand MCOp;
TmpInst.setOpcode(RISCV::JALR);
// Operand: rd
TmpInst.addOperand(MCOperand::createReg(RISCV::X0));
// Operand: rs1
lowerOperand(MI->getOperand(0), MCOp);
TmpInst.addOperand(MCOp);
// Operand: imm12
TmpInst.addOperand(MCOperand::createImm(0));
EmitToStreamer(OutStreamer, TmpInst);
break;
}
}
return true;
}
|