|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/ARM/ARMGenSubtargetInfo.inc19932 && (Register::isVirtualRegister(MI->getOperand(0).getReg()))
19936 && (Register::isVirtualRegister(MI->getOperand(0).getReg()))
19940 && (Register::isVirtualRegister(MI->getOperand(0).getReg()))
19944 && (Register::isVirtualRegister(MI->getOperand(0).getReg()))
19948 && (Register::isVirtualRegister(MI->getOperand(0).getReg()))
19952 && (Register::isVirtualRegister(MI->getOperand(0).getReg()))
19956 && (Register::isVirtualRegister(MI->getOperand(0).getReg()))
19960 && (Register::isVirtualRegister(MI->getOperand(0).getReg()))
19964 && (Register::isVirtualRegister(MI->getOperand(0).getReg()))
19968 && (Register::isPhysicalRegister(MI->getOperand(0).getReg()))
19972 && (Register::isPhysicalRegister(MI->getOperand(0).getReg()))
19976 && (Register::isPhysicalRegister(MI->getOperand(0).getReg()))
19980 && (Register::isPhysicalRegister(MI->getOperand(0).getReg()))
19984 && (Register::isPhysicalRegister(MI->getOperand(0).getReg()))
19988 && (Register::isPhysicalRegister(MI->getOperand(0).getReg()))
19992 && (Register::isPhysicalRegister(MI->getOperand(0).getReg()))
19996 && (Register::isPhysicalRegister(MI->getOperand(0).getReg()))
20000 && (Register::isPhysicalRegister(MI->getOperand(0).getReg()))
20007 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
20010 if ((Register::isPhysicalRegister(MI->getOperand(0).getReg()))
20013 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
20016 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
20019 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
20022 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
20025 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
20028 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
20031 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
20034 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
20037 if ((Register::isPhysicalRegister(MI->getOperand(0).getReg()))
20040 if ((Register::isPhysicalRegister(MI->getOperand(0).getReg()))
20043 if ((Register::isPhysicalRegister(MI->getOperand(0).getReg()))
20046 if ((Register::isPhysicalRegister(MI->getOperand(0).getReg()))
20049 if ((Register::isPhysicalRegister(MI->getOperand(0).getReg()))
20052 if ((Register::isPhysicalRegister(MI->getOperand(0).getReg()))
20055 if ((Register::isPhysicalRegister(MI->getOperand(0).getReg()))
20058 if ((Register::isPhysicalRegister(MI->getOperand(0).getReg()))
21450 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
21453 if ((Register::isPhysicalRegister(MI->getOperand(0).getReg()))
21456 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
21459 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
21462 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
21465 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
21468 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
21471 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
21474 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
21477 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
21480 if ((Register::isPhysicalRegister(MI->getOperand(0).getReg()))
21483 if ((Register::isPhysicalRegister(MI->getOperand(0).getReg()))
21486 if ((Register::isPhysicalRegister(MI->getOperand(0).getReg()))
21489 if ((Register::isPhysicalRegister(MI->getOperand(0).getReg()))
21492 if ((Register::isPhysicalRegister(MI->getOperand(0).getReg()))
21495 if ((Register::isPhysicalRegister(MI->getOperand(0).getReg()))
21498 if ((Register::isPhysicalRegister(MI->getOperand(0).getReg()))
21501 if ((Register::isPhysicalRegister(MI->getOperand(0).getReg()))
21508 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
21511 if ((Register::isPhysicalRegister(MI->getOperand(0).getReg()))
21514 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
21517 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
21520 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
21523 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
21526 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
21529 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
21532 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
21535 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
21538 if ((Register::isPhysicalRegister(MI->getOperand(0).getReg()))
21541 if ((Register::isPhysicalRegister(MI->getOperand(0).getReg()))
21544 if ((Register::isPhysicalRegister(MI->getOperand(0).getReg()))
21547 if ((Register::isPhysicalRegister(MI->getOperand(0).getReg()))
21550 if ((Register::isPhysicalRegister(MI->getOperand(0).getReg()))
21553 if ((Register::isPhysicalRegister(MI->getOperand(0).getReg()))
21556 if ((Register::isPhysicalRegister(MI->getOperand(0).getReg()))
21559 if ((Register::isPhysicalRegister(MI->getOperand(0).getReg()))
21680 && (Register::isVirtualRegister(MI->getOperand(0).getReg()))
21684 && (Register::isVirtualRegister(MI->getOperand(0).getReg()))
21688 && (Register::isVirtualRegister(MI->getOperand(0).getReg()))
21692 && (Register::isVirtualRegister(MI->getOperand(0).getReg()))
21696 && (Register::isVirtualRegister(MI->getOperand(0).getReg()))
21700 && (Register::isVirtualRegister(MI->getOperand(0).getReg()))
21704 && (Register::isVirtualRegister(MI->getOperand(0).getReg()))
21708 && (Register::isVirtualRegister(MI->getOperand(0).getReg()))
21712 && (Register::isVirtualRegister(MI->getOperand(0).getReg()))
21716 && (Register::isPhysicalRegister(MI->getOperand(0).getReg()))
21720 && (Register::isPhysicalRegister(MI->getOperand(0).getReg()))
21724 && (Register::isPhysicalRegister(MI->getOperand(0).getReg()))
21728 && (Register::isPhysicalRegister(MI->getOperand(0).getReg()))
21732 && (Register::isPhysicalRegister(MI->getOperand(0).getReg()))
21736 && (Register::isPhysicalRegister(MI->getOperand(0).getReg()))
21740 && (Register::isPhysicalRegister(MI->getOperand(0).getReg()))
21744 && (Register::isPhysicalRegister(MI->getOperand(0).getReg()))
21748 && (Register::isPhysicalRegister(MI->getOperand(0).getReg()))
22385 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
22388 if ((Register::isPhysicalRegister(MI->getOperand(0).getReg()))
22391 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
22394 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
22397 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
22400 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
22403 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
22406 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
22409 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
22412 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
22415 if ((Register::isPhysicalRegister(MI->getOperand(0).getReg()))
22418 if ((Register::isPhysicalRegister(MI->getOperand(0).getReg()))
22421 if ((Register::isPhysicalRegister(MI->getOperand(0).getReg()))
22424 if ((Register::isPhysicalRegister(MI->getOperand(0).getReg()))
22427 if ((Register::isPhysicalRegister(MI->getOperand(0).getReg()))
22430 if ((Register::isPhysicalRegister(MI->getOperand(0).getReg()))
22433 if ((Register::isPhysicalRegister(MI->getOperand(0).getReg()))
22436 if ((Register::isPhysicalRegister(MI->getOperand(0).getReg()))
include/llvm/ADT/ArrayRef.h 43 using iterator = const T *;
44 using const_iterator = const T *;
50 const T *Data = nullptr;
66 /*implicit*/ ArrayRef(const T &OneElt)
70 /*implicit*/ ArrayRef(const T *data, size_t length)
74 ArrayRef(const T *begin, const T *end)
74 ArrayRef(const T *begin, const T *end)
81 /*implicit*/ ArrayRef(const SmallVectorTemplateCommon<T, U> &Vec)
87 /*implicit*/ ArrayRef(const std::vector<T, A> &Vec)
92 /*implicit*/ constexpr ArrayRef(const std::array<T, N> &Arr)
97 /*implicit*/ constexpr ArrayRef(const T (&Arr)[N]) : Data(Arr), Length(N) {}
100 /*implicit*/ ArrayRef(const std::initializer_list<T> &Vec)
145 const T *data() const { return Data; }
151 const T &front() const {
157 const T &back() const {
163 template <typename Allocator> ArrayRef<T> copy(Allocator &A) {
178 ArrayRef<T> slice(size_t N, size_t M) const {
184 ArrayRef<T> slice(size_t N) const { return slice(N, size() - N); }
187 ArrayRef<T> drop_front(size_t N = 1) const {
193 ArrayRef<T> drop_back(size_t N = 1) const {
200 template <class PredicateT> ArrayRef<T> drop_while(PredicateT Pred) const {
206 template <class PredicateT> ArrayRef<T> drop_until(PredicateT Pred) const {
211 ArrayRef<T> take_front(size_t N = 1) const {
218 ArrayRef<T> take_back(size_t N = 1) const {
226 template <class PredicateT> ArrayRef<T> take_while(PredicateT Pred) const {
232 template <class PredicateT> ArrayRef<T> take_until(PredicateT Pred) const {
239 const T &operator[](size_t Index) const {
249 typename std::enable_if<std::is_same<U, T>::value, ArrayRef<T>>::type &
257 typename std::enable_if<std::is_same<U, T>::value, ArrayRef<T>>::type &
263 std::vector<T> vec() const {
270 operator std::vector<T>() const {
450 ArrayRef<T> makeArrayRef(const T &OneElt) {
450 ArrayRef<T> makeArrayRef(const T &OneElt) {
468 ArrayRef<T> makeArrayRef(const SmallVectorImpl<T> &Vec) {
468 ArrayRef<T> makeArrayRef(const SmallVectorImpl<T> &Vec) {
480 ArrayRef<T> makeArrayRef(const std::vector<T> &Vec) {
480 ArrayRef<T> makeArrayRef(const std::vector<T> &Vec) {
491 template <typename T> ArrayRef<T> makeArrayRef(const ArrayRef<T> &Vec) {
491 template <typename T> ArrayRef<T> makeArrayRef(const ArrayRef<T> &Vec) {
496 template <typename T> ArrayRef<T> &makeArrayRef(ArrayRef<T> &Vec) {
496 template <typename T> ArrayRef<T> &makeArrayRef(ArrayRef<T> &Vec) {
include/llvm/ADT/DenseMap.h 40 struct DenseMapPair : public std::pair<KeyT, ValueT> {
40 struct DenseMapPair : public std::pair<KeyT, ValueT> {
43 KeyT &getFirst() { return std::pair<KeyT, ValueT>::first; }
44 const KeyT &getFirst() const { return std::pair<KeyT, ValueT>::first; }
45 ValueT &getSecond() { return std::pair<KeyT, ValueT>::second; }
46 const ValueT &getSecond() const { return std::pair<KeyT, ValueT>::second; }
65 using key_type = KeyT;
66 using mapped_type = ValueT;
69 using iterator = DenseMapIterator<KeyT, ValueT, KeyInfoT, BucketT>;
69 using iterator = DenseMapIterator<KeyT, ValueT, KeyInfoT, BucketT>;
71 DenseMapIterator<KeyT, ValueT, KeyInfoT, BucketT, true>;
71 DenseMapIterator<KeyT, ValueT, KeyInfoT, BucketT, true>;
123 is_trivially_copyable<ValueT>::value) {
145 size_type count(const_arg_type_t<KeyT> Val) const {
150 iterator find(const_arg_type_t<KeyT> Val) {
156 const_iterator find(const_arg_type_t<KeyT> Val) const {
185 ValueT lookup(const_arg_type_t<KeyT> Val) const {
185 ValueT lookup(const_arg_type_t<KeyT> Val) const {
195 std::pair<iterator, bool> insert(const std::pair<KeyT, ValueT> &KV) {
195 std::pair<iterator, bool> insert(const std::pair<KeyT, ValueT> &KV) {
202 std::pair<iterator, bool> insert(std::pair<KeyT, ValueT> &&KV) {
202 std::pair<iterator, bool> insert(std::pair<KeyT, ValueT> &&KV) {
210 std::pair<iterator, bool> try_emplace(KeyT &&Key, Ts &&... Args) {
219 InsertIntoBucket(TheBucket, std::move(Key), std::forward<Ts>(Args)...);
229 std::pair<iterator, bool> try_emplace(const KeyT &Key, Ts &&... Args) {
249 std::pair<iterator, bool> insert_as(std::pair<KeyT, ValueT> &&KV,
249 std::pair<iterator, bool> insert_as(std::pair<KeyT, ValueT> &&KV,
272 bool erase(const KeyT &Val) {
291 value_type& FindAndConstruct(const KeyT &Key) {
299 ValueT &operator[](const KeyT &Key) {
299 ValueT &operator[](const KeyT &Key) {
303 value_type& FindAndConstruct(KeyT &&Key) {
311 ValueT &operator[](KeyT &&Key) {
311 ValueT &operator[](KeyT &&Key) {
334 const KeyT EmptyKey = getEmptyKey(), TombstoneKey = getTombstoneKey();
349 const KeyT EmptyKey = getEmptyKey();
351 ::new (&B->getFirst()) KeyT(EmptyKey);
369 const KeyT EmptyKey = getEmptyKey();
370 const KeyT TombstoneKey = getTombstoneKey();
380 ::new (&DestBucket->getSecond()) ValueT(std::move(B->getSecond()));
392 const DenseMapBase<OtherBaseT, KeyT, ValueT, KeyInfoT, BucketT> &other) {
392 const DenseMapBase<OtherBaseT, KeyT, ValueT, KeyInfoT, BucketT> &other) {
414 static unsigned getHashValue(const KeyT &Val) {
419 static unsigned getHashValue(const LookupKeyT &Val) {
423 static const KeyT getEmptyKey() {
429 static const KeyT getTombstoneKey() {
437 if (shouldReverseIterate<KeyT>()) {
515 BucketT *InsertIntoBucket(BucketT *TheBucket, KeyArg &&Key,
516 ValueArgs &&... Values) {
520 ::new (&TheBucket->getSecond()) ValueT(std::forward<ValueArgs>(Values)...);
520 ::new (&TheBucket->getSecond()) ValueT(std::forward<ValueArgs>(Values)...);
525 BucketT *InsertIntoBucketWithLookup(BucketT *TheBucket, KeyT &&Key,
526 ValueT &&Value, LookupKeyT &Lookup) {
535 BucketT *InsertIntoBucketImpl(const KeyT &Key, const LookupKeyT &Lookup,
535 BucketT *InsertIntoBucketImpl(const KeyT &Key, const LookupKeyT &Lookup,
566 const KeyT EmptyKey = getEmptyKey();
578 bool LookupBucketFor(const LookupKeyT &Val,
590 const KeyT EmptyKey = getEmptyKey();
591 const KeyT TombstoneKey = getTombstoneKey();
629 bool LookupBucketFor(const LookupKeyT &Val, BucketT *&FoundBucket) {
684 class DenseMap : public DenseMapBase<DenseMap<KeyT, ValueT, KeyInfoT, BucketT>,
684 class DenseMap : public DenseMapBase<DenseMap<KeyT, ValueT, KeyInfoT, BucketT>,
685 KeyT, ValueT, KeyInfoT, BucketT> {
685 KeyT, ValueT, KeyInfoT, BucketT> {
690 using BaseT = DenseMapBase<DenseMap, KeyT, ValueT, KeyInfoT, BucketT>;
690 using BaseT = DenseMapBase<DenseMap, KeyT, ValueT, KeyInfoT, BucketT>;
1163 using ConstIterator = DenseMapIterator<KeyT, ValueT, KeyInfoT, Bucket, true>;
1163 using ConstIterator = DenseMapIterator<KeyT, ValueT, KeyInfoT, Bucket, true>;
1186 if (shouldReverseIterate<KeyT>()) {
1199 const DenseMapIterator<KeyT, ValueT, KeyInfoT, Bucket, IsConstSrc> &I)
1199 const DenseMapIterator<KeyT, ValueT, KeyInfoT, Bucket, IsConstSrc> &I)
1204 if (shouldReverseIterate<KeyT>())
1210 if (shouldReverseIterate<KeyT>())
1249 const KeyT Empty = KeyInfoT::getEmptyKey();
1250 const KeyT Tombstone = KeyInfoT::getTombstoneKey();
1259 const KeyT Empty = KeyInfoT::getEmptyKey();
1260 const KeyT Tombstone = KeyInfoT::getTombstoneKey();
include/llvm/ADT/IndexedMap.h 34 using StorageT = SmallVector<T, 0>;
37 T nullVal_;
43 explicit IndexedMap(const T& val) : nullVal_(val) {}
include/llvm/ADT/Optional.h 144 T value;
160 explicit OptionalStorage(in_place_t, Args &&... args)
161 : value(std::forward<Args>(args)...), hasVal(true) {}
172 T &getValue() LLVM_LVALUE_FUNCTION noexcept {
176 T const &getValue() const LLVM_LVALUE_FUNCTION noexcept {
181 T &&getValue() && noexcept {
206 ::new ((void *)std::addressof(value)) T(std::move(y));
216 optional_detail::OptionalStorage<T> Storage;
219 using value_type = T;
224 Optional(const T &y) : Storage(optional_detail::in_place_t{}, y) {}
227 Optional(T &&y) : Storage(optional_detail::in_place_t{}, std::move(y)) {}
230 Optional &operator=(T &&y) {
241 static inline Optional create(const T *y) {
245 Optional &operator=(const T &y) {
253 const T *getPointer() const { return &Storage.getValue(); }
254 T *getPointer() { return &Storage.getValue(); }
255 const T &getValue() const LLVM_LVALUE_FUNCTION { return Storage.getValue(); }
256 T &getValue() LLVM_LVALUE_FUNCTION { return Storage.getValue(); }
260 const T *operator->() const { return getPointer(); }
261 T *operator->() { return getPointer(); }
262 const T &operator*() const LLVM_LVALUE_FUNCTION { return getValue(); }
263 T &operator*() LLVM_LVALUE_FUNCTION { return getValue(); }
266 constexpr T getValueOr(U &&value) const LLVM_LVALUE_FUNCTION {
271 T &&getValue() && { return std::move(Storage.getValue()); }
272 T &&operator*() && { return std::move(Storage.getValue()); }
275 T getValueOr(U &&value) && {
include/llvm/ADT/STLExtras.h 1186 auto find(R &&Range, const T &Val) -> decltype(adl_begin(Range)) {
1224 bool is_contained(R &&Range, const E &Element) {
include/llvm/ADT/SmallSet.h 138 SmallVector<T, N> Vector;
139 std::set<T, C> Set;
141 using VIterator = typename SmallVector<T, N>::const_iterator;
142 using mutable_iterator = typename SmallVector<T, N>::iterator;
151 using const_iterator = SmallSetIterator<T, N, C>;
164 size_type count(const T &V) const {
180 std::pair<NoneType, bool> insert(const T &V) {
207 bool erase(const T &V) {
238 VIterator vfind(const T &V) const {
include/llvm/ADT/SmallVector.h 75 AlignedCharArrayUnion<T> FirstEl;
114 using value_type = T;
115 using iterator = T *;
116 using const_iterator = const T *;
121 using reference = T &;
122 using const_reference = const T &;
123 using pointer = T *;
124 using const_pointer = const T *;
259 class SmallVectorTemplateBase<T, true> : public SmallVectorTemplateCommon<T> {
264 static void destroy_range(T *, T *) {}
264 static void destroy_range(T *, T *) {}
286 T1 *I, T1 *E, T2 *Dest,
286 T1 *I, T1 *E, T2 *Dest,
286 T1 *I, T1 *E, T2 *Dest,
287 typename std::enable_if<std::is_same<typename std::remove_const<T1>::type,
288 T2>::value>::type * = nullptr) {
294 memcpy(reinterpret_cast<void *>(Dest), I, (E - I) * sizeof(T));
299 void grow(size_t MinSize = 0) { this->grow_pod(MinSize, sizeof(T)); }
302 void push_back(const T &Elt) {
305 memcpy(reinterpret_cast<void *>(this->end()), &Elt, sizeof(T));
315 class SmallVectorImpl : public SmallVectorTemplateBase<T> {
316 using SuperClass = SmallVectorTemplateBase<T>;
352 new (&*I) T();
357 void resize(size_type N, const T &NV) {
374 LLVM_NODISCARD T pop_back_val() {
375 T Result = ::std::move(this->back());
397 void append(size_type NumInputs, const T &Elt) {
405 void append(std::initializer_list<T> IL) {
412 void assign(size_type NumElts, const T &Elt) {
429 void assign(std::initializer_list<T> IL) {
467 iterator insert(iterator I, T &&Elt) {
497 iterator insert(iterator I, const T &Elt) {
526 iterator insert(iterator I, size_type NumToInsert, const T &Elt) {
637 void insert(iterator I, std::initializer_list<T> IL) {
641 template <typename... ArgTypes> reference emplace_back(ArgTypes &&... Args) {
644 ::new ((void *)this->end()) T(std::forward<ArgTypes>(Args)...);
820 AlignedCharArrayUnion<T> InlineElts[N];
837 class SmallVector : public SmallVectorImpl<T>, SmallVectorStorage<T, N> {
837 class SmallVector : public SmallVectorImpl<T>, SmallVectorStorage<T, N> {
846 explicit SmallVector(size_t Size, const T &Value = T())
865 SmallVector(std::initializer_list<T> IL) : SmallVectorImpl<T>(N) {
884 SmallVector(SmallVectorImpl<T> &&RHS) : SmallVectorImpl<T>(N) {
include/llvm/ADT/StringSwitch.h 48 Optional<T> Result;
67 StringSwitch &Case(StringLiteral S, T Value) {
74 StringSwitch& EndsWith(StringLiteral S, T Value) {
81 StringSwitch& StartsWith(StringLiteral S, T Value) {
88 StringSwitch &Cases(StringLiteral S0, StringLiteral S1, T Value) {
93 T Value) {
98 StringLiteral S3, T Value) {
103 StringLiteral S3, StringLiteral S4, T Value) {
109 T Value) {
115 StringLiteral S6, T Value) {
121 StringLiteral S6, StringLiteral S7, T Value) {
128 T Value) {
135 StringLiteral S9, T Value) {
140 StringSwitch &CaseLower(StringLiteral S, T Value) {
147 StringSwitch &EndsWithLower(StringLiteral S, T Value) {
154 StringSwitch &StartsWithLower(StringLiteral S, T Value) {
161 StringSwitch &CasesLower(StringLiteral S0, StringLiteral S1, T Value) {
166 T Value) {
171 StringLiteral S3, T Value) {
176 StringLiteral S3, StringLiteral S4, T Value) {
181 R Default(T Value) {
181 R Default(T Value) {
188 operator R() {
include/llvm/CodeGen/CallingConvLower.h 150 Register getLocReg() const { assert(isRegLoc()); return Loc; }
include/llvm/CodeGen/FastISel.h 96 SmallVector<Register, 16> OutRegs;
98 SmallVector<Register, 4> InRegs;
include/llvm/CodeGen/GlobalISel/CallLowering.h 47 SmallVector<Register, 4> Regs;
51 SmallVector<Register, 2> OrigRegs;
56 ArgInfo(ArrayRef<Register> Regs, Type *Ty,
87 Register SwiftErrorVReg = 0;
128 virtual Register getStackAddress(uint64_t Size, int64_t Offset,
134 virtual void assignValueToReg(Register ValVReg, Register PhysReg,
134 virtual void assignValueToReg(Register ValVReg, Register PhysReg,
140 virtual void assignValueToAddress(Register ValVReg, Register Addr,
140 virtual void assignValueToAddress(Register ValVReg, Register Addr,
155 Register extendRegister(Register ValReg, CCValAssign &VA);
155 Register extendRegister(Register ValReg, CCValAssign &VA);
194 Register packRegs(ArrayRef<Register> SrcRegs, Type *PackedTy,
194 Register packRegs(ArrayRef<Register> SrcRegs, Type *PackedTy,
202 void unpackRegs(ArrayRef<Register> DstRegs, Register SrcReg, Type *PackedTy,
202 void unpackRegs(ArrayRef<Register> DstRegs, Register SrcReg, Type *PackedTy,
265 ArrayRef<Register> VRegs,
266 Register SwiftErrorVReg) const {
277 ArrayRef<Register> VRegs) const {
293 ArrayRef<ArrayRef<Register>> VRegs) const {
332 ArrayRef<Register> ResRegs,
333 ArrayRef<ArrayRef<Register>> ArgRegs, Register SwiftErrorVReg,
333 ArrayRef<ArrayRef<Register>> ArgRegs, Register SwiftErrorVReg,
include/llvm/CodeGen/GlobalISel/CombinerHelper.h 53 void replaceRegWith(MachineRegisterInfo &MRI, Register FromReg, Register ToReg) const;
53 void replaceRegWith(MachineRegisterInfo &MRI, Register FromReg, Register ToReg) const;
58 Register ToReg) const;
109 SmallVectorImpl<Register> &Ops);
113 const ArrayRef<Register> Ops);
127 SmallVectorImpl<Register> &Ops);
130 const ArrayRef<Register> Ops);
170 bool optimizeMemcpy(MachineInstr &MI, Register Dst, Register Src,
170 bool optimizeMemcpy(MachineInstr &MI, Register Dst, Register Src,
173 bool optimizeMemmove(MachineInstr &MI, Register Dst, Register Src,
173 bool optimizeMemmove(MachineInstr &MI, Register Dst, Register Src,
176 bool optimizeMemset(MachineInstr &MI, Register Dst, Register Val,
176 bool optimizeMemset(MachineInstr &MI, Register Dst, Register Val,
183 bool findPostIndexCandidate(MachineInstr &MI, Register &Addr, Register &Base,
183 bool findPostIndexCandidate(MachineInstr &MI, Register &Addr, Register &Base,
184 Register &Offset);
190 bool findPreIndexCandidate(MachineInstr &MI, Register &Addr, Register &Base,
190 bool findPreIndexCandidate(MachineInstr &MI, Register &Addr, Register &Base,
191 Register &Offset);
include/llvm/CodeGen/GlobalISel/GISelKnownBits.h 39 virtual void computeKnownBitsImpl(Register R, KnownBits &Known,
44 KnownBits getKnownBits(Register R);
47 APInt getKnownZeroes(Register R);
48 APInt getKnownOnes(Register R);
53 bool maskedValueIsZero(Register Val, const APInt &Mask) {
59 bool signBitIsZero(Register Op);
63 void computeKnownBitsForFrameIndex(Register R, KnownBits &Known,
include/llvm/CodeGen/GlobalISel/IRTranslator.h 74 using VRegListT = SmallVector<Register, 1>;
203 bool translate(const Constant &C, Register Reg);
219 void getStackGuard(Register DstReg, MachineIRBuilder &MIRBuilder);
560 ArrayRef<Register> getOrCreateVRegs(const Value &Val);
562 Register getOrCreateVReg(const Value &Val) {
include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h 101 if (Register::isPhysicalRegister(MO.getReg())) {
include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h 53 Register DstReg = MI.getOperand(0).getReg();
54 Register SrcReg = lookThroughCopyInstrs(MI.getOperand(1).getReg());
57 Register TruncSrc;
66 Register ExtSrc;
98 Register DstReg = MI.getOperand(0).getReg();
99 Register SrcReg = lookThroughCopyInstrs(MI.getOperand(1).getReg());
102 Register TruncSrc;
139 Register DstReg = MI.getOperand(0).getReg();
140 Register SrcReg = lookThroughCopyInstrs(MI.getOperand(1).getReg());
143 Register TruncSrc;
165 Register DstReg = MI.getOperand(0).getReg();
166 Register SrcReg = lookThroughCopyInstrs(MI.getOperand(1).getReg());
196 Register DstReg = MI.getOperand(0).getReg();
291 SmallVector<Register, 2> DstRegs;
297 SmallVector<Register, 2> TmpRegs;
328 SmallVector<Register, 2> Regs;
342 Register MergeSrc = MergeI->getOperand(Idx + 1).getReg();
556 unsigned lookThroughCopyInstrs(Register Reg) {
557 Register TmpReg;
include/llvm/CodeGen/GlobalISel/LegalizerHelper.h 144 void extractParts(Register Reg, LLT Ty, int NumParts,
145 SmallVectorImpl<Register> &VRegs);
148 bool extractParts(Register Reg, LLT RegTy, LLT MainTy,
150 SmallVectorImpl<Register> &VRegs,
151 SmallVectorImpl<Register> &LeftoverVRegs);
162 void insertParts(Register DstReg, LLT ResultTy,
163 LLT PartTy, ArrayRef<Register> PartRegs,
164 LLT LeftoverTy = LLT(), ArrayRef<Register> LeftoverRegs = {});
169 void multiplyRegisters(SmallVectorImpl<Register> &DstRegs,
170 ArrayRef<Register> Src1Regs,
171 ArrayRef<Register> Src2Regs, LLT NarrowTy);
include/llvm/CodeGen/GlobalISel/MIPatternMatch.h 24 bool mi_match(Reg R, const MachineRegisterInfo &MRI, Pattern &&P) {
74 bool match(const MachineRegisterInfo &MRI, MatchSrc &&src) {
86 bool match(const MachineRegisterInfo &MRI, MatchSrc &&src) {
93 bool match(const MachineRegisterInfo &MRI, MatchSrc &&src) {
104 bool match(const MachineRegisterInfo &MRI, MatchSrc &&src) {
118 static bool bind(const MachineRegisterInfo &MRI, BindTy &VR, BindTy &V) {
118 static bool bind(const MachineRegisterInfo &MRI, BindTy &VR, BindTy &V) {
154 Class &VR;
156 bind_ty(Class &V) : VR(V) {}
158 template <typename ITy> bool match(const MachineRegisterInfo &MRI, ITy &&V) {
159 return bind_helper<Class>::bind(MRI, VR, V);
163 inline bind_ty<Register> m_Reg(Register &R) { return R; }
163 inline bind_ty<Register> m_Reg(Register &R) { return R; }
179 bool match(const MachineRegisterInfo &MRI, OpTy &&Op) {
247 bool match(const MachineRegisterInfo &MRI, OpTy &&Op) {
include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h 62 Register Reg;
69 DstOp(Register R) : Reg(R), Ty(DstType::Ty_Reg) {}
100 Register getReg() const {
123 Register Reg;
130 SrcOp(Register R) : Reg(R), Ty(SrcType::Ty_Reg) {}
172 Register getReg() const {
347 MachineInstrBuilder buildDirectDbgValue(Register Reg, const MDNode *Variable,
353 MachineInstrBuilder buildIndirectDbgValue(Register Reg,
437 Optional<MachineInstrBuilder> materializeGEP(Register &Res, Register Op0,
437 Optional<MachineInstrBuilder> materializeGEP(Register &Res, Register Op0,
636 MachineInstrBuilder buildBrCond(Register Tst, MachineBasicBlock &Dest);
646 MachineInstrBuilder buildBrIndirect(Register Tgt);
659 MachineInstrBuilder buildBrJT(Register TablePtr, unsigned JTI,
660 Register IndexReg);
770 void buildSequence(Register Res, ArrayRef<Register> Ops,
770 void buildSequence(Register Res, ArrayRef<Register> Ops,
784 MachineInstrBuilder buildMerge(const DstOp &Res, ArrayRef<Register> Ops);
797 MachineInstrBuilder buildUnmerge(ArrayRef<Register> Res, const SrcOp &Op);
812 ArrayRef<Register> Ops);
833 ArrayRef<Register> Ops);
847 ArrayRef<Register> Ops);
849 MachineInstrBuilder buildInsert(Register Res, Register Src,
849 MachineInstrBuilder buildInsert(Register Res, Register Src,
850 Register Op, unsigned Index);
862 MachineInstrBuilder buildIntrinsic(Intrinsic::ID ID, ArrayRef<Register> Res,
982 buildAtomicCmpXchgWithSuccess(Register OldValRes, Register SuccessRes,
982 buildAtomicCmpXchgWithSuccess(Register OldValRes, Register SuccessRes,
983 Register Addr, Register CmpVal, Register NewVal,
983 Register Addr, Register CmpVal, Register NewVal,
983 Register Addr, Register CmpVal, Register NewVal,
1000 MachineInstrBuilder buildAtomicCmpXchg(Register OldValRes, Register Addr,
1000 MachineInstrBuilder buildAtomicCmpXchg(Register OldValRes, Register Addr,
1001 Register CmpVal, Register NewVal,
1001 Register CmpVal, Register NewVal,
1033 MachineInstrBuilder buildAtomicRMWXchg(Register OldValRes, Register Addr,
1033 MachineInstrBuilder buildAtomicRMWXchg(Register OldValRes, Register Addr,
1034 Register Val, MachineMemOperand &MMO);
1048 MachineInstrBuilder buildAtomicRMWAdd(Register OldValRes, Register Addr,
1048 MachineInstrBuilder buildAtomicRMWAdd(Register OldValRes, Register Addr,
1049 Register Val, MachineMemOperand &MMO);
1063 MachineInstrBuilder buildAtomicRMWSub(Register OldValRes, Register Addr,
1063 MachineInstrBuilder buildAtomicRMWSub(Register OldValRes, Register Addr,
1064 Register Val, MachineMemOperand &MMO);
1078 MachineInstrBuilder buildAtomicRMWAnd(Register OldValRes, Register Addr,
1078 MachineInstrBuilder buildAtomicRMWAnd(Register OldValRes, Register Addr,
1079 Register Val, MachineMemOperand &MMO);
1094 MachineInstrBuilder buildAtomicRMWNand(Register OldValRes, Register Addr,
1094 MachineInstrBuilder buildAtomicRMWNand(Register OldValRes, Register Addr,
1095 Register Val, MachineMemOperand &MMO);
1109 MachineInstrBuilder buildAtomicRMWOr(Register OldValRes, Register Addr,
1109 MachineInstrBuilder buildAtomicRMWOr(Register OldValRes, Register Addr,
1110 Register Val, MachineMemOperand &MMO);
1124 MachineInstrBuilder buildAtomicRMWXor(Register OldValRes, Register Addr,
1124 MachineInstrBuilder buildAtomicRMWXor(Register OldValRes, Register Addr,
1125 Register Val, MachineMemOperand &MMO);
1140 MachineInstrBuilder buildAtomicRMWMax(Register OldValRes, Register Addr,
1140 MachineInstrBuilder buildAtomicRMWMax(Register OldValRes, Register Addr,
1141 Register Val, MachineMemOperand &MMO);
1156 MachineInstrBuilder buildAtomicRMWMin(Register OldValRes, Register Addr,
1156 MachineInstrBuilder buildAtomicRMWMin(Register OldValRes, Register Addr,
1157 Register Val, MachineMemOperand &MMO);
1172 MachineInstrBuilder buildAtomicRMWUmax(Register OldValRes, Register Addr,
1172 MachineInstrBuilder buildAtomicRMWUmax(Register OldValRes, Register Addr,
1173 Register Val, MachineMemOperand &MMO);
1188 MachineInstrBuilder buildAtomicRMWUmin(Register OldValRes, Register Addr,
1188 MachineInstrBuilder buildAtomicRMWUmin(Register OldValRes, Register Addr,
1189 Register Val, MachineMemOperand &MMO);
1212 MachineInstrBuilder buildBlockAddress(Register Res, const BlockAddress *BA);
include/llvm/CodeGen/GlobalISel/RegBankSelect.h 526 bool assignmentMatch(Register Reg,
565 const iterator_range<SmallVectorImpl<Register>::const_iterator>
include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h 285 SmallVector<Register, 8> NewVRegs;
306 iterator_range<SmallVectorImpl<Register>::iterator>
312 SmallVectorImpl<Register>::const_iterator
314 SmallVectorImpl<Register>::iterator getNewVRegsEnd(unsigned StartIdx,
360 void setVRegs(unsigned OpIdx, unsigned PartialMapIdx, Register NewVReg);
374 iterator_range<SmallVectorImpl<Register>::const_iterator>
438 getMinimalPhysRegClass(Register Reg, const TargetRegisterInfo &TRI) const;
583 const RegisterBank *getRegBank(Register Reg, const MachineRegisterInfo &MRI,
644 constrainGenericRegister(Register Reg, const TargetRegisterClass &RC,
729 unsigned getSizeInBits(Register Reg, const MachineRegisterInfo &MRI,
include/llvm/CodeGen/GlobalISel/Utils.h 138 MachineInstr *getOpcodeDef(unsigned Opcode, Register Reg,
144 MachineInstr *getDefIgnoringCopies(Register Reg,
163 bool isKnownNeverNaN(Register Val, const MachineRegisterInfo &MRI,
167 inline bool isKnownNeverSNaN(Register Val, const MachineRegisterInfo &MRI) {
include/llvm/CodeGen/LiveIntervals.h 114 LiveInterval &getInterval(Register Reg) {
121 const LiveInterval &getInterval(Register Reg) const {
125 bool hasInterval(Register Reg) const {
131 LiveInterval &createEmptyInterval(Register Reg) {
138 LiveInterval &createAndComputeVirtRegInterval(Register Reg) {
include/llvm/CodeGen/LiveRegUnits.h 56 Register Reg = O->getReg();
include/llvm/CodeGen/MachineInstr.h 1188 bool readsRegister(Register Reg,
1196 bool readsVirtualRegister(Register Reg) const {
1203 std::pair<bool,bool> readsWritesVirtualRegister(Register Reg,
1209 bool killsRegister(Register Reg,
1218 bool definesRegister(Register Reg,
1226 bool modifiesRegister(Register Reg, const TargetRegisterInfo *TRI) const {
1233 bool registerDefIsDead(Register Reg,
1240 bool hasRegisterImplicitUseOperand(Register Reg) const;
1245 int findRegisterUseOperandIdx(Register Reg, bool isKill = false,
1250 MachineOperand *findRegisterUseOperand(Register Reg, bool isKill = false,
1257 Register Reg, bool isKill = false,
1269 int findRegisterDefOperandIdx(Register Reg,
1276 findRegisterDefOperand(Register Reg, bool isDead = false,
1284 findRegisterDefOperand(Register Reg, bool isDead = false,
1331 Register Reg, const TargetRegisterClass *CurRC,
1394 void substituteRegister(Register FromReg, Register ToReg, unsigned SubIdx,
1394 void substituteRegister(Register FromReg, Register ToReg, unsigned SubIdx,
1401 bool addRegisterKilled(Register IncomingReg,
1407 void clearRegisterKills(Register Reg, const TargetRegisterInfo *RegInfo);
1413 bool addRegisterDead(Register Reg, const TargetRegisterInfo *RegInfo,
1417 void clearRegisterDeads(Register Reg);
1422 void setRegisterDefReadUndef(Register Reg, bool IsUndef = true);
1426 void addRegisterDefined(Register Reg,
1434 void setPhysRegsDeadExcept(ArrayRef<Register> UsedRegs,
1659 void changeDebugValuesDefReg(Register Reg);
1690 unsigned OpIdx, Register Reg, const TargetRegisterClass *CurRC,
include/llvm/CodeGen/MachineInstrBuilder.h 85 Register getReg(unsigned Idx) const { return MI->getOperand(Idx).getReg(); }
88 const MachineInstrBuilder &addReg(Register RegNo, unsigned flags = 0,
107 const MachineInstrBuilder &addDef(Register RegNo, unsigned Flags = 0,
114 const MachineInstrBuilder &addUse(Register RegNo, unsigned Flags = 0,
324 const MCInstrDesc &MCID, Register DestReg) {
335 Register DestReg) {
360 Register DestReg) {
370 Register DestReg) {
424 const MCInstrDesc &MCID, Register DestReg) {
434 Register Reg, const MDNode *Variable,
450 Register Reg, const MDNode *Variable,
503 getRenamableRegState(Register::isPhysicalRegister(RegOp.getReg()) &&
include/llvm/CodeGen/MachineOperand.h 353 Register getReg() const {
462 void setReg(Register Reg);
475 void substVirtReg(Register Reg, unsigned SubIdx, const TargetRegisterInfo&);
748 void ChangeToRegister(Register Reg, bool isDef, bool isImp = false,
774 static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp = false,
include/llvm/CodeGen/MachineRegisterInfo.h 110 MachineOperand *&getRegUseDefListHead(Register RegNo) {
116 MachineOperand *getRegUseDefListHead(Register RegNo) const {
217 bool shouldTrackSubRegLiveness(Register VReg) const {
377 bool reg_nodbg_empty(Register RegNo) const {
631 const TargetRegisterClass *getRegClass(Register Reg) const {
720 Register createVirtualRegister(const TargetRegisterClass *RegClass,
725 Register cloneVirtualRegister(Register VReg, StringRef Name = "");
725 Register cloneVirtualRegister(Register VReg, StringRef Name = "");
730 if (Register::isVirtualRegister(Reg) && VRegToType.inBounds(Reg))
740 Register createGenericVirtualRegister(LLT Ty, StringRef Name = "");
792 getRegAllocationHint(Register VReg) const {
802 Register getSimpleHint(Register VReg) const {
802 Register getSimpleHint(Register VReg) const {
897 bool isReserved(Register PhysReg) const {
1179 if (Register::isVirtualRegister(RegUnit)) {
include/llvm/CodeGen/ModuloSchedule.h 329 Register getEquivalentRegisterIn(Register Reg, MachineBasicBlock *BB);
329 Register getEquivalentRegisterIn(Register Reg, MachineBasicBlock *BB);
include/llvm/CodeGen/Register.h 120 bool operator==(const Register &Other) const { return Reg == Other.Reg; }
121 bool operator!=(const Register &Other) const { return Reg != Other.Reg; }
146 static unsigned getHashValue(const Register &Val) {
149 static bool isEqual(const Register &LHS, const Register &RHS) {
149 static bool isEqual(const Register &LHS, const Register &RHS) {
include/llvm/CodeGen/RegisterPressure.h 279 if (Register::isVirtualRegister(Reg))
280 return Register::virtReg2Index(Reg) + NumRegUnits;
287 return Register::index2VirtReg(SparseIndex-NumRegUnits);
include/llvm/CodeGen/RegisterScavenging.h 54 Register Reg;
122 bool isRegUsed(Register Reg, bool includeReserved = true) const;
129 Register FindUnusedReg(const TargetRegisterClass *RC) const;
163 Register scavengeRegister(const TargetRegisterClass *RC,
166 Register scavengeRegister(const TargetRegisterClass *RegClass, int SPAdj,
180 Register scavengeRegisterBackwards(const TargetRegisterClass &RC,
186 void setRegUsed(Register Reg, LaneBitmask LaneMask = LaneBitmask::getAll());
190 bool isReserved(Register Reg) const { return MRI->isReserved(Reg); }
206 void addRegUnits(BitVector &BV, Register Reg);
209 void removeRegUnits(BitVector &BV, Register Reg);
215 Register findSurvivorReg(MachineBasicBlock::iterator StartMI,
228 ScavengedInfo &spill(Register Reg, const TargetRegisterClass &RC, int SPAdj,
include/llvm/CodeGen/ScheduleDAGInstrs.h 61 return Register::virtReg2Index(VirtReg);
include/llvm/CodeGen/SwiftErrorValueTracking.h 45 DenseMap<std::pair<const MachineBasicBlock *, const Value *>, Register>
51 DenseMap<std::pair<const MachineBasicBlock *, const Value *>, Register>
56 llvm::DenseMap<PointerIntPair<const Instruction *, 1, bool>, Register>
80 Register getOrCreateVReg(const MachineBasicBlock *, const Value *);
84 void setCurrentVReg(const MachineBasicBlock *MBB, const Value *, Register);
88 Register getOrCreateVRegDefAt(const Instruction *, const MachineBasicBlock *,
93 Register getOrCreateVRegUseAt(const Instruction *, const MachineBasicBlock *,
include/llvm/CodeGen/TargetLowering.h 2990 virtual bool isIndexingLegal(MachineInstr &MI, Register Base, Register Offset,
2990 virtual bool isIndexingLegal(MachineInstr &MI, Register Base, Register Offset,
3183 Register R, KnownBits &Known,
3699 virtual Register getRegisterByName(const char* RegName, EVT VT,
include/llvm/CodeGen/TargetRegisterInfo.h 92 if (!Register::isPhysicalRegister(Reg))
101 if (!Register::isPhysicalRegister(Reg1) ||
102 !Register::isPhysicalRegister(Reg2))
380 bool regsOverlap(Register regA, Register regB) const {
380 bool regsOverlap(Register regA, Register regB) const {
960 virtual Register getFrameRegister(const MachineFunction &MF) const = 0;
979 inline Register getSubReg(MCRegister Reg, unsigned Idx) const {
1133 return Register::virtReg2Index(Reg);
1147 Printable printReg(Register Reg, const TargetRegisterInfo *TRI = nullptr,
include/llvm/CodeGen/VirtRegMap.h 52 IndexedMap<Register, VirtReg2IndexFunctor> Virt2PhysMap;
96 bool hasPhys(Register virtReg) const {
102 Register getPhys(Register virtReg) const {
102 Register getPhys(Register virtReg) const {
109 void assignVirt2Phys(Register virtReg, MCPhysReg physReg);
113 void clearVirt(Register virtReg) {
127 bool hasPreferredPhys(Register VirtReg);
132 bool hasKnownPreference(Register VirtReg);
135 void setIsSplitFromReg(Register virtReg, unsigned SReg) {
140 unsigned getPreSplitReg(Register virtReg) const {
155 bool isAssignedReg(Register virtReg) const {
166 int getStackSlot(Register virtReg) const {
173 int assignVirt2StackSlot(Register virtReg);
177 void assignVirt2StackSlot(Register virtReg, int SS);
include/llvm/Support/AlignOf.h 30 T t;
39 template <typename T> union SizerImpl<T> { char arr[sizeof(T)]; };
50 llvm::detail::SizerImpl<T, Ts...>)];
include/llvm/Support/type_traits.h 65 using type = const T &;
91 T t;
122 static auto get(F*) -> decltype(std::declval<F &>() = std::declval<const F &>(), std::true_type{});
122 static auto get(F*) -> decltype(std::declval<F &>() = std::declval<const F &>(), std::true_type{});
122 static auto get(F*) -> decltype(std::declval<F &>() = std::declval<const F &>(), std::true_type{});
130 static auto get(F*) -> decltype(std::declval<F &>() = std::declval<F &&>(), std::true_type{});
130 static auto get(F*) -> decltype(std::declval<F &>() = std::declval<F &&>(), std::true_type{});
130 static auto get(F*) -> decltype(std::declval<F &>() = std::declval<F &&>(), std::true_type{});
145 std::is_copy_constructible<detail::trivial_helper<T>>::value;
147 !std::is_copy_constructible<T>::value;
151 std::is_move_constructible<detail::trivial_helper<T>>::value;
153 !std::is_move_constructible<T>::value;
157 is_copy_assignable<detail::trivial_helper<T>>::value;
159 !is_copy_assignable<T>::value;
163 is_move_assignable<detail::trivial_helper<T>>::value;
165 !is_move_assignable<T>::value;
169 std::is_destructible<detail::trivial_helper<T>>::value;
181 static_assert(value == std::is_trivially_copyable<T>::value,
lib/CodeGen/AggressiveAntiDepBreaker.cpp 235 Register Reg = MO.getReg();
255 const Register Reg = MO.getReg();
368 Register Reg = MO.getReg();
378 Register Reg = MO.getReg();
421 Register Reg = MO.getReg();
474 Register Reg = MO.getReg();
509 Register Reg = MO.getReg();
lib/CodeGen/AsmPrinter/AsmPrinter.cpp 793 Register RegNo = MI->getOperand(0).getReg();
lib/CodeGen/AsmPrinter/DbgEntityHistoryCalculator.cpp 41 static Register isDescribedByReg(const MachineInstr &MI) {
180 if (Register Reg = isDescribedByReg(DV))
186 if (Register NewReg = isDescribedByReg(DV)) {
237 Register FrameReg = TRI->getFrameRegister(*MF);
278 if (Register::isVirtualRegister(MO.getReg()))
299 if (Reg != SP && Register::isPhysicalRegister(Reg) &&
lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp 401 if (Register::isPhysicalRegister(Location.getReg()))
lib/CodeGen/AsmPrinter/DwarfDebug.cpp 591 Register::isPhysicalRegister(MO.getReg())) {
653 Register RegLoc = ParamValue->first.getReg();
655 Register FP = TRI->getFrameRegister(*MF);
lib/CodeGen/AsmPrinter/DwarfExpression.cpp 101 if (!llvm::Register::isPhysicalRegister(MachineReg)) {
lib/CodeGen/BranchFolding.cpp 1854 if (Register::isPhysicalRegister(Reg)) {
1882 Register Reg = MO.getReg();
1920 Register Reg = MO.getReg();
1948 Register Reg = MO.getReg();
1955 if (Register::isPhysicalRegister(Reg)) {
2021 Register Reg = MO.getReg();
2071 Register Reg = MO.getReg();
2077 if (Register::isPhysicalRegister(Reg)) {
2089 Register Reg = MO.getReg();
2090 if (!Reg || Register::isVirtualRegister(Reg))
lib/CodeGen/BreakFalseDeps.cpp 112 Register OriginalReg = MO.getReg();
165 Register reg = MI->getOperand(OpIdx).getReg();
lib/CodeGen/CalcSpillWeights.cpp 43 unsigned Reg = Register::index2VirtReg(i);
51 static Register copyHint(const MachineInstr *mi, unsigned reg,
55 Register hreg;
69 if (Register::isVirtualRegister(hreg))
73 Register CopiedPReg = (hsub ? tri.getSubReg(hreg, hsub) : hreg);
116 if (!Register::isVirtualRegister(Reg) ||
247 Register hint = copyHint(mi, li.reg, tri, mri);
255 if (Register::isVirtualRegister(hint) || mri.isAllocatable(hint))
257 CopyHint(hint, hweight, Register::isPhysicalRegister(hint)));
lib/CodeGen/CriticalAntiDepBreaker.cpp 190 Register Reg = MO.getReg();
275 Register Reg = MO.getReg();
306 Register Reg = MO.getReg();
616 Register Reg = MO.getReg();
lib/CodeGen/DeadMachineInstructionElim.cpp 78 Register Reg = MO.getReg();
79 if (Register::isPhysicalRegister(Reg)) {
143 Register Reg = MO.getReg();
144 if (Register::isPhysicalRegister(Reg)) {
162 Register Reg = MO.getReg();
163 if (Register::isPhysicalRegister(Reg)) {
lib/CodeGen/DetectDeadLanes.cpp 157 Register SrcReg = MO.getReg();
197 Register MOReg = MO.getReg();
198 if (!Register::isVirtualRegister(MOReg))
206 unsigned MORegIdx = Register::virtReg2Index(MOReg);
222 if (!MO.isReg() || !Register::isVirtualRegister(MO.getReg()))
253 Register DefReg = Def.getReg();
288 Register DefReg = Def.getReg();
289 if (!Register::isVirtualRegister(DefReg))
291 unsigned DefRegIdx = Register::virtReg2Index(DefReg);
363 unsigned RegIdx = Register::virtReg2Index(Reg);
380 Register MOReg = MO.getReg();
385 if (Register::isPhysicalRegister(MOReg)) {
431 Register DefReg = Def.getReg();
434 if (Register::isVirtualRegister(DefReg)) {
473 Register DefReg = Def.getReg();
474 if (!Register::isVirtualRegister(DefReg))
476 unsigned DefRegIdx = Register::virtReg2Index(DefReg);
485 Register MOReg = MO.getReg();
486 if (Register::isVirtualRegister(MOReg)) {
497 unsigned Reg = Register::index2VirtReg(RegIdx);
511 unsigned Reg = Register::index2VirtReg(RegIdx);
539 Register Reg = MO.getReg();
540 if (!Register::isVirtualRegister(Reg))
542 unsigned RegIdx = Register::virtReg2Index(Reg);
lib/CodeGen/EarlyIfConversion.cpp 262 Register Reg = MO.getReg();
265 if (MO.isDef() && Register::isPhysicalRegister(Reg))
269 if (!MO.readsReg() || !Register::isVirtualRegister(Reg))
382 Register Reg = MO.getReg();
383 if (!Register::isPhysicalRegister(Reg))
569 Register DstReg = PI.PHI->getOperand(0).getReg();
596 Register PHIDst = PI.PHI->getOperand(0).getReg();
lib/CodeGen/ExpandPostRAPseudos.cpp 82 Register DstReg = MI->getOperand(0).getReg();
83 Register InsReg = MI->getOperand(2).getReg();
88 Register DstSubReg = TRI->getSubReg(DstReg, SubIdx);
lib/CodeGen/GlobalISel/CSEInfo.cpp 336 Register Reg = MO.getReg();
lib/CodeGen/GlobalISel/CallLowering.cpp 33 ArrayRef<Register> ResRegs,
34 ArrayRef<ArrayRef<Register>> ArgRegs,
35 Register SwiftErrorVReg,
126 Register CallLowering::packRegs(ArrayRef<Register> SrcRegs, Type *PackedTy,
126 Register CallLowering::packRegs(ArrayRef<Register> SrcRegs, Type *PackedTy,
140 Register Dst = MRI->createGenericVirtualRegister(PackedLLT);
143 Register NewDst = MRI->createGenericVirtualRegister(PackedLLT);
151 void CallLowering::unpackRegs(ArrayRef<Register> DstRegs, Register SrcReg,
151 void CallLowering::unpackRegs(ArrayRef<Register> DstRegs, Register SrcReg,
232 Register Reg =
258 Register LargeReg = Args[i].Regs[0];
297 Register ArgReg = Args[i].Regs[0];
323 Register NewReg =
369 Register StackAddr = Handler.getStackAddress(Size, Offset, MPO);
454 Register CallLowering::ValueHandler::extendRegister(Register ValReg,
454 Register CallLowering::ValueHandler::extendRegister(Register ValReg,
471 Register NewReg = MRI.createGenericVirtualRegister(LocTy);
476 Register NewReg = MRI.createGenericVirtualRegister(LocTy);
lib/CodeGen/GlobalISel/CombinerHelper.cpp 42 void CombinerHelper::replaceRegWith(MachineRegisterInfo &MRI, Register FromReg,
43 Register ToReg) const {
56 Register ToReg) const {
75 Register DstReg = MI.getOperand(0).getReg();
76 Register SrcReg = MI.getOperand(1).getReg();
86 Register DstReg = MI.getOperand(0).getReg();
87 Register SrcReg = MI.getOperand(1).getReg();
94 SmallVector<Register, 4> Ops;
103 SmallVectorImpl<Register> &Ops) {
116 Register Reg = MO.getReg();
155 MachineInstr &MI, bool IsUndef, const ArrayRef<Register> Ops) {
158 Register DstReg = MI.getOperand(0).getReg();
160 Register NewDstReg = MRI.cloneVirtualRegister(DstReg);
177 SmallVector<Register, 4> Ops;
186 SmallVectorImpl<Register> &Ops) {
190 Register Src1 = MI.getOperand(1).getReg();
234 Register UndefReg;
235 Register Src2 = MI.getOperand(2).getReg();
252 const ArrayRef<Register> Ops) {
253 Register DstReg = MI.getOperand(0).getReg();
255 Register NewDstReg = MRI.cloneVirtualRegister(DstReg);
426 Register ChosenDstReg = Preferred.MI->getOperand(0).getReg();
443 Register NewDstReg = MRI.cloneVirtualRegister(MI.getOperand(0).getReg());
470 Register UseDstReg = UseMI->getOperand(0).getReg();
555 bool CombinerHelper::findPostIndexCandidate(MachineInstr &MI, Register &Addr,
556 Register &Base, Register &Offset) {
556 Register &Base, Register &Offset) {
622 bool CombinerHelper::findPreIndexCandidate(MachineInstr &MI, Register &Addr,
623 Register &Base, Register &Offset) {
623 Register &Base, Register &Offset) {
690 Register Addr, Base, Offset;
891 static Register getMemsetValue(Register Val, LLT Ty, MachineIRBuilder &MIB) {
891 static Register getMemsetValue(Register Val, LLT Ty, MachineIRBuilder &MIB) {
919 bool CombinerHelper::optimizeMemset(MachineInstr &MI, Register Dst, Register Val,
919 bool CombinerHelper::optimizeMemset(MachineInstr &MI, Register Dst, Register Val,
977 Register MemSetValue = getMemsetValue(Val, LargestTy, MIB);
999 Register Value = MemSetValue;
1015 Register Ptr = Dst;
1032 bool CombinerHelper::optimizeMemcpy(MachineInstr &MI, Register Dst,
1033 Register Src, unsigned KnownLen,
1119 Register LoadPtr = Src;
1120 Register Offset;
1129 Register StorePtr =
1140 bool CombinerHelper::optimizeMemmove(MachineInstr &MI, Register Dst,
1141 Register Src, unsigned KnownLen,
1210 SmallVector<Register, 16> LoadVals;
1217 Register LoadPtr = Src;
1234 Register StorePtr = Dst;
1265 Register Dst = MI.getOperand(1).getReg();
1266 Register Src = MI.getOperand(2).getReg();
1267 Register Len = MI.getOperand(3).getReg();
lib/CodeGen/GlobalISel/GISelKnownBits.cpp 51 void GISelKnownBits::computeKnownBitsForFrameIndex(Register R, KnownBits &Known,
69 KnownBits GISelKnownBits::getKnownBits(Register R) {
78 bool GISelKnownBits::signBitIsZero(Register R) {
84 APInt GISelKnownBits::getKnownZeroes(Register R) {
88 APInt GISelKnownBits::getKnownOnes(Register R) { return getKnownBits(R).One; }
90 void GISelKnownBits::computeKnownBitsImpl(Register R, KnownBits &Known,
350 Register SrcReg = MI.getOperand(1).getReg();
lib/CodeGen/GlobalISel/IRTranslator.cpp 173 ArrayRef<Register> IRTranslator::getOrCreateVRegs(const Value &Val) {
293 Register Op0 = getOrCreateVReg(*U.getOperand(0));
294 Register Op1 = getOrCreateVReg(*U.getOperand(1));
295 Register Res = getOrCreateVReg(U);
310 Register Op1 = getOrCreateVReg(*U.getOperand(1));
311 Register Res = getOrCreateVReg(U);
325 Register Op0 = getOrCreateVReg(*U.getOperand(0));
326 Register Res = getOrCreateVReg(U);
339 Register Op0 = getOrCreateVReg(*U.getOperand(0));
340 Register Op1 = getOrCreateVReg(*U.getOperand(1));
341 Register Res = getOrCreateVReg(U);
368 ArrayRef<Register> VRegs;
372 Register SwiftErrorVReg = 0;
389 Register Tst = getOrCreateVReg(*BrInst.getCondition());
532 Register SwitchOpReg = getOrCreateVReg(SValue);
553 auto Cst = getOrCreateVReg(
569 Register CondLHS = getOrCreateVReg(*CB.CmpLHS);
570 Register Cond;
590 Register CondRHS = getOrCreateVReg(*CB.CmpRHS);
599 Register CmpOpReg = getOrCreateVReg(*CB.CmpMHS);
601 Register CondRHS = getOrCreateVReg(*CB.CmpRHS);
840 const Register Tgt = getOrCreateVReg(*BrInst.getAddress());
869 ArrayRef<Register> Regs = getOrCreateVRegs(LI);
871 Register Base = getOrCreateVReg(*LI.getPointerOperand());
878 Register VReg = SwiftError.getOrCreateVRegUseAt(&LI, &MIRBuilder.getMBB(),
887 Register Addr;
911 ArrayRef<Register> Vals = getOrCreateVRegs(*SI.getValueOperand());
913 Register Base = getOrCreateVReg(*SI.getPointerOperand());
921 Register VReg = SwiftError.getOrCreateVRegDefAt(&SI, &MIRBuilder.getMBB(),
928 Register Addr;
970 ArrayRef<Register> SrcRegs = getOrCreateVRegs(*Src);
987 ArrayRef<Register> SrcRegs = getOrCreateVRegs(*Src);
988 ArrayRef<Register> InsertedRegs = getOrCreateVRegs(*U.getOperand(1));
1003 Register Tst = getOrCreateVReg(*U.getOperand(0));
1004 ArrayRef<Register> ResRegs = getOrCreateVRegs(U);
1005 ArrayRef<Register> Op0Regs = getOrCreateVRegs(*U.getOperand(1));
1006 ArrayRef<Register> Op1Regs = getOrCreateVRegs(*U.getOperand(2));
1026 Register SrcReg = getOrCreateVReg(*U.getOperand(0));
1043 Register Op = getOrCreateVReg(*U.getOperand(0));
1044 Register Res = getOrCreateVReg(U);
1056 Register BaseReg = getOrCreateVReg(Op0);
1088 Register IdxReg = getOrCreateVReg(*Idx);
1094 Register GepOffsetReg;
1126 ArrayRef<Register> Res;
1165 void IRTranslator::getStackGuard(Register DstReg,
1188 ArrayRef<Register> ResRegs = getOrCreateVRegs(CI);
1385 for (Register Reg : getOrCreateVRegs(*V)) {
1410 Register Dst = getOrCreateVReg(CI);
1411 Register Op0 = getOrCreateVReg(*CI.getArgOperand(0));
1412 Register Op1 = getOrCreateVReg(*CI.getArgOperand(1));
1413 Register Op2 = getOrCreateVReg(*CI.getArgOperand(2));
1435 Register Reg = getOrCreateVReg(CI);
1451 Register GuardVal = MRI->createGenericVirtualRegister(PtrTy);
1468 Register Reg = getOrCreateVReg(CI);
1469 Register StackPtr = MF->getSubtarget()
1482 Register Reg = getOrCreateVReg(*CI.getArgOperand(0));
1483 Register StackPtr = MF->getSubtarget()
1510 Register Undef = MRI->createGenericVirtualRegister(PtrTy);
1547 ArrayRef<Register> Res = getOrCreateVRegs(I);
1549 SmallVector<ArrayRef<Register>, 8> Args;
1550 Register SwiftInVReg = 0;
1551 Register SwiftErrorVReg = 0;
1615 ArrayRef<Register> ResultRegs;
1644 ArrayRef<Register> VRegs = getOrCreateVRegs(*Arg.value());
1755 Register Undef = MRI->createGenericVirtualRegister(Ty);
1764 Register ExceptionReg = TLI.getExceptionPointerRegister(PersonalityFn);
1769 ArrayRef<Register> ResRegs = getOrCreateVRegs(LP);
1772 Register SelectorReg = TLI.getExceptionSelectorRegister(PersonalityFn);
1777 Register PtrVReg = MRI->createGenericVirtualRegister(Tys[0]);
1792 Register Res = getOrCreateVReg(AI);
1807 Register NumElts = getOrCreateVReg(*AI.getArraySize());
1812 Register ExtElts = MRI->createGenericVirtualRegister(IntPtrTy);
1817 Register AllocSize = MRI->createGenericVirtualRegister(IntPtrTy);
1818 Register TySize =
1861 Register Elt = getOrCreateVReg(*U.getOperand(1));
1872 Register Res = getOrCreateVReg(U);
1873 Register Val = getOrCreateVReg(*U.getOperand(0));
1874 Register Elt = getOrCreateVReg(*U.getOperand(1));
1875 Register Idx = getOrCreateVReg(*U.getOperand(2));
1885 Register Elt = getOrCreateVReg(*U.getOperand(0));
1895 Register Res = getOrCreateVReg(U);
1896 Register Val = getOrCreateVReg(*U.getOperand(0));
1899 Register Idx;
1931 for (auto Reg : getOrCreateVRegs(PI)) {
1955 Register OldValRes = Res[0];
1956 Register SuccessRes = Res[1];
1957 Register Addr = getOrCreateVReg(*I.getPointerOperand());
1958 Register Cmp = getOrCreateVReg(*I.getCompareOperand());
1959 Register NewVal = getOrCreateVReg(*I.getNewValOperand());
1981 Register Res = getOrCreateVReg(I);
1982 Register Addr = getOrCreateVReg(*I.getPointerOperand());
1983 Register Val = getOrCreateVReg(*I.getValOperand());
2065 ArrayRef<Register> ValRegs = getOrCreateVRegs(*PI->getIncomingValue(i));
2109 bool IRTranslator::translate(const Constant &C, Register Reg) {
2122 Register ZeroReg = getOrCreateVReg(*ZeroVal);
2132 SmallVector<Register, 4> Ops;
2142 SmallVector<Register, 4> Ops;
2160 SmallVector<Register, 4> Ops;
2297 SmallVector<ArrayRef<Register>, 8> VRegArgs;
2301 ArrayRef<Register> VRegs = getOrCreateVRegs(Arg);
lib/CodeGen/GlobalISel/InstructionSelect.cpp 170 Register SrcReg = MI.getOperand(1).getReg();
171 Register DstReg = MI.getOperand(0).getReg();
172 if (Register::isVirtualRegister(SrcReg) &&
173 Register::isVirtualRegister(DstReg)) {
190 unsigned VReg = Register::index2VirtReg(I);
lib/CodeGen/GlobalISel/LegalizerHelper.cpp 123 void LegalizerHelper::extractParts(Register Reg, LLT Ty, int NumParts,
124 SmallVectorImpl<Register> &VRegs) {
130 bool LegalizerHelper::extractParts(Register Reg, LLT RegTy,
132 SmallVectorImpl<Register> &VRegs,
133 SmallVectorImpl<Register> &LeftoverRegs) {
160 Register NewReg = MRI.createGenericVirtualRegister(MainTy);
167 Register NewReg = MRI.createGenericVirtualRegister(LeftoverTy);
195 void LegalizerHelper::insertParts(Register DstReg,
197 ArrayRef<Register> PartRegs,
199 ArrayRef<Register> LeftoverRegs) {
218 Register CurResultReg = MRI.createGenericVirtualRegister(ResultTy);
222 for (Register PartReg : PartRegs) {
223 Register NewResultReg = MRI.createGenericVirtualRegister(ResultTy);
231 Register NewResultReg = (I + 1 == E) ?
400 Register Reg = MI.getOperand(i).getReg();
615 SmallVector<Register, 2> DstRegs;
620 Register DstReg = MI.getOperand(0).getReg();
635 SmallVector<Register, 4> PartRegs;
645 SmallVector<Register, 1> LeftoverRegs;
664 Register SrcReg = MI.getOperand(1).getReg();
694 Register ZeroReg = MIRBuilder.buildConstant(SrcTy, 0).getReg(0);
696 SmallVector<Register, 4> Srcs = {MI.getOperand(1).getReg()};
727 SmallVector<Register, 2> Src1Regs, Src2Regs, DstRegs;
731 Register CarryIn;
733 Register DstReg = MRI.createGenericVirtualRegister(NarrowTy);
734 Register CarryOut = MRI.createGenericVirtualRegister(LLT::scalar(1));
746 Register DstReg = MI.getOperand(0).getReg();
762 SmallVector<Register, 2> Src1Regs, Src2Regs, DstRegs;
766 Register DstReg = MRI.createGenericVirtualRegister(NarrowTy);
767 Register BorrowOut = MRI.createGenericVirtualRegister(LLT::scalar(1));
771 Register BorrowIn = BorrowOut;
795 Register DstReg = MI.getOperand(0).getReg();
801 Register TmpReg = MRI.createGenericVirtualRegister(NarrowTy);
814 Register DstReg = MI.getOperand(0).getReg();
815 Register PtrReg = MI.getOperand(1).getReg();
817 Register TmpReg = MRI.createGenericVirtualRegister(NarrowTy);
841 Register SrcReg = MI.getOperand(0).getReg();
853 Register TmpReg = MRI.createGenericVirtualRegister(NarrowTy);
913 SmallVector<Register, 2> DstRegs;
914 SmallVector<SmallVector<Register, 2>, 2> SrcRegs;
956 Register LHSL = MRI.createGenericVirtualRegister(NarrowTy);
957 Register LHSH = MRI.createGenericVirtualRegister(NarrowTy);
960 Register RHSL = MRI.createGenericVirtualRegister(NarrowTy);
961 Register RHSH = MRI.createGenericVirtualRegister(NarrowTy);
1005 Register DstExt = MRI.createGenericVirtualRegister(NarrowTy);
1022 SmallVector<Register, 2> DstRegs;
1024 SmallVector<Register, 2> SrcRegs;
1028 Register SrcReg = MRI.createGenericVirtualRegister(NarrowTy);
1036 Register AshrCstReg =
1040 Register FullExtensionReg = 0;
1041 Register PartialExtensionReg = 0;
1073 Register DstReg = MI.getOperand(0).getReg();
1099 Register DstExt = MRI.createGenericVirtualRegister(WideTy);
1108 Register DstTrunc = MRI.createGenericVirtualRegister(NarrowTy);
1117 Register DstExt = MRI.createGenericVirtualRegister(WideTy);
1135 SmallVector<Register, 8> Parts;
1138 Register ImpDef = MIRBuilder.buildUndef(OldTy).getReg(0);
1147 Register MoreReg = MRI.createGenericVirtualRegister(MoreTy);
1148 Register ImpDef = MIRBuilder.buildUndef(MoreTy).getReg(0);
1159 Register DstReg = MI.getOperand(0).getReg();
1164 Register Src1 = MI.getOperand(1).getReg();
1177 Register ResultReg = MIRBuilder.buildZExt(WideTy, Src1).getReg(0);
1182 Register SrcReg = MI.getOperand(I).getReg();
1187 Register NextResult = I + 1 == NumOps && WideTy == DstTy ? DstReg :
1229 SmallVector<Register, 8> Parts;
1230 SmallVector<Register, 8> NewMergeRegs;
1231 SmallVector<Register, 8> Unmerges;
1236 Register SrcReg = MI.getOperand(I).getReg();
1248 Register UndefReg = MIRBuilder.buildUndef(GCDTy).getReg(0);
1256 ArrayRef<Register> Slicer(Unmerges);
1282 Register SrcReg = MI.getOperand(NumDst).getReg();
1287 Register Dst0Reg = MI.getOperand(0).getReg();
1318 Register DstReg = MI.getOperand(0).getReg();
1319 Register SrcReg = MI.getOperand(1).getReg();
1459 Register SrcReg = MI.getOperand(1).getReg();
1492 Register DstReg = MI.getOperand(0).getReg();
1494 Register ShrReg = MRI.createGenericVirtualRegister(WideTy);
1495 Register DstExt = MRI.createGenericVirtualRegister(WideTy);
1496 Register ShiftAmtReg = MRI.createGenericVirtualRegister(WideTy);
1518 Register DstReg = MI.getOperand(0).getReg();
1522 Register DstExt = MRI.createGenericVirtualRegister(WideTy);
1776 Register VecReg = MI.getOperand(1).getReg();
1801 Register VecReg = MI.getOperand(1).getReg();
1918 Register QuotReg = MRI.createGenericVirtualRegister(Ty);
1924 Register ProdReg = MRI.createGenericVirtualRegister(Ty);
1938 Register Res = MI.getOperand(0).getReg();
1939 Register Overflow = MI.getOperand(1).getReg();
1940 Register LHS = MI.getOperand(2).getReg();
1941 Register RHS = MI.getOperand(3).getReg();
1949 Register HiPart = MRI.createGenericVirtualRegister(Ty);
1955 Register Zero = MRI.createGenericVirtualRegister(Ty);
1961 Register Shifted = MRI.createGenericVirtualRegister(Ty);
1962 Register ShiftAmt = MRI.createGenericVirtualRegister(Ty);
1980 Register Res = MI.getOperand(0).getReg();
2002 Register SubByReg = MI.getOperand(1).getReg();
2003 Register ZeroReg = Zero->getOperand(0).getReg();
2015 Register Res = MI.getOperand(0).getReg();
2016 Register LHS = MI.getOperand(1).getReg();
2017 Register RHS = MI.getOperand(2).getReg();
2018 Register Neg = MRI.createGenericVirtualRegister(Ty);
2027 Register OldValRes = MI.getOperand(0).getReg();
2028 Register SuccessRes = MI.getOperand(1).getReg();
2029 Register Addr = MI.getOperand(2).getReg();
2030 Register CmpVal = MI.getOperand(3).getReg();
2031 Register NewVal = MI.getOperand(4).getReg();
2042 Register DstReg = MI.getOperand(0).getReg();
2043 Register PtrReg = MI.getOperand(1).getReg();
2079 Register LargeLdReg = MRI.createGenericVirtualRegister(AnyExtTy);
2080 Register SmallLdReg = MRI.createGenericVirtualRegister(AnyExtTy);
2086 Register GEPReg = MRI.createGenericVirtualRegister(PtrTy);
2104 Register TmpReg =
2133 Register SrcReg = MI.getOperand(0).getReg();
2134 Register PtrReg = MI.getOperand(1).getReg();
2158 Register GEPReg = MRI.createGenericVirtualRegister(PtrTy);
2178 Register Res = MI.getOperand(0).getReg();
2179 Register CarryOut = MI.getOperand(1).getReg();
2180 Register LHS = MI.getOperand(2).getReg();
2181 Register RHS = MI.getOperand(3).getReg();
2190 Register Res = MI.getOperand(0).getReg();
2191 Register CarryOut = MI.getOperand(1).getReg();
2192 Register LHS = MI.getOperand(2).getReg();
2193 Register RHS = MI.getOperand(3).getReg();
2194 Register CarryIn = MI.getOperand(4).getReg();
2196 Register TmpRes = MRI.createGenericVirtualRegister(Ty);
2197 Register ZExtCarryIn = MRI.createGenericVirtualRegister(Ty);
2208 Register Res = MI.getOperand(0).getReg();
2209 Register BorrowOut = MI.getOperand(1).getReg();
2210 Register LHS = MI.getOperand(2).getReg();
2211 Register RHS = MI.getOperand(3).getReg();
2220 Register Res = MI.getOperand(0).getReg();
2221 Register BorrowOut = MI.getOperand(1).getReg();
2222 Register LHS = MI.getOperand(2).getReg();
2223 Register RHS = MI.getOperand(3).getReg();
2224 Register BorrowIn = MI.getOperand(4).getReg();
2226 Register TmpRes = MRI.createGenericVirtualRegister(Ty);
2227 Register ZExtBorrowIn = MRI.createGenericVirtualRegister(Ty);
2228 Register LHS_EQ_RHS = MRI.createGenericVirtualRegister(LLT::scalar(1));
2229 Register LHS_ULT_RHS = MRI.createGenericVirtualRegister(LLT::scalar(1));
2263 Register DstReg = MI.getOperand(0).getReg();
2264 Register SrcReg = MI.getOperand(1).getReg();
2266 Register TmpRes = MRI.createGenericVirtualRegister(DstTy);
2287 SmallVector<Register, 2> DstRegs;
2290 Register DstReg = MI.getOperand(0).getReg();
2299 Register TmpReg = MRI.createGenericVirtualRegister(NarrowTy);
2319 const Register DstReg = MI.getOperand(0).getReg();
2334 Register AccumDstReg = MRI.createGenericVirtualRegister(DstTy);
2342 Register PartOpReg = MRI.createGenericVirtualRegister(NarrowTy);
2347 Register PartDstReg = MRI.createGenericVirtualRegister(NarrowTy);
2350 Register PartInsertReg = MRI.createGenericVirtualRegister(DstTy);
2358 Register PartOpReg = MRI.createGenericVirtualRegister(EltTy);
2364 Register PartDstReg = MRI.createGenericVirtualRegister(EltTy);
2372 SmallVector<Register, 2> DstRegs, Src0Regs, Src1Regs, Src2Regs;
2383 Register DstReg = MRI.createGenericVirtualRegister(NarrowTy);
2428 const Register DstReg = MI.getOperand(0).getReg();
2441 SmallVector<Register, 4> DstRegs, LeftoverDstRegs;
2442 SmallVector<Register, 4> PartRegs, LeftoverRegs;
2446 Register SrcReg = MI.getOperand(I).getReg();
2460 for (Register PartReg : PartRegs) {
2461 Register PartDstReg = MRI.createGenericVirtualRegister(NarrowTy0);
2468 for (Register LeftoverReg : LeftoverRegs) {
2469 Register PartDstReg = MRI.createGenericVirtualRegister(LeftoverTy0);
2508 Register DstReg = MI.getOperand(0).getReg();
2509 Register SrcReg = MI.getOperand(1).getReg();
2529 SmallVector<Register, 4> SrcRegs, DstRegs;
2533 Register DstReg = MRI.createGenericVirtualRegister(NarrowTy0);
2554 Register DstReg = MI.getOperand(0).getReg();
2555 Register Src0Reg = MI.getOperand(2).getReg();
2592 SmallVector<Register, 2> Src1Regs, Src2Regs, DstRegs;
2597 Register DstReg = MRI.createGenericVirtualRegister(NarrowTy0);
2621 Register DstReg = MI.getOperand(0).getReg();
2622 Register CondReg = MI.getOperand(1).getReg();
2667 SmallVector<Register, 2> DstRegs, Src0Regs, Src1Regs, Src2Regs;
2675 Register DstReg = MRI.createGenericVirtualRegister(NarrowTy0);
2693 const Register DstReg = MI.getOperand(0).getReg();
2706 SmallVector<Register, 4> DstRegs, LeftoverDstRegs;
2714 Register PartDstReg = MRI.createGenericVirtualRegister(Ty);
2727 SmallVector<Register, 4> PartRegs, LeftoverRegs;
2734 Register SrcReg = MI.getOperand(I).getReg();
2765 const Register SrcReg = MI.getOperand(NumDst).getReg();
2802 Register DstReg = MI.getOperand(0).getReg();
2811 SmallVector<Register, 8> ConcatOps;
2812 SmallVector<Register, 8> SubBuildVector;
2814 Register UndefReg;
2834 Register SrcReg = MI.getOperand(SrcIdx + 1).getReg();
2872 Register ValReg = MI.getOperand(0).getReg();
2873 Register AddrReg = MI.getOperand(1).getReg();
2879 SmallVector<Register, 8> NarrowRegs, NarrowLeftoverRegs;
2909 Register NewAddrReg;
2917 Register Dst = MRI.createGenericVirtualRegister(PartTy);
3045 Register InL = MRI.createGenericVirtualRegister(HalfTy);
3046 Register InH = MRI.createGenericVirtualRegister(HalfTy);
3140 Register DstReg = MI.getOperand(0).getReg();
3145 Register Amt = MI.getOperand(2).getReg();
3169 Register InL = MRI.createGenericVirtualRegister(HalfTy);
3170 Register InH = MRI.createGenericVirtualRegister(HalfTy);
3180 Register ResultRegs[2];
3349 void LegalizerHelper::multiplyRegisters(SmallVectorImpl<Register> &DstRegs,
3350 ArrayRef<Register> Src1Regs,
3351 ArrayRef<Register> Src2Regs,
3358 Register FactorSum =
3363 SmallVector<Register, 4> Factors;
3385 Register CarrySum;
3414 Register DstReg = MI.getOperand(0).getReg();
3415 Register Src1 = MI.getOperand(1).getReg();
3416 Register Src2 = MI.getOperand(2).getReg();
3433 SmallVector<Register, 2> Src1Parts, Src2Parts, DstTmpRegs;
3440 ArrayRef<Register> DstRegs(
3462 SmallVector<Register, 2> SrcRegs, DstRegs;
3466 Register OpReg = MI.getOperand(0).getReg();
3493 Register SegReg = SrcRegs[i];
3503 Register DstReg = MI.getOperand(0).getReg();
3529 SmallVector<Register, 2> SrcRegs, DstRegs;
3533 Register OpReg = MI.getOperand(2).getReg();
3565 Register SegReg = OpReg;
3572 Register DstReg = MRI.createGenericVirtualRegister(NarrowTy);
3578 Register DstReg = MI.getOperand(0).getReg();
3590 Register DstReg = MI.getOperand(0).getReg();
3595 SmallVector<Register, 4> DstRegs, DstLeftoverRegs;
3596 SmallVector<Register, 4> Src0Regs, Src0LeftoverRegs;
3597 SmallVector<Register, 4> Src1Regs, Src1LeftoverRegs;
3634 Register CondReg = MI.getOperand(1).getReg();
3639 Register DstReg = MI.getOperand(0).getReg();
3642 SmallVector<Register, 4> DstRegs, DstLeftoverRegs;
3643 SmallVector<Register, 4> Src1Regs, Src1LeftoverRegs;
3644 SmallVector<Register, 4> Src2Regs, Src2LeftoverRegs;
3693 Register SrcReg = MI.getOperand(1).getReg();
3719 Register Op = SrcReg;
3743 Register SrcReg = MI.getOperand(1).getReg();
3791 Register Dst = MI.getOperand(0).getReg();
3792 Register Src = MI.getOperand(1).getReg();
3847 Register Dst = MI.getOperand(0).getReg();
3848 Register Src = MI.getOperand(1).getReg();
3868 Register Dst = MI.getOperand(0).getReg();
3869 Register Src = MI.getOperand(1).getReg();
3886 Register L = Src;
3906 Register Dst = MI.getOperand(0).getReg();
3907 Register Src = MI.getOperand(1).getReg();
3963 Register Dst = MI.getOperand(0).getReg();
3964 Register Src0 = MI.getOperand(1).getReg();
3965 Register Src1 = MI.getOperand(2).getReg();
3979 Register Dst = MI.getOperand(0).getReg();
3980 Register Src0 = MI.getOperand(1).getReg();
3981 Register Src1 = MI.getOperand(2).getReg();
4030 Register Dst = MI.getOperand(0).getReg();
4031 Register Src0 = MI.getOperand(1).getReg();
4032 Register Src1 = MI.getOperand(2).getReg();
4058 Register DstReg = MI.getOperand(0).getReg();
4072 const Register SrcReg = MI.getOperand(NumDst).getReg();
4075 Register Dst0Reg = MI.getOperand(0).getReg();
4083 Register Cast = MIRBuilder.buildBitcast(IntTy, SrcReg).getReg(0);
4104 Register DstReg = MI.getOperand(0).getReg();
4105 Register Src0Reg = MI.getOperand(1).getReg();
4106 Register Src1Reg = MI.getOperand(2).getReg();
4122 Register Val;
4132 Register Undef;
4133 SmallVector<Register, 32> BuildVec;
4148 Register SrcVec = Idx < NumElts ? Src0Reg : Src1Reg;
4163 Register Dst = MI.getOperand(0).getReg();
4164 Register AllocSize = MI.getOperand(1).getReg();
4173 Register SPReg = TLI.getStackPointerRegisterToSaveRestore();
4198 Register Dst = MI.getOperand(0).getReg();
4199 Register Src = MI.getOperand(1).getReg();
4230 Register Dst = MI.getOperand(0).getReg();
4231 Register Src = MI.getOperand(1).getReg();
4232 Register InsertSrc = MI.getOperand(2).getReg();
4247 Register ExtInsSrc = MIRBuilder.buildZExt(IntDstTy, InsertSrc).getReg(0);
4270 Register Dst0 = MI.getOperand(0).getReg();
4271 Register Dst1 = MI.getOperand(1).getReg();
4272 Register LHS = MI.getOperand(2).getReg();
4273 Register RHS = MI.getOperand(3).getReg();
lib/CodeGen/GlobalISel/Localizer.cpp 82 Register Reg = MI.getOperand(0).getReg();
124 Register Reg = MI.getOperand(0).getReg();
154 Register NewReg = MRI->createGenericVirtualRegister(MRI->getType(Reg));
180 Register Reg = MI->getOperand(0).getReg();
lib/CodeGen/GlobalISel/MachineIRBuilder.cpp 90 MachineIRBuilder::buildDirectDbgValue(Register Reg, const MDNode *Variable,
103 MachineIRBuilder::buildIndirectDbgValue(Register Reg, const MDNode *Variable,
233 MachineIRBuilder::materializeGEP(Register &Res, Register Op0,
233 MachineIRBuilder::materializeGEP(Register &Res, Register Op0,
265 MachineInstrBuilder MachineIRBuilder::buildBrIndirect(Register Tgt) {
270 MachineInstrBuilder MachineIRBuilder::buildBrJT(Register TablePtr,
272 Register IndexReg) {
361 MachineInstrBuilder MachineIRBuilder::buildBrCond(Register Tst,
535 void MachineIRBuilder::buildSequence(Register Res, ArrayRef<Register> Ops,
535 void MachineIRBuilder::buildSequence(Register Res, ArrayRef<Register> Ops,
544 for (auto Op : Ops)
564 Register ResIn = getMRI()->createGenericVirtualRegister(ResTy);
568 Register ResOut = i + 1 == Ops.size()
581 ArrayRef<Register> Ops) {
603 SmallVector<Register, 8> TmpVec;
609 MachineInstrBuilder MachineIRBuilder::buildUnmerge(ArrayRef<Register> Res,
620 ArrayRef<Register> Ops) {
636 ArrayRef<Register> Ops) {
645 MachineIRBuilder::buildConcatVectors(const DstOp &Res, ArrayRef<Register> Ops) {
653 MachineInstrBuilder MachineIRBuilder::buildInsert(Register Res, Register Src,
653 MachineInstrBuilder MachineIRBuilder::buildInsert(Register Res, Register Src,
654 Register Op, unsigned Index) {
672 ArrayRef<Register> ResultRegs,
744 Register OldValRes, Register SuccessRes, Register Addr, Register CmpVal,
744 Register OldValRes, Register SuccessRes, Register Addr, Register CmpVal,
744 Register OldValRes, Register SuccessRes, Register Addr, Register CmpVal,
744 Register OldValRes, Register SuccessRes, Register Addr, Register CmpVal,
745 Register NewVal, MachineMemOperand &MMO) {
771 MachineIRBuilder::buildAtomicCmpXchg(Register OldValRes, Register Addr,
771 MachineIRBuilder::buildAtomicCmpXchg(Register OldValRes, Register Addr,
772 Register CmpVal, Register NewVal,
772 Register CmpVal, Register NewVal,
820 MachineIRBuilder::buildAtomicRMWXchg(Register OldValRes, Register Addr,
820 MachineIRBuilder::buildAtomicRMWXchg(Register OldValRes, Register Addr,
821 Register Val, MachineMemOperand &MMO) {
826 MachineIRBuilder::buildAtomicRMWAdd(Register OldValRes, Register Addr,
826 MachineIRBuilder::buildAtomicRMWAdd(Register OldValRes, Register Addr,
827 Register Val, MachineMemOperand &MMO) {
832 MachineIRBuilder::buildAtomicRMWSub(Register OldValRes, Register Addr,
832 MachineIRBuilder::buildAtomicRMWSub(Register OldValRes, Register Addr,
833 Register Val, MachineMemOperand &MMO) {
838 MachineIRBuilder::buildAtomicRMWAnd(Register OldValRes, Register Addr,
838 MachineIRBuilder::buildAtomicRMWAnd(Register OldValRes, Register Addr,
839 Register Val, MachineMemOperand &MMO) {
844 MachineIRBuilder::buildAtomicRMWNand(Register OldValRes, Register Addr,
844 MachineIRBuilder::buildAtomicRMWNand(Register OldValRes, Register Addr,
845 Register Val, MachineMemOperand &MMO) {
849 MachineInstrBuilder MachineIRBuilder::buildAtomicRMWOr(Register OldValRes,
850 Register Addr,
851 Register Val,
857 MachineIRBuilder::buildAtomicRMWXor(Register OldValRes, Register Addr,
857 MachineIRBuilder::buildAtomicRMWXor(Register OldValRes, Register Addr,
858 Register Val, MachineMemOperand &MMO) {
863 MachineIRBuilder::buildAtomicRMWMax(Register OldValRes, Register Addr,
863 MachineIRBuilder::buildAtomicRMWMax(Register OldValRes, Register Addr,
864 Register Val, MachineMemOperand &MMO) {
869 MachineIRBuilder::buildAtomicRMWMin(Register OldValRes, Register Addr,
869 MachineIRBuilder::buildAtomicRMWMin(Register OldValRes, Register Addr,
870 Register Val, MachineMemOperand &MMO) {
875 MachineIRBuilder::buildAtomicRMWUmax(Register OldValRes, Register Addr,
875 MachineIRBuilder::buildAtomicRMWUmax(Register OldValRes, Register Addr,
876 Register Val, MachineMemOperand &MMO) {
881 MachineIRBuilder::buildAtomicRMWUmin(Register OldValRes, Register Addr,
881 MachineIRBuilder::buildAtomicRMWUmin(Register OldValRes, Register Addr,
882 Register Val, MachineMemOperand &MMO) {
910 MachineIRBuilder::buildBlockAddress(Register Res, const BlockAddress *BA) {
lib/CodeGen/GlobalISel/RegBankSelect.cpp 111 Register Reg, const RegisterBankInfo::ValueMapping &ValMapping,
136 const iterator_range<SmallVectorImpl<Register>::const_iterator> &NewVRegs) {
148 Register Src = MO.getReg();
149 Register Dst = *NewVRegs.begin();
196 for (Register SrcReg : NewVRegs)
203 for (Register DefReg : NewVRegs)
400 Register Reg = MO.getReg();
401 if (Register::isPhysicalRegister(Reg)) {
471 Register Reg = MO.getReg();
597 Register Reg = MO.getReg();
761 Register Reg = MO.getReg();
lib/CodeGen/GlobalISel/RegisterBankInfo.cpp 83 RegisterBankInfo::getRegBank(Register Reg, const MachineRegisterInfo &MRI,
85 if (Register::isPhysicalRegister(Reg))
98 RegisterBankInfo::getMinimalPhysRegClass(Register Reg,
127 Register Reg, const TargetRegisterClass &RC, MachineRegisterInfo &MRI) {
182 Register Reg = MO.getReg();
231 Register Reg = MO.getReg();
456 iterator_range<SmallVectorImpl<Register>::const_iterator> NewRegs =
462 Register OrigReg = MO.getReg();
463 Register NewReg = *NewRegs.begin();
488 unsigned RegisterBankInfo::getSizeInBits(Register Reg,
491 if (Register::isPhysicalRegister(Reg)) {
610 Register Reg = MO.getReg();
655 iterator_range<SmallVectorImpl<Register>::iterator>
671 SmallVectorImpl<Register>::iterator End =
677 SmallVectorImpl<Register>::const_iterator
682 SmallVectorImpl<Register>::iterator
694 iterator_range<SmallVectorImpl<Register>::iterator> NewVRegsForOpIdx =
698 for (Register &NewVReg : NewVRegsForOpIdx) {
714 Register NewVReg) {
726 iterator_range<SmallVectorImpl<Register>::const_iterator>
738 SmallVectorImpl<Register>::const_iterator End =
740 iterator_range<SmallVectorImpl<Register>::const_iterator> Res =
743 for (Register VReg : Res)
792 for (Register VReg : getVRegs(Idx)) {
lib/CodeGen/GlobalISel/Utils.cpp 46 Register Reg = RegMO.getReg();
75 Register Reg = RegMO.getReg();
131 Register Reg = MO.getReg();
133 if (Register::isPhysicalRegister(Reg))
171 Register Reg = MO.getReg();
172 if (Register::isPhysicalRegister(Reg) || !MRI.use_nodbg_empty(Reg))
257 if (Register::isPhysicalRegister(VReg))
303 llvm::MachineInstr *llvm::getDefIgnoringCopies(Register Reg,
310 Register SrcReg = DefMI->getOperand(1).getReg();
319 llvm::MachineInstr *llvm::getOpcodeDef(unsigned Opcode, Register Reg,
389 bool llvm::isKnownNeverNaN(Register Val, const MachineRegisterInfo &MRI,
lib/CodeGen/IfConversion.cpp 1948 Register Reg = MO.getReg();
2116 Register Reg = MO.getReg();
lib/CodeGen/ImplicitNullChecks.cpp 281 Register RegA = MOA.getReg();
286 Register RegB = MOB.getReg();
520 const Register PointerReg = MBP.LHS.getReg();
692 Register Reg = MO.getReg();
lib/CodeGen/InlineSpiller.cpp 349 return Register::isVirtualRegister(Reg) && VRM.getOriginal(Reg) == Original;
379 Register SrcReg = CopyMI.getOperand(1).getReg();
847 Register Reg = MO->getReg();
848 if (!Reg || Register::isVirtualRegister(Reg) || MRI.isReserved(Reg)) {
1460 unsigned Reg = Register::index2VirtReg(i);
lib/CodeGen/LiveDebugValues.cpp 84 static Register isDbgValueDescribedByReg(const MachineInstr &MI) {
816 Register::isPhysicalRegister(MO.getReg()) &&
1013 Register SrcReg = SrcRegOp->getReg();
1014 Register DestReg = DestRegOp->getReg();
1299 Register FP = TRI->getFrameRegister(MF);
lib/CodeGen/LiveDebugVariables.cpp 569 Register::isVirtualRegister(locations[i].getReg()))
617 Register::isVirtualRegister(MI.getOperand(0).getReg())) {
618 const Register Reg = MI.getOperand(0).getReg();
768 if (!Register::isVirtualRegister(LI->reg))
778 Register DstReg = MI->getOperand(0).getReg();
784 if (!Register::isVirtualRegister(DstReg))
855 if (Register::isVirtualRegister(LocMO.getReg())) {
1172 Register::isVirtualRegister(Loc.getReg())) {
1173 Register VirtReg = Loc.getReg();
1175 Register::isPhysicalRegister(VRM.getPhys(VirtReg))) {
1269 Register Reg = LocMO.getReg();
lib/CodeGen/LiveInterval.cpp 889 if (!Register::isVirtualRegister(Reg) || !Reg)
lib/CodeGen/LiveIntervals.cpp 111 delete VirtRegIntervals[Register::index2VirtReg(i)];
164 unsigned Reg = Register::index2VirtReg(i);
189 float Weight = Register::isPhysicalRegister(reg) ? huge_valf : 0.0F;
204 unsigned Reg = Register::index2VirtReg(i);
691 unsigned Reg = Register::index2VirtReg(i);
989 Register Reg = MO.getReg();
992 if (Register::isVirtualRegister(Reg)) {
1402 if (Register::isVirtualRegister(Reg)) {
1447 Register::isPhysicalRegister(MO->getReg()) &&
1603 if (MOI->isReg() && Register::isVirtualRegister(MOI->getReg()) &&
1611 if (!Register::isVirtualRegister(Reg))
1662 Register NewVReg = MRI->createVirtualRegister(RegClass);
lib/CodeGen/LivePhysRegs.cpp 49 Register Reg = O->getReg();
50 if (!Register::isPhysicalRegister(Reg))
63 Register Reg = O->getReg();
64 if (!Register::isPhysicalRegister(Reg))
89 Register Reg = O->getReg();
90 if (!Register::isPhysicalRegister(Reg))
295 Register Reg = MO->getReg();
312 Register Reg = MO->getReg();
lib/CodeGen/LiveRangeCalc.cpp 375 if (Register::isPhysicalRegister(PhysReg) && !MBB->isLiveIn(PhysReg)) {
lib/CodeGen/LiveRangeEdit.cpp 35 Register VReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg));
55 Register VReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg));
117 if (Register::isPhysicalRegister(MO.getReg())) {
311 Register Reg = MOI->getReg();
312 if (!Register::isVirtualRegister(Reg)) {
352 if (MO.isReg() && Register::isPhysicalRegister(MO.getReg()))
lib/CodeGen/LiveRangeShrink.cpp 175 Register Reg = MO.getReg();
178 if (!Register::isVirtualRegister(Reg)) {
lib/CodeGen/LiveRegMatrix.cpp 121 Register PhysReg = VRM->getPhys(VirtReg.reg);
lib/CodeGen/LiveRegUnits.cpp 50 Register Reg = O->getReg();
51 if (!Register::isPhysicalRegister(Reg))
62 Register Reg = O->getReg();
63 if (!Register::isPhysicalRegister(Reg))
73 Register Reg = O->getReg();
74 if (!Register::isPhysicalRegister(Reg))
lib/CodeGen/LiveStacks.cpp 64 std::forward_as_tuple(Register::index2StackSlot(Slot), 0.0F))
lib/CodeGen/LiveVariables.cpp 218 Register DefReg = MO.getReg();
523 Register MOReg = MO.getReg();
525 if (!(Register::isPhysicalRegister(MOReg) && MRI->isReserved(MOReg)))
533 if (Register::isPhysicalRegister(MOReg) && !MRI->isReserved(MOReg))
543 if (Register::isVirtualRegister(MOReg))
556 if (Register::isVirtualRegister(MOReg))
656 const unsigned Reg = Register::index2VirtReg(i);
694 Register Reg = MO.getReg();
695 if (Register::isVirtualRegister(Reg)) {
785 if (I->isReg() && Register::isVirtualRegister(I->getReg())) {
796 unsigned Reg = Register::index2VirtReg(i);
lib/CodeGen/MIRCanonicalizerPass.cpp 173 if (Register::isVirtualRegister(MO.getReg()))
190 if (!MO.isReg() || !Register::isVirtualRegister(MO.getReg()))
203 if (!Register::isVirtualRegister(II->getOperand(i).getReg()))
323 const Register Dst = MI->getOperand(0).getReg();
324 const Register Src = MI->getOperand(1).getReg();
326 if (!Register::isVirtualRegister(Dst))
328 if (!Register::isVirtualRegister(Src))
429 Register vRegToRename = MI.getOperand(0).getReg();
lib/CodeGen/MIRParser/MIParser.cpp 1412 if (!Register::isVirtualRegister(Reg))
1416 if (!Register::isVirtualRegister(Reg))
1446 if (!Register::isVirtualRegister(Reg))
1461 } else if (Register::isVirtualRegister(Reg)) {
lib/CodeGen/MIRParser/MIRParser.cpp 309 unsigned Reg = Register::index2VirtReg(I);
lib/CodeGen/MIRPrinter.cpp 293 unsigned Reg = Register::index2VirtReg(I);
lib/CodeGen/MIRVRegNamerUtils.cpp 26 Register Reg;
29 TypedVReg(Register Reg) : Type(RSE_Reg), Reg(Reg) {}
39 Register getReg() const {
61 const Register Dst = MI->getOperand(0).getReg();
62 DoesMISideEffect |= !Register::isVirtualRegister(Dst);
101 Register Reg = TReg.getReg();
103 if (Register::isVirtualRegister(Reg)) {
158 const std::vector<Register> &renamedInOtherBB,
185 } else if (!Register::isVirtualRegister(vreg.getReg())) {
194 auto Reg = vreg.getReg();
225 bool doVRegRenaming(std::vector<Register> &renamedInOtherBB,
254 std::vector<Register> &renamedInOtherBB,
279 if (!(MO.isReg() && Register::isVirtualRegister(MO.getReg())))
lib/CodeGen/MIRVRegNamerUtils.h 54 std::vector<Register> RenamedInOtherBB;
lib/CodeGen/MachineBasicBlock.cpp 509 Register VirtReg = I->getOperand(0).getReg();
516 Register VirtReg = MRI.createVirtualRegister(RC);
911 Register Reg = OI->getReg();
912 if (Register::isPhysicalRegister(Reg) ||
932 Register Reg = OI->getReg();
999 if (Register::isVirtualRegister(Reg))
1032 Register Reg = MO.getReg();
1048 unsigned Reg = Register::index2VirtReg(i);
lib/CodeGen/MachineCSE.cpp 170 Register Reg = MO.getReg();
171 if (!Register::isVirtualRegister(Reg))
177 Register SrcReg = DefMI->getOperand(1).getReg();
178 if (!Register::isVirtualRegister(SrcReg))
285 Register Reg = MO.getReg();
288 if (Register::isVirtualRegister(Reg))
304 Register Reg = MO.getReg();
307 if (Register::isVirtualRegister(Reg))
381 Register MOReg = MO.getReg();
382 if (Register::isVirtualRegister(MOReg))
438 if (Register::isVirtualRegister(CSReg) && Register::isVirtualRegister(Reg)) {
438 if (Register::isVirtualRegister(CSReg) && Register::isVirtualRegister(Reg)) {
466 if (MO.isReg() && MO.isUse() && Register::isVirtualRegister(MO.getReg())) {
598 Register OldReg = MO.getReg();
599 Register NewReg = CSMI->getOperand(i).getReg();
781 if (!Register::isVirtualRegister(def.getReg()))
785 if (use.isReg() && !Register::isVirtualRegister(use.getReg()))
827 Register VReg = MI->getOperand(0).getReg();
828 Register NewReg = MRI->cloneVirtualRegister(VReg);
lib/CodeGen/MachineCombiner.cpp 140 if (MO.isReg() && Register::isVirtualRegister(MO.getReg()))
171 if (!(MO.isReg() && Register::isVirtualRegister(MO.getReg())))
226 if (!(MO.isReg() && Register::isVirtualRegister(MO.getReg())))
lib/CodeGen/MachineCopyPropagation.cpp 122 Register Def = MI->getOperand(0).getReg();
123 Register Src = MI->getOperand(1).getReg();
166 Register AvailSrc = AvailCopy->getOperand(1).getReg();
167 Register AvailDef = AvailCopy->getOperand(0).getReg();
265 Register PreviousSrc = PreviousCopy.getOperand(1).getReg();
266 Register PreviousDef = PreviousCopy.getOperand(0).getReg();
303 Register CopyDef = Copy.getOperand(0).getReg();
322 Register CopySrcReg = Copy.getOperand(1).getReg();
413 Register CopyDstReg = Copy->getOperand(0).getReg();
415 Register CopySrcReg = CopySrc.getReg();
471 Register Def = MI->getOperand(0).getReg();
472 Register Src = MI->getOperand(1).getReg();
507 Register Reg = MO.getReg();
530 Register Reg = MO.getReg();
544 Register Reg = MO.getReg();
563 Register Reg = MO.getReg();
586 Register Reg = MaybeDead->getOperand(0).getReg();
lib/CodeGen/MachineInstr.cpp 630 if (!Register::isVirtualRegister(MO.getReg()) ||
631 !Register::isVirtualRegister(OMO.getReg()))
686 Register Reg = MO.getReg();
871 Register Reg, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII,
888 unsigned OpIdx, Register Reg, const TargetRegisterClass *CurRC,
931 bool MachineInstr::hasRegisterImplicitUseOperand(Register Reg) const {
944 Register Reg, bool isKill, const TargetRegisterInfo *TRI) const {
949 Register MOReg = MO.getReg();
963 MachineInstr::readsWritesVirtualRegister(Register Reg,
992 MachineInstr::findRegisterDefOperandIdx(Register Reg, bool isDead, bool Overlap,
994 bool isPhys = Register::isPhysicalRegister(Reg);
1003 Register MOReg = MO.getReg();
1005 if (!Found && TRI && isPhys && Register::isPhysicalRegister(MOReg)) {
1139 void MachineInstr::substituteRegister(Register FromReg, Register ToReg,
1139 void MachineInstr::substituteRegister(Register FromReg, Register ToReg,
1142 if (Register::isPhysicalRegister(ToReg)) {
1361 Register Reg = getOperand(1).getReg();
1784 bool MachineInstr::addRegisterKilled(Register IncomingReg,
1787 bool isPhysReg = Register::isPhysicalRegister(IncomingReg);
1803 Register Reg = MO.getReg();
1818 } else if (hasAliases && MO.isKill() && Register::isPhysicalRegister(Reg)) {
1850 void MachineInstr::clearRegisterKills(Register Reg,
1852 if (!Register::isPhysicalRegister(Reg))
1857 Register OpReg = MO.getReg();
1863 bool MachineInstr::addRegisterDead(Register Reg,
1866 bool isPhysReg = Register::isPhysicalRegister(Reg);
1875 Register MOReg = MO.getReg();
1883 Register::isPhysicalRegister(MOReg)) {
1916 void MachineInstr::clearRegisterDeads(Register Reg) {
1924 void MachineInstr::setRegisterDefReadUndef(Register Reg, bool IsUndef) {
1932 void MachineInstr::addRegisterDefined(Register Reg,
1934 if (Register::isPhysicalRegister(Reg)) {
1950 void MachineInstr::setPhysRegsDeadExcept(ArrayRef<Register> UsedRegs,
1959 Register Reg = MO.getReg();
1971 for (ArrayRef<Register>::iterator I = UsedRegs.begin(), E = UsedRegs.end();
1983 if (MO.isReg() && MO.isDef() && Register::isVirtualRegister(MO.getReg()))
2015 Register Reg, const MDNode *Variable,
2121 void MachineInstr::changeDebugValuesDefReg(Register Reg) {
lib/CodeGen/MachineInstrBundle.cpp 157 Register Reg = MO.getReg();
180 Register Reg = MO.getReg();
197 if (!MO.isDead() && Register::isPhysicalRegister(Reg)) {
332 Register MOReg = MO.getReg();
333 if (!MOReg || !Register::isPhysicalRegister(MOReg))
lib/CodeGen/MachineLICM.cpp 426 Register Reg = MO.getReg();
528 Register Reg = MO.getReg();
556 Register Reg = MO.getReg();
854 Register Reg = MO.getReg();
855 if (!Register::isVirtualRegister(Reg))
924 Register Reg = MO.getReg();
927 if (Register::isVirtualRegister(Reg))
929 if (Register::isVirtualRegister(Reg))
957 Register CopySrcReg = MI.getOperand(1).getReg();
958 if (Register::isVirtualRegister(CopySrcReg))
964 Register CopyDstReg = MI.getOperand(0).getReg();
1012 Register Reg = MO.getReg();
1016 if (Register::isPhysicalRegister(Reg)) {
1063 Register Reg = MO.getReg();
1064 if (!Register::isVirtualRegister(Reg))
1106 Register MOReg = MO.getReg();
1134 Register Reg = DefMO.getReg();
1135 if (Register::isPhysicalRegister(Reg))
1227 Register Reg = MO.getReg();
1228 if (!Register::isVirtualRegister(Reg))
1306 Register Reg = MRI->createVirtualRegister(RC);
1385 !Register::isPhysicalRegister(MO.getReg()))
1392 Register Reg = MI->getOperand(Idx).getReg();
1393 Register DupReg = Dup->getOperand(Idx).getReg();
1405 Register Reg = MI->getOperand(Idx).getReg();
1406 Register DupReg = Dup->getOperand(Idx).getReg();
lib/CodeGen/MachineLoopUtils.cpp 45 DenseMap<unsigned, Register> Remaps;
51 Register OrigR = MO.getReg();
54 Register &R = Remaps[OrigR];
89 Register R = MI.getOperand(LoopRegIdx).getReg();
98 Register LoopReg = OrigPhi.getOperand(LoopRegIdx).getReg();
lib/CodeGen/MachineOperand.cpp 52 void MachineOperand::setReg(Register Reg) {
74 void MachineOperand::substVirtReg(Register Reg, unsigned SubIdx,
233 void MachineOperand::ChangeToRegister(Register Reg, bool isDef, bool isImp,
751 Register Reg = getReg();
767 if (Register::isPhysicalRegister(getReg()) && isRenamable())
773 if (Register::isVirtualRegister(Reg)) {
788 if (Register::isVirtualRegister(Reg)) {
lib/CodeGen/MachinePipeliner.cpp 364 Register NewReg = MRI.createVirtualRegister(RC);
772 Register Reg = MOI->getReg();
851 Register OrigBase = I.getInstr()->getOperand(BasePos).getReg();
1556 Register Reg = MO.getReg();
1557 if (Register::isVirtualRegister(Reg))
1567 Register Reg = MO.getReg();
1568 if (Register::isVirtualRegister(Reg)) {
2066 Register BaseReg = BaseOp->getReg();
2104 Register BaseReg = MI->getOperand(BasePosLd).getReg();
2159 Register BaseReg = MI->getOperand(BasePos).getReg();
2474 if (!MO.isReg() || !Register::isVirtualRegister(MO.getReg()))
2477 Register Reg = MO.getReg();
2651 if (Register::isPhysicalRegister(SI.getReg()))
lib/CodeGen/MachineRegisterInfo.cpp 147 unsigned Reg = Register::index2VirtReg(getNumVirtRegs());
157 Register
172 Register MachineRegisterInfo::cloneVirtualRegister(Register VReg,
172 Register MachineRegisterInfo::cloneVirtualRegister(Register VReg,
187 Register
205 unsigned Reg = Register::index2VirtReg(i);
258 verifyUseList(Register::index2VirtReg(i));
389 if (Register::isPhysicalRegister(ToReg)) {
lib/CodeGen/MachineSSAUpdater.cpp 98 Register SrcReg = I->getOperand(i).getReg();
121 Register NewVR = MRI->createVirtualRegister(RC);
lib/CodeGen/MachineScheduler.cpp 938 Register Reg = MO.getReg();
939 if (!Register::isVirtualRegister(Reg))
1100 if (!Register::isVirtualRegister(Reg))
1324 if (!Register::isVirtualRegister(Reg))
1692 Register SrcReg = SrcOp.getReg();
1693 if (!Register::isVirtualRegister(SrcReg) || !SrcOp.readsReg())
1697 Register DstReg = DstOp.getReg();
1698 if (!Register::isVirtualRegister(DstReg) || DstOp.isDead())
2919 if (Register::isPhysicalRegister(MI->getOperand(ScheduledOper).getReg()))
2924 if (Register::isPhysicalRegister(MI->getOperand(UnscheduledOper).getReg()))
2934 if (Op.isReg() && !Register::isPhysicalRegister(Op.getReg())) {
3263 !Register::isPhysicalRegister(Dep.getReg()))
lib/CodeGen/MachineSink.cpp 206 Register SrcReg = MI.getOperand(1).getReg();
207 Register DstReg = MI.getOperand(0).getReg();
208 if (!Register::isVirtualRegister(SrcReg) ||
209 !Register::isVirtualRegister(DstReg) || !MRI->hasOneNonDBGUse(SrcReg))
442 Register Reg = MO.getReg();
448 if (Register::isPhysicalRegister(Reg))
641 Register Reg = MO.getReg();
644 if (Register::isPhysicalRegister(Reg)) {
881 Register Reg = MO.getReg();
882 if (Reg == 0 || !Register::isPhysicalRegister(Reg))
1149 Register SrcReg = MO.getReg();
1172 Register Reg = MI->getOperand(U).getReg();
1188 Register Reg = MO.getReg();
1257 if (MO.isReg() && Register::isPhysicalRegister(MO.getReg())) {
lib/CodeGen/MachineTraceMetrics.cpp 663 Register Reg = MO.getReg();
666 if (Register::isPhysicalRegister(Reg)) {
690 Register Reg = UseMI.getOperand(i).getReg();
711 Register Reg = MO.getReg();
712 if (!Register::isPhysicalRegister(Reg))
768 if (!Register::isVirtualRegister(LIR.Reg))
905 Register Reg = MO.getReg();
906 if (!Register::isPhysicalRegister(Reg))
933 Register Reg = MI.getOperand(ReadOps[i]).getReg();
1029 if (Register::isVirtualRegister(LI.Reg)) {
lib/CodeGen/MachineVerifier.cpp 125 if (Register::isPhysicalRegister(Reg))
162 if (!Register::isVirtualRegister(Reg))
181 if (!Register::isVirtualRegister(Reg))
555 if (Register::isVirtualRegister(VRegOrUnit)) {
800 if (!Register::isPhysicalRegister(LI.PhysReg)) {
960 if (MO->isReg() && Register::isPhysicalRegister(MO->getReg()))
1629 else if (Register::isPhysicalRegister(MO->getReg())) {
1633 else if (Register::isPhysicalRegister(MOTied.getReg()) &&
1647 const Register Reg = MO->getReg();
1685 if (Register::isPhysicalRegister(Reg)) {
1949 if (LiveVars && Register::isVirtualRegister(Reg) && MO->isKill()) {
1959 if (Register::isPhysicalRegister(Reg) && !isReserved(Reg)) {
1968 if (Register::isVirtualRegister(Reg)) {
2003 if (Register::isPhysicalRegister(Reg)) {
2025 if (!Register::isPhysicalRegister(MOP.getReg()))
2063 if (MRI->isSSA() && Register::isVirtualRegister(Reg) &&
2072 if (Register::isVirtualRegister(Reg)) {
2110 if (Register::isPhysicalRegister(*I) &&
2222 Register DefReg = MODef.getReg();
2223 if (!Register::isVirtualRegister(DefReg))
2315 unsigned Reg = Register::index2VirtReg(i);
2341 unsigned Reg = Register::index2VirtReg(i);
2418 if (Register::isVirtualRegister(Reg)) {
2422 if (!Register::isPhysicalRegister(MOI->getReg()) ||
2505 if (!Register::isVirtualRegister(Reg) && VNI->isPHIDef() &&
2549 if (Register::isVirtualRegister(Reg)) {
2622 if (!Register::isVirtualRegister(Reg) && MFI->isEHPad()) {
lib/CodeGen/ModuloSchedule.cpp 81 Register Reg = Op.getReg();
385 Register Def = BBI->getOperand(0).getReg();
626 !Register::isVirtualRegister(MO.getReg()))
631 Register Def = MO.getReg();
664 Register NewReg = MRI.createVirtualRegister(RC);
729 Register reg = MOI->getReg();
731 if (Register::isPhysicalRegister(reg)) {
767 Register reg = MI->getOperand(0).getReg();
789 Register Def = PHI.getOperand(0).getReg();
921 Register BaseReg = BaseOp->getReg();
1027 if (!MO.isReg() || !Register::isVirtualRegister(MO.getReg()))
1029 Register reg = MO.getReg();
1033 Register NewReg = MRI.createVirtualRegister(RC);
1114 Register PhiDef = PHI.getOperand(0).getReg();
1254 DenseMap<const TargetRegisterClass *, Register> Undefs;
1257 DenseMap<std::pair<unsigned, unsigned>, Register> Phis;
1259 DenseMap<Register, Register> UndefPhis;
1259 DenseMap<Register, Register> UndefPhis;
1263 Register remapUse(Register Reg, MachineInstr &MI);
1263 Register remapUse(Register Reg, MachineInstr &MI);
1267 Register phi(Register LoopReg, Optional<Register> InitReg = {},
1267 Register phi(Register LoopReg, Optional<Register> InitReg = {},
1267 Register phi(Register LoopReg, Optional<Register> InitReg = {},
1270 Register undef(const TargetRegisterClass *RC);
1322 Register Reg = remapUse(MO.getReg(), MI);
1334 Register R = MI->getOperand(0).getReg();
1350 Register KernelRewriter::remapUse(Register Reg, MachineInstr &MI) {
1350 Register KernelRewriter::remapUse(Register Reg, MachineInstr &MI) {
1375 SmallVector<Optional<Register>, 4> Defaults;
1376 Register LoopReg = Reg;
1386 Optional<Register> IllegalPhiDefault;
1436 Register R = MRI.createVirtualRegister(RC);
1448 Register KernelRewriter::phi(Register LoopReg, Optional<Register> InitReg,
1448 Register KernelRewriter::phi(Register LoopReg, Optional<Register> InitReg,
1448 Register KernelRewriter::phi(Register LoopReg, Optional<Register> InitReg,
1466 Register R = I->second;
1483 Register R = MRI.createVirtualRegister(RC);
1498 Register KernelRewriter::undef(const TargetRegisterClass *RC) {
1499 Register &R = Undefs[RC];
1519 SmallVector<Register, 4> PhiDefaults;
1543 Register Default = getInitPhiReg(*MI, BB);
1639 Register Reg = MI.getOperand(1).getReg();
1680 Register OldR = MI.getOperand(3).getReg();
1681 Register R = MRI.createVirtualRegister(RC);
1711 Register
1712 PeelingModuloScheduleExpander::getEquivalentRegisterIn(Register Reg,
1723 Register PhiR = MI->getOperand(0).getReg();
1724 Register R = MI->getOperand(3).getReg();
1743 SmallVector<std::pair<MachineInstr *, Register>, 4> Subs;
1748 Register Reg = getEquivalentRegisterIn(UseMI.getOperand(0).getReg(),
lib/CodeGen/OptimizePHIs.cpp 100 Register DstReg = MI->getOperand(0).getReg();
112 Register SrcReg = MI->getOperand(i).getReg();
120 Register::isVirtualRegister(SrcMI->getOperand(1).getReg())) {
144 Register DstReg = MI->getOperand(0).getReg();
179 Register OldReg = MI->getOperand(0).getReg();
lib/CodeGen/PHIElimination.cpp 173 Register DefReg = DefMI->getOperand(0).getReg();
250 Register DestReg = MPhi->getOperand(0).getReg();
376 Register SrcReg = MPhi->getOperand(i * 2 + 1).getReg();
575 Register Reg = BBI->getOperand(i).getReg();
lib/CodeGen/PeepholeOptimizer.cpp 421 if (!Register::isPhysicalRegister(Reg)) {
463 if (Register::isPhysicalRegister(DstReg) ||
464 Register::isPhysicalRegister(SrcReg))
584 Register NewVR = MRI->createVirtualRegister(RC);
612 Register::isPhysicalRegister(SrcReg) ||
613 (SrcReg2 != 0 && Register::isPhysicalRegister(SrcReg2)))
666 if (Register::isPhysicalRegister(Reg))
678 if (Register::isPhysicalRegister(CurSrcPair.Reg))
726 if (Register::isPhysicalRegister(CurSrcPair.Reg))
764 Register NewVR = MRI.createVirtualRegister(NewRC);
1173 if (Register::isPhysicalRegister(MODef.getReg()))
1232 Register NewVReg = MRI->createVirtualRegister(DefRC);
1283 if (Register::isPhysicalRegister(Def.Reg))
1318 Register Reg = MI.getOperand(0).getReg();
1322 if (!MI.getOperand(0).getSubReg() && Register::isVirtualRegister(Reg) &&
1338 Register Reg = MI.getOperand(0).getReg();
1339 if (Register::isVirtualRegister(Reg)) {
1361 Register Reg = MO.getReg();
1362 if (!Register::isVirtualRegister(Reg))
1395 Register SrcReg = MI.getOperand(1).getReg();
1396 if (!Register::isVirtualRegister(SrcReg))
1399 Register DstReg = MI.getOperand(0).getReg();
1400 if (!Register::isVirtualRegister(DstReg))
1418 Register PrevDstReg = PrevCopy->getOperand(0).getReg();
1435 return Register::isPhysicalRegister(Reg) && !MRI->isAllocatable(Reg);
1445 Register DstReg = MI.getOperand(0).getReg();
1446 Register SrcReg = MI.getOperand(1).getReg();
1447 if (isNAPhysCopy(SrcReg) && Register::isVirtualRegister(DstReg)) {
1455 if (!(Register::isVirtualRegister(SrcReg) && isNAPhysCopy(DstReg)))
1468 Register PrevDstReg = PrevCopy->second->getOperand(0).getReg();
1490 return Register::isVirtualRegister(MO.getReg());
1663 Register Reg = MO.getReg();
2097 if (!Register::isPhysicalRegister(Reg) && OneRegSrc) {
lib/CodeGen/ProcessImplicitDefs.cpp 76 Register Reg = MI->getOperand(0).getReg();
78 if (Register::isVirtualRegister(Reg)) {
103 Register UserReg = MO.getReg();
104 if (!Register::isPhysicalRegister(UserReg) ||
lib/CodeGen/RegAllocBase.cpp 76 unsigned Reg = Register::index2VirtReg(i);
lib/CodeGen/RegAllocFast.cpp 93 return Register::virtReg2Index(VirtReg);
203 return LiveVirtRegs.find(Register::virtReg2Index(VirtReg));
207 return LiveVirtRegs.find(Register::virtReg2Index(VirtReg));
267 if (MayLiveAcrossBlocks.test(Register::virtReg2Index(VirtReg))) {
275 MayLiveAcrossBlocks.set(Register::virtReg2Index(VirtReg));
285 MayLiveAcrossBlocks.set(Register::virtReg2Index(VirtReg));
296 if (MayLiveAcrossBlocks.test(Register::virtReg2Index(VirtReg)))
304 MayLiveAcrossBlocks.set(Register::virtReg2Index(VirtReg));
458 Register PhysReg = MO.getReg();
628 if (Register::isPhysicalRegister(Reg))
648 Register Reg = MI.getOperand(1).getReg();
673 if (Register::isPhysicalRegister(Hint0) && MRI->isAllocatable(Hint0) &&
694 if (Register::isPhysicalRegister(Hint1) && MRI->isAllocatable(Hint1) &&
753 Register VirtReg = MO.getReg();
785 if ((!Hint || !Register::isPhysicalRegister(Hint)) &&
892 Register Reg = MO.getReg();
893 if (!Register::isVirtualRegister(Reg))
907 Register Reg = MO.getReg();
908 if (!Reg || !Register::isPhysicalRegister(Reg))
922 Register Reg = MO.getReg();
923 if (!Register::isVirtualRegister(Reg))
948 Register Reg = MO.getReg();
949 if (!Register::isVirtualRegister(Reg))
963 Register Reg = MO.getReg();
964 if (!Reg || !Register::isPhysicalRegister(Reg))
1046 Register Reg = MO.getReg();
1048 if (Register::isVirtualRegister(Reg)) {
1097 Register Reg = MO.getReg();
1098 if (!Register::isVirtualRegister(Reg))
1126 Register Reg = MO.getReg();
1127 if (!Register::isVirtualRegister(Reg))
1141 Register Reg = MO.getReg();
1142 if (!Reg || !Register::isPhysicalRegister(Reg))
1169 Register Reg = MO.getReg();
1171 if (!Reg || !Register::isPhysicalRegister(Reg) || !MRI->isAllocatable(Reg))
1182 Register Reg = MO.getReg();
1185 if (Register::isPhysicalRegister(Reg))
1217 Register Reg = MO.getReg();
1218 if (!Register::isVirtualRegister(Reg))
lib/CodeGen/RegAllocGreedy.cpp 987 if (!Register::isVirtualRegister(Intf->reg))
2877 Register OtherReg = Instr.getOperand(0).getReg();
2884 Register OtherPhysReg = Register::isPhysicalRegister(OtherReg)
2884 Register OtherPhysReg = Register::isPhysicalRegister(OtherReg)
2922 Register PhysReg = VRM->getPhys(Reg);
2935 if (Register::isPhysicalRegister(Reg))
2943 Register CurrPhys = VRM->getPhys(Reg);
lib/CodeGen/RegAllocPBQP.cpp 561 unsigned Reg = Register::index2VirtReg(I);
lib/CodeGen/RegisterCoalescer.cpp 409 if (Register::isPhysicalRegister(Src)) {
410 if (Register::isPhysicalRegister(Dst))
419 if (Register::isPhysicalRegister(Dst)) {
486 if (Register::isPhysicalRegister(DstReg))
510 if (Register::isPhysicalRegister(DstReg)) {
511 if (!Register::isPhysicalRegister(Dst))
805 Register NewReg = NewDstMO.getReg();
838 if (Register::isVirtualRegister(IntA.reg) &&
839 Register::isVirtualRegister(IntB.reg) &&
880 if (Register::isPhysicalRegister(NewReg))
1212 if (Register::isPhysicalRegister(SrcReg))
1243 Register CopyDstReg = DstOperand.getReg();
1257 if (Register::isPhysicalRegister(DstReg)) {
1320 if (Register::isPhysicalRegister(MO.getReg()))
1344 if (Register::isVirtualRegister(DstReg)) {
1483 if (Register::isPhysicalRegister(DstReg))
1654 bool DstIsPhys = Register::isPhysicalRegister(DstReg);
2414 Register SrcReg = MI->getOperand(1).getReg();
2415 if (!Register::isVirtualRegister(SrcReg))
3192 Register Reg = MI->getOperand(1).getReg();
3193 if (Register::isVirtualRegister(Reg) && Reg != CP.getSrcReg() &&
3466 Register SrcReg = Copy->getOperand(1).getReg();
3467 Register DstReg = Copy->getOperand(0).getReg();
3468 if (Register::isPhysicalRegister(SrcReg) ||
3469 Register::isPhysicalRegister(DstReg))
3529 if (Register::isPhysicalRegister(DstReg) ||
3533 Register::isPhysicalRegister(SrcReg) || !isTerminalReg(DstReg, Copy, MRI))
3556 if (Register::isPhysicalRegister(OtherReg) ||
lib/CodeGen/RegisterPressure.cpp 238 if (Register::isVirtualRegister(Reg))
364 if (Register::isVirtualRegister(RegUnit)
425 if (Register::isVirtualRegister(RegUnit)) {
502 Register Reg = MO.getReg();
522 if (Register::isVirtualRegister(Reg)) {
533 Register Reg = MO.getReg();
554 if (Register::isVirtualRegister(Reg)) {
609 if (Register::isVirtualRegister(RegUnit) &&
635 if (!Register::isVirtualRegister(RegUnit))
844 if (Register::isVirtualRegister(RegUnit) &&
lib/CodeGen/RegisterScavenging.cpp 52 void RegScavenger::setRegUsed(Register Reg, LaneBitmask LaneMask) {
99 void RegScavenger::addRegUnits(BitVector &BV, Register Reg) {
104 void RegScavenger::removeRegUnits(BitVector &BV, Register Reg) {
136 Register Reg = MO.getReg();
137 if (!Register::isPhysicalRegister(Reg) || isReserved(Reg))
207 Register Reg = MO.getReg();
208 if (!Register::isPhysicalRegister(Reg) || isReserved(Reg))
281 bool RegScavenger::isRegUsed(Register Reg, bool includeReserved) const {
287 Register RegScavenger::FindUnusedReg(const TargetRegisterClass *RC) const {
288 for (Register Reg : *RC) {
300 for (Register Reg : *RC)
306 Register RegScavenger::findSurvivorReg(MachineBasicBlock::iterator StartMI,
332 if (Register::isVirtualRegister(MO.getReg())) {
433 if (MO.isReg() && Register::isVirtualRegister(MO.getReg())) {
460 RegScavenger::spill(Register Reg, const TargetRegisterClass &RC, int SPAdj,
534 Register RegScavenger::scavengeRegister(const TargetRegisterClass *RC,
545 !Register::isVirtualRegister(MO.getReg()))
559 Register SReg = findSurvivorReg(I, Candidates, 25, UseMI);
579 Register RegScavenger::scavengeRegisterBackwards(const TargetRegisterClass &RC,
623 static Register scavengeVReg(MachineRegisterInfo &MRI, RegScavenger &RS,
624 Register VReg, bool ReserveAfter) {
667 Register SReg = RS.scavengeRegisterBackwards(RC, DefMI.getIterator(),
697 Register Reg = MO.getReg();
701 if (!Register::isVirtualRegister(Reg) ||
702 Register::virtReg2Index(Reg) >= InitialNumVirtRegs)
707 Register SReg = scavengeVReg(MRI, RS, Reg, true);
719 Register Reg = MO.getReg();
721 if (!Register::isVirtualRegister(Reg) ||
722 Register::virtReg2Index(Reg) >= InitialNumVirtRegs)
733 Register SReg = scavengeVReg(MRI, RS, Reg, false);
740 if (!MO.isReg() || !Register::isVirtualRegister(MO.getReg()))
lib/CodeGen/RenameIndependentSubregs.cpp 141 Register NewVReg = MRI->createVirtualRegister(RegClass);
393 unsigned Reg = Register::index2VirtReg(I);
lib/CodeGen/ScheduleDAGInstrs.cpp 207 Register Reg = MO.getReg();
208 if (Register::isPhysicalRegister(Reg)) {
210 } else if (Register::isVirtualRegister(Reg) && MO.readsReg()) {
287 Register Reg = MO.getReg();
363 Register Reg = MO.getReg();
391 Register Reg = MO.getReg();
511 Register Reg = MO.getReg();
841 Register Reg = MO.getReg();
842 if (Register::isPhysicalRegister(Reg)) {
844 } else if (Register::isVirtualRegister(Reg)) {
858 Register Reg = MO.getReg();
859 if (Register::isPhysicalRegister(Reg)) {
861 } else if (Register::isVirtualRegister(Reg) && MO.readsReg()) {
1091 Register Reg = MO.getReg();
1122 Register Reg = MO.getReg();
lib/CodeGen/SelectionDAG/FastISel.cpp 177 } else if (Register::isVirtualRegister(MO.getReg())) {
998 for (auto Reg : CLI.OutRegs)
1017 for (auto Reg : CLI.InRegs)
2022 if (Register::isVirtualRegister(Op)) {
lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp 428 if (!Register::isVirtualRegister(DestReg))
449 if (!Register::isVirtualRegister(SrcReg)) {
484 if (!Register::isVirtualRegister(SrcReg)) {
lib/CodeGen/SelectionDAG/InstrEmitter.cpp 74 if (Register::isPhysicalRegister(RN->getReg()))
89 if (Register::isVirtualRegister(SrcReg)) {
117 if (Register::isVirtualRegister(DestReg)) {
232 if (Register::isVirtualRegister(Reg)) {
275 Register VReg = MRI->createVirtualRegister(RC);
322 Register NewVReg = MRI->createVirtualRegister(OpRC);
388 if (OpRC && IIRC && OpRC != IIRC && Register::isVirtualRegister(VReg)) {
389 Register NewVReg = MRI->createVirtualRegister(IIRC);
467 Register NewReg = MRI->createVirtualRegister(RC);
487 if (Register::isVirtualRegister(DestReg)) {
505 if (R && Register::isPhysicalRegister(R->getReg())) {
531 if (Register::isVirtualRegister(Reg))
543 if (Register::isVirtualRegister(Reg))
616 Register NewVReg = MRI->createVirtualRegister(DstRC);
633 Register NewVReg = MRI->createVirtualRegister(TRI->getAllocatableClass(RC));
651 if (!R || !Register::isPhysicalRegister(R->getReg())) {
929 SmallVector<Register, 8> UsedRegs;
934 Register Reg = II.getImplicitDefs()[i - NumDefs];
961 Register Reg = R->getReg();
996 if (Register::isVirtualRegister(DestReg) && SrcVal.isMachineOpcode() &&
1095 getImplRegState(Register::isPhysicalRegister(Reg)));
1104 getImplRegState(Register::isPhysicalRegister(Reg)));
lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp 501 if (Register::isPhysicalRegister(Reg))
lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp 1381 if (Register::isPhysicalRegister(Reg))
2365 if (Register::isVirtualRegister(Reg)) {
2386 if (Register::isVirtualRegister(Reg)) {
2955 Register::isVirtualRegister(
3002 Register::isVirtualRegister(
lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp 118 if (Register::isVirtualRegister(Reg))
659 if (Register::isVirtualRegister(Reg))
811 Register VRBase = MRI.createVirtualRegister(SU->CopyDstRC);
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp 836 if (!Register::isVirtualRegister(Regs[Part + i]) ||
951 else if (!Regs.empty() && Register::isVirtualRegister(Regs.front())) {
4140 Register VReg =
5506 Register Reg;
5512 Register PR = RegInfo.getLiveInPhysReg(Reg);
7191 Register VReg = SwiftError.getOrCreateVRegDefAt(
7977 Register R = AssignedReg ? Register(*I) : RegInfo.createVirtualRegister(RC);
9767 Register SRetReg =
9873 if (Register::isVirtualRegister(Reg))
9885 if (Register::isVirtualRegister(Reg)) {
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp 528 if (Register::isVirtualRegister(From) && Register::isVirtualRegister(To))
528 if (Register::isVirtualRegister(From) && Register::isVirtualRegister(To))
573 Register Reg =
575 if (Register::isPhysicalRegister(Reg))
674 if (Register::isVirtualRegister(From) && Register::isVirtualRegister(To))
674 if (Register::isVirtualRegister(From) && Register::isVirtualRegister(To))
762 if (!Register::isVirtualRegister(DestReg))
1654 if (!OPI2->isReg() || (!Register::isPhysicalRegister(OPI->getReg()) &&
1655 Register::isPhysicalRegister(OPI2->getReg())))
2235 Register Reg =
2249 Register Reg = TLI->getRegisterByName(RegStr->getString().data(),
lib/CodeGen/SelectionDAG/TargetLowering.cpp 82 Register Reg = ArgLoc.getLocReg();
2592 GISelKnownBits &Analysis, Register R, KnownBits &Known,
lib/CodeGen/ShrinkWrap.cpp 281 Register PhysReg = MO.getReg();
lib/CodeGen/SplitKit.cpp 440 Register R = DefOp.getReg();
1376 Register Reg = EP.MO.getReg(), Sub = EP.MO.getSubReg();
lib/CodeGen/StackMaps.cpp 116 Register Reg = (++MOI)->getReg();
125 Register Reg = (++MOI)->getReg();
lib/CodeGen/StackSlotColoring.cpp 224 int FI = Register::stackSlot2Index(li.reg);
271 int FI = Register::stackSlot2Index(li->reg);
333 int SS = Register::stackSlot2Index(li->reg);
346 int SS = Register::stackSlot2Index(li->reg);
lib/CodeGen/SwiftErrorValueTracking.cpp 26 Register SwiftErrorValueTracking::getOrCreateVReg(const MachineBasicBlock *MBB,
37 auto VReg = MF->getRegInfo().createVirtualRegister(RC);
46 const Value *Val, Register VReg) {
50 Register SwiftErrorValueTracking::getOrCreateVRegDefAt(
59 Register VReg = MF->getRegInfo().createVirtualRegister(RC);
65 Register SwiftErrorValueTracking::getOrCreateVRegUseAt(
72 Register VReg = getOrCreateVReg(MBB, Val);
133 Register VReg = MF->getRegInfo().createVirtualRegister(RC);
165 Register UUseVReg = UpwardsUse ? UUseIt->second : Register();
181 SmallVector<std::pair<MachineBasicBlock *, Register>, 4> VRegs;
231 Register DestReg = UUseVReg;
242 Register PHIVReg =
lib/CodeGen/TailDuplicator.cpp 238 Register Dst = Copy->getOperand(0).getReg();
239 Register Src = Copy->getOperand(1).getReg();
315 Register SrcReg = MI.getOperand(i).getReg();
343 Register DefReg = MI->getOperand(0).getReg();
346 Register SrcReg = MI->getOperand(SrcOpIdx).getReg();
353 Register NewDef = MRI->createVirtualRegister(RC);
387 Register Reg = MO.getReg();
388 if (!Register::isVirtualRegister(Reg))
392 Register NewReg = MRI->createVirtualRegister(RC);
436 Register NewReg = MRI->createVirtualRegister(NewRC);
480 Register Reg = MO0.getReg();
lib/CodeGen/TargetInstrInfo.cpp 173 Register Reg0 = HasDef ? MI.getOperand(0).getReg() : Register();
174 Register Reg1 = MI.getOperand(Idx1).getReg();
175 Register Reg2 = MI.getOperand(Idx2).getReg();
187 bool Reg1IsRenamable = Register::isPhysicalRegister(Reg1)
190 bool Reg2IsRenamable = Register::isPhysicalRegister(Reg2)
232 if (Register::isPhysicalRegister(Reg1))
234 if (Register::isPhysicalRegister(Reg2))
446 Register FoldReg = FoldOp.getReg();
447 Register LiveReg = LiveOp.getReg();
454 if (Register::isPhysicalRegister(LiveOp.getReg()))
677 if (Op1.isReg() && Register::isVirtualRegister(Op1.getReg()))
679 if (Op2.isReg() && Register::isVirtualRegister(Op2.getReg()))
808 Register RegA = OpA.getReg();
809 Register RegB = OpB.getReg();
810 Register RegX = OpX.getReg();
811 Register RegY = OpY.getReg();
812 Register RegC = OpC.getReg();
814 if (Register::isVirtualRegister(RegA))
816 if (Register::isVirtualRegister(RegB))
818 if (Register::isVirtualRegister(RegX))
820 if (Register::isVirtualRegister(RegY))
822 if (Register::isVirtualRegister(RegC))
828 Register NewVR = MRI.createVirtualRegister(RC);
890 Register DefReg = MI.getOperand(0).getReg();
896 if (Register::isVirtualRegister(DefReg) && MI.getOperand(0).getSubReg() &&
927 Register Reg = MO.getReg();
932 if (Register::isPhysicalRegister(Reg)) {
lib/CodeGen/TargetRegisterInfo.cpp 89 Printable printReg(Register Reg, const TargetRegisterInfo *TRI,
94 else if (Register::isStackSlot(Reg))
95 OS << "SS#" << Register::stackSlot2Index(Reg);
96 else if (Register::isVirtualRegister(Reg)) {
101 OS << '%' << Register::virtReg2Index(Reg);
145 if (Register::isVirtualRegister(Unit)) {
146 OS << '%' << Register::virtReg2Index(Unit);
404 if (VRM && Register::isVirtualRegister(Phys))
412 if (!Register::isPhysicalRegister(Phys))
475 if (Register::isPhysicalRegister(Reg)) {
510 if (!Register::isVirtualRegister(CopySrcReg))
lib/CodeGen/TargetSchedule.cpp 303 Register Reg = DefMI->getOperand(DefOperIdx).getReg();
lib/CodeGen/TwoAddressInstructionPass.cpp 233 Register MOReg = MO.getReg();
302 Register MOReg = MO.getReg();
421 IsSrcPhys = Register::isPhysicalRegister(SrcReg);
422 IsDstPhys = Register::isPhysicalRegister(DstReg);
430 if (LIS && Register::isVirtualRegister(Reg) && !LIS->isNotInMIMap(*MI)) {
477 if (Register::isPhysicalRegister(Reg) &&
482 if (Register::isPhysicalRegister(Reg))
538 IsDstPhys = Register::isPhysicalRegister(DstReg);
548 while (Register::isVirtualRegister(Reg)) {
554 if (Register::isPhysicalRegister(Reg))
685 Register RegC = MI->getOperand(RegCIdx).getReg();
702 Register RegA = MI->getOperand(DstIdx).getReg();
913 Register MOReg = MO.getReg();
957 Register MOReg = MO.getReg();
1095 Register MOReg = MO.getReg();
1107 } else if (Register::isPhysicalRegister(MOReg)) {
1132 Register MOReg = MO.getReg();
1156 if (Register::isPhysicalRegister(MOReg) && LiveDefs.count(MOReg))
1209 Register DstOpReg = MI->getOperand(DstOpIdx).getReg();
1210 Register BaseOpReg = MI->getOperand(BaseOpIdx).getReg();
1222 Register OtherOpReg = MI->getOperand(OtherOpIdx).getReg();
1277 Register regA = MI.getOperand(DstIdx).getReg();
1278 Register regB = MI.getOperand(SrcIdx).getReg();
1284 if (Register::isVirtualRegister(regA))
1364 Register Reg = MRI->createVirtualRegister(RC);
1400 if (MO.isReg() && Register::isVirtualRegister(MO.getReg())) {
1474 Register SrcReg = SrcMO.getReg();
1475 Register DstReg = DstMO.getReg();
1485 if (Register::isVirtualRegister(DstReg))
1522 Register RegA = DstMO.getReg();
1559 if (Register::isVirtualRegister(RegA)) {
1580 if (Register::isVirtualRegister(RegA)) {
1600 if (Register::isVirtualRegister(RegA) && Register::isVirtualRegister(RegB))
1600 if (Register::isVirtualRegister(RegA) && Register::isVirtualRegister(RegB))
1742 Register SrcReg = mi->getOperand(SrcIdx).getReg();
1743 Register DstReg = mi->getOperand(DstIdx).getReg();
1801 Register DstReg = MI.getOperand(0).getReg();
1802 if (MI.getOperand(0).getSubReg() || Register::isPhysicalRegister(DstReg) ||
1818 Register SrcReg = UseMO.getReg();
1852 if (LV && isKill && !Register::isPhysicalRegister(SrcReg))
lib/CodeGen/UnreachableBlockElim.cpp 177 Register InputReg = Input.getReg();
178 Register OutputReg = Output.getReg();
lib/CodeGen/VirtRegMap.cpp 83 void VirtRegMap::assignVirt2Phys(Register virtReg, MCPhysReg physReg) {
101 bool VirtRegMap::hasPreferredPhys(Register VirtReg) {
102 Register Hint = MRI->getSimpleHint(VirtReg);
110 bool VirtRegMap::hasKnownPreference(Register VirtReg) {
112 if (Register::isPhysicalRegister(Hint.second))
114 if (Register::isVirtualRegister(Hint.second))
119 int VirtRegMap::assignVirt2StackSlot(Register virtReg) {
127 void VirtRegMap::assignVirt2StackSlot(Register virtReg, int SS) {
140 unsigned Reg = Register::index2VirtReg(i);
149 unsigned Reg = Register::index2VirtReg(i);
187 void addLiveInsForSubRanges(const LiveInterval &LI, Register PhysReg) const;
190 bool subRegLiveThrough(const MachineInstr &MI, Register SuperPhysReg) const;
267 Register PhysReg) const {
314 Register VirtReg = Register::index2VirtReg(Idx);
314 Register VirtReg = Register::index2VirtReg(Idx);
322 Register PhysReg = VRM->getPhys(VirtReg);
355 Register Reg = MO.getReg();
471 Register SuperPhysReg) const {
495 SmallVector<Register, 8> SuperDeads;
496 SmallVector<Register, 8> SuperDefs;
497 SmallVector<Register, 8> SuperKills;
517 Register VirtReg = MO.getReg();
518 Register PhysReg = VRM->getPhys(VirtReg);
lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp 555 Register OrigReg = U.getReg();
614 Register DestReg = MI->getOperand(0).getReg();
627 Register DestReg = MI->getOperand(0).getReg();
628 Register AccumReg = MI->getOperand(3).getReg();
lib/Target/AArch64/AArch64AdvSIMDScalarPass.cpp 108 if (Register::isVirtualRegister(Reg))
115 if (Register::isVirtualRegister(Reg))
204 Register OrigSrc0 = MI.getOperand(1).getReg();
205 Register OrigSrc1 = MI.getOperand(2).getReg();
239 Register Dst = MI.getOperand(0).getReg();
296 Register OrigSrc0 = MI.getOperand(1).getReg();
297 Register OrigSrc1 = MI.getOperand(2).getReg();
357 Register Dst = MRI->createVirtualRegister(&AArch64::FPR64RegClass);
lib/Target/AArch64/AArch64AsmPrinter.cpp 240 Register Reg = MI.getOperand(0).getReg();
505 Register Reg = MO.getReg();
529 Register Reg = MO.getReg();
553 Register Reg = MO.getReg();
627 Register Reg = MO.getReg();
757 Register DestReg = MI.getOperand(0).getReg();
758 Register ScratchReg = MI.getOperand(1).getReg();
759 Register ScratchRegW =
761 Register TableReg = MI.getOperand(2).getReg();
762 Register EntryReg = MI.getOperand(3).getReg();
832 Register ScratchReg = MI.getOperand(Opers.getNextScratchIdx()).getReg();
862 Register DestReg = MI.getOperand(0).getReg();
926 Register DestReg = MI->getOperand(0).getReg();
lib/Target/AArch64/AArch64CallLowering.cpp 60 Register getStackAddress(uint64_t Size, int64_t Offset,
65 Register AddrReg = MRI.createGenericVirtualRegister(LLT::pointer(0, 64));
71 void assignValueToReg(Register ValVReg, Register PhysReg,
71 void assignValueToReg(Register ValVReg, Register PhysReg,
88 void assignValueToAddress(Register ValVReg, Register Addr, uint64_t Size,
88 void assignValueToAddress(Register ValVReg, Register Addr, uint64_t Size,
141 Register getStackAddress(uint64_t Size, int64_t Offset,
150 Register FIReg = MRI.createGenericVirtualRegister(p0);
156 Register SPReg = MRI.createGenericVirtualRegister(p0);
159 Register OffsetReg = MRI.createGenericVirtualRegister(s64);
162 Register AddrReg = MRI.createGenericVirtualRegister(p0);
169 void assignValueToReg(Register ValVReg, Register PhysReg,
169 void assignValueToReg(Register ValVReg, Register PhysReg,
172 Register ExtReg = extendRegister(ValVReg, VA);
176 void assignValueToAddress(Register ValVReg, Register Addr, uint64_t Size,
176 void assignValueToAddress(Register ValVReg, Register Addr, uint64_t Size,
258 ArrayRef<Register> VRegs,
259 Register SwiftErrorVReg) const {
289 Register CurVReg = VRegs[i];
418 ArrayRef<ArrayRef<Register>> VRegs) const {
618 Register Reg = ArgLoc.getLocReg();
649 Register CopyRHS = RegDef->getOperand(1).getReg();
877 Register ForwardedReg = F.PReg;
lib/Target/AArch64/AArch64CallLowering.h 37 ArrayRef<Register> VRegs,
38 Register SwiftErrorVReg) const override;
41 ArrayRef<ArrayRef<Register>> VRegs) const override;
lib/Target/AArch64/AArch64CondBrTuning.cpp 81 if (!Register::isVirtualRegister(MO.getReg()))
101 Register NewDestReg = MI.getOperand(0).getReg();
lib/Target/AArch64/AArch64ConditionalCompares.cpp 223 Register Reg = I.getOperand(oi).getReg();
262 if (!Register::isVirtualRegister(DstReg))
634 Register DestReg =
lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp 148 Register Reg = MO.getReg();
149 if (!Register::isVirtualRegister(Reg) ||
lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp 112 Register DstReg = MI.getOperand(0).getReg();
153 Register DstReg = MI.getOperand(0).getReg();
177 Register StatusReg = MI.getOperand(1).getReg();
182 Register AddrReg = MI.getOperand(2).getReg();
183 Register DesiredReg = MI.getOperand(3).getReg();
184 Register NewReg = MI.getOperand(4).getReg();
257 Register StatusReg = MI.getOperand(2).getReg();
262 Register AddrReg = MI.getOperand(3).getReg();
263 Register DesiredLoReg = MI.getOperand(4).getReg();
264 Register DesiredHiReg = MI.getOperand(5).getReg();
265 Register NewLoReg = MI.getOperand(6).getReg();
266 Register NewHiReg = MI.getOperand(7).getReg();
348 Register SizeReg = MI.getOperand(2).getReg();
349 Register AddressReg = MI.getOperand(3).getReg();
478 Register DstReg = MI.getOperand(0).getReg();
551 Register DstReg = MI.getOperand(0).getReg();
595 Register DstReg = MI.getOperand(0).getReg();
680 Register SrcReg = FrameReg;
lib/Target/AArch64/AArch64FalkorHWPFFix.cpp 215 Register DestReg;
216 Register BaseReg;
645 Register BaseReg = MI.getOperand(BaseRegIdx).getReg();
lib/Target/AArch64/AArch64FastISel.cpp 3307 for (auto Reg : CLI.OutRegs)
3479 Register FramePtr = RegInfo->getFrameRegister(*(FuncInfo.MF));
3480 Register SrcReg = MRI.createVirtualRegister(&AArch64::GPR64RegClass);
3892 Register DestReg = VA.getLocReg();
4020 Register Reg64 = MRI.createVirtualRegister(&AArch64::GPR64RegClass);
4173 Register TmpReg = MRI.createVirtualRegister(RC);
4294 Register TmpReg = MRI.createVirtualRegister(RC);
4403 Register TmpReg = MRI.createVirtualRegister(RC);
4462 Register Src64 = MRI.createVirtualRegister(&AArch64::GPR64RegClass);
4545 Register LoadReg = MI->getOperand(1).getReg();
lib/Target/AArch64/AArch64FrameLowering.cpp 516 Register Reg0 = MBBI->getOperand(1).getReg();
517 Register Reg1 = MBBI->getOperand(2).getReg();
565 Register Reg0 = MBBI->getOperand(0).getReg();
566 Register Reg1 = MBBI->getOperand(1).getReg();
1191 Register FramePtr = RegInfo->getFrameRegister(MF);
lib/Target/AArch64/AArch64ISelLowering.cpp 1342 Register DestReg = MI.getOperand(0).getReg();
1343 Register IfTrueReg = MI.getOperand(1).getReg();
1344 Register IfFalseReg = MI.getOperand(2).getReg();
3354 Register Reg =
5542 Register AArch64TargetLowering::
5544 Register Reg = MatchRegisterName(RegName);
12394 Register NewVR = MRI->createVirtualRegister(RC);
lib/Target/AArch64/AArch64ISelLowering.h 716 Register getRegisterByName(const char* RegName, EVT VT,
lib/Target/AArch64/AArch64InstrInfo.cpp 418 while (Register::isVirtualRegister(VReg)) {
433 if (!Register::isVirtualRegister(VReg))
576 Register SrcReg = Cond[2].getReg();
1073 Register Reg = MO.getReg();
1074 if (Register::isPhysicalRegister(Reg)) {
1501 Register Reg = MI.getOperand(0).getReg();
1606 Register DstReg = MI.getOperand(0).getReg();
1636 Register DstReg = MI.getOperand(0).getReg();
1942 Register BaseReg = MI.getOperand(1).getReg();
2398 if (Register::isPhysicalRegister(Reg))
2791 if (Register::isPhysicalRegister(SrcReg)) {
2830 if (Register::isVirtualRegister(SrcReg))
2840 if (Register::isVirtualRegister(SrcReg))
2921 if (Register::isPhysicalRegister(DestReg)) {
2961 if (Register::isVirtualRegister(DestReg))
2971 if (Register::isVirtualRegister(DestReg))
3195 Register DstReg = MI.getOperand(0).getReg();
3196 Register SrcReg = MI.getOperand(1).getReg();
3197 if (SrcReg == AArch64::SP && Register::isVirtualRegister(DstReg)) {
3201 if (DstReg == AArch64::SP && Register::isVirtualRegister(SrcReg)) {
3241 Register DstReg = DstMO.getReg();
3242 Register SrcReg = SrcMO.getReg();
3246 return Register::isVirtualRegister(Reg) ? MRI.getRegClass(Reg)
3272 if (IsSpill && DstMO.isUndef() && Register::isPhysicalRegister(SrcReg)) {
3600 if (MO.isReg() && Register::isVirtualRegister(MO.getReg()))
3988 const Register *ReplacedAddend = nullptr) {
3993 Register ResultReg = Root.getOperand(0).getReg();
3994 Register SrcReg0 = MUL->getOperand(1).getReg();
3996 Register SrcReg1 = MUL->getOperand(2).getReg();
4010 if (Register::isVirtualRegister(ResultReg))
4012 if (Register::isVirtualRegister(SrcReg0))
4014 if (Register::isVirtualRegister(SrcReg1))
4016 if (Register::isVirtualRegister(SrcReg2))
4070 Register ResultReg = Root.getOperand(0).getReg();
4071 Register SrcReg0 = MUL->getOperand(1).getReg();
4073 Register SrcReg1 = MUL->getOperand(2).getReg();
4076 if (Register::isVirtualRegister(ResultReg))
4078 if (Register::isVirtualRegister(SrcReg0))
4080 if (Register::isVirtualRegister(SrcReg1))
4082 if (Register::isVirtualRegister(VR))
4171 Register NewVR = MRI.createVirtualRegister(OrrRC);
4213 Register NewVR = MRI.createVirtualRegister(SubRC);
4263 Register NewVR = MRI.createVirtualRegister(OrrRC);
4538 Register NewVR = MRI.createVirtualRegister(RC);
4585 Register NewVR = MRI.createVirtualRegister(RC);
4645 Register NewVR = MRI.createVirtualRegister(RC);
4665 Register NewVR = MRI.createVirtualRegister(RC);
4685 Register NewVR = MRI.createVirtualRegister(RC);
4786 Register VReg = MI.getOperand(0).getReg();
4787 if (!Register::isVirtualRegister(VReg))
4794 Register CopyVReg = DefMI->getOperand(1).getReg();
4822 Register NewReg = MO.getReg();
4823 if (!Register::isVirtualRegister(NewReg))
lib/Target/AArch64/AArch64InstructionSelector.cpp 100 Register Scalar,
109 MachineInstr *emitLaneInsert(Optional<Register> DstReg, Register SrcReg,
109 MachineInstr *emitLaneInsert(Optional<Register> DstReg, Register SrcReg,
110 Register EltReg, unsigned LaneIdx,
138 MachineInstr *emitVectorConcat(Optional<Register> Dst, Register Op1,
138 MachineInstr *emitVectorConcat(Optional<Register> Dst, Register Op1,
139 Register Op2,
144 MachineInstr *emitADD(Register DefReg, MachineOperand &LHS, MachineOperand &RHS,
148 MachineInstr *emitTST(const Register &LHS, const Register &RHS,
148 MachineInstr *emitTST(const Register &LHS, const Register &RHS,
150 MachineInstr *emitExtractVectorElt(Optional<Register> DstReg,
152 Register VecReg, unsigned LaneIdx,
162 MachineInstr *emitCSetForICMP(Register DefReg, unsigned Pred,
234 Register narrowExtendRegIfNeeded(Register ExtReg,
234 Register narrowExtendRegIfNeeded(Register ExtReg,
424 if (!Register::isVirtualRegister(MO.getReg())) {
559 const Register DstReg = I.getOperand(0).getReg();
560 const Register SrcReg = I.getOperand(1).getReg();
593 const RegisterBankInfo &RBI, Register SrcReg,
606 if (!Register::isPhysicalRegister(I.getOperand(0).getReg()))
620 Register DstReg = I.getOperand(0).getReg();
621 Register SrcReg = I.getOperand(1).getReg();
646 Register DstReg = I.getOperand(0).getReg();
647 Register SrcReg = I.getOperand(1).getReg();
723 Register PromoteReg =
740 if (Register::isPhysicalRegister(DstReg))
955 const Register CondReg = I.getOperand(0).getReg();
963 Register LHS = CCMI->getOperand(2).getReg();
964 Register RHS = CCMI->getOperand(3).getReg();
1012 Register DstReg = I.getOperand(0).getReg();
1014 Register Src1Reg = I.getOperand(1).getReg();
1015 Register Src2Reg = I.getOperand(2).getReg();
1042 Register DstReg = I.getOperand(0).getReg();
1044 Register Src1Reg = I.getOperand(1).getReg();
1045 Register Src2Reg = I.getOperand(2).getReg();
1091 Register ListReg = I.getOperand(0).getReg();
1093 Register ArgsAddrReg = MRI.createVirtualRegister(&AArch64::GPR64RegClass);
1131 Register DstReg = ForceDstReg
1147 Register DstReg = BuildMovK(MovZ.getReg(0),
1169 Register SrcReg = I.getOperand(1).getReg();
1170 Register ShiftReg = I.getOperand(2).getReg();
1253 Register DefDstReg = Def->getOperand(0).getReg();
1255 Register StoreSrcReg = I.getOperand(0).getReg();
1296 Register DefReg = I.getOperand(0).getReg();
1333 const Register DefReg = I.getOperand(0).getReg();
1404 const Register CondReg = I.getOperand(0).getReg();
1449 Register DstReg = I.getOperand(0).getReg();
1494 const Register DefReg = I.getOperand(0).getReg();
1552 const Register DefGPRReg = MRI.createVirtualRegister(&GPRRC);
1580 Register DstReg = I.getOperand(0).getReg();
1581 Register SrcReg = I.getOperand(1).getReg();
1660 Register SrcReg = MRI.createGenericVirtualRegister(LLT::scalar(64));
1744 const Register PtrReg = I.getOperand(1).getReg();
1754 const Register ValReg = I.getOperand(0).getReg();
1774 Register Ptr2Reg = PtrMI->getOperand(1).getReg();
1805 Register LdReg = MRI.createVirtualRegister(&AArch64::GPR32RegClass);
1806 Register DstReg = I.getOperand(0).getReg();
1827 const Register DefReg = I.getOperand(0).getReg();
1871 const Register DefReg = I.getOperand(0).getReg();
1946 const Register DstReg = I.getOperand(0).getReg();
1947 const Register SrcReg = I.getOperand(1).getReg();
2014 const Register DstReg = I.getOperand(0).getReg();
2015 const Register SrcReg = I.getOperand(1).getReg();
2046 Register ExtSrc = MRI.createVirtualRegister(&AArch64::GPR64allRegClass);
2061 const Register DefReg = I.getOperand(0).getReg();
2062 const Register SrcReg = I.getOperand(1).getReg();
2164 const Register CondReg = I.getOperand(1).getReg();
2165 const Register TReg = I.getOperand(2).getReg();
2166 const Register FReg = I.getOperand(3).getReg();
2171 Register CSelOpc = selectSelectOpc(I, MRI, RBI);
2238 const Register DefReg = I.getOperand(0).getReg();
2239 Register Def1Reg = DefReg;
2251 Register Def2Reg = MRI.createVirtualRegister(&AArch64::GPR32RegClass);
2282 const Register DstReg = I.getOperand(0).getReg();
2335 Register JTAddr = I.getOperand(0).getReg();
2337 Register Index = I.getOperand(2).getReg();
2340 Register TargetReg = MRI.createVirtualRegister(&AArch64::GPR64RegClass);
2341 Register ScratchReg = MRI.createVirtualRegister(&AArch64::GPR64spRegClass);
2357 Register DstReg = I.getOperand(0).getReg();
2512 Register DstReg = I.getOperand(0).getReg();
2514 Register SrcReg = I.getOperand(2).getReg();
2515 Register Src2Reg = I.getOperand(3).getReg();
2683 unsigned EltSize, const TargetRegisterClass *DstRC, Register Scalar,
2725 Register DstReg = I.getOperand(0).getReg();
2726 Register Src1Reg = I.getOperand(1).getReg();
2727 Register Src2Reg = I.getOperand(2).getReg();
2750 Register SubToRegDef = MRI.createVirtualRegister(DstRC);
2757 Register SubToRegDef2 = MRI.createVirtualRegister(DstRC);
2805 Optional<Register> DstReg, const RegisterBank &DstRB, LLT ScalarTy,
2806 Register VecReg, unsigned LaneIdx, MachineIRBuilder &MIRBuilder) const {
2833 Register InsertReg = VecReg;
2868 Register DstReg = I.getOperand(0).getReg();
2870 const Register SrcReg = I.getOperand(1).getReg();
2907 Register SrcReg = I.getOperand(NumElts).getReg();
2924 Register Dst = I.getOperand(OpIdx).getReg();
2952 Register SrcReg = I.getOperand(NumElts).getReg();
2977 SmallVector<Register, 4> InsertRegs;
2991 Register ImpDefReg = MRI.createVirtualRegister(&AArch64::FPR128RegClass);
2997 Register InsertReg = MRI.createVirtualRegister(&AArch64::FPR128RegClass);
3017 Register CopyTo = I.getOperand(0).getReg();
3024 for (Register InsReg : InsertRegs) {
3025 Register CopyTo = I.getOperand(LaneIdx).getReg();
3053 Register Dst = I.getOperand(0).getReg();
3054 Register Op1 = I.getOperand(1).getReg();
3055 Register Op2 = I.getOperand(2).getReg();
3145 AArch64InstructionSelector::emitADD(Register DefReg, MachineOperand &LHS,
3179 Register ZReg = Is32Bit ? AArch64::WZR : AArch64::XZR;
3196 AArch64InstructionSelector::emitTST(const Register &LHS, const Register &RHS,
3196 AArch64InstructionSelector::emitTST(const Register &LHS, const Register &RHS,
3203 Register ZReg = Is32Bit ? AArch64::WZR : AArch64::XZR;
3237 Register ZReg;
3272 Optional<Register> Dst, Register Op1, Register Op2,
3272 Optional<Register> Dst, Register Op1, Register Op2,
3272 Optional<Register> Dst, Register Op1, Register Op2,
3365 AArch64InstructionSelector::emitCSetForICMP(Register DefReg, unsigned Pred,
3415 Register::isPhysicalRegister(CondDef->getOperand(1).getReg()))
3598 Register ScalarReg = InsMI->getOperand(2).getReg();
3652 Register Src1Reg = I.getOperand(1).getReg();
3654 Register Src2Reg = I.getOperand(2).getReg();
3743 Optional<Register> DstReg, Register SrcReg, Register EltReg,
3743 Optional<Register> DstReg, Register SrcReg, Register EltReg,
3743 Optional<Register> DstReg, Register SrcReg, Register EltReg,
3778 Register DstReg = I.getOperand(0).getReg();
3783 Register EltReg = I.getOperand(2).getReg();
3791 Register IdxReg = I.getOperand(3).getReg();
3798 Register SrcReg = I.getOperand(1).getReg();
3821 Register DemoteVec = InsMI->getOperand(0).getReg();
3869 Register DstVec = ScalarToVec->getOperand(0).getReg();
3905 Register Reg = MRI.createVirtualRegister(RC);
3906 Register DstReg = I.getOperand(0).getReg();
3973 Register DstReg = I.getOperand(0).getReg();
3974 Register SrcReg = I.getOperand(2).getReg();
4151 Register DefReg = MI.getOperand(0).getReg();
4220 Register OffsetReg = OffsetInst->getOperand(1).getReg();
4221 Register ConstantReg = OffsetInst->getOperand(2).getReg();
4485 Register ShiftReg = ShiftLHS.getReg();
4552 Register AArch64InstructionSelector::narrowExtendRegIfNeeded(
4553 Register ExtReg, MachineIRBuilder &MIB) const {
4559 Register NarrowReg = MRI.createVirtualRegister(&AArch64::GPR32RegClass);
4578 Register ExtReg;
lib/Target/AArch64/AArch64LegalizerInfo.cpp 667 Register AmtReg = MI.getOperand(2).getReg();
697 Register ValReg = MI.getOperand(0).getReg();
714 Register NewReg = MRI.createGenericVirtualRegister(NewTy);
728 Register Dst = MI.getOperand(0).getReg();
729 Register ListPtr = MI.getOperand(1).getReg();
735 Register List = MRI.createGenericVirtualRegister(PtrTy);
741 Register DstPtr;
lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp 875 Register Reg = getLdStRegOp(*I).getReg();
904 Register DstRegX = DstMO.getReg();
906 Register DstRegW = TRI->getSubReg(DstRegX, AArch64::sub_32);
949 Register LdRt = getLdStRegOp(*LoadI).getReg();
951 Register StRt = getLdStRegOp(*StoreI).getReg();
1109 Register BaseReg = getLdStBaseOp(LoadMI).getReg();
1223 Register Reg = getLdStRegOp(FirstMI).getReg();
1224 Register BaseReg = getLdStBaseOp(FirstMI).getReg();
1255 Register MIBaseReg = getLdStBaseOp(MI).getReg();
1494 Register BaseReg = getLdStBaseOp(MemMI).getReg();
1512 Register DestReg = getLdStRegOp(MemMI, i).getReg();
1554 Register BaseReg = getLdStBaseOp(MemMI).getReg();
1566 Register DestReg = getLdStRegOp(MemMI, i).getReg();
lib/Target/AArch64/AArch64PBQPRegAlloc.cpp 165 if (Register::isPhysicalRegister(Rd) || Register::isPhysicalRegister(Ra)) {
165 if (Register::isPhysicalRegister(Rd) || Register::isPhysicalRegister(Ra)) {
362 Register Rd = MI.getOperand(0).getReg();
363 Register Ra = MI.getOperand(3).getReg();
372 Register Rd = MI.getOperand(0).getReg();
lib/Target/AArch64/AArch64RedundantCopyElimination.cpp 382 Register DefReg = MI->getOperand(0).getReg();
383 Register SrcReg = IsCopy ? MI->getOperand(1).getReg() : Register();
lib/Target/AArch64/AArch64RegisterBankInfo.cpp 566 Register DstReg = MI.getOperand(0).getReg();
567 Register SrcReg = MI.getOperand(1).getReg();
569 if ((Register::isPhysicalRegister(DstReg) ||
571 (Register::isPhysicalRegister(SrcReg) ||
696 Register VReg = MI.getOperand(0).getReg();
748 Register VReg = MI.getOperand(Idx).getReg();
816 Register VReg = MI.getOperand(1).getReg();
lib/Target/AArch64/AArch64RegisterInfo.cpp 290 Register
502 Register ScratchReg =
532 Register ScratchReg =
lib/Target/AArch64/AArch64RegisterInfo.h 116 Register getFrameRegister(const MachineFunction &MF) const override;
lib/Target/AArch64/AArch64SIMDInstrOpt.cpp 429 Register MulDest = MI.getOperand(0).getReg();
430 Register SrcReg0 = MI.getOperand(1).getReg();
432 Register SrcReg1 = MI.getOperand(2).getReg();
438 Register SrcReg2 = MI.getOperand(3).getReg();
lib/Target/AArch64/AArch64SpeculationHardening.cpp 525 Register Reg = Use.getReg();
565 Register DstReg = MI.getOperand(0).getReg();
566 Register SrcReg = MI.getOperand(1).getReg();
lib/Target/AArch64/AArch64StackTaggingPreRA.cpp 160 Register::isVirtualRegister(UseI->getOperand(0).getReg())) {
lib/Target/AArch64/AArch64StorePairSuppress.cpp 154 Register BaseReg = BaseOp->getReg();
lib/Target/AMDGPU/AMDGPUArgumentUsageInfo.h 32 Register Reg;
47 static ArgDescriptor createRegister(Register Reg, unsigned Mask = ~0u) {
71 Register getRegister() const {
lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp 707 Register Reg = MO.getReg();
lib/Target/AMDGPU/AMDGPUCallLowering.cpp 42 Register getStackAddress(uint64_t Size, int64_t Offset,
47 void assignValueToAddress(Register ValVReg, Register Addr, uint64_t Size,
47 void assignValueToAddress(Register ValVReg, Register Addr, uint64_t Size,
52 void assignValueToReg(Register ValVReg, Register PhysReg,
52 void assignValueToReg(Register ValVReg, Register PhysReg,
54 Register ExtReg;
82 Register getStackAddress(uint64_t Size, int64_t Offset,
87 Register AddrReg = MRI.createGenericVirtualRegister(
94 void assignValueToReg(Register ValVReg, Register PhysReg,
94 void assignValueToReg(Register ValVReg, Register PhysReg,
120 void assignValueToAddress(Register ValVReg, Register Addr, uint64_t Size,
120 void assignValueToAddress(Register ValVReg, Register Addr, uint64_t Size,
187 SmallVector<Register, 8> SplitRegs;
196 Register PartReg = MRI.createGenericVirtualRegister(PartLLT);
219 ArrayRef<Register> DstRegs,
220 Register SrcReg,
251 Register BigReg = MRI.createGenericVirtualRegister(BigTy);
262 const Value *Val, ArrayRef<Register> VRegs,
293 ArrayRef<Register> VRegs) const {
318 Register ReturnAddrVReg;
329 Register LiveInReturn = MF.addLiveIn(TRI->getReturnAddressReg(MF),
340 Register AMDGPUCallLowering::lowerParameterPtr(MachineIRBuilder &B,
351 Register DstReg = MRI.createGenericVirtualRegister(PtrType);
352 Register KernArgSegmentPtr =
354 Register KernArgSegmentVReg = MRI.getLiveInVirtReg(KernArgSegmentPtr);
356 Register OffsetReg = MRI.createGenericVirtualRegister(LLT::scalar(64));
367 Register DstReg) const {
374 Register PtrReg = lowerParameterPtr(B, ParamTy, Offset);
412 Register InputPtrReg = Info.addKernargSegmentPtr(TRI);
414 Register VReg = MRI.createGenericVirtualRegister(P4);
439 ArrayRef<ArrayRef<Register>> VRegs) const {
471 ArrayRef<Register> OrigArgRegs = VRegs[i];
472 Register ArgReg =
491 ArrayRef<Register> OrigRegs,
492 ArrayRef<Register> Regs,
529 SmallVector<Register, 8> EltMerges;
552 ArrayRef<ArrayRef<Register>> VRegs) const {
577 Register ReturnAddrReg = TRI->getReturnAddressReg(MF);
578 Register LiveInReturn = MF.addLiveIn(ReturnAddrReg,
585 Register ImplicitBufferPtrReg = Info->addImplicitBufferPtr(*TRI);
lib/Target/AMDGPU/AMDGPUCallLowering.h 26 Register lowerParameterPtr(MachineIRBuilder &B, Type *ParamTy,
30 unsigned Align, Register DstReg) const;
33 using SplitArgTy = std::function<void(ArrayRef<Register>, LLT, LLT, int)>;
42 ArrayRef<Register> VRegs, MachineInstrBuilder &Ret) const;
48 ArrayRef<Register> VRegs) const override;
51 ArrayRef<ArrayRef<Register>> VRegs) const;
54 ArrayRef<ArrayRef<Register>> VRegs) const override;
lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp 550 if (Register::isVirtualRegister(Reg)) {
lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp 72 static bool isSCC(Register Reg, const MachineRegisterInfo &MRI) {
73 if (Register::isPhysicalRegister(Reg))
94 bool AMDGPUInstructionSelector::isVCC(Register Reg,
96 if (Register::isPhysicalRegister(Reg))
119 Register DstReg = Dst.getReg();
120 Register SrcReg = Src.getReg();
168 if (Register::isPhysicalRegister(MO.getReg()))
181 const Register DefReg = I.getOperand(0).getReg();
221 Register DstReg = MRI->createVirtualRegister(&SubRC);
225 Register Reg = MO.getReg();
266 Register DstReg = Dst.getReg();
302 Register DstReg = I.getOperand(0).getReg();
330 Register UnusedCarry = MRI->createVirtualRegister(TRI.getWaveMaskRegClass());
353 Register DstLo = MRI->createVirtualRegister(&HalfRC);
354 Register DstHi = MRI->createVirtualRegister(&HalfRC);
365 Register CarryReg = MRI->createVirtualRegister(CarryRC);
401 Register Dst0Reg = I.getOperand(0).getReg();
402 Register Dst1Reg = I.getOperand(1).getReg();
416 Register Src0Reg = I.getOperand(2).getReg();
417 Register Src1Reg = I.getOperand(3).getReg();
462 Register DstReg = MI.getOperand(0).getReg();
505 Register SrcReg = Src.getReg();
506 Register DstReg0 = MI.getOperand(0).getReg();
563 Register DstReg = I.getOperand(0).getReg();
564 Register Src0Reg = I.getOperand(1).getReg();
565 Register Src1Reg = I.getOperand(2).getReg();
626 Register DstReg = I.getOperand(0).getReg();
627 Register Src0Reg = I.getOperand(2).getReg();
628 Register Src1Reg = I.getOperand(3).getReg();
632 for (Register Reg : { DstReg, Src0Reg, Src1Reg })
720 Register SrcReg = I.getOperand(2).getReg();
725 Register CCReg = I.getOperand(0).getReg();
775 static bool isZero(Register Reg, MachineRegisterInfo &MRI) {
801 static std::tuple<Register, unsigned, MachineInstr *>
802 getBaseWithConstantOffset(MachineRegisterInfo &MRI, Register Reg) {
919 std::tuple<Register, unsigned, unsigned>
921 Register OrigOffset) const {
923 Register BaseReg;
959 Register OverflowVal = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass);
964 Register NewBaseReg = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass);
982 Register VData = MI.getOperand(1).getReg();
993 Register RSrc = MI.getOperand(2).getReg();
994 Register VOffset = MI.getOperand(3).getReg();
995 Register SOffset = MI.getOperand(4).getReg();
1056 Register Reg0 = I.getOperand(3).getReg();
1057 Register Reg1 = I.getOperand(4).getReg();
1058 Register Undef = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass);
1076 Register Reg = I.getOperand(1).getReg();
1096 Register DstReg = I.getOperand(0).getReg();
1100 Register CCReg = CCOp.getReg();
1166 Register DstReg = I.getOperand(0).getReg();
1167 Register SrcReg = I.getOperand(1).getReg();
1221 const Register DstReg = I.getOperand(0).getReg();
1222 const Register SrcReg = I.getOperand(1).getReg();
1245 Register TmpReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass);
1320 Register ExtReg = MRI->createVirtualRegister(&AMDGPU::SReg_64RegClass);
1321 Register UndefReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass);
1372 Register Src = I.getOperand(1).getReg();
1377 Register DstReg = I.getOperand(0).getReg();
1410 Register DstReg = I.getOperand(0).getReg();
1444 Register LoReg = MRI->createVirtualRegister(RC);
1445 Register HiReg = MRI->createVirtualRegister(RC);
1559 Register CondReg = CondOp.getReg();
1563 Register CondPhysReg;
1601 Register DstReg = I.getOperand(0).getReg();
1618 Register DstReg = I.getOperand(0).getReg();
1619 Register SrcReg = I.getOperand(1).getReg();
1640 Register ImmReg = MRI->createVirtualRegister(&RegRC);
1652 Register HiReg = MRI->createVirtualRegister(&RegRC);
1653 Register LoReg = MRI->createVirtualRegister(&RegRC);
1654 Register MaskLo = MRI->createVirtualRegister(&RegRC);
1779 std::pair<Register, unsigned>
1781 Register Src) const {
1811 Register Src;
1825 Register Src;
1848 Register Src;
1940 Register OffsetReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass);
1976 Register BasePtr = OpDef->getOperand(1).getReg();
2009 Register HighBits = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass);
2027 Register SOffsetReg = isStackPtrRelative(PtrInfo)
2042 Register VAddr = Root.getReg();
2071 Register SOffset = FI.hasValue() ? Info->getStackPtrOffsetReg()
2123 Register SOffsetReg = isStackPtrRelative(PtrInfo)
lib/Target/AMDGPU/AMDGPUInstructionSelector.h 70 bool isVCC(Register Reg, const MachineRegisterInfo &MRI) const;
95 std::tuple<Register, unsigned, unsigned>
96 splitBufferOffsets(MachineIRBuilder &B, Register OrigOffset) const;
116 std::pair<Register, unsigned>
117 selectVOP3ModsImpl(Register Src) const;
lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp 1136 Register AMDGPULegalizerInfo::getSegmentAperture(
1160 Register ApertureReg = MRI.createGenericVirtualRegister(S32);
1161 Register GetReg = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
1177 Register QueuePtr = MRI.createGenericVirtualRegister(
1202 Register LoadResult = MRI.createGenericVirtualRegister(S32);
1203 Register LoadAddr;
1218 Register Dst = MI.getOperand(0).getReg();
1219 Register Src = MI.getOperand(1).getReg();
1268 Register PtrLo32 = MRI.createGenericVirtualRegister(DstTy);
1273 Register CmpRes = MRI.createGenericVirtualRegister(LLT::scalar(1));
1292 Register ApertureReg = getSegmentAperture(SrcAS, MRI, B);
1296 Register CmpRes = MRI.createGenericVirtualRegister(LLT::scalar(1));
1299 Register BuildPtr = MRI.createGenericVirtualRegister(DstTy);
1302 Register SrcAsInt = MRI.createGenericVirtualRegister(S32);
1321 Register Src = MI.getOperand(1).getReg();
1351 Register Src = MI.getOperand(1).getReg();
1397 Register Src = MI.getOperand(1).getReg();
1402 Register Hi = Unmerge.getReg(1);
1439 Register Dst = MI.getOperand(0).getReg();
1440 Register Src = MI.getOperand(1).getReg();
1501 Register Dst = MI.getOperand(0).getReg();
1502 Register Vec = MI.getOperand(1).getReg();
1530 Register Dst = MI.getOperand(0).getReg();
1531 Register Vec = MI.getOperand(1).getReg();
1532 Register Ins = MI.getOperand(2).getReg();
1554 Register DstReg = MI.getOperand(0).getReg();
1555 Register SrcReg = MI.getOperand(1).getReg();
1559 Register TrigVal;
1571 B.buildIntrinsic(TrigIntrin, makeArrayRef<Register>(DstReg), false)
1579 Register DstReg, LLT PtrTy,
1615 Register PCReg = PtrTy.getSizeInBits() != 32 ? DstReg :
1637 Register DstReg = MI.getOperand(0).getReg();
1683 Register GOTAddr = MRI.createGenericVirtualRegister(PtrTy);
1739 Register DstReg = MI.getOperand(0).getReg();
1740 Register PtrReg = MI.getOperand(1).getReg();
1741 Register CmpVal = MI.getOperand(2).getReg();
1742 Register NewVal = MI.getOperand(3).getReg();
1752 Register PackedVal = B.buildBuildVector(VecTy, { NewVal, CmpVal }).getReg(0);
1767 Register CondDef = MI.getOperand(0).getReg();
1776 Register AMDGPULegalizerInfo::getLiveInRegister(MachineRegisterInfo &MRI,
1777 Register Reg, LLT Ty) const {
1778 Register LiveIn = MRI.getLiveInVirtReg(Reg);
1782 Register NewReg = MRI.createGenericVirtualRegister(Ty);
1787 bool AMDGPULegalizerInfo::loadInputValue(Register DstReg, MachineIRBuilder &B,
1797 Register LiveIn = getLiveInRegister(MRI, Arg->getRegister(), Ty);
1805 Register AndMaskSrc = LiveIn;
1863 Register Dst = MI.getOperand(0).getReg();
1879 Register Res = MI.getOperand(0).getReg();
1880 Register LHS = MI.getOperand(1).getReg();
1881 Register RHS = MI.getOperand(2).getReg();
1940 Register Res = MI.getOperand(0).getReg();
1941 Register LHS = MI.getOperand(1).getReg();
1942 Register RHS = MI.getOperand(2).getReg();
1973 Register Res = MI.getOperand(0).getReg();
1974 Register LHS = MI.getOperand(2).getReg();
1975 Register RHS = MI.getOperand(3).getReg();
2019 Register DstReg = MI.getOperand(0).getReg();
2030 Register KernargPtrReg = MRI.createGenericVirtualRegister(DstTy);
2044 Register ApertureReg = getSegmentAperture(AddrSpace, MRI, B);
2052 Register AMDGPULegalizerInfo::handleD16VData(MachineIRBuilder &B,
2054 Register Reg) const {
2065 SmallVector<Register, 4> WideRegs;
2079 Register VData = MI.getOperand(1).getReg();
2089 Register AnyExt = B.buildAnyExt(LLT::scalar(32), VData).getReg(0);
2118 Register Def = MI.getOperand(1).getReg();
2119 Register Use = MI.getOperand(3).getReg();
2140 Register Reg = MI.getOperand(2).getReg();
lib/Target/AMDGPU/AMDGPULegalizerInfo.h 39 Register getSegmentAperture(unsigned AddrSpace,
63 Register DstReg, LLT PtrTy, MachineIRBuilder &B, const GlobalValue *GV,
78 Register getLiveInRegister(MachineRegisterInfo &MRI,
79 Register Reg, LLT Ty) const;
81 bool loadInputValue(Register DstReg, MachineIRBuilder &B,
101 Register handleD16VData(MachineIRBuilder &B, MachineRegisterInfo &MRI,
102 Register Reg) const;
lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp 697 if (Register::isVirtualRegister(Reg)) {
737 if (Register::isVirtualRegister(Reg)) {
952 if (Register::isPhysicalRegister(NewRegister)) {
1026 Register Reg = RI.getReg();
1027 if (Register::isVirtualRegister(Reg)) {
1407 Register LinearizeDestReg =
1895 Register CondReg = Cond[0].getReg();
1934 Register TrueBBReg = MRI->createVirtualRegister(RegClass);
1935 Register FalseBBReg = MRI->createVirtualRegister(RegClass);
2001 Register NextDestReg = MRI->createVirtualRegister(RegClass);
2061 Register PHIDestReg = MRI->createVirtualRegister(RegClass);
2062 Register IfSourceReg = MRI->createVirtualRegister(RegClass);
2177 Register NewBackedgeReg = MRI->createVirtualRegister(RegClass);
2235 if (Register::isPhysicalRegister(NewRegister)) {
2314 Register CodeBBSelectReg = MRI->createVirtualRegister(RegClass);
2451 Register NewDestReg = MRI->createVirtualRegister(RegClass);
2739 Register InnerSelectReg =
2741 Register NewInReg = MRI->createVirtualRegister(MRI->getRegClass(InReg));
lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp 62 Register Reg = Op.getReg();
188 Register Reg = MI.getOperand(RegSrcOpIdx[I]).getReg();
604 SmallVector<Register, 2> &Regs,
606 Register Reg) const {
609 Register LoLHS = MRI->createGenericVirtualRegister(HalfTy);
610 Register HiLHS = MRI->createGenericVirtualRegister(HalfTy);
625 static void setRegsToType(MachineRegisterInfo &MRI, ArrayRef<Register> Regs,
627 for (Register Reg : Regs) {
666 SmallVector<Register, 4> ResultRegs;
667 SmallVector<Register, 4> InitResultRegs;
668 SmallVector<Register, 4> PhiRegs;
690 Register InitReg = B.buildUndef(ResTy).getReg(0);
691 Register PhiReg = MRI.createGenericVirtualRegister(ResTy);
699 Register SaveExecReg = MRI.createVirtualRegister(WaveRC);
700 Register InitSaveExecReg = MRI.createVirtualRegister(WaveRC);
706 Register PhiExec = MRI.createVirtualRegister(WaveRC);
707 Register NewExec = MRI.createVirtualRegister(WaveRC);
762 Register CondReg;
776 Register CurrentLaneOpReg
786 Register NewCondReg = MRI.createVirtualRegister(WaveRC);
799 Register AndReg = MRI.createVirtualRegister(WaveRC);
810 SmallVector<Register, 8> ReadlanePieces;
832 Register UnmergePiece = Unmerge.getReg(PieceIdx);
834 Register CurrentLaneOpReg;
836 Register CurrentLaneOpRegLo = MRI.createGenericVirtualRegister(S32);
837 Register CurrentLaneOpRegHi = MRI.createGenericVirtualRegister(S32);
881 Register NewCondReg = MRI.createVirtualRegister(WaveRC);
892 Register AndReg = MRI.createVirtualRegister(WaveRC);
962 SmallSet<Register, 4> &SGPROperandRegs, MachineInstr &MI,
966 Register Reg = MI.getOperand(Op).getReg();
981 SmallSet<Register, 4> SGPROperandRegs;
1001 Register Reg = MI.getOperand(OpIdx).getReg();
1007 Register SGPR = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
1026 Register Reg,
1040 Register DstReg = MI.getOperand(0).getReg();
1053 Register PtrReg = MI.getOperand(1).getReg();
1069 Register BasePtrReg = SrcRegs[0];
1095 Register TmpReg = MRI.createGenericVirtualRegister(MRI.getType(DstReg));
1100 Register IdxReg = MRI.createGenericVirtualRegister(LLT::scalar(32));
1149 Register AMDGPURegisterBankInfo::handleD16VData(MachineIRBuilder &B,
1151 Register Reg) const {
1163 SmallVector<Register, 4> WideRegs;
1173 static std::pair<Register, unsigned>
1174 getBaseWithConstantOffset(MachineRegisterInfo &MRI, Register Reg) {
1179 Register Base;
1187 std::pair<Register, unsigned>
1189 Register OrigOffset) const {
1191 Register BaseReg;
1231 static bool isZero(Register Reg, MachineRegisterInfo &MRI) {
1256 Register VData = MI.getOperand(1).getReg();
1270 Register RSrc = MI.getOperand(2).getReg();
1271 Register VOffset = MI.getOperand(3).getReg();
1272 Register SOffset = MI.getOperand(4).getReg();
1333 Register DstReg = MI.getOperand(0).getReg();
1340 SmallVector<Register, 2> DefRegs(OpdMapper.getVRegs(0));
1341 SmallVector<Register, 1> Src0Regs(OpdMapper.getVRegs(1));
1342 SmallVector<Register, 2> Src1Regs(OpdMapper.getVRegs(2));
1343 SmallVector<Register, 2> Src2Regs(OpdMapper.getVRegs(3));
1383 Register DstReg = MI.getOperand(0).getReg();
1389 SmallVector<Register, 2> DefRegs(OpdMapper.getVRegs(0));
1390 SmallVector<Register, 2> Src0Regs(OpdMapper.getVRegs(1));
1391 SmallVector<Register, 2> Src1Regs(OpdMapper.getVRegs(2));
1437 Register DstReg = MI.getOperand(0).getReg();
1462 Register DstReg = MI.getOperand(0).getReg();
1495 Register SrcReg = MI.getOperand(1).getReg();
1502 Register DstReg = MI.getOperand(0).getReg();
1513 SmallVector<Register, 2> DefRegs(OpdMapper.getVRegs(0));
1538 SmallVector<Register, 2> DefRegs(OpdMapper.getVRegs(0));
1593 Register DstReg = MI.getOperand(0).getReg();
1608 Register Lo = MI.getOperand(1).getReg();
1609 Register Hi = MI.getOperand(2).getReg();
1615 Register ZextLo;
1616 Register ShiftHi;
1622 Register ZextHi = B.buildZExt(S32, Hi).getReg(0);
1631 Register MaskLo = B.buildConstant(S32, 0xffff).getReg(0);
1652 SmallVector<Register, 2> DstRegs(OpdMapper.getVRegs(0));
1662 Register DstReg = MI.getOperand(0).getReg();
1663 Register SrcReg = MI.getOperand(1).getReg();
1664 Register IdxReg = MI.getOperand(2).getReg();
1701 SmallSet<Register, 4> OpsToWaterfall;
1716 SmallVector<Register, 2> InsRegs(OpdMapper.getVRegs(2));
1728 Register DstReg = MI.getOperand(0).getReg();
1729 Register SrcReg = MI.getOperand(1).getReg();
1730 Register InsReg = MI.getOperand(2).getReg();
1731 Register IdxReg = MI.getOperand(3).getReg();
1772 SmallSet<Register, 4> OpsToWaterfall;
1909 Register Reg = MI.getOperand(i).getReg();
1949 Register Reg1 = MI.getOperand(OpdIdx).getReg();
2008 Register OpReg = MI.getOperand(I).getReg();
2038 Register PtrReg = MI.getOperand(1).getReg();
2071 AMDGPURegisterBankInfo::getRegBankID(Register Reg,
2087 AMDGPURegisterBankInfo::getSGPROpMapping(Register Reg,
2098 AMDGPURegisterBankInfo::getVGPROpMapping(Register Reg,
2147 Register Reg = MI.getOperand(I).getReg();
2414 Register Dst = MI.getOperand(0).getReg();
2415 Register Src = MI.getOperand(1).getReg();
2426 Register Dst = MI.getOperand(0).getReg();
2427 Register Src = MI.getOperand(1).getReg();
2630 Register RSrc = MI.getOperand(2).getReg(); // SGPR
2631 Register Offset = MI.getOperand(3).getReg(); // SGPR/imm
2665 Register Src0Reg = MI.getOperand(2).getReg();
2666 Register Src1Reg = MI.getOperand(3).getReg();
2691 Register IdxReg = MI.getOperand(3).getReg();
2706 Register SrcReg = MI.getOperand(2).getReg();
2709 Register IdxReg = MI.getOperand(3).getReg();
2780 Register RSrc = MI.getOperand(2).getReg(); // SGPR
2781 Register VIndex = MI.getOperand(3).getReg(); // VGPR
2782 Register Offset = MI.getOperand(4).getReg(); // SGPR/VGPR/imm
lib/Target/AMDGPU/AMDGPURegisterBankInfo.h 48 SmallSet<Register, 4> &SGPROperandRegs,
77 Register handleD16VData(MachineIRBuilder &B, MachineRegisterInfo &MRI,
78 Register Reg) const;
80 std::pair<Register, unsigned>
81 splitBufferOffsets(MachineIRBuilder &B, Register Offset) const;
92 unsigned getRegBankID(Register Reg, const MachineRegisterInfo &MRI,
97 const ValueMapping *getSGPROpMapping(Register Reg,
102 const ValueMapping *getVGPROpMapping(Register Reg,
109 SmallVector<Register, 2> &Regs,
111 Register Reg) const;
lib/Target/AMDGPU/AMDGPURegisterInfo.cpp 128 Register SIRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
lib/Target/AMDGPU/AMDILCFGStructurizer.cpp 1310 Register CmpResReg =
1319 Register InitReg =
lib/Target/AMDGPU/GCNDPPCombine.cpp 356 auto DPPMovReg = DstOpnd->getReg();
459 Register FwdReg = OrigMI.getOperand(0).getReg();
lib/Target/AMDGPU/GCNHazardRecognizer.cpp 729 Register Reg = Def.getReg();
795 Register LaneSelectReg = LaneSelectOp->getReg();
894 Register Reg = Src0->getReg();
980 const Register SDSTReg = SDST->getReg();
1255 Register Reg = Op.getReg();
1262 Register DstReg = MI->getOperand(0).getReg();
1308 Register DstReg = MI->getOperand(0).getReg();
1334 Register DstReg = MI->getOperand(0).getReg();
1341 Register Reg = TII.getNamedOperand(*MI, AMDGPU::OpName::src2)->getReg();
1380 Register Reg = Op.getReg();
lib/Target/AMDGPU/GCNNSAReassign.cpp 176 Register Reg = Op.getReg();
177 if (Register::isPhysicalRegister(Reg) || !VRM->isAssignedReg(Reg))
180 Register PhysReg = VRM->getPhys(Reg);
279 Register Reg = Op.getReg();
lib/Target/AMDGPU/GCNRegBankReassign.cpp 233 if (Register::isPhysicalRegister(Reg)) {
296 if (Register::isVirtualRegister(Reg)) {
367 Register R = Op.getReg();
423 if (Register::isPhysicalRegister(Reg) || !VRM->isAssignedReg(Reg))
428 Register PhysReg = VRM->getPhys(Reg);
657 Register OrigReg = VRM->getPhys(C.Reg);
lib/Target/AMDGPU/GCNRegPressure.cpp 43 const unsigned Reg = Register::index2VirtReg(I);
234 if (!MO.isReg() || !Register::isVirtualRegister(MO.getReg()))
241 auto Reg = MO.getReg();
280 auto Reg = Register::index2VirtReg(I);
331 if (!MO.isReg() || !Register::isVirtualRegister(MO.getReg()) || MO.isDead())
334 auto Reg = MO.getReg();
409 Register Reg = MO.getReg();
410 if (!Register::isVirtualRegister(Reg))
501 unsigned Reg = Register::index2VirtReg(I);
lib/Target/AMDGPU/GCNRegPressure.h 217 auto Reg = Register::index2VirtReg(I);
lib/Target/AMDGPU/R600ControlFlowFinalizer.cpp 306 Register Reg = MO.getReg();
315 Register Reg = MO.getReg();
lib/Target/AMDGPU/R600ExpandSpecialInstrs.cpp 138 Register DstReg = MI.getOperand(0).getReg();
158 Register Src0 =
161 Register Src1 =
208 Register DstReg =
210 Register Src0 =
lib/Target/AMDGPU/R600ISelLowering.cpp 338 Register maskedRegister = MI.getOperand(0).getReg();
lib/Target/AMDGPU/R600InstrInfo.cpp 100 if (I->isReg() && !Register::isVirtualRegister(I->getReg()) && I->isUse() &&
245 if (!I->isReg() || !I->isUse() || Register::isVirtualRegister(I->getReg()))
296 Register Reg = MO.getReg();
319 Register Reg = MO.getReg();
350 Register Reg = Src.first->getReg();
867 Register Reg = MI.getOperand(idx).getReg();
1040 Register OffsetReg = MI.getOperand(OffsetOpIdx).getReg();
1054 Register OffsetReg = MI.getOperand(OffsetOpIdx).getReg();
1195 if (Register::isVirtualRegister(Reg) || !IndirectRC->contains(Reg))
lib/Target/AMDGPU/R600MachineScheduler.cpp 186 return !Register::isVirtualRegister(MI->getOperand(1).getReg());
212 if (!Register::isVirtualRegister(Reg)) {
273 Register DestReg = MI->getOperand(0).getReg();
360 Register DestReg = MI->getOperand(DstIndex).getReg();
lib/Target/AMDGPU/R600OptimizeVectorRegisters.cpp 61 if (Register::isPhysicalRegister(Reg))
200 Register Reg = RSI->Instr->getOperand(0).getReg();
205 Register SrcVec = BaseRSI->Instr->getOperand(0).getReg();
210 Register DstReg = MRI->createVirtualRegister(&R600::R600_Reg128RegClass);
353 Register Reg = MI.getOperand(1).getReg();
366 Register Reg = MI.getOperand(0).getReg();
lib/Target/AMDGPU/R600Packetizer.cpp 93 Register Dst = BI->getOperand(DstIdx).getReg();
139 Register Src = MI.getOperand(OperandIdx).getReg();
189 Register PredI = (OpI > -1)?MII->getOperand(OpI).getReg() : Register(),
lib/Target/AMDGPU/R600RegisterInfo.cpp 70 Register R600RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
lib/Target/AMDGPU/R600RegisterInfo.h 29 Register getFrameRegister(const MachineFunction &MF) const override;
lib/Target/AMDGPU/SIAddIMGInit.cpp 132 Register PrevDst =
153 Register SubReg =
lib/Target/AMDGPU/SIFixSGPRCopies.cpp 157 !Register::isVirtualRegister(MI.getOperand(i).getReg()))
170 Register DstReg = Copy.getOperand(0).getReg();
171 Register SrcReg = Copy.getOperand(1).getReg();
173 const TargetRegisterClass *SrcRC = Register::isVirtualRegister(SrcReg)
180 const TargetRegisterClass *DstRC = Register::isVirtualRegister(DstReg)
206 Register DstReg = MI.getOperand(0).getReg();
207 Register SrcReg = Src.getReg();
208 if (!Register::isVirtualRegister(SrcReg) ||
209 !Register::isVirtualRegister(DstReg))
245 Register DstReg = MI.getOperand(0).getReg();
257 if (Register::isPhysicalRegister(CopyUse.getOperand(0).getReg()))
288 Register SrcReg = MI.getOperand(I).getReg();
298 Register TmpReg = MRI.createVirtualRegister(NewSrcRC);
306 Register TmpAReg = MRI.createVirtualRegister(NewSrcRC);
611 Register DstReg = MI.getOperand(0).getReg();
616 if (!Register::isVirtualRegister(DstReg)) {
622 Register TmpReg
635 Register SrcReg = MI.getOperand(1).getReg();
636 if (!Register::isVirtualRegister(SrcReg)) {
718 if (Register::isVirtualRegister(MO->getReg())) {
802 Register PHIRes = MI.getOperand(0).getReg();
lib/Target/AMDGPU/SIFixupVectorISel.cpp 94 if (!WOp->isReg() || !Register::isVirtualRegister(WOp->getReg()))
lib/Target/AMDGPU/SIFoldOperands.cpp 258 Register NewReg0 = MRI.createVirtualRegister(Dst0RC);
450 Register UseReg, uint8_t OpTy,
505 Register UseReg = OpToFold.getReg();
506 if (!Register::isVirtualRegister(UseReg))
562 Register RegSeqDstReg = UseMI->getOperand(0).getReg();
613 Register DestReg = UseMI->getOperand(0).getReg();
623 Register SrcReg = UseMI->getOperand(1).getReg();
675 Register UseReg = OpToFold.getReg();
698 DenseMap<TargetInstrInfo::RegSubRegPair, Register> VGPRCopies;
707 auto Tmp = MRI->createVirtualRegister(&AMDGPU::AGPR_32RegClass);
734 auto Tmp = MRI->createVirtualRegister(&AMDGPU::AGPR_32RegClass);
741 Register Vgpr;
749 auto Tmp = MRI->createVirtualRegister(&AMDGPU::AGPR_32RegClass);
846 Register UseReg = UseOp.getReg();
948 !Register::isVirtualRegister(Op.getReg()))
1211 if (Fold.isReg() && Register::isVirtualRegister(Fold.OpToFold->getReg())) {
1212 Register Reg = Fold.OpToFold->getReg();
1506 if (OpToFold.isReg() && !Register::isVirtualRegister(OpToFold.getReg()))
1516 if (Dst.isReg() && !Register::isVirtualRegister(Dst.getReg()))
lib/Target/AMDGPU/SIFormMemoryClauses.cpp 123 Register ResReg = ResMO.getReg();
147 if (Register::isPhysicalRegister(MO.getReg()) && MO.isRenamable())
155 if (LaneMask.all() || Register::isPhysicalRegister(Reg) ||
219 Register Reg = MO.getReg();
230 if (Register::isPhysicalRegister(Reg))
268 Register Reg = MO.getReg();
272 LaneBitmask Mask = Register::isVirtualRegister(Reg)
392 if (Register::isPhysicalRegister(Reg))
400 if (Register::isPhysicalRegister(Reg))
lib/Target/AMDGPU/SIFrameLowering.cpp 209 Register FlatScratchInitReg =
216 Register FlatScrInitLo = TRI->getSubReg(FlatScratchInitReg, AMDGPU::sub0);
217 Register FlatScrInitHi = TRI->getSubReg(FlatScratchInitReg, AMDGPU::sub1);
431 Register PreloadedScratchWaveOffsetReg = MFI->getPreloadedReg(
546 Register RsrcLo = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub0);
547 Register RsrcHi = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub1);
548 Register Rsrc01 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub0_sub1);
608 Register Rsrc2 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub2);
609 Register Rsrc3 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub3);
615 Register Rsrc01 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub0_sub1);
647 Register Rsrc0 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub0);
648 Register Rsrc1 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub1);
lib/Target/AMDGPU/SIISelLowering.cpp 1621 Register Reg = AMDGPU::VGPR0;
1629 Register Reg = AMDGPU::VGPR1;
1637 Register Reg = AMDGPU::VGPR2;
1669 Register LiveInVReg = MF.addLiveIn(Reg, &AMDGPU::VGPR_32RegClass);
1788 Register InputPtrReg = Info.addKernargSegmentPtr(TRI);
1791 Register VReg = MF.addLiveIn(InputPtrReg, &AMDGPU::SGPR_64RegClass);
1892 Register PrivateSegmentBufferReg =
1953 Register PreloadedSP = Info.getPreloadedReg(
2003 Register NewVR = MRI->createVirtualRegister(RC);
2166 Register Reg = VA.getLocReg();
2982 Register SITargetLowering::getRegisterByName(const char* RegName, EVT VT,
2984 Register Reg = StringSwitch<Register>(RegName)
3143 Register Reg = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
3184 Register PhiExec = MRI.createVirtualRegister(BoolRC);
3185 Register NewExec = MRI.createVirtualRegister(BoolRC);
3186 Register CurrentIdxReg = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
3187 Register CondReg = MRI.createVirtualRegister(BoolRC);
3286 Register DstReg = MI.getOperand(0).getReg();
3287 Register SaveExec = MRI.createVirtualRegister(BoolXExecRC);
3288 Register TmpExec = MRI.createVirtualRegister(BoolXExecRC);
3361 Register Tmp = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
3397 Register Dst = MI.getOperand(0).getReg();
3398 Register SrcReg = TII->getNamedOperand(MI, AMDGPU::OpName::src)->getReg();
3436 Register PhiReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
3437 Register InitReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
3488 Register Dst = MI.getOperand(0).getReg();
3551 Register PhiReg = MRI.createVirtualRegister(VecRC);
3610 Register DestSub0 = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
3611 Register DestSub1 = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
3678 Register InputReg = MI.getOperand(0).getReg();
3679 Register CountReg = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
3753 Register Dst = MI.getOperand(0).getReg();
3754 Register Src0 = MI.getOperand(1).getReg();
3755 Register Src1 = MI.getOperand(2).getReg();
3757 Register SrcCond = MI.getOperand(3).getReg();
3759 Register DstLo = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
3760 Register DstHi = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
3762 Register SrcCondCopy = MRI.createVirtualRegister(CondRC);
10256 Register::isPhysicalRegister(DestReg->getReg())) {
10409 !Register::isVirtualRegister(Op.getReg()) ||
10447 Register Def = MI.getOperand(0).getReg();
10837 if (Register::isPhysicalRegister(Reg))
lib/Target/AMDGPU/SIISelLowering.h 332 Register getRegisterByName(const char* RegName, EVT VT,
lib/Target/AMDGPU/SIInstrInfo.cpp 478 const Register Reg = FirstDst->getReg();
480 const TargetRegisterClass *DstRC = Register::isVirtualRegister(Reg)
827 Register SReg = MRI.createVirtualRegister(BoolXExecRC);
840 Register SReg = MRI.createVirtualRegister(BoolXExecRC);
854 Register SReg = MRI.createVirtualRegister(BoolXExecRC);
870 Register SReg = MRI.createVirtualRegister(BoolXExecRC);
884 Register SReg = MRI.createVirtualRegister(BoolXExecRC);
896 Register SReg = MRI.createVirtualRegister(BoolXExecRC);
897 Register SReg2 = MRI.createVirtualRegister(RI.getBoolRC());
914 Register SReg = MRI.createVirtualRegister(BoolXExecRC);
915 Register SReg2 = MRI.createVirtualRegister(RI.getBoolRC());
945 Register Reg = MRI.createVirtualRegister(RI.getBoolRC());
958 Register Reg = MRI.createVirtualRegister(RI.getBoolRC());
1072 if (Register::isVirtualRegister(SrcReg) && SpillSize == 4) {
1098 Register Tmp = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
1197 if (Register::isVirtualRegister(DestReg) && SpillSize == 4) {
1217 Register Tmp = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
1251 Register TIDIGXReg =
1253 Register TIDIGYReg =
1255 Register TIDIGZReg =
1257 Register InputPtrReg =
1419 Register Dst = MI.getOperand(0).getReg();
1420 Register DstLo = RI.getSubReg(Dst, AMDGPU::sub0);
1421 Register DstHi = RI.getSubReg(Dst, AMDGPU::sub1);
1482 Register VecReg = MI.getOperand(0).getReg();
1505 Register Reg = MI.getOperand(0).getReg();
1506 Register RegLo = RI.getSubReg(Reg, AMDGPU::sub0);
1507 Register RegHi = RI.getSubReg(Reg, AMDGPU::sub1);
1571 Register Dst = MI.getOperand(0).getReg();
1582 auto Tmp = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
1595 Register Src = SrcOp.getReg();
1645 Register Reg = RegOp.getReg();
1782 Register PCReg = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
2235 Register DstElt = MRI.createVirtualRegister(EltRC);
2399 Register Src1Reg = Src1->getReg();
2439 } else if ((Register::isPhysicalRegister(Src0->getReg()) &&
2442 (Register::isVirtualRegister(Src0->getReg()) &&
2457 } else if ((Register::isPhysicalRegister(Src1->getReg()) &&
2459 (Register::isVirtualRegister(Src1->getReg()) &&
3114 if (Register::isVirtualRegister(MO.getReg()))
3183 if (Register::isPhysicalRegister(SubReg.getReg()))
3223 Register Reg = Op.getReg();
3224 if (!Register::isVirtualRegister(Reg) && !RC->contains(Reg)) {
3288 Register Reg = MI.getOperand(i).getReg();
3289 if (Reg == AMDGPU::NoRegister || Register::isVirtualRegister(Reg))
3382 } else if (Register::isPhysicalRegister(TiedMO.getReg()) &&
3491 Register SGPRUsed = AMDGPU::NoRegister;
3813 Register Reg = MI.getOperand(OpNo).getReg();
3815 if (Register::isVirtualRegister(Reg))
3846 Register Reg = MRI.createVirtualRegister(VRC);
3861 Register SubReg = MRI.createVirtualRegister(SubRC);
3873 Register NewSuperReg = MRI.createVirtualRegister(SuperRC);
3919 Register Reg = MO.getReg();
3920 const TargetRegisterClass *RC = Register::isVirtualRegister(Reg)
4037 Register Reg = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
4043 Register Reg = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
4069 Register Reg = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
4105 Register Src0Reg = Src0.getReg();
4141 Register Reg = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
4147 Register Reg = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
4215 Register DstReg = MRI.createVirtualRegister(SRC);
4220 Register NewSrcReg = MRI.createVirtualRegister(VRC);
4236 Register SGPR = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
4278 Register OpReg = Op.getReg();
4288 Register DstReg = MRI.createVirtualRegister(DstRC);
4336 Register VRsrc = Rsrc.getReg();
4339 Register SaveExec = MRI.createVirtualRegister(BoolXExecRC);
4340 Register CondReg0 = MRI.createVirtualRegister(BoolXExecRC);
4341 Register CondReg1 = MRI.createVirtualRegister(BoolXExecRC);
4342 Register AndCond = MRI.createVirtualRegister(BoolXExecRC);
4343 Register SRsrcSub0 = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
4344 Register SRsrcSub1 = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
4345 Register SRsrcSub2 = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
4346 Register SRsrcSub3 = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
4347 Register SRsrc = MRI.createVirtualRegister(&AMDGPU::SGPR_128RegClass);
4415 Register SaveExec = MRI.createVirtualRegister(BoolXExecRC);
4483 Register Zero64 = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
4484 Register SRsrcFormatLo = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
4485 Register SRsrcFormatHi = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
4486 Register NewSRsrc = MRI.createVirtualRegister(&AMDGPU::SGPR_128RegClass);
4543 !Register::isVirtualRegister(MI.getOperand(i).getReg()))
4579 if (!Op.isReg() || !Register::isVirtualRegister(Op.getReg()))
4604 if (!Op.isReg() || !Register::isVirtualRegister(Op.getReg()))
4623 Register Dst = MI.getOperand(0).getReg();
4624 Register Src0 = MI.getOperand(1).getReg();
4698 Register NewVAddrLo = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
4699 Register NewVAddrHi = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
4700 Register NewVAddr = MRI.createVirtualRegister(&AMDGPU::VReg_64RegClass);
4703 Register CondReg0 = MRI.createVirtualRegister(BoolXExecRC);
4704 Register CondReg1 = MRI.createVirtualRegister(BoolXExecRC);
4744 Register NewVAddr = MRI.createVirtualRegister(&AMDGPU::VReg_64RegClass);
5056 Register DstReg = Inst.getOperand(0).getReg();
5057 if (Register::isPhysicalRegister(DstReg))
5066 Register::isVirtualRegister(Inst.getOperand(1).getReg()) &&
5111 Register OldDstReg = Inst.getOperand(0).getReg();
5112 Register ResultReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
5145 Register TmpReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
5146 Register ResultReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
5175 Register NewDest = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
5195 Register Temp = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
5196 Register NewDest = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
5240 Register NewDest = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
5241 Register Interm = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
5269 Register NewDest = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
5270 Register Interm = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
5312 Register DestSub0 = MRI.createVirtualRegister(NewDestSubRC);
5318 Register DestSub1 = MRI.createVirtualRegister(NewDestSubRC);
5321 Register FullDestReg = MRI.createVirtualRegister(NewDestRC);
5349 Register FullDestReg = MRI.createVirtualRegister(&AMDGPU::VReg_64RegClass);
5350 Register DestSub0 = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
5351 Register DestSub1 = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
5353 Register CarryReg = MRI.createVirtualRegister(CarryRC);
5354 Register DeadCarryReg = MRI.createVirtualRegister(CarryRC);
5450 Register DestSub0 = MRI.createVirtualRegister(NewDestSubRC);
5455 Register DestSub1 = MRI.createVirtualRegister(NewDestSubRC);
5460 Register FullDestReg = MRI.createVirtualRegister(NewDestRC);
5491 Register Interm = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
5507 Register NewDest = MRI.createVirtualRegister(DestRC);
5534 Register MidReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
5535 Register ResultReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
5574 Register MidRegLo = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
5575 Register MidRegHi = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
5576 Register ResultReg = MRI.createVirtualRegister(&AMDGPU::VReg_64RegClass);
5599 Register TmpReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
5600 Register ResultReg = MRI.createVirtualRegister(&AMDGPU::VReg_64RegClass);
5655 Register ResultReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
5663 Register ImmReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
5664 Register TmpReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
5682 Register ImmReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
5692 Register ImmReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
5693 Register TmpReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
5820 Register Reg = MO.getReg();
6075 Register DstReg = MRI.createVirtualRegister(RI.getBoolRC());
6102 Register DstReg = MRI.createVirtualRegister(RI.getBoolRC());
6103 Register BackEdgeReg = MRI.createVirtualRegister(RI.getBoolRC());
6113 Register ZeroReg = MRI.createVirtualRegister(RI.getBoolRC());
6197 Register UnusedCarry = MRI.createVirtualRegister(RI.getBoolRC());
6212 Register UnusedCarry = RS.scavengeRegister(RI.getBoolRC(), I, 0, false);
6419 if (!Register::isVirtualRegister(P.Reg))
6430 if (Op1.isReg() && Register::isVirtualRegister(Op1.getReg())) {
6452 Register VReg,
6485 Register VReg,
lib/Target/AMDGPU/SIInstrInfo.h 1064 Register VReg,
1072 Register VReg,
lib/Target/AMDGPU/SILoadStoreOptimizer.cpp 173 if (Register::isPhysicalRegister(AddrOp->getReg()))
566 else if (Op.readsReg() && Register::isPhysicalRegister(Op.getReg()))
598 (Use.isDef() && Register::isPhysicalRegister(Use.getReg()) &&
903 Register DestReg = MRI->createVirtualRegister(SuperRC);
907 Register BaseReg = AddrReg->getReg();
911 Register ImmReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass);
1000 Register BaseReg = AddrReg->getReg();
1004 Register ImmReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass);
1045 Register DestReg = MRI->createVirtualRegister(SuperRC);
1099 Register DestReg = MRI->createVirtualRegister(SuperRC);
1151 Register DestReg = MRI->createVirtualRegister(SuperRC);
1308 Register SrcReg = MRI->createVirtualRegister(SuperRC);
1360 Register Reg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass);
1391 Register CarryReg = MRI->createVirtualRegister(CarryRC);
1392 Register DeadCarryReg = MRI->createVirtualRegister(CarryRC);
1394 Register DestSub0 = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass);
1395 Register DestSub1 = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass);
1415 Register FullDestReg = MRI->createVirtualRegister(&AMDGPU::VReg_64RegClass);
lib/Target/AMDGPU/SILowerControlFlow.cpp 101 Register getSaveExec(MachineInstr* MI);
149 Register SaveExecReg = MI.getOperand(0).getReg();
180 Register SILowerControlFlow::getSaveExec(MachineInstr *MI) {
185 Register SaveExecReg = SaveExec.getReg();
202 Register SaveExecReg = getSaveExec(&MI);
216 Register CopyReg = SimpleIf ? SaveExecReg
223 Register Tmp = MRI->createVirtualRegister(BoolRC);
285 Register DstReg = getSaveExec(&MI);
293 Register CopyReg = MRI->createVirtualRegister(BoolRC);
300 Register SaveReg = ExecModified ?
357 auto Dst = getSaveExec(&MI);
444 if (!Op.isReg() || !Register::isVirtualRegister(Op.getReg())) {
464 (Register::isVirtualRegister(SrcOp.getReg()) || SrcOp.getReg() == Exec))
487 Register Reg = MI.getOperand(OpToReplace).getReg();
lib/Target/AMDGPU/SILowerI1Copies.cpp 99 return Register::isVirtualRegister(Reg) &&
495 Register Reg) {
509 Register DstReg = MI.getOperand(0).getReg();
510 Register SrcReg = MI.getOperand(1).getReg();
569 Register DstReg = MI->getOperand(0).getReg();
576 Register IncomingReg = MI->getOperand(i).getReg();
680 Register DstReg = MI.getOperand(0).getReg();
697 Register SrcReg = MI.getOperand(1).getReg();
700 if (!Register::isVirtualRegister(SrcReg) ||
745 if (!Register::isVirtualRegister(Reg))
lib/Target/AMDGPU/SILowerSGPRSpills.cpp 281 Register VReg =
lib/Target/AMDGPU/SIMachineFunctionInfo.h 667 Register getPreloadedReg(AMDGPUFunctionArgInfo::PreloadedValue Value) const {
lib/Target/AMDGPU/SIMachineScheduler.cpp 351 if (Register::isVirtualRegister(RegMaskPair.RegUnit))
379 if (Register::isVirtualRegister(Reg) &&
1693 if (!Register::isVirtualRegister(Reg))
1753 if (!Register::isVirtualRegister(Reg))
1765 if (!Register::isVirtualRegister(Reg))
1916 if (!Register::isVirtualRegister(Reg))
lib/Target/AMDGPU/SIOptimizeExecMasking.cpp 325 Register CopyFromExec = CopyFromExecInst->getOperand(0).getReg();
lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp 214 Register CmpReg = AndCC->getReg();
237 Register SelReg = Op1->getReg();
256 Register CCReg = CC->getReg();
270 if ((Register::isVirtualRegister(CmpReg) && MRI.use_nodbg_empty(CmpReg)) ||
282 if (Register::isVirtualRegister(SelReg) && MRI.use_nodbg_empty(SelReg)) {
416 Register SavedExec = SaveExec->getOperand(0).getReg();
437 if (Register::isVirtualRegister(Reg)) {
lib/Target/AMDGPU/SIPeepholeSDWA.cpp 577 if (Register::isPhysicalRegister(Src1->getReg()) ||
578 Register::isPhysicalRegister(Dst->getReg()))
616 if (Register::isPhysicalRegister(Src1->getReg()) ||
617 Register::isPhysicalRegister(Dst->getReg()))
680 if (Register::isPhysicalRegister(Src0->getReg()) ||
681 Register::isPhysicalRegister(Dst->getReg()))
709 if (Register::isPhysicalRegister(ValSrc->getReg()) ||
710 Register::isPhysicalRegister(Dst->getReg()))
1192 Register VGPR = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass);
lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp 93 Register Reg = MO.getReg();
98 if (Register::isPhysicalRegister(Reg))
127 const Register VirtReg = MO.getReg();
128 if (Register::isPhysicalRegister(VirtReg))
134 Register PhysReg = VRM->getPhys(VirtReg);
152 const Register PhysReg = VRM->getPhys(Reg);
lib/Target/AMDGPU/SIRegisterInfo.cpp 362 Register OffsetReg = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
364 Register FIReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
646 Register TmpReg =
687 Register SubReg = NumSubRegs == 1
762 Register SuperReg = MI->getOperand(0).getReg();
784 Register TmpVGPR;
789 Register SubReg =
881 Register SuperReg = MI->getOperand(0).getReg();
894 Register TmpVGPR;
897 Register SubReg =
998 Register FrameReg = getFrameRegister(*MF);
1099 Register TmpDiffReg =
1103 Register DiffReg = TmpDiffReg.isValid() ? TmpDiffReg : FrameReg;
1106 Register ResultReg = IsCopy ?
1122 Register ScaledReg =
1140 Register ConstOffsetReg =
1160 Register TmpScaledReg =
1162 Register ScaledReg = TmpScaledReg.isValid() ? TmpScaledReg : DiffReg;
1229 Register TmpReg = RS->scavengeRegister(&AMDGPU::VGPR_32RegClass, MI, 0);
1692 if (Register::isVirtualRegister(Reg))
1872 if (Register::isVirtualRegister(Reg)) {
lib/Target/AMDGPU/SIRegisterInfo.h 71 Register getFrameRegister(const MachineFunction &MF) const override;
140 if (Register::isVirtualRegister(Reg))
lib/Target/AMDGPU/SIShrinkInstructions.cpp 80 Register Reg = Src0.getReg();
81 if (Register::isVirtualRegister(Reg) && MRI.hasOneUse(Reg)) {
363 if (Register::isVirtualRegister(Dest->getReg()) && SrcReg->isReg()) {
396 if (Register::isPhysicalRegister(Reg) &&
397 Register::isPhysicalRegister(MO.getReg())) {
400 } else if (MO.getReg() == Reg && Register::isVirtualRegister(Reg)) {
426 if (Register::isPhysicalRegister(Reg)) {
460 Register T = MovT.getOperand(0).getReg();
466 Register X = Xop.getReg();
485 Register Y = MovY.getOperand(0).getReg();
580 Register::isPhysicalRegister(MI.getOperand(0).getReg())) {
644 if (Register::isVirtualRegister(Dest->getReg()) && Src0->isReg()) {
672 if (Src.isImm() && Register::isPhysicalRegister(Dst.getReg())) {
720 Register DstReg = MI.getOperand(0).getReg();
721 if (Register::isVirtualRegister(DstReg)) {
744 Register SReg = Src2->getReg();
745 if (Register::isVirtualRegister(SReg)) {
765 if (Register::isVirtualRegister(SDst->getReg()))
773 if (Register::isVirtualRegister(Src2->getReg()))
lib/Target/AMDGPU/SIWholeQuadMode.cpp 276 Register Reg = Use.getReg();
281 if (!Register::isVirtualRegister(Reg)) {
364 Register Reg = Inactive.getReg();
365 if (Register::isVirtualRegister(Reg)) {
393 Register Reg = MO.getReg();
395 if (!Register::isVirtualRegister(Reg) &&
559 Register SaveReg = MRI->createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
843 Register Dest = MI->getOperand(0).getReg();
858 const Register Reg = MI->getOperand(0).getReg();
861 const TargetRegisterClass *regClass = Register::isVirtualRegister(Reg)
lib/Target/ARC/ARCISelLowering.cpp 719 Register FrameReg = ARI.getFrameRegister(MF);
lib/Target/ARC/ARCOptAddrMode.cpp 183 Register R = Add->getOperand(0).getReg();
207 Register B = Base.getReg();
208 if (Register::isStackSlot(B) || !Register::isVirtualRegister(B)) {
208 if (Register::isStackSlot(B) || !Register::isVirtualRegister(B)) {
286 Register BaseReg = Ldst->getOperand(BasePos).getReg();
295 Register StReg = Ldst->getOperand(0).getReg();
425 Register ValReg = IsLoad ? Ldst->getOperand(0).getReg() : Register();
448 Register BaseReg = Ldst.getOperand(BasePos).getReg();
lib/Target/ARC/ARCRegisterInfo.cpp 193 Register FrameReg = getFrameRegister(MF);
209 Register Reg = MI.getOperand(0).getReg();
226 Register ARCRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
lib/Target/ARC/ARCRegisterInfo.h 49 Register getFrameRegister(const MachineFunction &MF) const override;
lib/Target/ARM/A15SDOptimizer.cpp 136 Register Reg = MO.getReg();
138 if (Register::isVirtualRegister(Reg))
154 if (!Register::isVirtualRegister(SReg))
169 if (Register::isVirtualRegister(SReg)) {
194 Register Reg = MO.getReg();
195 if (!Register::isVirtualRegister(Reg))
216 Register DefReg = MODef.getReg();
217 if (!Register::isVirtualRegister(DefReg)) {
248 Register DPRReg = MI->getOperand(1).getReg();
249 Register SPRReg = MI->getOperand(2).getReg();
251 if (Register::isVirtualRegister(DPRReg) && Register::isVirtualRegister(SPRReg)) {
251 if (Register::isVirtualRegister(DPRReg) && Register::isVirtualRegister(SPRReg)) {
270 Register FullReg = SPRMI->getOperand(1).getReg();
299 Register OpReg = MI->getOperand(I).getReg();
301 if (!Register::isVirtualRegister(OpReg))
345 if (!Register::isVirtualRegister(MI->getOperand(1).getReg()))
372 Register Reg = MI->getOperand(I).getReg();
373 if (!Register::isVirtualRegister(Reg)) {
382 if (!Register::isVirtualRegister(MI->getOperand(1).getReg()))
421 Register Out =
437 Register Out = MRI->createVirtualRegister(TRC);
451 Register Out = MRI->createVirtualRegister(&ARM::QPRRegClass);
469 Register Out = MRI->createVirtualRegister(&ARM::DPRRegClass);
481 Register Out = MRI->createVirtualRegister(&ARM::DPR_VFP2RegClass);
497 Register Out = MRI->createVirtualRegister(&ARM::DPRRegClass);
605 if (!Register::isVirtualRegister(*I))
625 Register DPRDefReg = MI->getOperand(0).getReg();
lib/Target/ARM/ARMAsmPrinter.cpp 206 Register Reg = MO.getReg();
278 Register Reg = MI->getOperand(OpNum).getReg();
305 Register RegBegin = MO.getReg();
312 Register Reg0 = TRI->getSubReg(RegBegin, ARM::gsub_0);
381 Register Reg =
394 Register Reg = MO.getReg();
403 Register Reg = MI->getOperand(OpNum).getReg();
407 Register SubReg =
422 Register Reg = MO.getReg();
1075 Register FramePtr = TargetRegInfo->getFrameRegister(MF);
1139 Register Reg = MO.getReg();
1329 Register TReg = MI->getOperand(0).getReg();
1666 Register Base = MI->getOperand(0).getReg();
1667 Register Idx = MI->getOperand(1).getReg();
1847 Register SrcReg = MI->getOperand(0).getReg();
1848 Register ValReg = MI->getOperand(1).getReg();
1913 Register SrcReg = MI->getOperand(0).getReg();
1914 Register ValReg = MI->getOperand(1).getReg();
1970 Register SrcReg = MI->getOperand(0).getReg();
1971 Register ScratchReg = MI->getOperand(1).getReg();
2030 Register SrcReg = MI->getOperand(0).getReg();
2031 Register ScratchReg = MI->getOperand(1).getReg();
2098 Register SrcReg = MI->getOperand(0).getReg();
lib/Target/ARM/ARMBaseInstrInfo.cpp 175 Register WBReg = WB.getReg();
176 Register BaseReg = Base.getReg();
177 Register OffReg = Offset.getReg();
279 if (MO.isReg() && Register::isVirtualRegister(MO.getReg())) {
280 Register Reg = MO.getReg();
969 Register Dst = TRI->getSubReg(DestReg, BeginIdx + i * Spacing);
970 Register Src = TRI->getSubReg(SrcReg, BeginIdx + i * Spacing);
1022 if (Register::isPhysicalRegister(Reg))
1342 if (Register::isPhysicalRegister(DestReg))
1388 if (Register::isPhysicalRegister(DestReg))
1412 if (Register::isPhysicalRegister(DestReg))
1432 if (Register::isPhysicalRegister(DestReg))
1590 Register DstRegS = MI.getOperand(0).getReg();
1591 Register SrcRegS = MI.getOperand(1).getReg();
1801 Register Addr0 = MI0.getOperand(1).getReg();
1802 Register Addr1 = MI1.getOperand(1).getReg();
1804 if (!MRI || !Register::isVirtualRegister(Addr0) ||
1805 !Register::isVirtualRegister(Addr1))
2179 if (!Register::isVirtualRegister(Reg))
2201 if (Register::isPhysicalRegister(MO.getReg()))
2249 Register DestReg = MI.getOperand(0).getReg();
3315 Register Reg1 = UseMI.getOperand(OpIdx).getReg();
3317 Register NewReg = MRI->createVirtualRegister(MRI->getRegClass(Reg));
3379 Register Rt = MI.getOperand(0).getReg();
3380 Register Rm = MI.getOperand(3).getReg();
3386 Register Rt = MI.getOperand(0).getReg();
3387 Register Rm = MI.getOperand(3).getReg();
3416 Register Rt = MI.getOperand(0).getReg();
3417 Register Rm = MI.getOperand(3).getReg();
3428 Register Rt = MI.getOperand(0).getReg();
3429 Register Rm = MI.getOperand(3).getReg();
3448 Register Rm = MI.getOperand(3).getReg();
3451 Register Rt = MI.getOperand(0).getReg();
3466 Register Rt = MI.getOperand(0).getReg();
3467 Register Rn = MI.getOperand(2).getReg();
3468 Register Rm = MI.getOperand(3).getReg();
3476 Register Rm = MI.getOperand(3).getReg();
3492 Register Rt = MI.getOperand(0).getReg();
3493 Register Rn = MI.getOperand(3).getReg();
3494 Register Rm = MI.getOperand(4).getReg();
3502 Register Rt = MI.getOperand(0).getReg();
3503 Register Rn = MI.getOperand(3).getReg();
3508 Register Rm = MI.getOperand(4).getReg();
3539 Register Rt = MI.getOperand(0).getReg();
3540 Register Rn = MI.getOperand(2).getReg();
3789 Register BaseReg = MI.getOperand(0).getReg();
4263 Register Reg = DefMO.getReg();
4752 Register Reg = MI.getOperand(i).getReg();
4775 Register Reg = MI->getOperand(0).getReg();
5148 Register Reg = MO.getReg();
5178 if (Register::isVirtualRegister(Reg)) {
5203 Register Reg = MO.getReg();
5381 Register Reg = CmpMI->getOperand(0).getReg();
lib/Target/ARM/ARMBaseRegisterInfo.cpp 331 if (Register::isPhysicalRegister(Paired)) {
361 Register::isVirtualRegister(Hint.second)) {
371 if (Register::isVirtualRegister(NewReg))
446 Register
811 Register PredReg = (PIdx == -1) ? Register() : MI.getOperand(PIdx+1).getReg();
818 (Register::isVirtualRegister(FrameReg) || RegClass->contains(FrameReg)))
lib/Target/ARM/ARMBaseRegisterInfo.h 179 Register getFrameRegister(const MachineFunction &MF) const override;
lib/Target/ARM/ARMCallLowering.cpp 95 Register getStackAddress(uint64_t Size, int64_t Offset,
102 Register SPReg = MRI.createGenericVirtualRegister(p0);
105 Register OffsetReg = MRI.createGenericVirtualRegister(s32);
108 Register AddrReg = MRI.createGenericVirtualRegister(p0);
115 void assignValueToReg(Register ValVReg, Register PhysReg,
115 void assignValueToReg(Register ValVReg, Register PhysReg,
123 Register ExtReg = extendRegister(ValVReg, VA);
128 void assignValueToAddress(Register ValVReg, Register Addr, uint64_t Size,
128 void assignValueToAddress(Register ValVReg, Register Addr, uint64_t Size,
133 Register ExtReg = extendRegister(ValVReg, VA);
158 Register NewRegs[] = {MRI.createGenericVirtualRegister(LLT::scalar(32)),
230 Register PartReg = OrigArg.Regs[i];
238 const Value *Val, ArrayRef<Register> VRegs,
267 ArrayRef<Register> VRegs) const {
292 Register getStackAddress(uint64_t Size, int64_t Offset,
302 Register AddrReg =
309 void assignValueToAddress(Register ValVReg, Register Addr, uint64_t Size,
309 void assignValueToAddress(Register ValVReg, Register Addr, uint64_t Size,
321 auto LoadVReg = MRI.createGenericVirtualRegister(LLT::scalar(32));
330 void buildLoad(Register Val, Register Addr, uint64_t Size, unsigned Alignment,
330 void buildLoad(Register Val, Register Addr, uint64_t Size, unsigned Alignment,
337 void assignValueToReg(Register ValVReg, Register PhysReg,
337 void assignValueToReg(Register ValVReg, Register PhysReg,
357 auto PhysRegToVReg =
382 Register NewRegs[] = {MRI.createGenericVirtualRegister(LLT::scalar(32)),
418 ArrayRef<ArrayRef<Register>> VRegs) const {
531 auto CalleeReg = Info.Callee.getReg();
532 if (CalleeReg && !Register::isPhysicalRegister(CalleeReg)) {
lib/Target/ARM/ARMCallLowering.h 36 ArrayRef<Register> VRegs) const override;
39 ArrayRef<ArrayRef<Register>> VRegs) const override;
46 ArrayRef<Register> VRegs,
lib/Target/ARM/ARMConstantIslandPass.cpp 1661 Register CCReg = MI->getOperand(2).getReg();
1954 Register Reg = Cmp.MI->getOperand(0).getReg();
2047 Register EntryReg = JumpMI->getOperand(0).getReg();
2048 Register BaseReg = LEAMI->getOperand(0).getReg();
2125 Register EntryReg = JumpMI->getOperand(0).getReg();
2222 Register BaseReg = User.MI->getOperand(0).getReg();
2232 Register ShiftedIdxReg = Shift->getOperand(0).getReg();
lib/Target/ARM/ARMExpandPseudoInsts.cpp 484 Register DstReg = MI.getOperand(OpIdx++).getReg();
495 Register SubReg = TRI->getSubReg(DstReg, SubRegIndex);
627 Register SrcReg = MI.getOperand(OpIdx++).getReg();
763 Register SrcReg = MI.getOperand(OpIdx++).getReg();
832 Register DstReg = MI.getOperand(0).getReg();
936 Register TempReg = MI.getOperand(1).getReg();
940 Register AddrReg = MI.getOperand(2).getReg();
941 Register DesiredReg = MI.getOperand(3).getReg();
942 Register NewReg = MI.getOperand(4).getReg();
1039 Register RegLo = TRI->getSubReg(Reg.getReg(), ARM::gsub_0);
1040 Register RegHi = TRI->getSubReg(Reg.getReg(), ARM::gsub_1);
1055 Register TempReg = MI.getOperand(1).getReg();
1059 Register AddrReg = MI.getOperand(2).getReg();
1060 Register DesiredReg = MI.getOperand(3).getReg();
1064 Register DestLo = TRI->getSubReg(Dest.getReg(), ARM::gsub_0);
1065 Register DestHi = TRI->getSubReg(Dest.getReg(), ARM::gsub_1);
1066 Register DesiredLo = TRI->getSubReg(DesiredReg, ARM::gsub_0);
1067 Register DesiredHi = TRI->getSubReg(DesiredReg, ARM::gsub_1);
1343 Register FramePtr = RI.getFrameRegister(MF);
1419 Register Reg = MI.getOperand(0).getReg();
1450 Register DstReg = MI.getOperand(0).getReg();
1472 Register DstReg = MI.getOperand(0).getReg();
1530 Register DstReg = MI.getOperand(0).getReg();
1594 Register DstReg = MI.getOperand(OpIdx++).getReg();
1604 Register D0 = TRI->getSubReg(DstReg, ARM::dsub_0);
1605 Register D1 = TRI->getSubReg(DstReg, ARM::dsub_1);
1625 Register SrcReg = MI.getOperand(OpIdx++).getReg();
1636 Register D0 = TRI->getSubReg(SrcReg, ARM::dsub_0);
1637 Register D1 = TRI->getSubReg(SrcReg, ARM::dsub_1);
1927 Register Reg = MI.getOperand(0).getReg();
lib/Target/ARM/ARMFastISel.cpp 195 bool ARMEmitLoad(MVT VT, Register &ResultReg, Address &Addr,
222 SmallVectorImpl<Register> &ArgRegs,
225 SmallVectorImpl<Register> &RegArgs,
230 bool FinishCall(MVT RetVT, SmallVectorImpl<Register> &UsedRegs,
304 Register ResultReg = createResultReg(RC);
916 bool ARMFastISel::ARMEmitLoad(MVT VT, Register &ResultReg, Address &Addr,
1048 Register ResultReg;
1888 SmallVectorImpl<Register> &ArgRegs,
1891 SmallVectorImpl<Register> &RegArgs,
1955 Register Arg = ArgRegs[VA.getValNo()];
2034 bool ARMFastISel::FinishCall(MVT RetVT, SmallVectorImpl<Register> &UsedRegs,
2055 Register ResultReg = createResultReg(DstRC);
2076 Register ResultReg = createResultReg(DstRC);
2157 Register DstReg = VA.getLocReg();
2226 SmallVector<Register, 8> ArgRegs;
2251 SmallVector<Register, 4> RegArgs;
2257 Register CalleeReg;
2276 for (Register R : RegArgs)
2284 SmallVector<Register, 4> UsedRegs;
2334 SmallVector<Register, 8> ArgRegs;
2371 Register Arg = getRegForValue(*i);
2384 SmallVector<Register, 4> RegArgs;
2394 Register CalleeReg;
2420 for (Register R : RegArgs)
2428 SmallVector<Register, 4> UsedRegs;
2469 Register ResultReg;
2499 Register FramePtr = RegInfo->getFrameRegister(*(FuncInfo.MF));
2940 Register ResultReg = MI->getOperand(0).getReg();
2967 Register TempReg = MF->getRegInfo().createVirtualRegister(&ARM::rGPRRegClass);
lib/Target/ARM/ARMFrameLowering.cpp 379 Register FramePtr = RegInfo->getFrameRegister(MF);
783 Register FramePtr = RegInfo->getFrameRegister(MF);
1657 Register FramePtr = RegInfo->getFrameRegister(MF);
lib/Target/ARM/ARMISelDAGToDAG.cpp 4719 Register GPVR = MRI.createVirtualRegister(&ARM::GPRPairRegClass);
4755 Register GPVR = MRI.createVirtualRegister(&ARM::GPRPairRegClass);
lib/Target/ARM/ARMISelLowering.cpp 2515 if (!Register::isVirtualRegister(VR))
5560 Register FrameReg = ARI.getFrameRegister(MF);
5570 Register ARMTargetLowering::getRegisterByName(const char* RegName, EVT VT,
5572 Register Reg = StringSwitch<unsigned>(RegName)
9378 Register NewVReg1 = MRI->createVirtualRegister(TRC);
9384 Register NewVReg2 = MRI->createVirtualRegister(TRC);
9390 Register NewVReg3 = MRI->createVirtualRegister(TRC);
9408 Register NewVReg1 = MRI->createVirtualRegister(TRC);
9413 Register NewVReg2 = MRI->createVirtualRegister(TRC);
9418 Register NewVReg3 = MRI->createVirtualRegister(TRC);
9423 Register NewVReg4 = MRI->createVirtualRegister(TRC);
9429 Register NewVReg5 = MRI->createVirtualRegister(TRC);
9444 Register NewVReg1 = MRI->createVirtualRegister(TRC);
9450 Register NewVReg2 = MRI->createVirtualRegister(TRC);
9572 Register NewVReg1 = MRI->createVirtualRegister(TRC);
9585 Register VReg1 = MRI->createVirtualRegister(TRC);
9610 Register NewVReg3 = MRI->createVirtualRegister(TRC);
9615 Register NewVReg4 = MRI->createVirtualRegister(TRC);
9628 Register NewVReg1 = MRI->createVirtualRegister(TRC);
9651 Register VReg1 = MRI->createVirtualRegister(TRC);
9667 Register NewVReg2 = MRI->createVirtualRegister(TRC);
9674 Register NewVReg3 = MRI->createVirtualRegister(TRC);
9679 Register NewVReg4 = MRI->createVirtualRegister(TRC);
9689 Register NewVReg5 = MRI->createVirtualRegister(TRC);
9710 Register NewVReg1 = MRI->createVirtualRegister(TRC);
9723 Register VReg1 = MRI->createVirtualRegister(TRC);
9752 Register VReg1 = MRI->createVirtualRegister(TRC);
9769 Register NewVReg3 = MRI->createVirtualRegister(TRC);
9775 Register NewVReg4 = MRI->createVirtualRegister(TRC);
9782 Register NewVReg5 = MRI->createVirtualRegister(TRC);
10017 Register dest = MI.getOperand(0).getReg();
10018 Register src = MI.getOperand(1).getReg();
10069 Register srcOut = MRI.createVirtualRegister(TRC);
10070 Register destOut = MRI.createVirtualRegister(TRC);
10071 Register scratch = MRI.createVirtualRegister(IsNeon ? VecTRC : TRC);
10084 Register srcOut = MRI.createVirtualRegister(TRC);
10085 Register destOut = MRI.createVirtualRegister(TRC);
10086 Register scratch = MRI.createVirtualRegister(TRC);
10129 Register varEnd = MRI.createVirtualRegister(TRC);
10179 Register varLoop = MRI.createVirtualRegister(TRC);
10180 Register varPhi = MRI.createVirtualRegister(TRC);
10181 Register srcLoop = MRI.createVirtualRegister(TRC);
10182 Register srcPhi = MRI.createVirtualRegister(TRC);
10183 Register destLoop = MRI.createVirtualRegister(TRC);
10184 Register destPhi = MRI.createVirtualRegister(TRC);
10198 Register scratch = MRI.createVirtualRegister(IsNeon ? VecTRC : TRC);
10239 Register srcOut = MRI.createVirtualRegister(TRC);
10240 Register destOut = MRI.createVirtualRegister(TRC);
10241 Register scratch = MRI.createVirtualRegister(TRC);
10301 Register Reg = MRI.createVirtualRegister(&ARM::rGPRRegClass);
10549 Register LHS1 = MI.getOperand(1).getReg();
10550 Register LHS2 = MI.getOperand(2).getReg();
10560 Register RHS1 = MI.getOperand(3).getReg();
10561 Register RHS2 = MI.getOperand(4).getReg();
10622 Register ABSSrcReg = MI.getOperand(1).getReg();
10623 Register ABSDstReg = MI.getOperand(0).getReg();
10629 Register NewRsbDstReg = MRI.createVirtualRegister(
10709 Register TmpReg = MRI.createVirtualRegister(isThumb1 ? &ARM::tGPRRegClass
17115 Register NewVR = MRI->createVirtualRegister(RC);
lib/Target/ARM/ARMISelLowering.h 735 Register getRegisterByName(const char* RegName, EVT VT,
lib/Target/ARM/ARMInstrInfo.cpp 120 Register Reg = MI->getOperand(0).getReg();
lib/Target/ARM/ARMInstructionSelector.cpp 213 Register DstReg = I.getOperand(0).getReg();
214 if (Register::isPhysicalRegister(DstReg))
239 Register VReg0 = MIB->getOperand(0).getReg();
244 Register VReg1 = MIB->getOperand(1).getReg();
249 Register VReg2 = MIB->getOperand(2).getReg();
271 Register VReg0 = MIB->getOperand(0).getReg();
276 Register VReg1 = MIB->getOperand(1).getReg();
281 Register VReg2 = MIB->getOperand(2).getReg();
530 auto ResReg = MIB->getOperand(0).getReg();
542 auto LHSReg = MIB->getOperand(2).getReg();
543 auto RHSReg = MIB->getOperand(3).getReg();
549 auto ZeroReg = MRI.createVirtualRegister(&ARM::GPRRegClass);
559 auto IntermediateRes = MRI.createVirtualRegister(&ARM::GPRRegClass);
687 auto ResultReg = MIB->getOperand(0).getReg();
688 auto AddressReg = MRI.createVirtualRegister(&ARM::GPRRegClass);
718 auto Offset = MRI.createVirtualRegister(&ARM::GPRRegClass);
773 auto CondReg = MIB->getOperand(1).getReg();
785 auto ResReg = MIB->getOperand(0).getReg();
786 auto TrueReg = MIB->getOperand(2).getReg();
787 auto FalseReg = MIB->getOperand(3).getReg();
876 Register SExtResult = I.getOperand(0).getReg();
879 Register AndResult = MRI.createVirtualRegister(&ARM::GPRRegClass);
914 auto SrcReg = I.getOperand(1).getReg();
915 auto DstReg = I.getOperand(0).getReg();
930 Register IgnoredBits = MRI.createVirtualRegister(&ARM::GPRRegClass);
1009 auto SrcReg = I.getOperand(1).getReg();
1010 auto DstReg = I.getOperand(0).getReg();
1041 Register OpReg = I.getOperand(2).getReg();
1084 Register Reg = I.getOperand(0).getReg();
1099 Register OriginalValue = I.getOperand(0).getReg();
1101 Register ValueToStore = MRI.createVirtualRegister(&ARM::GPRRegClass);
1161 Register DstReg = I.getOperand(0).getReg();
lib/Target/ARM/ARMLegalizerInfo.cpp 374 Register OriginalResult = MI.getOperand(0).getReg();
387 Register RetRegs[] = {MRI.createGenericVirtualRegister(LLT::scalar(32)),
402 auto OriginalResult = MI.getOperand(0).getReg();
421 SmallVector<Register, 2> Results;
423 auto LibcallResult = MRI.createGenericVirtualRegister(LLT::scalar(32));
432 auto ProcessedResult =
448 auto Zero = MRI.createGenericVirtualRegister(LLT::scalar(32));
lib/Target/ARM/ARMLoadStoreOptimizer.cpp 512 Register InstrSrcReg = getLoadStoreRegOp(*MBBI).getReg();
862 Register Reg = MO.getReg();
877 Register DefReg = MO.getReg();
896 Register Base = getLoadStoreBaseOp(*First).getReg();
1008 Register PReg = PMO.getReg();
1055 Register Reg = MO.getReg();
1264 Register Base = BaseOP.getReg();
1390 Register Base = getLoadStoreBaseOp(*MI).getReg();
1515 Register Base = BaseOp.getReg();
1658 Register BaseReg = BaseOp.getReg();
1659 Register EvenReg = MI->getOperand(0).getReg();
1660 Register OddReg = MI->getOperand(1).getReg();
1786 Register Reg = MO.getReg();
1787 Register Base = getLoadStoreBaseOp(*MBBI).getReg();
2124 Register Reg = MO.getReg();
2418 Register Base = MI.getOperand(1).getReg();
lib/Target/ARM/MLxExpansionPass.cpp 89 Register Reg = MI->getOperand(1).getReg();
90 if (Register::isPhysicalRegister(Reg))
100 if (Register::isVirtualRegister(Reg)) {
106 if (Register::isVirtualRegister(Reg)) {
117 Register Reg = MI->getOperand(0).getReg();
118 if (Register::isPhysicalRegister(Reg) || !MRI->hasOneNonDBGUse(Reg))
128 if (Register::isPhysicalRegister(Reg) || !MRI->hasOneNonDBGUse(Reg))
141 Register Reg = MI->getOperand(1).getReg();
142 if (Register::isPhysicalRegister(Reg))
155 Register SrcReg = DefMI->getOperand(i).getReg();
156 if (Register::isVirtualRegister(SrcReg)) {
164 if (Register::isVirtualRegister(Reg)) {
170 if (Register::isVirtualRegister(Reg)) {
272 Register DstReg = MI->getOperand(0).getReg();
274 Register AccReg = MI->getOperand(1).getReg();
275 Register Src1Reg = MI->getOperand(2).getReg();
276 Register Src2Reg = MI->getOperand(3).getReg();
282 Register PredReg = MI->getOperand(++NextOp).getReg();
287 Register TmpReg =
lib/Target/ARM/Thumb1FrameLowering.cpp 167 Register FramePtr = RegInfo->getFrameRegister(MF);
462 Register Dst = MI.getOperand(0).getReg();
463 Register Src = MI.getOperand(1).getReg();
486 Register FramePtr = RegInfo->getFrameRegister(MF);
lib/Target/ARM/Thumb1InstrInfo.cpp 87 (Register::isPhysicalRegister(SrcReg) && isARMLowRegister(SrcReg))) {
116 (Register::isPhysicalRegister(DestReg) && isARMLowRegister(DestReg))) {
lib/Target/ARM/Thumb2ITBlockPass.cpp 90 Register Reg = MO.getReg();
148 Register DstReg = MI->getOperand(0).getReg();
149 Register SrcReg = MI->getOperand(1).getReg();
lib/Target/ARM/Thumb2InstrInfo.cpp 162 if (Register::isVirtualRegister(SrcReg)) {
203 if (Register::isVirtualRegister(DestReg)) {
213 if (Register::isPhysicalRegister(DestReg))
555 Register OffsetReg = MI.getOperand(FrameRegIdx + 1).getReg();
652 (Register::isVirtualRegister(FrameReg) ||
654 if (Register::isVirtualRegister(FrameReg)) {
693 return Offset == 0 && (Register::isVirtualRegister(FrameReg) ||
lib/Target/ARM/Thumb2SizeReduction.cpp 303 Register Reg = MO.getReg();
312 Register Reg = MO.getReg();
383 Register Reg = MO.getReg();
467 Register Rt = MI->getOperand(IsStore ? 1 : 0).getReg();
468 Register Rn = MI->getOperand(IsStore ? 0 : 1).getReg();
471 Register PredReg = MI->getOperand(5).getReg();
499 Register BaseReg = MI->getOperand(0).getReg();
527 Register BaseReg = MI->getOperand(1).getReg();
540 Register BaseReg = MI->getOperand(1).getReg();
746 Register Reg0 = MI->getOperand(0).getReg();
747 Register Reg1 = MI->getOperand(1).getReg();
750 Register Reg2 = MI->getOperand(2).getReg();
785 Register Reg2 = MI->getOperand(2).getReg();
871 Register Reg = MO.getReg();
lib/Target/ARM/ThumbRegisterInfo.cpp 145 if (!isARMLowRegister(DestReg) && !Register::isVirtualRegister(DestReg))
375 Register DestReg = MI.getOperand(0).getReg();
513 Register TmpReg = MI.getOperand(0).getReg();
lib/Target/AVR/AVRAsmPrinter.cpp 100 Register Reg = RegOp.getReg();
lib/Target/AVR/AVRExpandPseudoInsts.cpp 143 Register DstReg = MI.getOperand(0).getReg();
144 Register SrcReg = MI.getOperand(2).getReg();
176 Register DstReg = MI.getOperand(0).getReg();
177 Register SrcReg = MI.getOperand(2).getReg();
223 Register DstReg = MI.getOperand(0).getReg();
877 !Register::isVirtualRegister(MO.getReg()))
lib/Target/AVR/AVRFrameLowering.cpp 327 Register SrcReg = MI.getOperand(2).getReg();
lib/Target/AVR/AVRISelDAGToDAG.cpp 254 CanHandleRegImmOpt &= (Register::isVirtualRegister(Reg) ||
lib/Target/AVR/AVRISelLowering.cpp 1520 Register ShiftReg = RI.createVirtualRegister(RC);
1521 Register ShiftReg2 = RI.createVirtualRegister(RC);
1522 Register ShiftAmtSrcReg = MI.getOperand(2).getReg();
1523 Register SrcReg = MI.getOperand(1).getReg();
1524 Register DstReg = MI.getOperand(0).getReg();
1571 Register SrcReg = I->getOperand(1).getReg();
2009 Register AVRTargetLowering::getRegisterByName(const char *RegName, EVT VT,
2011 Register Reg;
lib/Target/AVR/AVRISelLowering.h 128 Register getRegisterByName(const char* RegName, EVT VT,
lib/Target/AVR/AVRRegisterInfo.cpp 161 Register DstReg = MI.getOperand(0).getReg();
248 Register AVRRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
lib/Target/AVR/AVRRegisterInfo.h 44 Register getFrameRegister(const MachineFunction &MF) const override;
lib/Target/BPF/BPFISelLowering.cpp 239 Register VReg = RegInfo.createVirtualRegister(
573 Register PromotedReg0 = RegInfo.createVirtualRegister(RC);
574 Register PromotedReg1 = RegInfo.createVirtualRegister(RC);
575 Register PromotedReg2 = RegInfo.createVirtualRegister(RC);
701 Register LHS = MI.getOperand(1).getReg();
718 Register RHS = MI.getOperand(2).getReg();
lib/Target/BPF/BPFInstrInfo.cpp 46 Register DstReg = MI->getOperand(0).getReg();
47 Register SrcReg = MI->getOperand(1).getReg();
50 Register ScratchReg = MI->getOperand(4).getReg();
lib/Target/BPF/BPFMIPeephole.cpp 108 Register Reg = opnd.getReg();
109 if ((Register::isVirtualRegister(Reg) &&
138 Register DstReg = MI.getOperand(0).getReg();
139 Register ShfReg = MI.getOperand(1).getReg();
163 Register SubReg = MovMI->getOperand(1).getReg();
261 Register dst = MI.getOperand(0).getReg();
262 Register src = MI.getOperand(1).getReg();
365 Register DstReg, SrcReg;
lib/Target/BPF/BPFMISimplifyPatchable.cpp 100 Register DstReg = MI.getOperand(0).getReg();
101 Register SrcReg = MI.getOperand(1).getReg();
lib/Target/BPF/BPFRegisterInfo.cpp 80 Register FrameReg = getFrameRegister(MF);
89 Register reg = MI.getOperand(i - 1).getReg();
108 Register reg = MI.getOperand(i - 1).getReg();
124 Register BPFRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
lib/Target/BPF/BPFRegisterInfo.h 35 Register getFrameRegister(const MachineFunction &MF) const override;
lib/Target/Hexagon/BitTracker.cpp 87 OS << 'v' << Register::virtReg2Index(PV.R);
338 if (Register::isVirtualRegister(RR.Reg)) {
343 Register PhysR =
354 if (Register::isPhysicalRegister(RR.Reg))
380 if (!Register::isVirtualRegister(RR.Reg))
878 if (!Register::isVirtualRegister(RD.Reg))
lib/Target/Hexagon/HexagonAsmPrinter.cpp 133 Register RegNumber = MO.getReg();
lib/Target/Hexagon/HexagonBitSimplify.cpp 150 return Register::virtReg2Index(v);
154 return Register::index2VirtReg(x);
293 Register R = Op.getReg();
294 if (!Register::isVirtualRegister(R))
305 Register R = Op.getReg();
306 if (!Register::isVirtualRegister(R))
356 if (!Register::isVirtualRegister(OldR) || !Register::isVirtualRegister(NewR))
356 if (!Register::isVirtualRegister(OldR) || !Register::isVirtualRegister(NewR))
369 if (!Register::isVirtualRegister(OldR) || !Register::isVirtualRegister(NewR))
369 if (!Register::isVirtualRegister(OldR) || !Register::isVirtualRegister(NewR))
385 if (!Register::isVirtualRegister(OldR) || !Register::isVirtualRegister(NewR))
385 if (!Register::isVirtualRegister(OldR) || !Register::isVirtualRegister(NewR))
896 if (!Register::isVirtualRegister(RR.Reg))
927 if (!Register::isVirtualRegister(RD.Reg) ||
928 !Register::isVirtualRegister(RS.Reg))
979 Register DR = UseI->getOperand(0).getReg();
1018 Register R = Op.getReg();
1019 if (!Register::isVirtualRegister(R) || !isDead(R)) {
1220 Register DefR = UseI.getOperand(0).getReg();
1221 if (!Register::isVirtualRegister(DefR))
1345 Register NewR = MRI.createVirtualRegister(FRC);
1412 Register Reg = MRI.createVirtualRegister(RC);
1470 if (!Register::isVirtualRegister(DR))
1609 Register NewR = MRI.createVirtualRegister(FRC);
1628 Register NewR = MRI.createVirtualRegister(FRC);
1819 if (!Register::isVirtualRegister(Reg))
2025 Register NewR = MRI.createVirtualRegister(&Hexagon::DoubleRegsRegClass);
2097 Register NewR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
2154 Register NewR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
2368 Register NewR = MRI.createVirtualRegister(&Hexagon::PredRegsRegClass);
2541 Register NewR = MRI.createVirtualRegister(FRC);
2613 Register NewR = MRI.createVirtualRegister(FRC);
2678 Register NewR = MRI.createVirtualRegister(FRC);
3071 Register PhiR = MRI->createVirtualRegister(PhiRC);
3083 Register NewDR = MRI->createVirtualRegister(RC);
3162 if (!Register::isVirtualRegister(DefR))
lib/Target/Hexagon/HexagonBitTracker.cpp 1045 Register R = Op.getReg();
1046 if (!Register::isVirtualRegister(R))
1223 if (!Register::isPhysicalRegister(RS.Reg))
lib/Target/Hexagon/HexagonBlockRanges.cpp 271 if (Register::isPhysicalRegister(R.Reg)) {
324 if (Register::isPhysicalRegister(R.Reg) && Reserved[R.Reg])
341 if (Register::isPhysicalRegister(S.Reg) && Reserved[S.Reg])
485 if (Register::isVirtualRegister(P.first.Reg))
lib/Target/Hexagon/HexagonConstExtenders.cpp 239 Reg = llvm::Register::index2StackSlot(Op.getIndex());
244 return Reg != 0 && !llvm::Register::isStackSlot(Reg) &&
245 llvm::Register::isVirtualRegister(Reg);
248 return Reg != 0 && llvm::Register::isStackSlot(Reg);
255 if (llvm::Register::isStackSlot(Reg)) {
256 int FI = llvm::Register::stackSlot2Index(Reg);
1528 llvm::Register DefR = MRI->createVirtualRegister(&Hexagon::IntRegsRegClass);
lib/Target/Hexagon/HexagonConstPropagation.cpp 211 if (!Register::isVirtualRegister(R))
218 if (!Register::isVirtualRegister(R))
655 if (!Register::isVirtualRegister(UseR.Reg))
697 if (!Register::isVirtualRegister(DefR.Reg))
1073 if (!Register::isVirtualRegister(R.Reg))
1929 if (!Register::isVirtualRegister(DefR.Reg))
2796 if (!Register::isVirtualRegister(R.Reg))
2816 Register R = MO.getReg();
2834 Register R = MO.getReg();
2835 if (!Register::isVirtualRegister(R))
2874 Register NewR = MRI->createVirtualRegister(PredRC);
2896 Register NewR = MRI->createVirtualRegister(NewRC);
3012 Register NewR = MRI->createVirtualRegister(RC);
lib/Target/Hexagon/HexagonCopyToCombine.cpp 136 Register DestReg = Op0.getReg();
137 Register SrcReg = Op1.getReg();
149 Register DestReg = Op0.getReg();
257 static Register UseReg(const MachineOperand& MO) {
268 Register I2UseReg = UseReg(I2.getOperand(1));
335 Register I1UseReg = UseReg(I1.getOperand(1));
413 Register Reg = Op.getReg();
445 Register Reg = Op.getReg();
531 Register I1DestReg = I1.getOperand(0).getReg();
547 Register I2DestReg = I2->getOperand(0).getReg();
582 Register I1DestReg = I1.getOperand(0).getReg();
583 Register I2DestReg = I2.getOperand(0).getReg();
761 Register LoReg = LoOperand.getReg();
810 Register HiReg = HiOperand.getReg();
860 Register LoReg = LoOperand.getReg();
861 Register HiReg = HiOperand.getReg();
lib/Target/Hexagon/HexagonEarlyIfConv.cpp 253 Register PredR = T1I->getOperand(0).getReg();
387 Register R = MO.getReg();
388 if (!Register::isVirtualRegister(R))
404 Register R = MO.getReg();
405 if (!Register::isVirtualRegister(R))
440 Register DefR = MI.getOperand(0).getReg();
494 Register R = MO.getReg();
495 if (!Register::isVirtualRegister(R))
801 Register MuxR = MRI->createVirtualRegister(DRC);
840 Register DR = PN->getOperand(0).getReg();
991 Register UseR = UO.getReg(), UseSR = UO.getSubReg();
992 Register DefR = PN->getOperand(0).getReg();
lib/Target/Hexagon/HexagonExpandCondsets.cpp 375 Register DR = Op.getReg(), DSR = Op.getSubReg();
376 if (!Register::isVirtualRegister(DR) || DR != Reg)
554 if (!Register::isVirtualRegister(R)) {
582 Register PhysR;
584 if (Register::isVirtualRegister(RS.Reg)) {
592 Register PhysS = (RS.Sub == 0) ? PhysR : TRI->getSubReg(PhysR, RS.Sub);
674 Register DR = MD.getReg(), DSR = MD.getSubReg();
805 if (!Register::isVirtualRegister(RR.Reg))
957 Register PredR = MP.getReg();
1002 if (!Register::isVirtualRegister(RR.Reg))
1094 if (!Register::isVirtualRegister(RR.Reg))
lib/Target/Hexagon/HexagonFrameLowering.cpp 306 Register R = MO.getReg();
309 if (Register::isVirtualRegister(R))
976 Register HiReg = HRI.getSubReg(Reg, Hexagon::isub_hi);
977 Register LoReg = HRI.getSubReg(Reg, Hexagon::isub_lo);
1573 Register DstR = MI->getOperand(0).getReg();
1574 Register SrcR = MI->getOperand(1).getReg();
1579 Register TmpR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
1598 Register SrcR = MI->getOperand(2).getReg();
1604 Register TmpR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
1631 Register DstR = MI->getOperand(0).getReg();
1635 Register TmpR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
1661 Register SrcR = MI->getOperand(2).getReg();
1670 Register TmpR0 = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
1671 Register TmpR1 = MRI.createVirtualRegister(RC);
1698 Register DstR = MI->getOperand(0).getReg();
1705 Register TmpR0 = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
1706 Register TmpR1 = MRI.createVirtualRegister(RC);
1748 Register SrcR = MI->getOperand(2).getReg();
1749 Register SrcLo = HRI.getSubReg(SrcR, Hexagon::vsub_lo);
1750 Register SrcHi = HRI.getSubReg(SrcR, Hexagon::vsub_hi);
1796 Register DstR = MI->getOperand(0).getReg();
1797 Register DstHi = HRI.getSubReg(DstR, Hexagon::vsub_hi);
1798 Register DstLo = HRI.getSubReg(DstR, Hexagon::vsub_lo);
1837 Register SrcR = MI->getOperand(2).getReg();
1866 Register DstR = MI->getOperand(0).getReg();
2302 Register DstR = MI.getOperand(0).getReg();
lib/Target/Hexagon/HexagonGenInsert.cpp 166 return Register::virtReg2Index(v);
170 return Register::index2VirtReg(x);
270 unsigned RInd = Register::virtReg2Index(VR);
609 Register R = MO.getReg();
611 if (Register::isVirtualRegister(R))
727 Register R = MO.getReg();
728 if (!Register::isVirtualRegister(R))
740 Register R = MO.getReg();
741 if (!Register::isVirtualRegister(R))
1402 Register NewVR = MRI->createVirtualRegister(RC);
1480 Register R = MO.getReg();
1481 if (!Register::isVirtualRegister(R) || !MRI->use_nodbg_empty(R)) {
1600 unsigned Idx = Register::virtReg2Index(I->first);
lib/Target/Hexagon/HexagonGenMux.cpp 174 Register R = MO.getReg();
242 Register DR = MI->getOperand(0).getReg();
249 Register PR = PredOp.getReg();
306 Register SR1 = Src1->isReg() ? Src1->getReg() : Register();
307 Register SR2 = Src2->isReg() ? Src2->getReg() : Register();
lib/Target/Hexagon/HexagonGenPredicate.cpp 54 RegisterSubReg(const Register &Reg) : R(Reg), S(0) {}
136 if (!Register::isVirtualRegister(R))
216 if (Register::isVirtualRegister(RD.R))
268 Register NewPR = MRI->createVirtualRegister(PredRC);
435 Register NewOutR = MRI->createVirtualRegister(RC);
474 if (!Register::isVirtualRegister(DR.R))
476 if (!Register::isVirtualRegister(SR.R))
lib/Target/Hexagon/HexagonHardwareLoops.cpp 438 Register PhiOpReg = Phi->getOperand(i).getReg();
444 Register IndReg = DI->getOperand(1).getReg();
448 Register UpdReg = DI->getOperand(0).getReg();
697 Register R = InitialValue->getReg();
707 Register R = EndValue->getReg();
913 Register SubR = MRI->createVirtualRegister(IntRC);
934 Register SubR = MRI->createVirtualRegister(IntRC);
953 Register AddR = MRI->createVirtualRegister(IntRC);
974 Register LsrR = MRI->createVirtualRegister(IntRC);
1041 Register Reg = MO.getReg();
1061 Register OPReg = OPO.getReg();
1095 Register Reg = MO.getReg();
1247 Register CountReg = MRI->createVirtualRegister(&Hexagon::IntRegsRegClass);
1260 Register CountReg = MRI->createVirtualRegister(&Hexagon::IntRegsRegClass);
1336 Register PredR = CmpI->getOperand(0).getReg();
1431 Register Reg = InitVal->getReg();
1434 if (!Register::isVirtualRegister(Reg))
1511 Register R = MO.getReg();
1512 if (!Register::isVirtualRegister(R))
1585 Register R = MO.getReg();
1589 Register NewR = MRI->createVirtualRegister(RC);
1637 Register PhiReg = Phi->getOperand(i).getReg();
1643 Register IndReg = DI->getOperand(1).getReg();
1647 Register UpdReg = DI->getOperand(0).getReg();
1705 Register P = Cond[CSz - 1].getReg();
1906 Register PR = PN->getOperand(0).getReg();
1908 Register NewPR = MRI->createVirtualRegister(RC);
1914 Register PredR = PN->getOperand(i).getReg();
lib/Target/Hexagon/HexagonISelLowering.cpp 243 Register HexagonTargetLowering::getRegisterByName(const char* RegName, EVT VT,
246 Register Reg = StringSwitch<Register>(RegName)
289 Register PredR = MRI.createVirtualRegister(&Hexagon::PredRegsRegClass);
739 Register VReg = MRI.createVirtualRegister(RC);
lib/Target/Hexagon/HexagonISelLowering.h 232 Register getRegisterByName(const char* RegName, EVT VT,
lib/Target/Hexagon/HexagonInstrInfo.cpp 196 Register Reg = MO.getReg();
683 Register LoopCount;
741 Register LoopCount = Loop->getOperand(1).getReg();
742 Register NewLoopCount = TII->createVR(MF, MVT::i32);
852 Register LoSrc = HRI.getSubReg(SrcReg, Hexagon::vsub_lo);
853 Register HiSrc = HRI.getSubReg(SrcReg, Hexagon::vsub_hi);
1030 Register Mx = MI.getOperand(MxOp).getReg();
1062 Register SrcReg = MI.getOperand(1).getReg();
1063 Register DstReg = MI.getOperand(0).getReg();
1072 Register SrcReg = MI.getOperand(1).getReg();
1073 Register DstReg = MI.getOperand(0).getReg();
1074 Register SrcSubLo = HRI.getSubReg(SrcReg, Hexagon::vsub_lo);
1081 Register SrcReg = MI.getOperand(1).getReg();
1082 Register DstReg = MI.getOperand(0).getReg();
1083 Register SrcSubHi = HRI.getSubReg(SrcReg, Hexagon::vsub_hi);
1092 Register SrcReg = MI.getOperand(2).getReg();
1093 Register SrcSubHi = HRI.getSubReg(SrcReg, Hexagon::vsub_hi);
1094 Register SrcSubLo = HRI.getSubReg(SrcReg, Hexagon::vsub_lo);
1116 Register DstReg = MI.getOperand(0).getReg();
1135 Register Reg = MI.getOperand(0).getReg();
1143 Register Reg = MI.getOperand(0).getReg();
1165 Register Vd = MI.getOperand(0).getReg();
1174 Register DstReg = MI.getOperand(0).getReg();
1175 Register Src1Reg = MI.getOperand(1).getReg();
1176 Register Src2Reg = MI.getOperand(2).getReg();
1177 Register Src1SubHi = HRI.getSubReg(Src1Reg, Hexagon::isub_hi);
1178 Register Src1SubLo = HRI.getSubReg(Src1Reg, Hexagon::isub_lo);
1179 Register Src2SubHi = HRI.getSubReg(Src2Reg, Hexagon::isub_hi);
1180 Register Src2SubLo = HRI.getSubReg(Src2Reg, Hexagon::isub_lo);
1198 Register DstReg = MI.getOperand(0).getReg();
1199 Register Src1Reg = MI.getOperand(1).getReg();
1200 Register Src2Reg = MI.getOperand(2).getReg();
1201 Register Src3Reg = MI.getOperand(3).getReg();
1202 Register Src1SubHi = HRI.getSubReg(Src1Reg, Hexagon::isub_hi);
1203 Register Src1SubLo = HRI.getSubReg(Src1Reg, Hexagon::isub_lo);
1204 Register Src2SubHi = HRI.getSubReg(Src2Reg, Hexagon::isub_hi);
1205 Register Src2SubLo = HRI.getSubReg(Src2Reg, Hexagon::isub_lo);
1206 Register Src3SubHi = HRI.getSubReg(Src3Reg, Hexagon::isub_hi);
1207 Register Src3SubLo = HRI.getSubReg(Src3Reg, Hexagon::isub_lo);
1232 Register Rd = Op0.getReg();
1233 Register Pu = Op1.getReg();
1234 Register Rs = Op2.getReg();
1235 Register Rt = Op3.getReg();
1259 Register PReg = Op1.getReg();
1293 Register PReg = Op1.getReg();
1300 Register SrcLo = HRI.getSubReg(Op2.getReg(), Hexagon::vsub_lo);
1301 Register SrcHi = HRI.getSubReg(Op2.getReg(), Hexagon::vsub_hi);
1312 Register SrcLo = HRI.getSubReg(Op3.getReg(), Hexagon::vsub_lo);
1313 Register SrcHi = HRI.getSubReg(Op3.getReg(), Hexagon::vsub_hi);
1884 Register BaseRegA = BaseA.getReg();
1892 Register BaseRegB = BaseB.getReg();
1996 Register NewReg = MRI.createVirtualRegister(TRC);
2106 if (Register::isPhysicalRegister(RegA))
2111 if (Register::isPhysicalRegister(RegB))
2617 Register DstReg = MI1.getOperand(0).getReg();
3386 Register DestReg = GA.getOperand(0).getReg();
4103 if (DefMO.isReg() && Register::isPhysicalRegister(DefMO.getReg())) {
lib/Target/Hexagon/HexagonNewValueJump.cpp 180 Register Reg = II->getOperand(i).getReg();
293 if (secondReg && !Register::isPhysicalRegister(cmpOp2)) {
519 afterRA = Register::isPhysicalRegister(predReg);
606 Register feederReg = MI.getOperand(0).getReg();
654 Register UseR = MO.getReg();
lib/Target/Hexagon/HexagonOptAddrMode.cpp 165 Register OffsetReg = MI.getOperand(2).getReg();
351 Register AddDefR = AddMI->getOperand(0).getReg();
384 Register BaseReg = AddMI->getOperand(1).getReg();
414 Register newReg = AddRegOp.getReg();
727 Register DefR = MI->getOperand(0).getReg();
lib/Target/Hexagon/HexagonPeephole.cpp 139 Register DstReg = Dst.getReg();
140 Register SrcReg = Src.getReg();
142 if (Register::isVirtualRegister(DstReg) &&
143 Register::isVirtualRegister(SrcReg)) {
160 Register DstReg = Dst.getReg();
161 Register SrcReg = Src2.getReg();
177 Register DstReg = Dst.getReg();
178 Register SrcReg = Src1.getReg();
188 Register DstReg = Dst.getReg();
189 Register SrcReg = Src.getReg();
191 if (Register::isVirtualRegister(DstReg) &&
192 Register::isVirtualRegister(SrcReg)) {
211 Register DstReg = Dst.getReg();
212 Register SrcReg = Src.getReg();
213 if (Register::isVirtualRegister(DstReg) &&
214 Register::isVirtualRegister(SrcReg)) {
240 Register Reg0 = Op0.getReg();
245 if (Register::isVirtualRegister(Reg0)) {
278 Register PSrc = MI.getOperand(PR).getReg();
lib/Target/Hexagon/HexagonRegisterInfo.cpp 220 Register TmpR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
252 Register DstReg = MI->getOperand(0).getReg();
253 Register SrcReg = MI->getOperand(1).getReg();
289 Register HexagonRegisterInfo::getFrameRegister(const MachineFunction
lib/Target/Hexagon/HexagonRegisterInfo.h 69 Register getFrameRegister(const MachineFunction &MF) const override;
lib/Target/Hexagon/HexagonSplitConst32AndConst64.cpp 79 Register DestReg = MI.getOperand(0).getReg();
86 Register DestReg = MI.getOperand(0).getReg();
89 Register DestLo = TRI->getSubReg(DestReg, Hexagon::isub_lo);
90 Register DestHi = TRI->getSubReg(DestReg, Hexagon::isub_hi);
lib/Target/Hexagon/HexagonSplitDouble.cpp 213 Register R = Op.getReg();
214 if (!Register::isVirtualRegister(R))
227 unsigned R = Register::index2VirtReg(i);
234 unsigned R = Register::index2VirtReg(x);
247 unsigned R = Register::index2VirtReg(x);
261 Register T = MO.getReg();
262 if (!Register::isVirtualRegister(T)) {
268 unsigned u = Register::virtReg2Index(T);
284 unsigned R = Register::index2VirtReg(x);
375 Register Rs = MI->getOperand(1).getReg();
376 Register Rt = MI->getOperand(2).getReg();
502 Register PR = Cond[1].getReg();
538 Register R = MD.getReg();
554 Register T = UseI->getOperand(0).getReg();
606 Register R = Op.getReg();
608 bool isVirtReg = Register::isVirtualRegister(R);
677 Register NewR = MRI->createVirtualRegister(RC);
792 Register LoR = P.first;
793 Register HiR = P.second;
816 Register TmpR = MRI->createVirtualRegister(IntRC);
956 Register TmpR1 = MRI->createVirtualRegister(IntRC);
961 Register TmpR2 = MRI->createVirtualRegister(IntRC);
1005 Register DstR = MI->getOperand(0).getReg();
1082 Register R = Op.getReg();
1107 Register R = Op.getReg();
1108 if (!Register::isVirtualRegister(R))
1116 Register NewDR = MRI->createVirtualRegister(DoubleRC);
1148 Register LoR = MRI->createVirtualRegister(IntRC);
1149 Register HiR = MRI->createVirtualRegister(IntRC);
lib/Target/Hexagon/HexagonStoreWidening.cpp 444 Register VReg = MF->getRegInfo().createVirtualRegister(RC);
lib/Target/Hexagon/HexagonSubtarget.cpp 233 Register::isPhysicalRegister(MI->getOperand(1).getReg())) {
246 } else if (MO.isDef() && Register::isPhysicalRegister(MO.getReg())) {
347 Register DReg = DstInst->getOperand(0).getReg();
lib/Target/Hexagon/HexagonVExtract.cpp 70 Register ElemR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
72 Register ExtIdxR = ExtI->getOperand(2).getReg();
89 Register IdxR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
114 Register VecR = MI.getOperand(1).getReg();
147 Register BaseR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
153 Register ExtR = ExtI->getOperand(0).getReg();
lib/Target/Hexagon/HexagonVLIWPacketizer.cpp 152 Register R = MO.getReg();
426 Register DestReg = MI.getOperand(0).getReg();
519 Register Reg = MI.getOperand(BPI).getReg();
792 Register R = MO.getReg();
1212 Register R = MO.getReg();
1589 Register R = Op.getReg();
lib/Target/Hexagon/RDFGraph.cpp 636 Register Reg = Op.getReg();
1294 Register R = Op.getReg();
1295 if (!R || !Register::isPhysicalRegister(R))
1339 Register R = Op.getReg();
1340 if (!R || !Register::isPhysicalRegister(R) || DoneDefs.test(R))
1368 Register R = Op.getReg();
1369 if (!R || !Register::isPhysicalRegister(R))
lib/Target/Hexagon/RDFLiveness.cpp 892 Register R = Op.getReg();
893 if (!Register::isPhysicalRegister(R))
901 Register R = Op.getReg();
902 if (!Register::isPhysicalRegister(R))
lib/Target/Hexagon/RDFRegisters.h 102 return Register::isStackSlot(R);
106 return Register::index2StackSlot(RegMasks.find(RM));
110 return RegMasks.get(Register::stackSlot2Index(R));
128 return MaskInfos[Register::stackSlot2Index(MaskId)].Units;
lib/Target/Lanai/LanaiAsmPrinter.cpp 136 Register Reg = MO.getReg();
lib/Target/Lanai/LanaiFrameLowering.cpp 75 Register Dst = MI.getOperand(0).getReg();
76 Register Src = MI.getOperand(1).getReg();
lib/Target/Lanai/LanaiISelLowering.cpp 215 Register LanaiTargetLowering::getRegisterByName(
219 Register Reg = StringSwitch<unsigned>(RegName)
463 Register VReg = RegInfo.createVirtualRegister(&Lanai::GPRRegClass);
lib/Target/Lanai/LanaiISelLowering.h 93 Register getRegisterByName(const char *RegName, EVT VT,
lib/Target/Lanai/LanaiInstrInfo.cpp 459 if (!Register::isVirtualRegister(Reg))
481 if (Register::isPhysicalRegister(MO.getReg()))
507 Register DestReg = MI.getOperand(0).getReg();
lib/Target/Lanai/LanaiRegisterInfo.cpp 158 Register FrameReg = getFrameRegister(MF);
261 Register
266 Register LanaiRegisterInfo::getBaseRegister() const { return Lanai::R14; }
lib/Target/Lanai/LanaiRegisterInfo.h 45 Register getFrameRegister(const MachineFunction &MF) const override;
46 Register getBaseRegister() const;
lib/Target/MSP430/MSP430ISelLowering.cpp 638 Register VReg = RegInfo.createVirtualRegister(&MSP430::GR16RegClass);
1452 Register SrcReg = MI.getOperand(1).getReg();
1453 Register DstReg = MI.getOperand(0).getReg();
1485 Register ShiftAmtReg = RI.createVirtualRegister(&MSP430::GR8RegClass);
1486 Register ShiftAmtReg2 = RI.createVirtualRegister(&MSP430::GR8RegClass);
1487 Register ShiftReg = RI.createVirtualRegister(RC);
1488 Register ShiftReg2 = RI.createVirtualRegister(RC);
1489 Register ShiftAmtSrcReg = MI.getOperand(2).getReg();
1490 Register SrcReg = MI.getOperand(1).getReg();
1491 Register DstReg = MI.getOperand(0).getReg();
lib/Target/MSP430/MSP430RegisterInfo.cpp 142 Register DstReg = MI.getOperand(0).getReg();
157 Register MSP430RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
lib/Target/MSP430/MSP430RegisterInfo.h 40 Register getFrameRegister(const MachineFunction &MF) const override;
lib/Target/Mips/MicroMipsSizeReduction.cpp 364 Register reg = MI->getOperand(0).getReg();
406 Register Reg1 = MI1->getOperand(0).getReg();
407 Register Reg2 = MI2->getOperand(0).getReg();
478 Register Reg1 = MI1->getOperand(1).getReg();
479 Register Reg2 = MI2->getOperand(1).getReg();
624 Register RegDstMI1 = MI1->getOperand(0).getReg();
625 Register RegSrcMI1 = MI1->getOperand(1).getReg();
636 Register RegDstMI2 = MI2->getOperand(0).getReg();
637 Register RegSrcMI2 = MI2->getOperand(1).getReg();
lib/Target/Mips/Mips16ISelDAGToDAG.cpp 75 Register V0, V1, V2, GlobalBaseReg = MipsFI->getGlobalBaseReg();
lib/Target/Mips/Mips16ISelLowering.cpp 711 Register regX = MI.getOperand(0).getReg();
712 Register regY = MI.getOperand(1).getReg();
728 Register regX = MI.getOperand(0).getReg();
761 Register CC = MI.getOperand(0).getReg();
762 Register regX = MI.getOperand(1).getReg();
763 Register regY = MI.getOperand(2).getReg();
780 Register CC = MI.getOperand(0).getReg();
781 Register regX = MI.getOperand(1).getReg();
lib/Target/Mips/Mips16InstrInfo.cpp 361 !Register::isVirtualRegister(MO.getReg()))
lib/Target/Mips/MipsAsmPrinter.cpp 380 Register stackReg = RI.getFrameRegister(*MF);
575 Register Reg = MO.getReg();
601 Register Reg = MO.getReg();
lib/Target/Mips/MipsCallLowering.cpp 27 bool MipsCallLowering::MipsHandler::assign(Register VReg, const CCValAssign &VA,
39 bool MipsCallLowering::MipsHandler::assignVRegs(ArrayRef<Register> VRegs,
50 SmallVectorImpl<Register> &VRegs) {
57 SmallVector<Register, 4> VRegs;
96 void assignValueToReg(Register ValVReg, const CCValAssign &VA,
99 Register getStackAddress(const CCValAssign &VA,
102 void assignValueToAddress(Register ValVReg, const CCValAssign &VA) override;
104 bool handleSplit(SmallVectorImpl<Register> &VRegs,
106 Register ArgsReg, const EVT &VT) override;
113 void buildLoad(Register Val, const CCValAssign &VA) {
115 Register Addr = getStackAddress(VA, MMO);
136 void IncomingValueHandler::assignValueToReg(Register ValVReg,
141 Register PhysReg = VA.getLocReg();
180 Register IncomingValueHandler::getStackAddress(const CCValAssign &VA,
195 Register AddrReg = MRI.createGenericVirtualRegister(LLT::pointer(0, 32));
201 void IncomingValueHandler::assignValueToAddress(Register ValVReg,
206 Register LoadReg = MRI.createGenericVirtualRegister(LLT::scalar(32));
213 bool IncomingValueHandler::handleSplit(SmallVectorImpl<Register> &VRegs,
216 Register ArgsReg, const EVT &VT) {
232 void assignValueToReg(Register ValVReg, const CCValAssign &VA,
235 Register getStackAddress(const CCValAssign &VA,
238 void assignValueToAddress(Register ValVReg, const CCValAssign &VA) override;
240 bool handleSplit(SmallVectorImpl<Register> &VRegs,
242 Register ArgsReg, const EVT &VT) override;
244 Register extendRegister(Register ValReg, const CCValAssign &VA);
244 Register extendRegister(Register ValReg, const CCValAssign &VA);
250 void OutgoingValueHandler::assignValueToReg(Register ValVReg,
253 Register PhysReg = VA.getLocReg();
281 Register ExtReg = extendRegister(ValVReg, VA);
287 Register OutgoingValueHandler::getStackAddress(const CCValAssign &VA,
294 Register SPReg = MRI.createGenericVirtualRegister(p0);
297 Register OffsetReg = MRI.createGenericVirtualRegister(s32);
301 Register AddrReg = MRI.createGenericVirtualRegister(p0);
313 void OutgoingValueHandler::assignValueToAddress(Register ValVReg,
316 Register Addr = getStackAddress(VA, MMO);
317 Register ExtReg = extendRegister(ValVReg, VA);
321 Register OutgoingValueHandler::extendRegister(Register ValReg,
321 Register OutgoingValueHandler::extendRegister(Register ValReg,
326 Register ExtReg = MRI.createGenericVirtualRegister(LocTy);
331 Register ExtReg = MRI.createGenericVirtualRegister(LocTy);
336 Register ExtReg = MRI.createGenericVirtualRegister(LocTy);
349 bool OutgoingValueHandler::handleSplit(SmallVectorImpl<Register> &VRegs,
352 Register ArgsReg, const EVT &VT) {
415 ArrayRef<Register> VRegs) const {
455 ArrayRef<ArrayRef<Register>> VRegs) const {
573 Register CalleeReg =
708 SmallVector<Register, 4> SplitVRegs;
lib/Target/Mips/MipsCallLowering.h 37 bool assignVRegs(ArrayRef<Register> VRegs, ArrayRef<CCValAssign> ArgLocs,
40 void setLeastSignificantFirst(SmallVectorImpl<Register> &VRegs);
46 bool assign(Register VReg, const CCValAssign &VA, const EVT &VT);
48 virtual Register getStackAddress(const CCValAssign &VA,
51 virtual void assignValueToReg(Register ValVReg, const CCValAssign &VA,
54 virtual void assignValueToAddress(Register ValVReg,
57 virtual bool handleSplit(SmallVectorImpl<Register> &VRegs,
59 unsigned ArgLocsStartIndex, Register ArgsReg,
66 ArrayRef<Register> VRegs) const override;
69 ArrayRef<ArrayRef<Register>> VRegs) const override;
lib/Target/Mips/MipsExpandPseudo.cpp 102 Register Dest = I->getOperand(0).getReg();
103 Register Ptr = I->getOperand(1).getReg();
104 Register Mask = I->getOperand(2).getReg();
105 Register ShiftCmpVal = I->getOperand(3).getReg();
106 Register Mask2 = I->getOperand(4).getReg();
107 Register ShiftNewVal = I->getOperand(5).getReg();
108 Register ShiftAmnt = I->getOperand(6).getReg();
109 Register Scratch = I->getOperand(7).getReg();
110 Register Scratch2 = I->getOperand(8).getReg();
243 Register Dest = I->getOperand(0).getReg();
244 Register Ptr = I->getOperand(1).getReg();
245 Register OldVal = I->getOperand(2).getReg();
246 Register NewVal = I->getOperand(3).getReg();
247 Register Scratch = I->getOperand(4).getReg();
377 Register Dest = I->getOperand(0).getReg();
378 Register Ptr = I->getOperand(1).getReg();
379 Register Incr = I->getOperand(2).getReg();
380 Register Mask = I->getOperand(3).getReg();
381 Register Mask2 = I->getOperand(4).getReg();
382 Register ShiftAmnt = I->getOperand(5).getReg();
383 Register OldVal = I->getOperand(6).getReg();
384 Register BinOpRes = I->getOperand(7).getReg();
385 Register StoreVal = I->getOperand(8).getReg();
516 Register OldVal = I->getOperand(0).getReg();
517 Register Ptr = I->getOperand(1).getReg();
518 Register Incr = I->getOperand(2).getReg();
519 Register Scratch = I->getOperand(3).getReg();
lib/Target/Mips/MipsFastISel.cpp 1566 for (auto Reg : CLI.OutRegs)
1731 Register DestReg = VA.getLocReg();
lib/Target/Mips/MipsISelDAGToDAG.cpp 68 Register GlobalBaseReg = MF->getInfo<MipsFunctionInfo>()->getGlobalBaseReg();
lib/Target/Mips/MipsISelLowering.cpp 1258 Register VReg = MF.getRegInfo().createVirtualRegister(RC);
1478 Register OldVal = MI.getOperand(0).getReg();
1479 Register Ptr = MI.getOperand(1).getReg();
1480 Register Incr = MI.getOperand(2).getReg();
1481 Register Scratch = RegInfo.createVirtualRegister(RegInfo.getRegClass(OldVal));
1520 Register PtrCopy = RegInfo.createVirtualRegister(RegInfo.getRegClass(Ptr));
1521 Register IncrCopy = RegInfo.createVirtualRegister(RegInfo.getRegClass(Incr));
1557 Register ScrReg = RegInfo.createVirtualRegister(RC);
1582 Register Dest = MI.getOperand(0).getReg();
1583 Register Ptr = MI.getOperand(1).getReg();
1584 Register Incr = MI.getOperand(2).getReg();
1586 Register AlignedAddr = RegInfo.createVirtualRegister(RCp);
1587 Register ShiftAmt = RegInfo.createVirtualRegister(RC);
1588 Register Mask = RegInfo.createVirtualRegister(RC);
1589 Register Mask2 = RegInfo.createVirtualRegister(RC);
1590 Register Incr2 = RegInfo.createVirtualRegister(RC);
1591 Register MaskLSB2 = RegInfo.createVirtualRegister(RCp);
1592 Register PtrLSB2 = RegInfo.createVirtualRegister(RC);
1593 Register MaskUpper = RegInfo.createVirtualRegister(RC);
1594 Register Scratch = RegInfo.createVirtualRegister(RC);
1595 Register Scratch2 = RegInfo.createVirtualRegister(RC);
1596 Register Scratch3 = RegInfo.createVirtualRegister(RC);
1679 Register Off = RegInfo.createVirtualRegister(RC);
1739 Register Dest = MI.getOperand(0).getReg();
1740 Register Ptr = MI.getOperand(1).getReg();
1741 Register OldVal = MI.getOperand(2).getReg();
1742 Register NewVal = MI.getOperand(3).getReg();
1744 Register Scratch = MRI.createVirtualRegister(RC);
1752 Register PtrCopy = MRI.createVirtualRegister(MRI.getRegClass(Ptr));
1753 Register OldValCopy = MRI.createVirtualRegister(MRI.getRegClass(OldVal));
1754 Register NewValCopy = MRI.createVirtualRegister(MRI.getRegClass(NewVal));
1791 Register Dest = MI.getOperand(0).getReg();
1792 Register Ptr = MI.getOperand(1).getReg();
1793 Register CmpVal = MI.getOperand(2).getReg();
1794 Register NewVal = MI.getOperand(3).getReg();
1796 Register AlignedAddr = RegInfo.createVirtualRegister(RCp);
1797 Register ShiftAmt = RegInfo.createVirtualRegister(RC);
1798 Register Mask = RegInfo.createVirtualRegister(RC);
1799 Register Mask2 = RegInfo.createVirtualRegister(RC);
1800 Register ShiftedCmpVal = RegInfo.createVirtualRegister(RC);
1801 Register ShiftedNewVal = RegInfo.createVirtualRegister(RC);
1802 Register MaskLSB2 = RegInfo.createVirtualRegister(RCp);
1803 Register PtrLSB2 = RegInfo.createVirtualRegister(RC);
1804 Register MaskUpper = RegInfo.createVirtualRegister(RC);
1805 Register MaskedCmpVal = RegInfo.createVirtualRegister(RC);
1806 Register MaskedNewVal = RegInfo.createVirtualRegister(RC);
1821 Register Scratch = RegInfo.createVirtualRegister(RC);
1822 Register Scratch2 = RegInfo.createVirtualRegister(RC);
1860 Register Off = RegInfo.createVirtualRegister(RC);
3168 Register LocRegLo = VA.getLocReg();
3524 Register ArgReg = VA.getLocReg();
4569 Register MipsTargetLowering::getRegisterByName(const char* RegName, EVT VT,
4574 Register Reg = StringSwitch<Register>(RegName)
4580 Register Reg = StringSwitch<Register>(RegName)
lib/Target/Mips/MipsISelLowering.h 351 Register getRegisterByName(const char* RegName, EVT VT,
lib/Target/Mips/MipsInstructionSelector.cpp 42 bool materialize32BitImm(Register DestReg, APInt Imm,
89 Register DstReg = I.getOperand(0).getReg();
90 if (Register::isPhysicalRegister(DstReg))
129 bool MipsInstructionSelector::materialize32BitImm(Register DestReg, APInt Imm,
151 Register LUiReg = B.getMRI()->createVirtualRegister(&Mips::GPR32RegClass);
168 const Register DestReg = I.getOperand(0).getReg();
266 Register PseudoMULTuReg = MRI.createVirtualRegister(&Mips::ACC64RegClass);
317 Register JTIndex = MRI.createVirtualRegister(&Mips::GPR32RegClass);
325 Register DestAddress = MRI.createVirtualRegister(&Mips::GPR32RegClass);
333 Register Dest = MRI.createVirtualRegister(&Mips::GPR32RegClass);
345 Register DestTmp = MRI.createVirtualRegister(&Mips::GPR32RegClass);
371 const Register DestReg = I.getOperand(0).getReg();
375 if (Register::isPhysicalRegister(DestReg))
424 Register HILOReg = MRI.createVirtualRegister(&Mips::ACC64RegClass);
483 Register GPRReg = MRI.createVirtualRegister(&Mips::GPR32RegClass);
494 Register GPRRegHigh = MRI.createVirtualRegister(&Mips::GPR32RegClass);
495 Register GPRRegLow = MRI.createVirtualRegister(&Mips::GPR32RegClass);
535 Register ResultInFPR = MRI.createVirtualRegister(&Mips::FGR32RegClass);
574 Register LWGOTDef = MRI.createVirtualRegister(&Mips::GPR32RegClass);
587 Register LUiReg = MRI.createVirtualRegister(&Mips::GPR32RegClass);
629 Register Def, LHS, RHS;
630 Instr(unsigned Opcode, Register Def, Register LHS, Register RHS)
630 Instr(unsigned Opcode, Register Def, Register LHS, Register RHS)
630 Instr(unsigned Opcode, Register Def, Register LHS, Register RHS)
641 Register ICMPReg = I.getOperand(0).getReg();
642 Register Temp = MRI.createVirtualRegister(&Mips::GPR32RegClass);
643 Register LHS = I.getOperand(2).getReg();
644 Register RHS = I.getOperand(3).getReg();
756 Register TrueInReg = MRI.createVirtualRegister(&Mips::GPR32RegClass);
792 Register LeaReg = MRI.createVirtualRegister(&Mips::GPR32RegClass);
lib/Target/Mips/MipsLegalizerInfo.cpp 256 Register Dst = MI.getOperand(0).getReg();
257 Register Src = MI.getOperand(1).getReg();
362 Register Tmp = MRI.createGenericVirtualRegister(LLT::pointer(0, 32));
lib/Target/Mips/MipsMachineFunction.cpp 47 Register MipsFunctionInfo::getGlobalBaseReg() {
54 Register MipsFunctionInfo::getGlobalBaseRegForGlobalISel() {
lib/Target/Mips/MipsMachineFunction.h 35 Register getGlobalBaseReg();
36 Register getGlobalBaseRegForGlobalISel();
lib/Target/Mips/MipsOptimizePICCall.cpp 130 if (!MO.isReg() || !MO.isUse() || !Register::isVirtualRegister(MO.getReg()))
154 Register SrcReg = I->getOperand(0).getReg();
lib/Target/Mips/MipsRegisterBankInfo.cpp 172 Register Reg, const MachineRegisterInfo &MRI) {
179 !Register::isPhysicalRegister(NonCopyInstr->getOperand(0).getReg()))
187 Register Reg, const MachineRegisterInfo &MRI) {
201 !Register::isPhysicalRegister(Ret->getOperand(0).getReg()) &&
215 !Register::isPhysicalRegister(Ret->getOperand(1).getReg()))
627 Register Dest = MI.getOperand(0).getReg();
lib/Target/Mips/MipsRegisterBankInfo.h 82 void addDefUses(Register Reg, const MachineRegisterInfo &MRI);
83 void addUseDef(Register Reg, const MachineRegisterInfo &MRI);
lib/Target/Mips/MipsRegisterInfo.cpp 280 Register MipsRegisterInfo::
lib/Target/Mips/MipsRegisterInfo.h 72 Register getFrameRegister(const MachineFunction &MF) const override;
lib/Target/Mips/MipsSEFrameLowering.cpp 174 Register VR = MRI.createVirtualRegister(RC);
175 Register Dst = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex();
189 Register VR = MRI.createVirtualRegister(RC);
190 Register Src = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex();
207 Register VR0 = MRI.createVirtualRegister(RC);
208 Register VR1 = MRI.createVirtualRegister(RC);
209 Register Dst = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex();
210 Register Lo = RegInfo.getSubReg(Dst, Mips::sub_lo);
211 Register Hi = RegInfo.getSubReg(Dst, Mips::sub_hi);
232 Register VR0 = MRI.createVirtualRegister(RC);
233 Register VR1 = MRI.createVirtualRegister(RC);
234 Register Src = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex();
245 Register Src = I->getOperand(1).getReg();
265 Register VR0 = MRI.createVirtualRegister(RC);
266 Register VR1 = MRI.createVirtualRegister(RC);
268 Register DstLo = RegInfo.getSubReg(Dst, Mips::sub_lo);
269 Register DstHi = RegInfo.getSubReg(Dst, Mips::sub_hi);
307 Register DstReg = I->getOperand(0).getReg();
308 Register LoReg = I->getOperand(1).getReg();
309 Register HiReg = I->getOperand(2).getReg();
349 Register DstReg = I->getOperand(0).getReg();
372 Register DstReg = I->getOperand(0).getReg();
373 Register SrcReg = Op1.getReg();
541 Register VR = MF.getRegInfo().createVirtualRegister(RC);
lib/Target/Mips/MipsSEISelLowering.cpp 3067 Register VR2 = RegInfo.createVirtualRegister(RC);
3073 Register VR1 = RegInfo.createVirtualRegister(RC);
3136 Register RD1 = RegInfo.createVirtualRegister(RC);
3142 Register RD2 = RegInfo.createVirtualRegister(RC);
3174 Register Fd = MI.getOperand(0).getReg();
3175 Register Ws = MI.getOperand(1).getReg();
3190 Register Wt = RegInfo.createVirtualRegister(
3219 Register Fd = MI.getOperand(0).getReg();
3220 Register Ws = MI.getOperand(1).getReg();
3227 Register Wt = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
3249 Register Wd = MI.getOperand(0).getReg();
3250 Register Wd_in = MI.getOperand(1).getReg();
3252 Register Fs = MI.getOperand(3).getReg();
3253 Register Wt = RegInfo.createVirtualRegister(
3285 Register Wd = MI.getOperand(0).getReg();
3286 Register Wd_in = MI.getOperand(1).getReg();
3288 Register Fs = MI.getOperand(3).getReg();
3289 Register Wt = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
3331 Register Wd = MI.getOperand(0).getReg();
3332 Register SrcVecReg = MI.getOperand(1).getReg();
3333 Register LaneReg = MI.getOperand(2).getReg();
3334 Register SrcValReg = MI.getOperand(3).getReg();
3375 Register Wt = RegInfo.createVirtualRegister(VecRC);
3385 Register LaneTmp1 = RegInfo.createVirtualRegister(GPRRC);
3393 Register WdTmp1 = RegInfo.createVirtualRegister(VecRC);
3399 Register WdTmp2 = RegInfo.createVirtualRegister(VecRC);
3418 Register LaneTmp2 = RegInfo.createVirtualRegister(GPRRC);
3445 Register Wd = MI.getOperand(0).getReg();
3446 Register Fs = MI.getOperand(1).getReg();
3447 Register Wt1 = RegInfo.createVirtualRegister(
3450 Register Wt2 = RegInfo.createVirtualRegister(
3480 Register Wd = MI.getOperand(0).getReg();
3481 Register Fs = MI.getOperand(1).getReg();
3482 Register Wt1 = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
3483 Register Wt2 = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
3514 Register Ws = MI.getOperand(0).getReg();
3515 Register Rt = MI.getOperand(1).getReg();
3527 Register Rs = RegInfo.createVirtualRegister(&Mips::GPR32RegClass);
3531 Register Tmp = RegInfo.createVirtualRegister(&Mips::GPR64RegClass);
3569 Register Wd = MI.getOperand(0).getReg();
3580 Register Rt = RegInfo.createVirtualRegister(RC);
3588 Register Tmp = RegInfo.createVirtualRegister(&Mips::GPR32RegClass);
3663 Register Wd = MI.getOperand(0).getReg();
3664 Register Fs = MI.getOperand(1).getReg();
3667 Register Wtemp = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
3676 Register Rtemp = RegInfo.createVirtualRegister(GPRRC);
3682 Register Rtemp2 = RegInfo.createVirtualRegister(GPRRC);
3684 Register Wtemp2 = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
3685 Register Wtemp3 = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
3698 Register Wtemp2 = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
3768 Register Fd = MI.getOperand(0).getReg();
3769 Register Ws = MI.getOperand(1).getReg();
3777 Register COPYOpc = IsFGR64onMips64 ? Mips::COPY_S_D : Mips::COPY_S_W;
3779 Register Wtemp = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
3780 Register WPHI = Wtemp;
3789 Register Rtemp = RegInfo.createVirtualRegister(GPRRC);
3790 Register FPRPHI = IsFGR64onMips32
3797 Register Rtemp2 = RegInfo.createVirtualRegister(GPRRC);
3822 Register Ws1 = RegInfo.createVirtualRegister(RC);
3823 Register Ws2 = RegInfo.createVirtualRegister(RC);
3851 Register Ws1 = RegInfo.createVirtualRegister(RC);
3852 Register Ws2 = RegInfo.createVirtualRegister(RC);
lib/Target/Mips/MipsSEInstrInfo.cpp 631 Register Reg = RegInfo.createVirtualRegister(RC);
737 Register DstReg = I->getOperand(0).getReg();
738 Register DstLo = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo);
739 Register DstHi = getRegisterInfo().getSubReg(DstReg, Mips::sub_hi);
776 Register DstReg = I->getOperand(0).getReg();
777 Register SrcReg = I->getOperand(1).getReg();
783 Register SubReg = getRegisterInfo().getSubReg(SrcReg, SubIdx);
818 Register DstReg = I->getOperand(0).getReg();
886 Register OffsetReg = I->getOperand(0).getReg();
887 Register TargetReg = I->getOperand(1).getReg();
lib/Target/Mips/MipsSERegisterInfo.cpp 225 Register Reg = RegInfo.createVirtualRegister(PtrRC);
lib/Target/NVPTX/NVPTXAsmPrinter.cpp 285 if (Register::isVirtualRegister(Reg)) {
510 Register RegNo = MI->getOperand(0).getReg();
511 if (Register::isVirtualRegister(RegNo)) {
1654 unsigned int vr = Register::index2VirtReg(i);
2213 if (Register::isPhysicalRegister(MO.getReg())) {
lib/Target/NVPTX/NVPTXPeephole.cpp 84 if (Op.isReg() && Register::isVirtualRegister(Op.getReg())) {
lib/Target/NVPTX/NVPTXRegisterInfo.cpp 129 Register NVPTXRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
lib/Target/NVPTX/NVPTXRegisterInfo.h 45 Register getFrameRegister(const MachineFunction &MF) const override;
lib/Target/PowerPC/PPCAsmPrinter.cpp 278 Register Reg = MI->getOperand(OpNo).getReg();
391 Register ScratchReg = MI.getOperand(Opers.getNextScratchIdx()).getReg();
549 Register Reg = MO.getReg();
lib/Target/PowerPC/PPCBranchCoalescing.cpp 344 Register::isPhysicalRegister(Op1.getReg())
359 Register::isVirtualRegister(Op1.getReg()) &&
360 Register::isVirtualRegister(Op2.getReg())) {
460 if (Use.isReg() && Register::isVirtualRegister(Use.getReg())) {
lib/Target/PowerPC/PPCBranchSelector.cpp 339 Register CRReg = I->getOperand(1).getReg();
345 Register CRBit = I->getOperand(0).getReg();
348 Register CRBit = I->getOperand(0).getReg();
lib/Target/PowerPC/PPCFastISel.cpp 165 bool PPCEmitLoad(MVT VT, Register &ResultReg, Address &Addr,
454 bool PPCFastISel::PPCEmitLoad(MVT VT, Register &ResultReg, Address &Addr,
615 Register ResultReg = 0;
1054 Register ResultReg = 0;
1179 Register ResultReg = 0;
1720 Register RetReg = VA.getLocReg();
2355 Register ResultReg = MI->getOperand(0).getReg();
lib/Target/PowerPC/PPCFrameLowering.cpp 381 Register SrcReg = MI.getOperand(1).getReg();
382 Register DstReg = MI.getOperand(0).getReg();
833 Register BPReg = RegInfo->getBaseRegister(MF);
1404 Register BPReg = RegInfo->getBaseRegister(MF);
1983 Register BP = RegInfo->getBaseRegister(MF);
lib/Target/PowerPC/PPCISelDAGToDAG.cpp 374 unsigned Reg = Register::index2VirtReg(i);
394 Register InVRSAVE = RegInfo->createVirtualRegister(&PPC::GPRCRegClass);
395 Register UpdatedVRSAVE = RegInfo->createVirtualRegister(&PPC::GPRCRegClass);
450 Register TempReg = RegInfo->createVirtualRegister(&PPC::GPRCRegClass);
lib/Target/PowerPC/PPCISelLowering.cpp10335 Register dest = MI.getOperand(0).getReg();
10336 Register ptrA = MI.getOperand(1).getReg();
10337 Register ptrB = MI.getOperand(2).getReg();
10338 Register incr = MI.getOperand(3).getReg();
10354 Register TmpReg = (!BinOpcode) ? incr :
10388 Register ExtReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass);
10439 Register dest = MI.getOperand(0).getReg();
10440 Register ptrA = MI.getOperand(1).getReg();
10441 Register ptrB = MI.getOperand(2).getReg();
10442 Register incr = MI.getOperand(3).getReg();
10462 Register PtrReg = RegInfo.createVirtualRegister(RC);
10463 Register Shift1Reg = RegInfo.createVirtualRegister(GPRC);
10464 Register ShiftReg =
10466 Register Incr2Reg = RegInfo.createVirtualRegister(GPRC);
10467 Register MaskReg = RegInfo.createVirtualRegister(GPRC);
10468 Register Mask2Reg = RegInfo.createVirtualRegister(GPRC);
10469 Register Mask3Reg = RegInfo.createVirtualRegister(GPRC);
10470 Register Tmp2Reg = RegInfo.createVirtualRegister(GPRC);
10471 Register Tmp3Reg = RegInfo.createVirtualRegister(GPRC);
10472 Register Tmp4Reg = RegInfo.createVirtualRegister(GPRC);
10473 Register TmpDestReg = RegInfo.createVirtualRegister(GPRC);
10474 Register Ptr1Reg;
10475 Register TmpReg =
10560 Register SReg = RegInfo.createVirtualRegister(GPRC);
10571 Register ValueSReg = RegInfo.createVirtualRegister(GPRC);
10622 Register DstReg = MI.getOperand(0).getReg();
10625 Register mainDstReg = MRI.createVirtualRegister(RC);
10626 Register restoreDstReg = MRI.createVirtualRegister(RC);
10678 Register LabelReg = MRI.createVirtualRegister(PtrRC);
10679 Register BufReg = MI.getOperand(1).getReg();
10766 Register Tmp = MRI.createVirtualRegister(RC);
10783 Register BufReg = MI.getOperand(0).getReg();
11024 Register ReadAgainReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass);
11025 Register LoReg = MI.getOperand(0).getReg();
11026 Register HiReg = MI.getOperand(1).getReg();
11032 Register CmpReg = RegInfo.createVirtualRegister(&PPC::CRRCRegClass);
11174 Register dest = MI.getOperand(0).getReg();
11175 Register ptrA = MI.getOperand(1).getReg();
11176 Register ptrB = MI.getOperand(2).getReg();
11177 Register oldval = MI.getOperand(3).getReg();
11178 Register newval = MI.getOperand(4).getReg();
11253 Register dest = MI.getOperand(0).getReg();
11254 Register ptrA = MI.getOperand(1).getReg();
11255 Register ptrB = MI.getOperand(2).getReg();
11256 Register oldval = MI.getOperand(3).getReg();
11257 Register newval = MI.getOperand(4).getReg();
11277 Register PtrReg = RegInfo.createVirtualRegister(RC);
11278 Register Shift1Reg = RegInfo.createVirtualRegister(GPRC);
11279 Register ShiftReg =
11281 Register NewVal2Reg = RegInfo.createVirtualRegister(GPRC);
11282 Register NewVal3Reg = RegInfo.createVirtualRegister(GPRC);
11283 Register OldVal2Reg = RegInfo.createVirtualRegister(GPRC);
11284 Register OldVal3Reg = RegInfo.createVirtualRegister(GPRC);
11285 Register MaskReg = RegInfo.createVirtualRegister(GPRC);
11286 Register Mask2Reg = RegInfo.createVirtualRegister(GPRC);
11287 Register Mask3Reg = RegInfo.createVirtualRegister(GPRC);
11288 Register Tmp2Reg = RegInfo.createVirtualRegister(GPRC);
11289 Register Tmp4Reg = RegInfo.createVirtualRegister(GPRC);
11290 Register TmpDestReg = RegInfo.createVirtualRegister(GPRC);
11291 Register Ptr1Reg;
11292 Register TmpReg = RegInfo.createVirtualRegister(GPRC);
11293 Register ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
11434 Register Dest = MI.getOperand(0).getReg();
11435 Register Src1 = MI.getOperand(1).getReg();
11436 Register Src2 = MI.getOperand(2).getReg();
11440 Register MFFSReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass);
11466 Register Dest = RegInfo.createVirtualRegister(
11479 Register CRReg = RegInfo.createVirtualRegister(&PPC::CRRCRegClass);
11493 Register OldFPSCRReg = MI.getOperand(0).getReg();
11574 Register OldFPSCRReg = MI.getOperand(0).getReg();
11589 Register OldFPSCRTmpReg = RegInfo.createVirtualRegister(&PPC::G8RCRegClass);
11593 Register ImDefReg = RegInfo.createVirtualRegister(&PPC::G8RCRegClass);
11594 Register ExtSrcReg = RegInfo.createVirtualRegister(&PPC::G8RCRegClass);
11605 Register NewFPSCRTmpReg = RegInfo.createVirtualRegister(&PPC::G8RCRegClass);
11612 Register NewFPSCRReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass);
14570 Register PPCTargetLowering::getRegisterByName(const char* RegName, EVT VT,
14580 Register Reg = StringSwitch<Register>(RegName)
15047 Register NewVR = MRI->createVirtualRegister(RC);
lib/Target/PowerPC/PPCISelLowering.h 739 Register getRegisterByName(const char* RegName, EVT VT,
lib/Target/PowerPC/PPCInstrInfo.cpp 186 Register Reg = DefMO.getReg();
189 if (Register::isVirtualRegister(Reg)) {
395 Register Reg0 = MI.getOperand(0).getReg();
396 Register Reg1 = MI.getOperand(1).getReg();
397 Register Reg2 = MI.getOperand(2).getReg();
425 Register Reg0 = ChangeReg0 ? Reg2 : MI.getOperand(0).getReg();
1643 Register CRReg = CmpInstr.getOperand(0).getReg();
1666 if (Register::isVirtualRegister(ActualSrc))
1932 Register GPRRes = MI->getOperand(0).getReg();
2117 Register TargetReg = MI.getOperand(0).getReg();
2179 Register TargetReg = MI.getOperand(0).getReg();
2189 Register SrcReg = MI.getOperand(0).getReg();
2201 Register TargetReg = MI.getOperand(0).getReg();
2209 Register SrcReg = MI.getOperand(0).getReg();
2221 auto Val = MI.getOperand(0).getReg();
2274 Register InUseReg = MI.getOperand(OpNo).getReg();
2354 Register Reg = MI.getOperand(i).getReg();
2355 if (!Register::isVirtualRegister(Reg))
2358 if (Register::isVirtualRegister(TrueReg)) {
2396 Register Reg = MI.getOperand(i).getReg();
2767 Register ForwardingOperandReg = MI.getOperand(ForwardingOperand).getReg();
2823 Register DefReg = MI.getOperand(0).getReg();
2833 Register TrueReg = CompareUseMI.getOperand(1).getReg();
2834 Register FalseReg = CompareUseMI.getOperand(2).getReg();
3518 Register Reg = RegMO.getReg();
3742 Register OrigZeroReg = MI.getOperand(PosForOrigZero).getReg();
3743 Register NewZeroReg = MI.getOperand(III.ZeroIsSpecialNew).getReg();
3836 Register RegToModify = MI.getOperand(III.ZeroIsSpecialNew).getReg();
3837 if (Register::isVirtualRegister(RegToModify)) {
3982 Register StackReg = MI.getOperand(2).getReg();
4007 Register SrcReg = MI.getOperand(1).getReg();
4016 Register VReg = MI.getOperand(0).getReg();
4053 if (!Register::isVirtualRegister(SrcReg))
4076 Register SrcReg = MI.getOperand(1).getReg();
4077 if (!Register::isVirtualRegister(SrcReg))
4105 Register SrcReg = MI.getOperand(I).getReg();
4106 if (!Register::isVirtualRegister(SrcReg))
4128 Register SrcReg1 = MI.getOperand(1).getReg();
4129 Register SrcReg2 = MI.getOperand(2).getReg();
4131 if (!Register::isVirtualRegister(SrcReg1) ||
4132 !Register::isVirtualRegister(SrcReg2))
4239 Register LoopCountReg = LoopInst->getOperand(0).getReg();
lib/Target/PowerPC/PPCMIPeephole.cpp 151 Register Reg = Op->getReg();
152 if (!Register::isVirtualRegister(Reg))
347 if (TrueReg1 == TrueReg2 && Register::isVirtualRegister(TrueReg1)) {
360 if (Register::isVirtualRegister(DefReg)) {
446 if (!Register::isVirtualRegister(TrueReg))
455 Register ConvReg = DefMI->getOperand(1).getReg();
456 if (!Register::isVirtualRegister(ConvReg))
483 Register ShiftRes = DefMI->getOperand(0).getReg();
484 Register ShiftOp1 = DefMI->getOperand(1).getReg();
485 Register ShiftOp2 = DefMI->getOperand(2).getReg();
509 if (!Register::isVirtualRegister(TrueReg))
520 if (!Register::isVirtualRegister(DefsReg1) ||
521 !Register::isVirtualRegister(DefsReg2))
535 Register ConvReg1 = RoundInstr->getOperand(1).getReg();
536 Register FRSPDefines = RoundInstr->getOperand(0).getReg();
568 Register NarrowReg = MI.getOperand(1).getReg();
569 if (!Register::isVirtualRegister(NarrowReg))
612 Register NarrowReg = MI.getOperand(1).getReg();
613 if (!Register::isVirtualRegister(NarrowReg))
654 Register TmpReg =
681 Register SrcReg = MI.getOperand(1).getReg();
682 if (!Register::isVirtualRegister(SrcReg))
697 Register CopyReg = SubRegMI->getOperand(1).getReg();
698 if (Register::isVirtualRegister(CopyReg))
759 Register DominatorReg = Op2.getReg();
929 if (NextReg == SrcReg || !Register::isVirtualRegister(NextReg))
951 Register CndReg = (*BII).getOperand(1).getReg();
952 if (!Register::isVirtualRegister(CndReg) || !MRI->hasOneNonDBGUse(CndReg))
962 if (MO.isReg() && !Register::isVirtualRegister(MO.getReg()))
1272 Register Op1 = CMPI2->getOperand(1).getReg();
1273 Register Op2 = CMPI2->getOperand(2).getReg();
1296 Register NewVReg = MRI->createVirtualRegister(&PPC::CRRCRegClass);
1335 Register SrcReg = MI.getOperand(1).getReg();
1336 if (!Register::isVirtualRegister(SrcReg))
1415 Register SrcReg = MI.getOperand(1).getReg();
1416 if (!Register::isVirtualRegister(SrcReg))
1432 if (!Register::isVirtualRegister(SrcMI->getOperand(1).getReg()))
lib/Target/PowerPC/PPCPreEmitPeephole.cpp 96 Register Reg = BBI->getOperand(0).getReg();
226 Register CRBit = Br->getOperand(0).getReg();
lib/Target/PowerPC/PPCQPXLoadSplat.cpp 82 Register SplatReg = SMI->getOperand(0).getReg();
83 Register SrcReg = SMI->getOperand(1).getReg();
105 Register SplatSubReg = TRI->getSubReg(SplatReg, SubRegIndex);
lib/Target/PowerPC/PPCReduceCRLogicals.cpp 538 if (!Register::isVirtualRegister(Reg))
544 Register CopySrc = Copy->getOperand(1).getReg();
546 if (!Register::isVirtualRegister(CopySrc)) {
lib/Target/PowerPC/PPCRegisterInfo.cpp 529 Register Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
551 Register NegSizeReg = MI.getOperand(1).getReg();
657 Register Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
658 Register SrcReg = MI.getOperand(0).getReg();
702 Register Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
703 Register DestReg = MI.getOperand(0).getReg();
746 Register Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
747 Register SrcReg = MI.getOperand(0).getReg();
825 Register Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
826 Register DestReg = MI.getOperand(0).getReg();
835 Register RegO = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
872 Register Reg = MF.getRegInfo().createVirtualRegister(GPRC);
873 Register SrcReg = MI.getOperand(0).getReg();
898 Register Reg = MF.getRegInfo().createVirtualRegister(GPRC);
899 Register DestReg = MI.getOperand(0).getReg();
1130 Register StackReg = MI.getOperand(FIOperandNum).getReg();
1135 Register PPCRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
1144 Register PPCRegisterInfo::getBaseRegister(const MachineFunction &MF) const {
lib/Target/PowerPC/PPCRegisterInfo.h 144 Register getFrameRegister(const MachineFunction &MF) const override;
147 Register getBaseRegister(const MachineFunction &MF) const;
lib/Target/PowerPC/PPCTLSDynamicCall.cpp 77 Register OutReg = MI.getOperand(0).getReg();
78 Register InReg = MI.getOperand(1).getReg();
lib/Target/PowerPC/PPCVSXCopy.cpp 53 if (Register::isVirtualRegister(Reg)) {
105 Register NewVReg = MRI.createVirtualRegister(SrcRC);
127 Register NewVReg = MRI.createVirtualRegister(DstRC);
lib/Target/PowerPC/PPCVSXFMAMutate.cpp 129 Register AddendSrcReg = AddendMI->getOperand(1).getReg();
130 if (Register::isVirtualRegister(AddendSrcReg)) {
185 Register OldFMAReg = MI.getOperand(0).getReg();
189 Register Reg2 = MI.getOperand(2).getReg();
190 Register Reg3 = MI.getOperand(3).getReg();
211 if (Register::isVirtualRegister(AddendSrcReg) &&
217 Register KilledProdReg = MI.getOperand(KilledProdOp).getReg();
218 Register OtherProdReg = MI.getOperand(OtherProdOp).getReg();
317 if (!Register::isVirtualRegister(AddendSrcReg))
lib/Target/PowerPC/PPCVSXSwapRemoval.cpp 161 if (Register::isVirtualRegister(Reg))
256 Register Reg = MO.getReg();
569 if (!Register::isVirtualRegister(CopySrcReg)) {
604 Register Reg = MO.getReg();
608 if (!Register::isVirtualRegister(Reg)) {
670 Register DefReg = MI->getOperand(0).getReg();
698 Register UseReg = MI->getOperand(0).getReg();
700 Register DefReg = DefMI->getOperand(0).getReg();
759 Register DefReg = MI->getOperand(0).getReg();
775 Register UseReg = MI->getOperand(0).getReg();
872 Register Reg1 = MI->getOperand(1).getReg();
873 Register Reg2 = MI->getOperand(2).getReg();
897 Register DstReg = MI->getOperand(0).getReg();
899 Register NewVReg = MRI->createVirtualRegister(DstRC);
913 Register VSRCTmp1 = MRI->createVirtualRegister(&PPC::VSRCRegClass);
914 Register VSRCTmp2 = MRI->createVirtualRegister(&PPC::VSRCRegClass);
lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp 83 void emitLoadImm(Register DestReg, int64_t Value, MCStreamer &Out);
208 Register RegNum;
744 static Register convertFPR64ToFPR32(Register Reg) {
744 static Register convertFPR64ToFPR32(Register Reg) {
755 Register Reg = Op.getReg();
949 static bool matchRegisterNameHelper(bool IsRV32E, Register &RegNo,
1004 Register RegNo;
1594 void RISCVAsmParser::emitLoadImm(Register DestReg, int64_t Value,
1599 Register SrcReg = RISCV::X0;
1753 Register Reg = Inst.getOperand(0).getReg();
lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp 72 Register Reg = RISCV::X0 + RegNo;
83 Register Reg = RISCV::F0_F + RegNo;
94 Register Reg = RISCV::F8_F + RegNo;
105 Register Reg = RISCV::F0_D + RegNo;
116 Register Reg = RISCV::F8_D + RegNo;
147 Register Reg = RISCV::X8 + RegNo;
lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp 104 Register Ra;
lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp 58 Register SP = MRI.getDwarfRegNum(RISCV::X2, true);
lib/Target/RISCV/RISCVCallLowering.cpp 26 ArrayRef<Register> VRegs) const {
39 ArrayRef<ArrayRef<Register>> VRegs) const {
lib/Target/RISCV/RISCVCallLowering.h 31 ArrayRef<Register> VRegs) const override;
34 ArrayRef<ArrayRef<Register>> VRegs) const override;
lib/Target/RISCV/RISCVExpandPseudoInsts.cpp 238 Register DestReg = MI.getOperand(0).getReg();
239 Register ScratchReg = MI.getOperand(1).getReg();
240 Register AddrReg = MI.getOperand(2).getReg();
241 Register IncrReg = MI.getOperand(3).getReg();
274 MachineBasicBlock *MBB, Register DestReg,
275 Register OldValReg, Register NewValReg,
275 Register OldValReg, Register NewValReg,
276 Register MaskReg, Register ScratchReg) {
276 Register MaskReg, Register ScratchReg) {
300 Register DestReg = MI.getOperand(0).getReg();
301 Register ScratchReg = MI.getOperand(1).getReg();
302 Register AddrReg = MI.getOperand(2).getReg();
303 Register IncrReg = MI.getOperand(3).getReg();
304 Register MaskReg = MI.getOperand(4).getReg();
397 MachineBasicBlock *MBB, Register ValReg,
398 Register ShamtReg) {
439 Register DestReg = MI.getOperand(0).getReg();
440 Register Scratch1Reg = MI.getOperand(1).getReg();
441 Register Scratch2Reg = MI.getOperand(2).getReg();
442 Register AddrReg = MI.getOperand(3).getReg();
443 Register IncrReg = MI.getOperand(4).getReg();
444 Register MaskReg = MI.getOperand(5).getReg();
552 Register DestReg = MI.getOperand(0).getReg();
553 Register ScratchReg = MI.getOperand(1).getReg();
554 Register AddrReg = MI.getOperand(2).getReg();
555 Register CmpValReg = MI.getOperand(3).getReg();
556 Register NewValReg = MI.getOperand(4).getReg();
585 Register MaskReg = MI.getOperand(5).getReg();
632 Register DestReg = MI.getOperand(0).getReg();
lib/Target/RISCV/RISCVFrameLowering.cpp 86 Register ScratchReg = MRI.createVirtualRegister(&RISCV::GPRRegClass);
96 static Register getFPReg(const RISCVSubtarget &STI) { return RISCV::X8; }
99 static Register getSPReg(const RISCVSubtarget &STI) { return RISCV::X2; }
117 Register FPReg = getFPReg(STI);
118 Register SPReg = getSPReg(STI);
168 Register Reg = Entry.getReg();
218 Register VR =
239 Register FPReg = getFPReg(STI);
240 Register SPReg = getSPReg(STI);
281 Register DestReg = I->getOperand(0).getReg();
302 Register Reg = Entry.getReg();
442 Register SPReg = RISCV::X2;
lib/Target/RISCV/RISCVISelLowering.cpp 674 Register FrameReg = RI.getFrameRegister(MF);
717 Register Reg = MF.addLiveIn(RI.getRARegister(), getRegClassFor(XLenVT));
1122 Register ReadAgainReg = RegInfo.createVirtualRegister(&RISCV::GPRRegClass);
1123 Register LoReg = MI.getOperand(0).getReg();
1124 Register HiReg = MI.getOperand(1).getReg();
1159 Register LoReg = MI.getOperand(0).getReg();
1160 Register HiReg = MI.getOperand(1).getReg();
1161 Register SrcReg = MI.getOperand(2).getReg();
1191 Register DstReg = MI.getOperand(0).getReg();
1192 Register LoReg = MI.getOperand(1).getReg();
1193 Register HiReg = MI.getOperand(2).getReg();
1252 Register LHS = MI.getOperand(1).getReg();
1253 Register RHS = MI.getOperand(2).getReg();
1257 SmallSet<Register, 4> SelectDests;
1415 if (Register Reg = State.AllocateReg(ArgGPRs)) {
1432 if (Register Reg = State.AllocateReg(ArgGPRs)) {
1532 Register Reg = State.AllocateReg(ArgGPRs);
1574 Register Reg;
1710 Register VReg = RegInfo.createVirtualRegister(RC);
1788 Register LoVReg = RegInfo.createVirtualRegister(&RISCV::GPRRegClass);
1800 Register HiVReg = RegInfo.createVirtualRegister(&RISCV::GPRRegClass);
1983 const Register Reg = RegInfo.createVirtualRegister(RC);
2153 SmallVector<std::pair<Register, SDValue>, 8> RegsToPass;
2170 Register RegLo = VA.getLocReg();
2184 Register RegHigh = RegLo + 1;
2412 Register RegLo = VA.getLocReg();
2414 Register RegHi = RegLo + 1;
2477 const SmallVectorImpl<std::pair<llvm::Register, llvm::SDValue>> &Regs,
2579 Register XRegFromAlias = StringSwitch<Register>(Constraint.lower())
2624 std::pair<Register, Register> FReg =
2624 std::pair<Register, Register> FReg =
lib/Target/RISCV/RISCVISelLowering.h 217 const SmallVectorImpl<std::pair<llvm::Register, llvm::SDValue>> &Regs,
lib/Target/RISCV/RISCVInstrInfo.cpp 168 Register SrcReg = RISCV::X0;
169 Register Result = MRI.createVirtualRegister(&RISCV::GPRRegClass);
396 Register ScratchReg = MRI.createVirtualRegister(&RISCV::GPRRegClass);
lib/Target/RISCV/RISCVMergeBaseOffset.cpp 48 bool matchLargeOffset(MachineInstr &TailAdd, Register GSReg, int64_t &Offset);
88 Register HiLuiDestReg = HiLUI.getOperand(0).getReg();
135 Register GAReg,
138 Register Rs = TailAdd.getOperand(1).getReg();
139 Register Rt = TailAdd.getOperand(2).getReg();
140 Register Reg = Rs == GAReg ? Rt : Rs;
181 Register DestReg = LoADDI.getOperand(0).getReg();
235 Register BaseAddrReg = Tail.getOperand(1).getReg();
lib/Target/RISCV/RISCVRegisterInfo.cpp 131 Register ScratchReg = MRI.createVirtualRegister(&RISCV::GPRRegClass);
146 Register RISCVRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
lib/Target/RISCV/RISCVRegisterInfo.h 44 Register getFrameRegister(const MachineFunction &MF) const override;
lib/Target/RISCV/RISCVSubtarget.h 97 bool isRegisterReservedByUser(Register i) const {
lib/Target/Sparc/DelaySlotFiller.cpp 256 Register Reg = MO.getReg();
327 Register Reg = MO.getReg();
383 Register reg = AddMI->getOperand(0).getReg();
411 Register reg = OrMI->getOperand(0).getReg();
449 Register reg = SetHiMI->getOperand(0).getReg();
lib/Target/Sparc/SparcISelDAGToDAG.cpp 234 Register GPVR = MRI.createVirtualRegister(&SP::IntPairRegClass);
281 Register GPVR = MRI.createVirtualRegister(&SP::IntPairRegClass);
lib/Target/Sparc/SparcISelLowering.cpp 420 Register VRegHi = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
448 Register VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
555 Register VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
1019 Register SparcTargetLowering::getRegisterByName(const char* RegName, EVT VT,
1021 Register Reg = StringSwitch<unsigned>(RegName)
lib/Target/Sparc/SparcISelLowering.h 101 Register getRegisterByName(const char* RegName, EVT VT,
lib/Target/Sparc/SparcInstrInfo.cpp 378 Register Dst = TRI->getSubReg(DestReg, subRegIdx[i]);
379 Register Src = TRI->getSubReg(SrcReg, subRegIdx[i]);
lib/Target/Sparc/SparcRegisterInfo.cpp 185 Register SrcReg = MI.getOperand(2).getReg();
186 Register SrcEvenReg = getSubReg(SrcReg, SP::sub_even64);
187 Register SrcOddReg = getSubReg(SrcReg, SP::sub_odd64);
197 Register DestReg = MI.getOperand(0).getReg();
198 Register DestEvenReg = getSubReg(DestReg, SP::sub_even64);
199 Register DestOddReg = getSubReg(DestReg, SP::sub_odd64);
215 Register SparcRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
lib/Target/Sparc/SparcRegisterInfo.h 41 Register getFrameRegister(const MachineFunction &MF) const override;
lib/Target/SystemZ/SystemZElimCompare.cpp 155 if (Register MOReg = MO.getReg()) {
525 Register SrcReg = Compare.getOperand(0).getReg();
526 Register SrcReg2 =
lib/Target/SystemZ/SystemZFrameLowering.cpp 121 Register GPR32 = RI->getSubReg(GPR64, SystemZ::subreg_l32);
lib/Target/SystemZ/SystemZISelLowering.cpp 1354 Register VReg = MRI.createVirtualRegister(RC);
1449 Register Reg = VA.getLocReg();
1693 Register Reg = VA.getLocReg();
6502 static Register forceReg(MachineInstr &MI, MachineOperand &Base,
6511 Register Reg = MRI.createVirtualRegister(&SystemZ::ADDR64BitRegClass);
6589 Register DestReg = MI->getOperand(0).getReg();
6590 Register TrueReg = MI->getOperand(1).getReg();
6591 Register FalseReg = MI->getOperand(2).getReg();
6721 Register SrcReg = MI.getOperand(0).getReg();
6724 Register IndexReg = MI.getOperand(3).getReg();
6816 Register Dest = MI.getOperand(0).getReg();
6820 Register BitShift = IsSubWord ? MI.getOperand(4).getReg() : Register();
6821 Register NegBitShift = IsSubWord ? MI.getOperand(5).getReg() : Register();
6839 Register OrigVal = MRI.createVirtualRegister(RC);
6840 Register OldVal = MRI.createVirtualRegister(RC);
6841 Register NewVal = (BinOpcode || IsSubWord ?
6843 Register RotatedOldVal = (IsSubWord ? MRI.createVirtualRegister(RC) : OldVal);
6844 Register RotatedNewVal = (IsSubWord ? MRI.createVirtualRegister(RC) : NewVal);
6876 Register Tmp = MRI.createVirtualRegister(RC);
6885 Register Tmp2 = MRI.createVirtualRegister(RC);
6934 Register Dest = MI.getOperand(0).getReg();
6937 Register Src2 = MI.getOperand(3).getReg();
6938 Register BitShift = (IsSubWord ? MI.getOperand(4).getReg() : Register());
6939 Register NegBitShift = (IsSubWord ? MI.getOperand(5).getReg() : Register());
6957 Register OrigVal = MRI.createVirtualRegister(RC);
6958 Register OldVal = MRI.createVirtualRegister(RC);
6959 Register NewVal = MRI.createVirtualRegister(RC);
6960 Register RotatedOldVal = (IsSubWord ? MRI.createVirtualRegister(RC) : OldVal);
6961 Register RotatedAltVal = (IsSubWord ? MRI.createVirtualRegister(RC) : Src2);
6962 Register RotatedNewVal = (IsSubWord ? MRI.createVirtualRegister(RC) : NewVal);
7048 Register Dest = MI.getOperand(0).getReg();
7051 Register OrigCmpVal = MI.getOperand(3).getReg();
7052 Register OrigSwapVal = MI.getOperand(4).getReg();
7053 Register BitShift = MI.getOperand(5).getReg();
7054 Register NegBitShift = MI.getOperand(6).getReg();
7066 Register OrigOldVal = MRI.createVirtualRegister(RC);
7067 Register OldVal = MRI.createVirtualRegister(RC);
7068 Register CmpVal = MRI.createVirtualRegister(RC);
7069 Register SwapVal = MRI.createVirtualRegister(RC);
7070 Register StoreVal = MRI.createVirtualRegister(RC);
7071 Register RetryOldVal = MRI.createVirtualRegister(RC);
7072 Register RetryCmpVal = MRI.createVirtualRegister(RC);
7073 Register RetrySwapVal = MRI.createVirtualRegister(RC);
7172 Register Dest = MI.getOperand(0).getReg();
7173 Register Hi = MI.getOperand(1).getReg();
7174 Register Lo = MI.getOperand(2).getReg();
7175 Register Tmp1 = MRI.createVirtualRegister(&SystemZ::GR128BitRegClass);
7176 Register Tmp2 = MRI.createVirtualRegister(&SystemZ::GR128BitRegClass);
7200 Register Dest = MI.getOperand(0).getReg();
7201 Register Src = MI.getOperand(1).getReg();
7202 Register In128 = MRI.createVirtualRegister(&SystemZ::GR128BitRegClass);
7206 Register NewIn128 = MRI.createVirtualRegister(&SystemZ::GR128BitRegClass);
7207 Register Zero64 = MRI.createVirtualRegister(&SystemZ::GR64BitRegClass);
7245 Register StartCountReg = MI.getOperand(5).getReg();
7246 Register StartSrcReg = forceReg(MI, SrcBase, TII);
7247 Register StartDestReg = (HaveSingleBase ? StartSrcReg :
7251 Register ThisSrcReg = MRI.createVirtualRegister(RC);
7252 Register ThisDestReg = (HaveSingleBase ? ThisSrcReg :
7254 Register NextSrcReg = MRI.createVirtualRegister(RC);
7255 Register NextDestReg = (HaveSingleBase ? NextSrcReg :
7259 Register ThisCountReg = MRI.createVirtualRegister(RC);
7260 Register NextCountReg = MRI.createVirtualRegister(RC);
7351 Register Reg = MRI.createVirtualRegister(&SystemZ::ADDR64BitRegClass);
7360 Register Reg = MRI.createVirtualRegister(&SystemZ::ADDR64BitRegClass);
7517 Register SrcReg = MI.getOperand(0).getReg();
7521 Register DstReg = MRI->createVirtualRegister(RC);
lib/Target/SystemZ/SystemZInstrInfo.cpp 78 Register Reg128 = LowRegOp.getReg();
140 Register Reg = MI.getOperand(0).getReg();
154 Register DestReg = MI.getOperand(0).getReg();
155 Register SrcReg = MI.getOperand(1).getReg();
177 Register Reg = MI.getOperand(0).getReg();
189 Register Reg = MI.getOperand(0).getReg();
214 const Register Reg64 = MI->getOperand(0).getReg();
215 const Register Reg32 = RI.getSubReg(Reg64, SystemZ::subreg_l32);
588 Register TReg = MRI.createVirtualRegister(&SystemZ::GR32BitRegClass);
589 Register FReg = MRI.createVirtualRegister(&SystemZ::GR32BitRegClass);
1168 Register DstReg = MI.getOperand(0).getReg();
1169 Register DstPhys =
1170 (Register::isVirtualRegister(DstReg) ? VRM->getPhys(DstReg) : DstReg);
1171 Register SrcReg = (OpNum == 2 ? MI.getOperand(1).getReg()
1176 Register::isVirtualRegister(SrcReg) &&
lib/Target/SystemZ/SystemZPostRewrite.cpp 89 Register DestReg = MBBI->getOperand(0).getReg();
90 Register SrcReg = MBBI->getOperand(2).getReg();
110 Register DestReg = MBBI->getOperand(0).getReg();
111 Register Src1Reg = MBBI->getOperand(1).getReg();
112 Register Src2Reg = MBBI->getOperand(2).getReg();
164 Register DestReg = MI.getOperand(0).getReg();
165 Register SrcReg = MI.getOperand(2).getReg();
225 Register DstReg = MI.getOperand(0).getReg();
lib/Target/SystemZ/SystemZRegisterInfo.cpp 44 Register PhysReg = VRM->getPhys(MO.getReg());
123 Register OtherReg =
171 Register Reg = MO->getReg();
172 Register PhysReg =
173 Register::isPhysicalRegister(Reg) ? Reg : VRM->getPhys(Reg);
301 Register ScratchReg =
355 Register GR128Reg = MI->getOperand(WideOpNo).getReg();
356 Register GRNarReg = MI->getOperand((WideOpNo == 1) ? 0 : 1).getReg();
389 if (MO.isReg() && Register::isPhysicalRegister(MO.getReg())) {
407 Register
lib/Target/SystemZ/SystemZRegisterInfo.h 95 Register getFrameRegister(const MachineFunction &MF) const override;
lib/Target/SystemZ/SystemZShortenInst.cpp 78 Register Reg = MI.getOperand(0).getReg();
89 Register OtherReg = TRI->getSubReg(GR64BitReg, otherSubRegIdx);
lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp 70 Register RegNo = MO.getReg();
lib/Target/WebAssembly/WebAssemblyCFGStackify.cpp 716 if (!MO.isReg() || Register::isPhysicalRegister(MO.getReg()))
968 Register ExnReg = MRI.createVirtualRegister(&WebAssembly::EXNREFRegClass);
lib/Target/WebAssembly/WebAssemblyExplicitLocals.cpp 171 Register Reg = MO.getReg();
210 Register Reg = MI.getOperand(0).getReg();
224 UseEmpty[I] = MRI.use_empty(Register::index2VirtReg(I));
241 Register OldReg = MI.getOperand(2).getReg();
247 Register NewReg = MRI.createVirtualRegister(RC);
273 Register OldReg = MI.getOperand(0).getReg();
276 Register NewReg = MRI.createVirtualRegister(RC);
283 if (UseEmpty[Register::virtReg2Index(OldReg)]) {
313 Register OldReg = MO.getReg();
348 Register NewReg = MRI.createVirtualRegister(RC);
372 unsigned Reg = Register::index2VirtReg(I);
lib/Target/WebAssembly/WebAssemblyFastISel.cpp 1144 Register Reg = fastEmit_ISD_BITCAST_r(VT.getSimpleVT(), RetVT.getSimpleVT(),
lib/Target/WebAssembly/WebAssemblyFixIrreducibleControlFlow.cpp 362 Register Reg = MRI.createVirtualRegister(&WebAssembly::I32RegClass);
lib/Target/WebAssembly/WebAssemblyFrameLowering.cpp 186 Register BasePtr = MRI.createVirtualRegister(PtrRC);
193 Register OffsetReg = MRI.createVirtualRegister(PtrRC);
202 Register BitmaskReg = MRI.createVirtualRegister(PtrRC);
247 Register OffsetReg = MRI.createVirtualRegister(PtrRC);
lib/Target/WebAssembly/WebAssemblyISelLowering.cpp 338 Register OutReg = MI.getOperand(0).getReg();
339 Register InReg = MI.getOperand(1).getReg();
397 Register SecondCmpReg =
399 Register AndReg = MRI.createVirtualRegister(&WebAssembly::I32RegClass);
927 Register VarargVreg =
1084 Register FP =
lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp 63 Register::isVirtualRegister(DestReg)
lib/Target/WebAssembly/WebAssemblyLateEHPrepare.cpp 135 Register DstReg = MRI.createVirtualRegister(&WebAssembly::EXNREFRegClass);
172 Register ExnReg = Catch->getOperand(0).getReg();
297 Register ExnReg = Catch->getOperand(0).getReg();
344 Register Reg = MRI.createVirtualRegister(&WebAssembly::I32RegClass);
lib/Target/WebAssembly/WebAssemblyLowerBrUnless.cpp 71 Register Cond = MI->getOperand(1).getReg();
191 Register Tmp = MRI.createVirtualRegister(&WebAssembly::I32RegClass);
lib/Target/WebAssembly/WebAssemblyMachineFunctionInfo.h 99 auto I = Register::virtReg2Index(VReg);
105 auto I = Register::virtReg2Index(VReg);
110 auto I = Register::virtReg2Index(VReg);
119 auto I = Register::virtReg2Index(VReg);
124 auto I = Register::virtReg2Index(VReg);
lib/Target/WebAssembly/WebAssemblyMemIntrinsicResults.cpp 169 Register FromReg = MI.getOperand(2).getReg();
170 Register ToReg = MI.getOperand(0).getReg();
lib/Target/WebAssembly/WebAssemblyOptimizeLiveIntervals.cpp 84 unsigned Reg = Register::index2VirtReg(I);
lib/Target/WebAssembly/WebAssemblyPeephole.cpp 66 Register NewReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg));
94 Register Reg = MO.getReg();
120 Register NewReg = MRI.createVirtualRegister(RegClass);
167 Register OldReg = MO.getReg();
168 Register NewReg = Op2.getReg();
lib/Target/WebAssembly/WebAssemblyPrepareForLiveIntervals.cpp 98 unsigned Reg = Register::index2VirtReg(I);
lib/Target/WebAssembly/WebAssemblyRegColoring.cpp 101 unsigned VReg = Register::index2VirtReg(I);
lib/Target/WebAssembly/WebAssemblyRegNumbering.cpp 92 unsigned VReg = Register::index2VirtReg(VRegIdx);
lib/Target/WebAssembly/WebAssemblyRegStackify.cpp 123 Register TempReg = MRI.createVirtualRegister(&WebAssembly::I32RegClass);
337 Register Reg = MO.getReg();
344 if (Register::isPhysicalRegister(Reg)) {
439 Register DefReg = MO.getReg();
440 if (!Register::isVirtualRegister(DefReg) ||
502 Register NewReg = MRI.createVirtualRegister(MRI.getRegClass(Reg));
538 Register NewReg = MRI.createVirtualRegister(MRI.getRegClass(Reg));
610 Register TeeReg = MRI.createVirtualRegister(RegClass);
611 Register DefReg = MRI.createVirtualRegister(RegClass);
810 Register Reg = Op.getReg();
814 if (Register::isPhysicalRegister(Reg))
918 Register Reg = MO.getReg();
lib/Target/WebAssembly/WebAssemblyRegisterInfo.cpp 69 Register FrameRegister = getFrameRegister(MF);
94 Register OtherMOReg = OtherMO.getReg();
95 if (Register::isVirtualRegister(OtherMOReg)) {
120 Register OffsetOp = MRI.createVirtualRegister(PtrRC);
133 Register
lib/Target/WebAssembly/WebAssemblyRegisterInfo.h 42 Register getFrameRegister(const MachineFunction &MF) const override;
lib/Target/WebAssembly/WebAssemblyUtilities.cpp 35 Register Reg = MO.getReg();
36 return Register::isVirtualRegister(Reg) && MFI.isVRegStackified(Reg);
lib/Target/X86/X86AsmPrinter.cpp 245 Register Reg = MO.getReg();
391 Register Reg = MO.getReg();
lib/Target/X86/X86AvoidStoreForwardingBlocks.cpp 394 Register Reg1 = MRI->createVirtualRegister(
lib/Target/X86/X86CallFrameOptimization.cpp 338 Register Reg = MO.getReg();
339 if (!Register::isPhysicalRegister(Reg))
383 Register StackPtr = RegInfo.getStackRegister();
456 Register Reg = MO.getReg();
457 if (Register::isPhysicalRegister(Reg))
537 Register Reg = PushOp.getReg();
542 Register UndefReg = MRI->createVirtualRegister(&X86::GR64RegClass);
611 if (!Register::isVirtualRegister(Reg))
lib/Target/X86/X86CallLowering.cpp 79 SmallVector<Register, 8> SplitRegs;
107 Register getStackAddress(uint64_t Size, int64_t Offset,
111 Register SPReg = MRI.createGenericVirtualRegister(p0);
114 Register OffsetReg = MRI.createGenericVirtualRegister(SType);
117 Register AddrReg = MRI.createGenericVirtualRegister(p0);
124 void assignValueToReg(Register ValVReg, Register PhysReg,
124 void assignValueToReg(Register ValVReg, Register PhysReg,
128 Register ExtReg;
149 void assignValueToAddress(Register ValVReg, Register Addr, uint64_t Size,
149 void assignValueToAddress(Register ValVReg, Register Addr, uint64_t Size,
151 Register ExtReg = extendRegister(ValVReg, VA);
189 ArrayRef<Register> VRegs) const {
237 Register getStackAddress(uint64_t Size, int64_t Offset,
243 Register AddrReg = MRI.createGenericVirtualRegister(
249 void assignValueToAddress(Register ValVReg, Register Addr, uint64_t Size,
249 void assignValueToAddress(Register ValVReg, Register Addr, uint64_t Size,
257 void assignValueToReg(Register ValVReg, Register PhysReg,
257 void assignValueToReg(Register ValVReg, Register PhysReg,
329 ArrayRef<ArrayRef<Register>> VRegs) const {
465 SmallVector<Register, 8> NewRegs;
lib/Target/X86/X86CallLowering.h 32 ArrayRef<Register> VRegs) const override;
35 ArrayRef<ArrayRef<Register>> VRegs) const override;
42 using SplitArgTy = std::function<void(ArrayRef<Register>)>;
lib/Target/X86/X86CmovConversion.cpp 439 Register Reg = MO.getReg();
440 auto &RDM = RegDefMaps[Register::isVirtualRegister(Reg)];
459 Register Reg = MO.getReg();
460 RegDefMaps[Register::isVirtualRegister(Reg)][Reg] = &MI;
713 Register FalseReg =
756 Register TmpReg = MRI->createVirtualRegister(RC);
813 Register DestReg = MIIt->getOperand(0).getReg();
814 Register Op1Reg = MIIt->getOperand(1).getReg();
815 Register Op2Reg = MIIt->getOperand(2).getReg();
lib/Target/X86/X86DomainReassignment.cpp 185 Register Reg = MRI->createVirtualRegister(
222 Register DstReg = MI->getOperand(0).getReg();
223 if (Register::isPhysicalRegister(DstReg) &&
227 Register SrcReg = MI->getOperand(1).getReg();
228 if (Register::isPhysicalRegister(SrcReg) &&
244 if (Register::isPhysicalRegister(MO.getReg()))
439 if (!Register::isVirtualRegister(Reg))
596 Register DefReg = DefOp.getReg();
597 if (!Register::isVirtualRegister(DefReg)) {
754 unsigned Reg = Register::index2VirtReg(Idx);
lib/Target/X86/X86EvexToVex.cpp 134 Register Reg = MO.getReg();
lib/Target/X86/X86ExpandPseudo.cpp 291 Register StackPtr = TRI->getStackRegister();
351 Register SaveRbx = MBBI->getOperand(7).getReg();
lib/Target/X86/X86FastISel.cpp 1246 Register DstReg = VA.getLocReg();
3531 for (auto Reg : OutRegs)
3556 Register SrcReg = VA.getLocReg();
lib/Target/X86/X86FixupBWInsts.cpp 83 Register &SuperDestReg) const;
178 Register &SuperDestReg) const {
181 Register OrigDestReg = OrigMI->getOperand(0).getReg();
277 Register NewDestReg;
304 Register NewDestReg;
308 Register NewSrcReg = getX86SubSuperRegister(OldSrc.getReg(), 32);
337 Register NewDestReg;
lib/Target/X86/X86FixupLEAs.cpp 367 Register DestReg = MI.getOperand(0).getReg();
368 Register BaseReg = Base.getReg();
369 Register IndexReg = Index.getReg();
495 const Register DstR = Dst.getReg();
496 const Register SrcR1 = Base.getReg();
497 const Register SrcR2 = Index.getReg();
547 Register DestReg = Dest.getReg();
548 Register BaseReg = Base.getReg();
549 Register IndexReg = Index.getReg();
lib/Target/X86/X86FixupSetCC.cpp 139 Register ZeroReg = MRI->createVirtualRegister(RC);
140 Register InsertReg = MRI->createVirtualRegister(RC);
lib/Target/X86/X86FlagsCopyLowering.cpp 726 Register::isVirtualRegister(MI.getOperand(0).getReg())) {
743 Register Reg = MRI->createVirtualRegister(PromoteRC);
817 Register TmpReg = MRI->createVirtualRegister(PromoteRC);
978 Register ZeroReg = MRI->createVirtualRegister(&X86::GR32RegClass);
1003 Register ResultReg = MRI->createVirtualRegister(&SetBRC);
lib/Target/X86/X86FloatingPoint.cpp 291 Register DstReg = MI.getOperand(0).getReg();
292 Register SrcReg = MI.getOperand(1).getReg();
316 Register Reg = MO.getReg();
lib/Target/X86/X86FrameLowering.cpp 179 Register Reg = MO.getReg();
219 Register Reg = MO.getReg();
587 const Register SizeReg = InProlog ? X86::RAX
998 Register FramePtr = TRI->getFrameRegister(MF);
999 const Register MachineFramePtr =
1002 Register BasePtr = TRI->getBaseRegister();
1077 Register Establisher = X86::NoRegister;
1188 Register Reg = MBBI->getOperand(0).getReg();
1601 Register FramePtr = TRI->getFrameRegister(MF);
2004 Register FPReg = TRI->getFrameRegister(MF);
2228 Register BasePtr = TRI->getBaseRegister();
2953 Register FramePtr = TRI->getFrameRegister(MF);
2954 Register BasePtr = TRI->getBaseRegister();
lib/Target/X86/X86ISelLowering.cpp 4235 if (!Register::isVirtualRegister(VR))
4460 Register Reg = VA.getLocReg();
22245 Register Vreg = MRI.createVirtualRegister(AddrRegClass);
22255 Register SPReg = RegInfo->getStackRegister();
24252 Register X86TargetLowering::getRegisterByName(const char* RegName, EVT VT,
24256 Register Reg = StringSwitch<unsigned>(RegName)
24270 Register FrameReg = RegInfo->getPtrSizedFrameRegister(MF);
24316 Register FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
28312 Register BasePtr = TRI->getBaseRegister();
29212 Register DstReg = MI.getOperand(0).getReg();
29214 Register mainDstReg = MRI.createVirtualRegister(RC);
29215 Register fallDstReg = MRI.createVirtualRegister(RC);
29269 Register DestReg = MI.getOperand(0).getReg();
29405 Register RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
29415 Register OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
29427 Register NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
29452 Register OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
29466 Register TmpReg = MRI.createVirtualRegister(AddrRegClass);
29483 Register NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
29547 Register CountReg = MI.getOperand(0).getReg();
29684 Register DestReg = MIIt->getOperand(0).getReg();
29685 Register Op1Reg = MIIt->getOperand(1).getReg();
29686 Register Op2Reg = MIIt->getOperand(2).getReg();
29844 Register DestReg = FirstCMOV.getOperand(0).getReg();
29845 Register Op1Reg = FirstCMOV.getOperand(1).getReg();
29846 Register Op2Reg = FirstCMOV.getOperand(2).getReg();
30364 Register CalleeVReg = MI.getOperand(0).getReg();
30437 Register ZReg = MRI.createVirtualRegister(PtrRC);
30445 Register SSPCopyReg = MRI.createVirtualRegister(PtrRC);
30489 Register mainDstReg = MRI.createVirtualRegister(RC);
30490 Register restoreDstReg = MRI.createVirtualRegister(RC);
30604 Register FramePtr = RegInfo->getFrameRegister(*MF);
30605 Register BasePtr = RegInfo->getBaseRegister();
30687 Register ZReg = MRI.createVirtualRegister(PtrRC);
30695 Register SSPCopyReg = MRI.createVirtualRegister(PtrRC);
30710 Register PrevSSPReg = MRI.createVirtualRegister(PtrRC);
30728 Register SspSubReg = MRI.createVirtualRegister(PtrRC);
30742 Register SspFirstShrReg = MRI.createVirtualRegister(PtrRC);
30752 Register SspSecondShrReg = MRI.createVirtualRegister(PtrRC);
30764 Register SspAfterShlReg = MRI.createVirtualRegister(PtrRC);
30769 Register Value128InReg = MRI.createVirtualRegister(PtrRC);
30777 Register DecReg = MRI.createVirtualRegister(PtrRC);
30778 Register CounterReg = MRI.createVirtualRegister(PtrRC);
30818 Register Tmp = MRI.createVirtualRegister(RC);
30822 Register SP = RegInfo->getStackRegister();
31020 Register FP = RI.getFrameRegister(*MF);
31021 Register BP = RI.getBaseRegister();
31032 Register IReg = MRI->createVirtualRegister(&X86::GR32_NOSPRegClass);
31041 Register BReg = MRI->createVirtualRegister(&X86::GR64RegClass);
31042 Register IReg64 = MRI->createVirtualRegister(&X86::GR64_NOSPRegClass);
31068 Register OReg = MRI->createVirtualRegister(&X86::GR32RegClass);
31069 Register OReg64 = MRI->createVirtualRegister(&X86::GR64RegClass);
31070 Register TReg = MRI->createVirtualRegister(&X86::GR64RegClass);
31264 Register OldCW = MF->getRegInfo().createVirtualRegister(&X86::GR32RegClass);
31269 Register NewCW = MF->getRegInfo().createVirtualRegister(&X86::GR32RegClass);
31274 Register NewCW16 =
31379 Register computedAddrVReg = MRI.createVirtualRegister(AddrRegClass);
46192 Register NewVR = MRI->createVirtualRegister(RC);
lib/Target/X86/X86ISelLowering.h 1168 Register getRegisterByName(const char* RegName, EVT VT,
lib/Target/X86/X86InsertPrefetch.cpp 82 Register BaseReg = MI.getOperand(Op + X86::AddrBaseReg).getReg();
83 Register IndexReg = MI.getOperand(Op + X86::AddrIndexReg).getReg();
lib/Target/X86/X86InstrInfo.cpp 468 if (!Register::isVirtualRegister(BaseReg))
605 Register BaseReg = MI.getOperand(1 + X86::AddrBaseReg).getReg();
627 Register BaseReg = MI.getOperand(1 + X86::AddrBaseReg).getReg();
704 unsigned Opc, bool AllowSP, Register &NewSrc,
715 Register SrcReg = Src.getReg();
724 if (Register::isVirtualRegister(NewSrc) &&
733 if (Register::isPhysicalRegister(SrcReg)) {
780 Register InRegLEA = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
781 Register OutRegLEA = RegInfo.createVirtualRegister(&X86::GR32RegClass);
791 Register Dest = MI.getOperand(0).getReg();
792 Register Src = MI.getOperand(1).getReg();
834 Register Src2 = MI.getOperand(2).getReg();
928 if (Register::isVirtualRegister(Src.getReg()) &&
951 Register SrcReg;
987 Register SrcReg;
1010 Register SrcReg;
1045 Register SrcReg;
1053 Register SrcReg2;
1094 Register SrcReg;
1135 Register SrcReg;
1947 Register Op2Reg = MI.getOperand(CommutableOpIdx2).getReg();
3850 Register Reg = MO.getReg();
3880 Register Reg = MIB->getOperand(0).getReg();
3910 Register Reg = MIB->getOperand(0).getReg();
3986 Register Reg = MIB->getOperand(0).getReg();
4024 Register DestReg = MIB->getOperand(0).getReg();
4047 Register SrcReg = MIB->getOperand(X86::AddrNumOperands).getReg();
4108 Register SrcReg = MIB->getOperand(0).getReg();
4109 Register XReg = TRI->getSubReg(SrcReg, X86::sub_xmm);
4120 Register SrcReg = MIB->getOperand(0).getReg();
4134 Register SrcReg = MIB->getOperand(0).getReg();
4137 Register XReg = TRI->getSubReg(SrcReg, X86::sub_xmm);
4157 Register Reg = MIB->getOperand(0).getReg();
4164 Register Reg = MIB->getOperand(0).getReg();
4174 Register Reg = MIB->getOperand(0).getReg();
4175 Register MaskReg = MIB->getOperand(1).getReg();
4212 Register Reg = MIB->getOperand(0).getReg();
4213 Register Reg32 = RI.getSubReg(Reg, X86::sub_32bit);
4348 Register Reg = MO.getReg();
4349 if (Register::isVirtualRegister(Reg)) {
4561 if (MO.isUndef() && Register::isPhysicalRegister(MO.getReg())) {
4569 Register Reg = MI.getOperand(OpNum).getReg();
4585 Register XReg = TRI->getSubReg(Reg, X86::sub_xmm);
4594 Register XReg = TRI->getSubReg(Reg, X86::sub_32bit);
4643 Register Reg = MO.getReg();
4644 if (!Register::isVirtualRegister(Reg))
4928 Register DstReg = NewMI->getOperand(0).getReg();
4929 if (Register::isPhysicalRegister(DstReg))
4943 Register Reg0 = HasDef ? MI.getOperand(0).getReg() : Register();
4944 Register Reg1 = MI.getOperand(CommuteOpIdx1).getReg();
4945 Register Reg2 = MI.getOperand(CommuteOpIdx2).getReg();
7789 Register PBReg = RegInfo.createVirtualRegister(&X86::GR64RegClass);
7790 Register GOTReg = RegInfo.createVirtualRegister(&X86::GR64RegClass);
lib/Target/X86/X86InstrInfo.h 224 unsigned LEAOpcode, bool AllowSP, Register &NewSrc,
lib/Target/X86/X86InstructionSelector.cpp 232 Register DstReg = I.getOperand(0).getReg();
236 Register SrcReg = I.getOperand(1).getReg();
240 if (Register::isPhysicalRegister(DstReg)) {
252 Register ExtSrc = MRI.createVirtualRegister(DstRC);
281 Register::isPhysicalRegister(SrcReg)) {
506 const Register DefReg = I.getOperand(0).getReg();
566 const Register DefReg = I.getOperand(0).getReg();
619 const Register DefReg = I.getOperand(0).getReg();
638 const Register DefReg = I.getOperand(0).getReg();
711 const Register DstReg = I.getOperand(0).getReg();
712 const Register SrcReg = I.getOperand(1).getReg();
775 const Register DstReg = I.getOperand(0).getReg();
776 const Register SrcReg = I.getOperand(1).getReg();
886 const Register DstReg = I.getOperand(0).getReg();
887 const Register SrcReg = I.getOperand(1).getReg();
946 Register LHS = I.getOperand(2).getReg();
947 Register RHS = I.getOperand(3).getReg();
992 Register LhsReg = I.getOperand(2).getReg();
993 Register RhsReg = I.getOperand(3).getReg();
1027 Register ResultReg = I.getOperand(0).getReg();
1037 Register FlagReg1 = MRI.createVirtualRegister(&X86::GR8RegClass);
1038 Register FlagReg2 = MRI.createVirtualRegister(&X86::GR8RegClass);
1083 const Register DstReg = I.getOperand(0).getReg();
1084 const Register CarryOutReg = I.getOperand(1).getReg();
1085 const Register Op0Reg = I.getOperand(2).getReg();
1086 const Register Op1Reg = I.getOperand(3).getReg();
1087 Register CarryInReg = I.getOperand(4).getReg();
1143 const Register DstReg = I.getOperand(0).getReg();
1144 const Register SrcReg = I.getOperand(1).getReg();
1275 const Register DstReg = I.getOperand(0).getReg();
1276 const Register SrcReg = I.getOperand(1).getReg();
1277 const Register InsertReg = I.getOperand(2).getReg();
1335 Register SrcReg = I.getOperand(NumDefs).getReg();
1360 Register DstReg = I.getOperand(0).getReg();
1361 Register SrcReg0 = I.getOperand(1).getReg();
1370 Register DefReg = MRI.createGenericVirtualRegister(DstTy);
1376 Register Tmp = MRI.createGenericVirtualRegister(DstTy);
1407 const Register CondReg = I.getOperand(0).getReg();
1434 const Register DstReg = I.getOperand(0).getReg();
1452 Register AddrReg = MRI.createVirtualRegister(&X86::GR64RegClass);
1495 Register DstReg = I.getOperand(0).getReg();
1526 const Register DstReg = I.getOperand(0).getReg();
1527 const Register Op1Reg = I.getOperand(1).getReg();
1528 const Register Op2Reg = I.getOperand(2).getReg();
1652 Register Zero32 = MRI.createVirtualRegister(&X86::GR32RegClass);
1690 Register SourceSuperReg = MRI.createVirtualRegister(&X86::GR16RegClass);
1691 Register ResultSuperReg = MRI.createVirtualRegister(&X86::GR16RegClass);
lib/Target/X86/X86MCInstLower.cpp 1159 Register DefRegister = FaultingMI.getOperand(0).getReg();
1280 Register ScratchReg = MI.getOperand(ScratchIdx).getReg();
1340 const Register DestRegs[] = {X86::RDI, X86::RSI};
1343 Register SrcRegs[] = {0, 0};
1435 const Register DestRegs[] = {X86::RDI, X86::RSI, X86::RDX};
1439 Register SrcRegs[] = {0, 0, 0};
1854 Register Reg = MI->getOperand(0).getReg();
1901 Register Reg = MI->getOperand(0).getReg();
1902 Register Reg0 = RI->getSubReg(Reg, X86::sub_mask_0);
1903 Register Reg1 = RI->getSubReg(Reg, X86::sub_mask_1);
1932 Register Reg = MI->getOperand(X86::AddrNumOperands).getReg();
1933 Register Reg0 = RI->getSubReg(Reg, X86::sub_mask_0);
1934 Register Reg1 = RI->getSubReg(Reg, X86::sub_mask_1);
lib/Target/X86/X86OptimizeLEAs.cpp 201 (!MO1.isReg() || !Register::isPhysicalRegister(MO1.getReg()));
618 Register FirstVReg = First.getOperand(0).getReg();
619 Register LastVReg = Last.getOperand(0).getReg();
lib/Target/X86/X86RegisterInfo.cpp 555 Register BasePtr = getX86SubSuperRegister(getBaseRegister(), 64);
688 Register BasePtr = MI.getOperand(1).getReg();
694 Register NewDestReg = MI.getOperand(0).getReg();
757 Register MachineBasePtr = BasePtr;
793 Register X86RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
801 Register FrameReg = getFrameRegister(MF);
810 Register StackReg = getStackRegister();
lib/Target/X86/X86RegisterInfo.h 136 Register getFrameRegister(const MachineFunction &MF) const override;
139 Register getStackRegister() const { return StackPtr; }
140 Register getBaseRegister() const { return BasePtr; }
145 Register getFramePtr() const { return FramePtr; }
lib/Target/X86/X86SelectionDAGInfo.cpp 39 Register BaseReg = TRI->getBaseRegister();
lib/Target/X86/X86SpeculativeLoadHardening.cpp 480 Register PredStateSubReg = MRI->createVirtualRegister(&X86::GR32RegClass);
753 Register UpdatedStateReg = MRI->createVirtualRegister(PS->RC);
910 Register Reg = MRI->createVirtualRegister(UnfoldedRC);
1105 Register TargetReg = MRI->createVirtualRegister(&X86::GR64RegClass);
1156 Register AddrReg = MRI->createVirtualRegister(&X86::GR64RegClass);
1178 Register UpdatedStateReg = MRI->createVirtualRegister(PS->RC);
1881 Register Reg = MRI->createVirtualRegister(&X86::GR32RegClass);
1908 Register TmpReg = MRI->createVirtualRegister(PS->RC);
1928 Register PredStateReg = MRI->createVirtualRegister(PS->RC);
1929 Register TmpReg = MRI->createVirtualRegister(PS->RC);
2034 Register OpReg = Op->getReg();
2036 Register TmpReg = MRI->createVirtualRegister(OpRC);
2048 Register VStateReg = MRI->createVirtualRegister(&X86::VR128RegClass);
2057 Register VBStateReg = MRI->createVirtualRegister(OpRC);
2087 Register VStateReg = MRI->createVirtualRegister(OpRC);
2156 Register DefReg = MI.getOperand(0).getReg();
2213 Register UseDefReg = UseMI.getOperand(0).getReg();
2214 if (!Register::isVirtualRegister(UseDefReg) ||
2295 Register NarrowStateReg = MRI->createVirtualRegister(RC);
2305 Register NewReg = MRI->createVirtualRegister(RC);
2335 Register OldDefReg = DefOp.getReg();
2341 Register UnhardenedReg = MRI->createVirtualRegister(DefRC);
2543 Register ActualRetAddrReg = MRI->createVirtualRegister(AddrRC);
2560 Register UpdatedStateReg = MRI->createVirtualRegister(PS->RC);
2617 Register OldTargetReg = TargetOp.getReg();
lib/Target/X86/X86WinAllocaExpander.cpp 84 Register AmountReg = MI->getOperand(0).getReg();
264 Register AmountReg = MI->getOperand(0).getReg();
lib/Target/XCore/XCoreFrameLowering.cpp 370 Register EhStackReg = MBBI->getOperand(0).getReg();
371 Register EhHandlerReg = MBBI->getOperand(1).getReg();
lib/Target/XCore/XCoreFrameToArgsOffsetElim.cpp 58 Register Reg = OldInst.getOperand(0).getReg();
lib/Target/XCore/XCoreISelLowering.cpp 1312 Register VReg = RegInfo.createVirtualRegister(&XCore::GRRegsRegClass);
1363 Register VReg = RegInfo.createVirtualRegister(&XCore::GRRegsRegClass);
lib/Target/XCore/XCoreRegisterInfo.cpp 286 Register FrameReg = getFrameRegister(MF);
304 Register Reg = MI.getOperand(0).getReg();
324 Register XCoreRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
lib/Target/XCore/XCoreRegisterInfo.h 46 Register getFrameRegister(const MachineFunction &MF) const override;
unittests/CodeGen/GlobalISel/GISelMITest.h 127 static void collectCopies(SmallVectorImpl<Register> &Copies,
156 SmallVector<Register, 4> Copies;
unittests/CodeGen/GlobalISel/LegalizerHelperTest.cpp 894 Register Constant0 = B.buildConstant(S16, 1).getReg(0);
895 Register Constant1 = B.buildConstant(S16, 2).getReg(0);
947 SmallVector<Register, 8> Merge0Ops;
956 SmallVector<Register, 8> Merge1Ops;
962 SmallVector<Register, 8> Merge2Ops;
unittests/CodeGen/GlobalISel/MachineIRBuilderTest.cpp 81 SmallVector<Register, 4> Copies;
107 SmallVector<Register, 4> Copies;
128 SmallVector<Register, 4> Copies;
165 SmallVector<Register, 4> Copies;
173 SmallVector<Register, 1> Results;
195 SmallVector<Register, 4> Copies;
223 SmallVector<Register, 4> Copies;
251 SmallVector<Register, 4> Copies;
276 SmallVector<Register, 4> Copies;
303 SmallVector<Register, 4> Copies;
333 Register RegC0 = B.buildConstant(S32, 0)->getOperand(0).getReg();
334 Register RegC1 = B.buildConstant(S32, 1)->getOperand(0).getReg();
335 Register RegC2 = B.buildConstant(S32, 2)->getOperand(0).getReg();
336 Register RegC3 = B.buildConstant(S32, 3)->getOperand(0).getReg();
343 Register RegC0C1 =
345 Register RegC2C3 =
unittests/CodeGen/GlobalISel/PatternMatchTest.cpp 54 Register Src0, Src1, Src2;
147 Register Src;
206 Register Src0;
269 Register Src0;
286 Register Src0, Src1;
unittests/CodeGen/MachineInstrTest.cpp 94 Register getFrameRegister(const MachineFunction &MF) const override {
usr/include/c++/7.4.0/bits/alloc_traits.h 387 using allocator_type = allocator<_Tp>;
389 using value_type = _Tp;
392 using pointer = _Tp*;
395 using const_pointer = const _Tp*;
474 construct(allocator_type& __a, _Up* __p, _Args&&... __args)
474 construct(allocator_type& __a, _Up* __p, _Args&&... __args)
475 { __a.construct(__p, std::forward<_Args>(__args)...); }
486 destroy(allocator_type& __a, _Up* __p)
usr/include/c++/7.4.0/bits/allocator.h 108 class allocator: public __allocator_base<_Tp>
113 typedef _Tp* pointer;
114 typedef const _Tp* const_pointer;
115 typedef _Tp& reference;
116 typedef const _Tp& const_reference;
117 typedef _Tp value_type;
137 allocator(const allocator<_Tp1>&) throw() { }
usr/include/c++/7.4.0/bits/move.h 46 inline _GLIBCXX_CONSTEXPR _Tp*
47 __addressof(_Tp& __r) _GLIBCXX_NOEXCEPT
72 constexpr _Tp&&
73 forward(typename std::remove_reference<_Tp>::type& __t) noexcept
83 constexpr _Tp&&
84 forward(typename std::remove_reference<_Tp>::type&& __t) noexcept
98 move(_Tp&& __t) noexcept
104 : public __and_<__not_<is_nothrow_move_constructible<_Tp>>,
105 is_copy_constructible<_Tp>>::type { };
136 inline _GLIBCXX17_CONSTEXPR _Tp*
137 addressof(_Tp& __r) noexcept
143 const _Tp* addressof(const _Tp&&) = delete;
143 const _Tp* addressof(const _Tp&&) = delete;
184 typename enable_if<__and_<__not_<__is_tuple_like<_Tp>>,
185 is_move_constructible<_Tp>,
186 is_move_assignable<_Tp>>::value>::type
187 swap(_Tp& __a, _Tp& __b)
187 swap(_Tp& __a, _Tp& __b)
198 _Tp __tmp = _GLIBCXX_MOVE(__a);
usr/include/c++/7.4.0/bits/std_function.h 395 struct _Callable : __check_func_return_type<_Res2, _Res> { };
usr/include/c++/7.4.0/bits/stl_algo.h 3456 min(initializer_list<_Tp> __l, _Compare __comp)
3900 const _Tp& __val)
usr/include/c++/7.4.0/bits/stl_construct.h 74 _Construct(_T1* __p, _Args&&... __args)
74 _Construct(_T1* __p, _Args&&... __args)
75 { ::new(static_cast<void*>(__p)) _T1(std::forward<_Args>(__args)...); }
75 { ::new(static_cast<void*>(__p)) _T1(std::forward<_Args>(__args)...); }
204 allocator<_Tp>&)
usr/include/c++/7.4.0/bits/stl_function.h 108 typedef _Arg argument_type;
111 typedef _Result result_type;
121 typedef _Arg1 first_argument_type;
124 typedef _Arg2 second_argument_type;
381 struct less : public binary_function<_Tp, _Tp, bool>
381 struct less : public binary_function<_Tp, _Tp, bool>
385 operator()(const _Tp& __x, const _Tp& __y) const
385 operator()(const _Tp& __x, const _Tp& __y) const
870 : public unary_function<_Tp,_Tp>
870 : public unary_function<_Tp,_Tp>
872 _Tp&
873 operator()(_Tp& __x) const
876 const _Tp&
877 operator()(const _Tp& __x) const
usr/include/c++/7.4.0/bits/stl_iterator.h 1224 __make_move_if_noexcept_iterator(_Tp* __i)
usr/include/c++/7.4.0/bits/stl_iterator_base_types.h 181 typedef _Tp value_type;
183 typedef _Tp* pointer;
184 typedef _Tp& reference;
192 typedef _Tp value_type;
194 typedef const _Tp* pointer;
195 typedef const _Tp& reference;
usr/include/c++/7.4.0/bits/stl_pair.h 100 return __and_<is_constructible<_T1, const _U1&>,
100 return __and_<is_constructible<_T1, const _U1&>,
101 is_constructible<_T2, const _U2&>>::value;
101 is_constructible<_T2, const _U2&>>::value;
107 return __and_<is_convertible<const _U1&, _T1>,
107 return __and_<is_convertible<const _U1&, _T1>,
108 is_convertible<const _U2&, _T2>>::value;
108 is_convertible<const _U2&, _T2>>::value;
114 return __and_<is_constructible<_T1, _U1&&>,
114 return __and_<is_constructible<_T1, _U1&&>,
115 is_constructible<_T2, _U2&&>>::value;
115 is_constructible<_T2, _U2&&>>::value;
121 return __and_<is_convertible<_U1&&, _T1>,
121 return __and_<is_convertible<_U1&&, _T1>,
122 is_convertible<_U2&&, _T2>>::value;
122 is_convertible<_U2&&, _T2>>::value;
128 using __do_converts = __and_<is_convertible<const _U1&, _T1>,
128 using __do_converts = __and_<is_convertible<const _U1&, _T1>,
129 is_convertible<_U2&&, _T2>>;
129 is_convertible<_U2&&, _T2>>;
133 return __and_<is_constructible<_T1, const _U1&>,
133 return __and_<is_constructible<_T1, const _U1&>,
134 is_constructible<_T2, _U2&&>,
134 is_constructible<_T2, _U2&&>,
142 using __do_converts = __and_<is_convertible<_U1&&, _T1>,
142 using __do_converts = __and_<is_convertible<_U1&&, _T1>,
143 is_convertible<const _U2&, _T2>>;
143 is_convertible<const _U2&, _T2>>;
147 return __and_<is_constructible<_T1, _U1&&>,
147 return __and_<is_constructible<_T1, _U1&&>,
148 is_constructible<_T2, const _U2&&>,
148 is_constructible<_T2, const _U2&&>,
209 : private __pair_base<_T1, _T2>
209 : private __pair_base<_T1, _T2>
211 typedef _T1 first_type; /// @c first_type is the first bound type
212 typedef _T2 second_type; /// @c second_type is the second bound type
214 _T1 first; /// @c first is a copy of the first object
215 _T2 second; /// @c second is a copy of the second object
252 using _PCCP = _PCC<true, _T1, _T2>;
252 using _PCCP = _PCC<true, _T1, _T2>;
260 constexpr pair(const _T1& __a, const _T2& __b)
260 constexpr pair(const _T1& __a, const _T2& __b)
269 explicit constexpr pair(const _T1& __a, const _T2& __b)
269 explicit constexpr pair(const _T1& __a, const _T2& __b)
283 _T1, _T2>;
283 _T1, _T2>;
291 constexpr pair(const pair<_U1, _U2>& __p)
291 constexpr pair(const pair<_U1, _U2>& __p)
311 constexpr pair(_U1&& __x, const _T2& __y)
311 constexpr pair(_U1&& __x, const _T2& __y)
318 explicit constexpr pair(_U1&& __x, const _T2& __y)
325 constexpr pair(const _T1& __x, _U2&& __y)
325 constexpr pair(const _T1& __x, _U2&& __y)
332 explicit pair(const _T1& __x, _U2&& __y)
341 constexpr pair(_U1&& __x, _U2&& __y)
341 constexpr pair(_U1&& __x, _U2&& __y)
342 : first(std::forward<_U1>(__x)), second(std::forward<_U2>(__y)) { }
342 : first(std::forward<_U1>(__x)), second(std::forward<_U2>(__y)) { }
360 constexpr pair(pair<_U1, _U2>&& __p)
360 constexpr pair(pair<_U1, _U2>&& __p)
361 : first(std::forward<_U1>(__p.first)),
362 second(std::forward<_U2>(__p.second)) { }
379 __and_<is_copy_assignable<_T1>,
380 is_copy_assignable<_T2>>::value,
390 __and_<is_move_assignable<_T1>,
391 is_move_assignable<_T2>>::value,
402 typename enable_if<__and_<is_assignable<_T1&, const _U1&>,
402 typename enable_if<__and_<is_assignable<_T1&, const _U1&>,
403 is_assignable<_T2&, const _U2&>>::value,
403 is_assignable<_T2&, const _U2&>>::value,
405 operator=(const pair<_U1, _U2>& __p)
405 operator=(const pair<_U1, _U2>& __p)
413 typename enable_if<__and_<is_assignable<_T1&, _U1&&>,
413 typename enable_if<__and_<is_assignable<_T1&, _U1&&>,
414 is_assignable<_T2&, _U2&&>>::value,
414 is_assignable<_T2&, _U2&&>>::value,
416 operator=(pair<_U1, _U2>&& __p)
416 operator=(pair<_U1, _U2>&& __p)
418 first = std::forward<_U1>(__p.first);
419 second = std::forward<_U2>(__p.second);
522 constexpr pair<typename __decay_and_strip<_T1>::__type,
523 typename __decay_and_strip<_T2>::__type>
524 make_pair(_T1&& __x, _T2&& __y)
524 make_pair(_T1&& __x, _T2&& __y)
526 typedef typename __decay_and_strip<_T1>::__type __ds_type1;
527 typedef typename __decay_and_strip<_T2>::__type __ds_type2;
529 return __pair_type(std::forward<_T1>(__x), std::forward<_T2>(__y));
529 return __pair_type(std::forward<_T1>(__x), std::forward<_T2>(__y));
usr/include/c++/7.4.0/bits/stl_set.h 110 typedef _Key key_type;
111 typedef _Key value_type;
119 rebind<_Key>::other _Key_alloc_type;
usr/include/c++/7.4.0/bits/stl_tree.h 218 typedef _Rb_tree_node<_Val>* _Link_type;
231 __gnu_cxx::__aligned_membuf<_Val> _M_storage;
233 _Val*
237 const _Val*
258 typedef _Tp value_type;
259 typedef _Tp& reference;
260 typedef _Tp* pointer;
265 typedef _Rb_tree_iterator<_Tp> _Self;
267 typedef _Rb_tree_node<_Tp>* _Link_type;
328 typedef _Tp value_type;
329 typedef const _Tp& reference;
330 typedef const _Tp* pointer;
332 typedef _Rb_tree_iterator<_Tp> iterator;
337 typedef _Rb_tree_const_iterator<_Tp> _Self;
339 typedef const _Rb_tree_node<_Tp>* _Link_type;
447 rebind<_Rb_tree_node<_Val> >::other _Node_allocator;
454 typedef _Rb_tree_node<_Val>* _Link_type;
455 typedef const _Rb_tree_node<_Val>* _Const_Link_type;
554 operator()(_Arg&& __arg) const
563 typedef _Key key_type;
564 typedef _Val value_type;
621 _M_construct_node(_Link_type __node, _Args&&... __args)
625 ::new(__node) _Rb_tree_node<_Val>;
640 _M_create_node(_Args&&... __args)
758 static const _Key&
782 static const _Key&
834 _M_insert_(_Base_ptr __x, _Base_ptr __y, _Arg&& __v, _NodeGen&);
894 const _Key& __k);
898 const _Key& __k) const;
902 const _Key& __k);
906 const _Key& __k) const;
1011 _M_insert_unique(_Arg&& __x);
usr/include/c++/7.4.0/bits/stl_uninitialized.h 144 const _Tp& __x)
182 const _Tp& __x)
288 _ForwardIterator __result, allocator<_Tp>&)
usr/include/c++/7.4.0/bits/stl_vector.h 77 rebind<_Tp>::other _Tp_alloc_type;
216 class vector : protected _Vector_base<_Tp, _Alloc>
227 typedef _Vector_base<_Tp, _Alloc> _Base;
232 typedef _Tp value_type;
919 _Tp*
923 const _Tp*
962 emplace_back(_Args&&... __args);
1483 _M_realloc_insert(iterator __position, _Args&&... __args);
usr/include/c++/7.4.0/bits/vector.tcc 101 std::forward<_Args>(__args)...);
105 _M_realloc_insert(end(), std::forward<_Args>(__args)...);
418 std::forward<_Args>(__args)...);
usr/include/c++/7.4.0/ext/aligned_buffer.h 52 struct _Tp2 { _Tp _M_t; };
54 alignas(__alignof__(_Tp2::_M_t)) unsigned char _M_storage[sizeof(_Tp)];
69 _Tp*
73 const _Tp*
usr/include/c++/7.4.0/ext/alloc_traits.h 117 { typedef typename _Base_type::template rebind_alloc<_Tp> other; };
usr/include/c++/7.4.0/ext/new_allocator.h 63 typedef _Tp* pointer;
64 typedef const _Tp* const_pointer;
65 typedef _Tp& reference;
66 typedef const _Tp& const_reference;
67 typedef _Tp value_type;
111 return static_cast<_Tp*>(::operator new(__n * sizeof(_Tp)));
130 { return size_t(-1) / sizeof(_Tp); }
135 construct(_Up* __p, _Args&&... __args)
135 construct(_Up* __p, _Args&&... __args)
136 { ::new((void *)__p) _Up(std::forward<_Args>(__args)...); }
136 { ::new((void *)__p) _Up(std::forward<_Args>(__args)...); }
140 destroy(_Up* __p) { __p->~_Up(); }
usr/include/c++/7.4.0/initializer_list 50 typedef _E value_type;
51 typedef const _E& reference;
52 typedef const _E& const_reference;
54 typedef const _E* iterator;
55 typedef const _E* const_iterator;
usr/include/c++/7.4.0/tuple 56 struct __is_empty_non_tuple : is_empty<_Tp> { };
125 constexpr _Head_base(const _Head& __h)
132 constexpr _Head_base(_UHead&& __h)
133 : _M_head_impl(std::forward<_UHead>(__h)) { }
159 static constexpr _Head&
162 static constexpr const _Head&
165 _Head _M_head_impl;
186 : public _Tuple_impl<_Idx + 1, _Tail...>,
187 private _Head_base<_Idx, _Head>
191 typedef _Tuple_impl<_Idx + 1, _Tail...> _Inherited;
192 typedef _Head_base<_Idx, _Head> _Base;
194 static constexpr _Head&
197 static constexpr const _Head&
210 constexpr _Tuple_impl(const _Head& __head, const _Tail&... __tail)
210 constexpr _Tuple_impl(const _Head& __head, const _Tail&... __tail)
216 constexpr _Tuple_impl(_UHead&& __head, _UTail&&... __tail)
216 constexpr _Tuple_impl(_UHead&& __head, _UTail&&... __tail)
218 _Base(std::forward<_UHead>(__head)) { }
227 _Base(std::forward<_Head>(_M_head(__in))) { }
230 constexpr _Tuple_impl(const _Tuple_impl<_Idx, _UElements...>& __in)
235 constexpr _Tuple_impl(_Tuple_impl<_Idx, _UHead, _UTails...>&& __in)
235 constexpr _Tuple_impl(_Tuple_impl<_Idx, _UHead, _UTails...>&& __in)
237 (_Tuple_impl<_Idx, _UHead, _UTails...>::_M_tail(__in))),
237 (_Tuple_impl<_Idx, _UHead, _UTails...>::_M_tail(__in))),
238 _Base(std::forward<_UHead>
239 (_Tuple_impl<_Idx, _UHead, _UTails...>::_M_head(__in))) { }
239 (_Tuple_impl<_Idx, _UHead, _UTails...>::_M_head(__in))) { }
242 _Tuple_impl(allocator_arg_t __tag, const _Alloc& __a)
248 const _Head& __head, const _Tail&... __tail)
248 const _Head& __head, const _Tail&... __tail)
262 _Tuple_impl(allocator_arg_t __tag, const _Alloc& __a,
268 _Tuple_impl(allocator_arg_t __tag, const _Alloc& __a,
322 _M_head(*this) = std::forward<_UHead>
323 (_Tuple_impl<_Idx, _UHead, _UTails...>::_M_head(__in));
325 (_Tuple_impl<_Idx, _UHead, _UTails...>::_M_tail(__in));
344 : private _Head_base<_Idx, _Head>
348 typedef _Head_base<_Idx, _Head> _Base;
350 static constexpr _Head&
353 static constexpr const _Head&
360 constexpr _Tuple_impl(const _Head& __head)
365 constexpr _Tuple_impl(_UHead&& __head)
373 : _Base(std::forward<_Head>(_M_head(__in))) { }
376 constexpr _Tuple_impl(const _Tuple_impl<_Idx, _UHead>& __in)
380 constexpr _Tuple_impl(_Tuple_impl<_Idx, _UHead>&& __in)
381 : _Base(std::forward<_UHead>(_Tuple_impl<_Idx, _UHead>::_M_head(__in)))
381 : _Base(std::forward<_UHead>(_Tuple_impl<_Idx, _UHead>::_M_head(__in)))
390 const _Head& __head)
473 return __and_<is_constructible<_Elements, const _UElements&>...>::value;
473 return __and_<is_constructible<_Elements, const _UElements&>...>::value;
479 return __and_<is_convertible<const _UElements&, _Elements>...>::value;
479 return __and_<is_convertible<const _UElements&, _Elements>...>::value;
485 return __and_<is_constructible<_Elements, _UElements&&>...>::value;
485 return __and_<is_constructible<_Elements, _UElements&&>...>::value;
491 return __and_<is_convertible<_UElements&&, _Elements>...>::value;
491 return __and_<is_convertible<_UElements&&, _Elements>...>::value;
508 return __not_<is_same<tuple<_Elements...>,
556 class tuple : public _Tuple_impl<0, _Elements...>
558 typedef _Tuple_impl<0, _Elements...> _Inherited;
598 _Elements...>;
608 constexpr tuple(const _Elements&... __elements)
619 explicit constexpr tuple(const _Elements&... __elements)
628 _Elements...>;
636 _Elements...>;
646 constexpr tuple(_UElements&&... __elements)
647 : _Inherited(std::forward<_UElements>(__elements)...) { }
668 _Elements...>;
678 constexpr tuple(const tuple<_UElements...>& __in)
702 constexpr tuple(tuple<_UElements...>&& __in)
730 const _Elements&... __elements)
741 const _Elements&... __elements)
767 tuple(allocator_arg_t __tag, const _Alloc& __a, const tuple& __in)
771 tuple(allocator_arg_t __tag, const _Alloc& __a, tuple&& __in)
853 operator=(const tuple<_UElements...>& __in)
863 operator=(tuple<_UElements...>&& __in)
907 class tuple<_T1, _T2> : public _Tuple_impl<0, _T1, _T2>
909 typedef _Tuple_impl<0, _T1, _T2> _Inherited;
939 _TC<is_same<_Dummy, void>::value, _T1, _T2>;
947 constexpr tuple(const _T1& __a1, const _T2& __a2)
947 constexpr tuple(const _T1& __a1, const _T2& __a2)
956 explicit constexpr tuple(const _T1& __a1, const _T2& __a2)
956 explicit constexpr tuple(const _T1& __a1, const _T2& __a2)
961 using _TMC = _TC<true, _T1, _T2>;
971 constexpr tuple(_U1&& __a1, _U2&& __a2)
971 constexpr tuple(_U1&& __a1, _U2&& __a2)
995 constexpr tuple(const tuple<_U1, _U2>& __in)
1013 constexpr tuple(tuple<_U1, _U2>&& __in)
1066 tuple(allocator_arg_t __tag, const _Alloc& __a)
1078 const _T1& __a1, const _T2& __a2)
1078 const _T1& __a1, const _T2& __a2)
1090 const _T1& __a1, const _T2& __a2)
1090 const _T1& __a1, const _T2& __a2)
1241 operator=(const pair<_U1, _U2>& __in)
1250 operator=(pair<_U1, _U2>&& __in)
1252 this->_M_head(*this) = std::forward<_U1>(__in.first);
1288 typedef _Head type;
1302 constexpr _Head&
1303 __get_helper(_Tuple_impl<__i, _Head, _Tail...>& __t) noexcept
1307 constexpr const _Head&
1308 __get_helper(const _Tuple_impl<__i, _Head, _Tail...>& __t) noexcept
1309 { return _Tuple_impl<__i, _Head, _Tail...>::_M_head(__t); }
1313 constexpr __tuple_element_t<__i, tuple<_Elements...>>&
1313 constexpr __tuple_element_t<__i, tuple<_Elements...>>&
1313 constexpr __tuple_element_t<__i, tuple<_Elements...>>&
1314 get(tuple<_Elements...>& __t) noexcept
1319 constexpr const __tuple_element_t<__i, tuple<_Elements...>>&
1319 constexpr const __tuple_element_t<__i, tuple<_Elements...>>&
1319 constexpr const __tuple_element_t<__i, tuple<_Elements...>>&
1320 get(const tuple<_Elements...>& __t) noexcept
1325 constexpr __tuple_element_t<__i, tuple<_Elements...>>&&
1325 constexpr __tuple_element_t<__i, tuple<_Elements...>>&&
1325 constexpr __tuple_element_t<__i, tuple<_Elements...>>&&
1326 get(tuple<_Elements...>&& __t) noexcept
1410 operator<(const tuple<_TElements...>& __t,
1411 const tuple<_UElements...>& __u)
1415 using __compare = __tuple_compare<tuple<_TElements...>,
1416 tuple<_UElements...>,
1447 constexpr tuple<typename __decay_and_strip<_Elements>::__type...>
1448 make_tuple(_Elements&&... __args)
1450 typedef tuple<typename __decay_and_strip<_Elements>::__type...>
1452 return __result_type(std::forward<_Elements>(__args)...);
1588 constexpr tuple<_Elements&...>
1589 tie(_Elements&... __args) noexcept
usr/include/c++/7.4.0/type_traits 194 { typedef _Tp type; };
215 : public __is_void_helper<typename remove_cv<_Tp>::type>::type
326 : public __is_integral_helper<typename remove_cv<_Tp>::type>::type
354 : public __is_floating_point_helper<typename remove_cv<_Tp>::type>::type
381 : public __is_pointer_helper<typename remove_cv<_Tp>::type>::type
567 : public __is_null_pointer_helper<typename remove_cv<_Tp>::type>::type
581 : public __or_<is_lvalue_reference<_Tp>,
582 is_rvalue_reference<_Tp>>::type
588 : public __or_<is_integral<_Tp>, is_floating_point<_Tp>>::type
588 : public __or_<is_integral<_Tp>, is_floating_point<_Tp>>::type
601 : public __not_<__or_<is_function<_Tp>, is_reference<_Tp>,
601 : public __not_<__or_<is_function<_Tp>, is_reference<_Tp>,
602 is_void<_Tp>>>::type
611 : public __or_<is_arithmetic<_Tp>, is_enum<_Tp>, is_pointer<_Tp>,
611 : public __or_<is_arithmetic<_Tp>, is_enum<_Tp>, is_pointer<_Tp>,
611 : public __or_<is_arithmetic<_Tp>, is_enum<_Tp>, is_pointer<_Tp>,
612 is_member_pointer<_Tp>, is_null_pointer<_Tp>>::type
612 is_member_pointer<_Tp>, is_null_pointer<_Tp>>::type
631 : public __is_member_pointer_helper<typename remove_cv<_Tp>::type>::type
638 : public __or_<is_object<_Tp>, is_reference<_Tp>>::type
638 : public __or_<is_object<_Tp>, is_reference<_Tp>>::type
762 typename add_rvalue_reference<_Tp>::type declval() noexcept;
777 : public __and_<is_array<_Tp>, __not_<extent<_Tp>>>
777 : public __and_<is_array<_Tp>, __not_<extent<_Tp>>>
798 typedef decltype(__test<_Tp>(0)) type;
811 remove_all_extents<_Tp>::type>::type
825 : public __is_destructible_safe<_Tp>::type
889 typedef decltype(__test<_Tp>(0)) type;
894 : public __and_<__not_<is_void<_Tp>>,
895 __is_default_constructible_impl<_Tp>>
915 : public __is_default_constructible_atom<_Tp>::type
921 : public __is_default_constructible_safe<_Tp>::type
984 typedef decltype(__test<_Tp, _Arg>(0)) type;
989 : public __and_<is_destructible<_Tp>,
990 __is_direct_constructible_impl<_Tp, _Arg>>
1072 __is_direct_constructible_ref_cast<_Tp, _Arg>,
1073 __is_direct_constructible_new_safe<_Tp, _Arg>
1079 : public __is_direct_constructible_new<_Tp, _Arg>::type
1119 : public __is_direct_constructible<_Tp, _Arg>
1130 : public __is_constructible_impl<_Tp, _Args...>::type
1142 : public is_constructible<_Tp, const _Tp&>
1142 : public is_constructible<_Tp, const _Tp&>
1148 : public __is_copy_constructible_impl<_Tp>
1160 : public is_constructible<_Tp, _Tp&&>
1160 : public is_constructible<_Tp, _Tp&&>
1166 : public __is_move_constructible_impl<_Tp>
1215 : public __and_<is_constructible<_Tp, _Args...>,
1216 __is_nt_constructible_impl<_Tp, _Args...>>
1246 : public is_nothrow_constructible<_Tp, _Tp&&>
1246 : public is_nothrow_constructible<_Tp, _Tp&&>
1252 : public __is_nothrow_move_constructible_impl<_Tp>
1286 : public is_assignable<_Tp&, const _Tp&>
1286 : public is_assignable<_Tp&, const _Tp&>
1292 : public __is_copy_assignable_impl<_Tp>
1304 : public is_assignable<_Tp&, _Tp&&>
1304 : public is_assignable<_Tp&, _Tp&&>
1310 : public __is_move_assignable_impl<_Tp>
1352 : public is_nothrow_assignable<_Tp&, _Tp&&>
1352 : public is_nothrow_assignable<_Tp&, _Tp&&>
1358 : public __is_nt_move_assignable_impl<_Tp>
1377 static void __helper(const _Tp&);
1380 static true_type __test(const _Tp&,
1381 decltype(__helper<const _Tp&>({}))* = 0);
1390 typedef decltype(__test(declval<_Tp>())) type;
1395 : public __is_implicitly_default_constructible_impl<_Tp>::type
1400 : public __and_<is_default_constructible<_Tp>,
1401 __is_implicitly_default_constructible_safe<_Tp>>
1526 static void __test_aux(_To1);
1538 typedef decltype(__test<_From, _To>(0)) type;
1538 typedef decltype(__test<_From, _To>(0)) type;
1545 : public __is_convertible_helper<_From, _To>::type
1545 : public __is_convertible_helper<_From, _To>::type
1554 { typedef _Tp type; };
1558 { typedef _Tp type; };
1563 { typedef _Tp type; };
1574 remove_const<typename remove_volatile<_Tp>::type>::type type;
1629 { typedef _Tp type; };
1633 { typedef _Tp type; };
1659 { typedef _Tp&& type; };
1664 : public __add_rvalue_reference_helper<_Tp>
1955 { typedef _Tp type; };
2104 { typedef typename remove_cv<_Up>::type __type; };
2118 typedef typename remove_reference<_Tp>::type __remove_type;
2131 typedef _Tp __type;
2144 typename decay<_Tp>::type>::__type __type;
2277 struct __result_of_success : __success_type<_Tp>
2427 static __result_of_success<decltype(
2574 typename remove_reference<_Tp>::type>::type>::type
utils/unittest/googletest/include/gtest/gtest-printers.h 173 static void PrintValue(const T& value, ::std::ostream* os) {
205 ::std::basic_ostream<Char, CharTraits>& os, const T& x) {
206 TypeWithoutFormatter<T,
207 (internal::IsAProtocolMessage<T>::value ? kProtobuf :
208 internal::ImplicitlyConvertible<const T&, internal::BiggestInt>::value ?
223 void DefaultPrintNonContainerTo(const T& value, ::std::ostream* os) {
276 static ::std::string Format(const ToPrint& value) {
351 const T1& value, const T2& /* other_operand */) {
351 const T1& value, const T2& /* other_operand */) {
352 return FormatForComparison<T1, T2>::Format(value);
352 return FormatForComparison<T1, T2>::Format(value);
366 void UniversalPrint(const T& value, ::std::ostream* os);
373 const C& container, ::std::ostream* os) {
439 const T& value, ::std::ostream* os) {
455 void PrintTo(const T& value, ::std::ostream* os) {
478 DefaultPrintTo(IsContainerTest<T>(0), is_pointer<T>(), value, os);
699 static void Print(const T& value, ::std::ostream* os) {
784 static void Print(const T& value, ::std::ostream* os) {
856 typedef T T1;
983 internal::UniversalTersePrinter<T>::Print(value, &ss);
utils/unittest/googletest/include/gtest/gtest.h 1377 const T1& lhs, const T2& rhs) {
1377 const T1& lhs, const T2& rhs) {
1389 const T1& lhs,
1390 const T2& rhs) {
1419 const T1& lhs,
1420 const T2& rhs) {
utils/unittest/googletest/include/gtest/internal/custom/raw-ostream.h 29 static const T& printable(const T& V) { return V; }
29 static const T& printable(const T& V) { return V; }
35 auto printable(const T &V) -> decltype(StreamSwitch<T>::printable(V)) {
35 auto printable(const T &V) -> decltype(StreamSwitch<T>::printable(V)) {
37 return StreamSwitch<T>::printable(V);
utils/unittest/googletest/include/gtest/internal/gtest-internal.h 94 ::std::string PrintToString(const T& value);