|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
Declarations
include/llvm/CodeGen/FastISel.h 50 class MachineRegisterInfo;
include/llvm/CodeGen/FunctionLoweringInfo.h 44 class MachineRegisterInfo;
include/llvm/CodeGen/GlobalISel/CallLowering.h 36 class MachineRegisterInfo;
include/llvm/CodeGen/GlobalISel/Combiner.h 21 class MachineRegisterInfo;
include/llvm/CodeGen/GlobalISel/CombinerHelper.h 27 class MachineRegisterInfo;
include/llvm/CodeGen/GlobalISel/CombinerInfo.h 23 class MachineRegisterInfo;
include/llvm/CodeGen/GlobalISel/GISelChangeObserver.h 21 class MachineRegisterInfo;
include/llvm/CodeGen/GlobalISel/IRTranslator.h 46 class MachineRegisterInfo;
include/llvm/CodeGen/GlobalISel/InstructionSelector.h 39 class MachineRegisterInfo;
include/llvm/CodeGen/GlobalISel/Legalizer.h 28 class MachineRegisterInfo;
include/llvm/CodeGen/GlobalISel/LegalizerHelper.h 33 class MachineRegisterInfo;
include/llvm/CodeGen/GlobalISel/LegalizerInfo.h 39 class MachineRegisterInfo;
include/llvm/CodeGen/GlobalISel/Localizer.h 30 class MachineRegisterInfo;
include/llvm/CodeGen/GlobalISel/RegBankSelect.h 82 class MachineRegisterInfo;
include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h 30 class MachineRegisterInfo;
include/llvm/CodeGen/GlobalISel/Utils.h 30 class MachineRegisterInfo;
include/llvm/CodeGen/LiveInterval.h 45 class MachineRegisterInfo;
include/llvm/CodeGen/LiveIntervals.h 49 class MachineRegisterInfo;
include/llvm/CodeGen/LivePhysRegs.h 43 class MachineRegisterInfo;
include/llvm/CodeGen/LiveRangeCalc.h 40 class MachineRegisterInfo;
include/llvm/CodeGen/LiveVariables.h 43 class MachineRegisterInfo;
include/llvm/CodeGen/MachineFunction.h 63 class MachineRegisterInfo;
include/llvm/CodeGen/MachineInstr.h 46 class MachineRegisterInfo;
include/llvm/CodeGen/MachineLoopUtils.h 14 class MachineRegisterInfo;
include/llvm/CodeGen/MachineOperand.h 32 class MachineRegisterInfo;
include/llvm/CodeGen/MachineSSAUpdater.h 22 class MachineRegisterInfo;
include/llvm/CodeGen/MachineTraceMetrics.h 65 class MachineRegisterInfo;
include/llvm/CodeGen/RegisterPressure.h 36 class MachineRegisterInfo;
include/llvm/CodeGen/ScheduleDAG.h 37 class MachineRegisterInfo;
include/llvm/CodeGen/SelectionDAGISel.h 29 class MachineRegisterInfo;
include/llvm/CodeGen/TailDuplicator.h 32 class MachineRegisterInfo;
include/llvm/CodeGen/TargetInstrInfo.h 48 class MachineRegisterInfo;
include/llvm/CodeGen/TargetLowering.h 85 class MachineRegisterInfo;
include/llvm/CodeGen/VirtRegMap.h 29 class MachineRegisterInfo;
lib/CodeGen/AggressiveAntiDepBreaker.h 33 class MachineRegisterInfo;
lib/CodeGen/BranchFolding.h 29 class MachineRegisterInfo;
lib/CodeGen/CriticalAntiDepBreaker.h 30 class MachineRegisterInfo;
lib/CodeGen/RegAllocBase.h 48 class MachineRegisterInfo;
lib/CodeGen/SplitKit.h 42 class MachineRegisterInfo;
lib/Target/AArch64/AArch64CallLowering.h 29 class MachineRegisterInfo;
lib/Target/AMDGPU/AMDGPUInstructionSelector.h 40 class MachineRegisterInfo;
lib/Target/AMDGPU/GCNHazardRecognizer.h 27 class MachineRegisterInfo;
lib/Target/AMDGPU/GCNRegPressure.h 25 class MachineRegisterInfo;
lib/Target/AMDGPU/SIInstrInfo.h 40 class MachineRegisterInfo;
lib/Target/AMDGPU/SIRegisterInfo.h 25 class MachineRegisterInfo;
lib/Target/Hexagon/BitTracker.h 28 class MachineRegisterInfo;
lib/Target/Hexagon/HexagonBitTracker.h 23 class MachineRegisterInfo;
lib/Target/Hexagon/HexagonBlockRanges.h 25 class MachineRegisterInfo;
lib/Target/Hexagon/HexagonFrameLowering.h 27 class MachineRegisterInfo;
lib/Target/Hexagon/RDFDeadCode.h 31 class MachineRegisterInfo;
lib/Target/Hexagon/RDFLiveness.h 28 class MachineRegisterInfo;
lib/Target/X86/X86CallLowering.h 24 class MachineRegisterInfo;
References
gen/lib/Target/AArch64/AArch64GenGICombiner.inc 103 MachineRegisterInfo &MRI = MF->getRegInfo();
gen/lib/Target/AArch64/AArch64GenGlobalISel.inc 885 const MachineRegisterInfo &MRI = MF.getRegInfo();
1021 MachineRegisterInfo &MRI = MF.getRegInfo();
gen/lib/Target/AMDGPU/AMDGPUGenGlobalISel.inc 378 const MachineRegisterInfo &MRI = MF.getRegInfo();
440 MachineRegisterInfo &MRI = MF.getRegInfo();
gen/lib/Target/ARM/ARMGenGlobalISel.inc 747 const MachineRegisterInfo &MRI = MF.getRegInfo();
809 MachineRegisterInfo &MRI = MF.getRegInfo();
gen/lib/Target/Mips/MipsGenGlobalISel.inc 612 const MachineRegisterInfo &MRI = MF.getRegInfo();
634 MachineRegisterInfo &MRI = MF.getRegInfo();
gen/lib/Target/RISCV/RISCVGenGlobalISel.inc 258 const MachineRegisterInfo &MRI = MF.getRegInfo();
280 MachineRegisterInfo &MRI = MF.getRegInfo();
gen/lib/Target/X86/X86GenGlobalISel.inc 751 const MachineRegisterInfo &MRI = MF.getRegInfo();
773 MachineRegisterInfo &MRI = MF.getRegInfo();
include/llvm/CodeGen/FastISel.h 205 MachineRegisterInfo &MRI;
include/llvm/CodeGen/FunctionLoweringInfo.h 58 MachineRegisterInfo *RegInfo;
include/llvm/CodeGen/GlobalISel/CSEInfo.h 77 MachineRegisterInfo *MRI = nullptr;
169 const MachineRegisterInfo &MRI;
172 GISelInstProfileBuilder(FoldingSetNodeID &ID, const MachineRegisterInfo &MRI)
include/llvm/CodeGen/GlobalISel/CallLowering.h 113 ValueHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
164 MachineRegisterInfo &MRI;
include/llvm/CodeGen/GlobalISel/Combiner.h 39 MachineRegisterInfo *MRI = nullptr;
include/llvm/CodeGen/GlobalISel/CombinerHelper.h 42 MachineRegisterInfo &MRI;
53 void replaceRegWith(MachineRegisterInfo &MRI, Register FromReg, Register ToReg) const;
57 void replaceRegOpWith(MachineRegisterInfo &MRI, MachineOperand &FromRegOp,
include/llvm/CodeGen/GlobalISel/GISelChangeObserver.h 54 void changingAllUsesOfReg(const MachineRegisterInfo &MRI, unsigned Reg);
include/llvm/CodeGen/GlobalISel/GISelKnownBits.h 31 MachineRegisterInfo &MRI;
include/llvm/CodeGen/GlobalISel/IRTranslator.h 505 MachineRegisterInfo *MRI = nullptr;
include/llvm/CodeGen/GlobalISel/InstructionSelector.h 452 MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI,
488 const MachineRegisterInfo &MRI) const;
494 const MachineRegisterInfo &MRI) const;
include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h 53 MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI,
include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h 28 MachineRegisterInfo &MRI;
44 LegalizationArtifactCombiner(MachineIRBuilder &B, MachineRegisterInfo &MRI,
include/llvm/CodeGen/GlobalISel/Legalizer.h 62 bool combineExtracts(MachineInstr &MI, MachineRegisterInfo &MRI,
include/llvm/CodeGen/GlobalISel/LegalizerHelper.h 242 MachineRegisterInfo &MRI;
256 MachineRegisterInfo &MRI,
include/llvm/CodeGen/GlobalISel/LegalizerInfo.h 1141 const MachineRegisterInfo &MRI) const;
1146 bool isLegal(const MachineInstr &MI, const MachineRegisterInfo &MRI) const;
1148 const MachineRegisterInfo &MRI) const;
1150 virtual bool legalizeCustom(MachineInstr &MI, MachineRegisterInfo &MRI,
1156 virtual bool legalizeIntrinsic(MachineInstr &MI, MachineRegisterInfo &MRI,
include/llvm/CodeGen/GlobalISel/Localizer.h 47 MachineRegisterInfo *MRI;
include/llvm/CodeGen/GlobalISel/MIPatternMatch.h 24 bool mi_match(Reg R, const MachineRegisterInfo &MRI, Pattern &&P) {
33 bool match(const MachineRegisterInfo &MRI, unsigned Reg) {
46 bool match(const MachineRegisterInfo &MRI, unsigned Reg) {
63 bool match(const MachineRegisterInfo &MRI, unsigned Reg) { return true; }
64 bool match(const MachineRegisterInfo &MRI, MachineOperand *MO) {
74 bool match(const MachineRegisterInfo &MRI, MatchSrc &&src) {
86 bool match(const MachineRegisterInfo &MRI, MatchSrc &&src) {
93 bool match(const MachineRegisterInfo &MRI, MatchSrc &&src) {
104 bool match(const MachineRegisterInfo &MRI, MatchSrc &&src) {
118 static bool bind(const MachineRegisterInfo &MRI, BindTy &VR, BindTy &V) {
125 static bool bind(const MachineRegisterInfo &MRI, MachineInstr *&MI,
135 static bool bind(const MachineRegisterInfo &MRI, LLT &Ty, unsigned Reg) {
144 static bool bind(const MachineRegisterInfo &MRI, const ConstantFP *&F,
158 template <typename ITy> bool match(const MachineRegisterInfo &MRI, ITy &&V) {
179 bool match(const MachineRegisterInfo &MRI, OpTy &&Op) {
247 bool match(const MachineRegisterInfo &MRI, OpTy &&Op) {
328 bool match(const MachineRegisterInfo &MRI, unsigned Reg) {
include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h 44 MachineRegisterInfo *MRI;
74 void addDefToMIB(MachineRegisterInfo &MRI, MachineInstrBuilder &MIB) const {
88 LLT getLLTTy(const MachineRegisterInfo &MRI) const {
159 LLT getLLTTy(const MachineRegisterInfo &MRI) const {
271 MachineRegisterInfo *getMRI() { return State.MRI; }
272 const MachineRegisterInfo *getMRI() const { return State.MRI; }
include/llvm/CodeGen/GlobalISel/RegBankSelect.h 490 MachineRegisterInfo *MRI = nullptr;
include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h 288 MachineRegisterInfo &MRI;
322 MachineRegisterInfo &MRI);
333 MachineRegisterInfo &getMRI() const { return MRI; }
583 const RegisterBank *getRegBank(Register Reg, const MachineRegisterInfo &MRI,
645 MachineRegisterInfo &MRI);
729 unsigned getSizeInBits(Register Reg, const MachineRegisterInfo &MRI,
include/llvm/CodeGen/GlobalISel/Utils.h 45 unsigned constrainRegToClass(MachineRegisterInfo &MRI,
59 MachineRegisterInfo &MRI,
77 MachineRegisterInfo &MRI,
98 bool isTriviallyDead(const MachineInstr &MI, const MachineRegisterInfo &MRI);
114 const MachineRegisterInfo &MRI);
129 getConstantVRegValWithLookThrough(unsigned VReg, const MachineRegisterInfo &MRI,
133 const MachineRegisterInfo &MRI);
139 const MachineRegisterInfo &MRI);
145 const MachineRegisterInfo &MRI);
156 const MachineRegisterInfo &MRI);
159 uint64_t Imm, const MachineRegisterInfo &MRI);
163 bool isKnownNeverNaN(Register Val, const MachineRegisterInfo &MRI,
167 inline bool isKnownNeverSNaN(Register Val, const MachineRegisterInfo &MRI) {
include/llvm/CodeGen/LiveInterval.h 821 const MachineRegisterInfo &MRI,
859 void verify(const MachineRegisterInfo *MRI = nullptr) const;
986 MachineRegisterInfo &MRI);
include/llvm/CodeGen/LiveIntervals.h 56 MachineRegisterInfo* MRI;
include/llvm/CodeGen/LivePhysRegs.h 109 bool available(const MachineRegisterInfo &MRI, MCPhysReg Reg) const;
include/llvm/CodeGen/LiveRangeCalc.h 46 const MachineRegisterInfo *MRI = nullptr;
include/llvm/CodeGen/LiveRangeEdit.h 45 class LiveRangeEdit : private MachineRegisterInfo::Delegate {
72 MachineRegisterInfo &MRI;
include/llvm/CodeGen/LiveVariables.h 109 MachineRegisterInfo &MRI);
128 MachineRegisterInfo* MRI;
include/llvm/CodeGen/MachineFunction.h 231 MachineRegisterInfo *RegInfo;
486 MachineRegisterInfo &getRegInfo() { return *RegInfo; }
487 const MachineRegisterInfo &getRegInfo() const { return *RegInfo; }
include/llvm/CodeGen/MachineInstr.h 1509 const MachineRegisterInfo &MRI) const;
1671 MachineRegisterInfo *getRegInfo();
1676 void RemoveRegOperandsFromUseLists(MachineRegisterInfo&);
1681 void AddRegOperandsToUseLists(MachineRegisterInfo&);
include/llvm/CodeGen/MachineLoopUtils.h 36 MachineRegisterInfo &MRI,
include/llvm/CodeGen/MachinePipeliner.h 503 MachineRegisterInfo &MRI;
include/llvm/CodeGen/MachineRegisterInfo.h 150 MachineRegisterInfo(const MachineRegisterInfo &) = delete;
151 MachineRegisterInfo &operator=(const MachineRegisterInfo &) = delete;
151 MachineRegisterInfo &operator=(const MachineRegisterInfo &) = delete;
1177 PSetIterator(unsigned RegUnit, const MachineRegisterInfo *MRI) {
include/llvm/CodeGen/MachineSSAUpdater.h 52 MachineRegisterInfo *MRI;
include/llvm/CodeGen/MachineTraceMetrics.h 91 const MachineRegisterInfo *MRI = nullptr;
include/llvm/CodeGen/ModuloSchedule.h 165 MachineRegisterInfo &MRI;
277 MachineRegisterInfo &MRI;
include/llvm/CodeGen/RegisterPressure.h 161 const MachineRegisterInfo *MRI);
181 const MachineRegisterInfo &MRI, bool TrackLaneMasks,
193 const MachineRegisterInfo &MRI, SlotIndex Pos,
222 const MachineRegisterInfo &MRI);
293 void init(const MachineRegisterInfo &MRI);
362 const MachineRegisterInfo *MRI;
include/llvm/CodeGen/RegisterScavenging.h 37 MachineRegisterInfo* MRI;
include/llvm/CodeGen/ScheduleDAG.h 561 MachineRegisterInfo &MRI; ///< Virtual/real register map
include/llvm/CodeGen/SelectionDAGISel.h 52 MachineRegisterInfo *RegInfo;
include/llvm/CodeGen/TailDuplicator.h 41 MachineRegisterInfo *MRI;
include/llvm/CodeGen/TargetInstrInfo.h 526 const MachineRegisterInfo *MRI = nullptr) const;
1379 const MachineRegisterInfo *MRI) const {
1392 const MachineRegisterInfo *MRI,
1405 unsigned Reg, MachineRegisterInfo *MRI) const {
1469 const MachineRegisterInfo *MRI,
include/llvm/CodeGen/TargetLowering.h 2991 bool IsPre, MachineRegisterInfo &MRI) const {
3038 bool parametersInCSRMatch(const MachineRegisterInfo &MRI,
3185 const MachineRegisterInfo &MRI,
include/llvm/CodeGen/TargetRegisterInfo.h 409 const MachineRegisterInfo *MRI) const;
741 unsigned getRegSizeInBits(unsigned Reg, const MachineRegisterInfo &MRI) const;
972 const MachineRegisterInfo &MRI) const {
1149 const MachineRegisterInfo *MRI = nullptr);
1167 Printable printRegClassOrBank(unsigned Reg, const MachineRegisterInfo &RegInfo,
include/llvm/CodeGen/VirtRegMap.h 42 MachineRegisterInfo *MRI;
89 MachineRegisterInfo &getRegInfo() const { return *MRI; }
include/llvm/Support/Allocator.h 88 !std::is_same<typename std::remove_cv<T>::type, void>::value, void>::type
89 Deallocate(T *Ptr, size_t Num = 1) {
90 Deallocate(static_cast<const void *>(Ptr), Num * sizeof(T));
lib/CodeGen/AggressiveAntiDepBreaker.h 119 MachineRegisterInfo &MRI;
lib/CodeGen/BranchFolding.cpp 186 MachineRegisterInfo &MRI = MF.getRegInfo();
lib/CodeGen/BranchFolding.h 127 const MachineRegisterInfo *MRI;
lib/CodeGen/CalcSpillWeights.cpp 40 MachineRegisterInfo &MRI = MF.getRegInfo();
53 const MachineRegisterInfo &mri) {
153 MachineRegisterInfo &mri = MF.getRegInfo();
206 for (MachineRegisterInfo::reg_instr_iterator
lib/CodeGen/CriticalAntiDepBreaker.h 38 MachineRegisterInfo &MRI;
lib/CodeGen/DeadMachineInstructionElim.cpp 33 const MachineRegisterInfo *MRI;
lib/CodeGen/DetectDeadLanes.cpp 109 const MachineRegisterInfo *MRI;
152 static bool isCrossCopy(const MachineRegisterInfo &MRI,
lib/CodeGen/EarlyIfConversion.cpp 84 MachineRegisterInfo *MRI;
704 MachineRegisterInfo *MRI;
941 MachineRegisterInfo *MRI;
lib/CodeGen/ExecutionDomainFix.cpp 428 const MachineRegisterInfo &MRI = mf.getRegInfo();
lib/CodeGen/GlobalISel/CallLowering.cpp 131 MachineRegisterInfo *MRI = MIRBuilder.getMRI();
lib/CodeGen/GlobalISel/CombinerHelper.cpp 42 void CombinerHelper::replaceRegWith(MachineRegisterInfo &MRI, Register FromReg,
54 void CombinerHelper::replaceRegOpWith(MachineRegisterInfo &MRI,
892 MachineRegisterInfo &MRI = *MIB.getMRI();
lib/CodeGen/GlobalISel/GISelChangeObserver.cpp 19 const MachineRegisterInfo &MRI, unsigned Reg) {
lib/CodeGen/GlobalISel/InstructionSelect.cpp 86 MachineRegisterInfo &MRI = MF.getRegInfo();
lib/CodeGen/GlobalISel/InstructionSelector.cpp 42 MachineRegisterInfo &MRI = MF.getRegInfo();
50 const MachineRegisterInfo &MRI) const {
58 const MachineOperand &Root, const MachineRegisterInfo &MRI) const {
lib/CodeGen/GlobalISel/Legalizer.cpp 155 MachineRegisterInfo &MRI = MF.getRegInfo();
lib/CodeGen/GlobalISel/LegalizerHelper.cpp 392 llvm::createMemLibcall(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
lib/CodeGen/GlobalISel/LegalizerInfo.cpp 391 const MachineRegisterInfo &MRI, unsigned OpIdx,
477 const MachineRegisterInfo &MRI) const {
508 const MachineRegisterInfo &MRI) const {
513 const MachineRegisterInfo &MRI) const {
520 bool LegalizerInfo::legalizeCustom(MachineInstr &MI, MachineRegisterInfo &MRI,
683 MachineRegisterInfo &MRI,
739 const MachineRegisterInfo &MRI = MF.getRegInfo();
lib/CodeGen/GlobalISel/RegisterBankInfo.cpp 83 RegisterBankInfo::getRegBank(Register Reg, const MachineRegisterInfo &MRI,
127 Register Reg, const TargetRegisterClass &RC, MachineRegisterInfo &MRI) {
168 const MachineRegisterInfo &MRI = MF.getRegInfo();
435 MachineRegisterInfo &MRI = OpdMapper.getMRI();
489 const MachineRegisterInfo &MRI,
648 MachineRegisterInfo &MRI)
lib/CodeGen/GlobalISel/Utils.cpp 30 unsigned llvm::constrainRegToClass(MachineRegisterInfo &MRI,
42 MachineRegisterInfo &MRI, const TargetInstrInfo &TII,
72 MachineRegisterInfo &MRI, const TargetInstrInfo &TII,
119 MachineRegisterInfo &MRI = MF.getRegInfo();
159 const MachineRegisterInfo &MRI) {
208 const MachineRegisterInfo &MRI) {
219 unsigned VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs,
296 const MachineRegisterInfo &MRI) {
304 const MachineRegisterInfo &MRI) {
320 const MachineRegisterInfo &MRI) {
340 const MachineRegisterInfo &MRI) {
389 bool llvm::isKnownNeverNaN(Register Val, const MachineRegisterInfo &MRI,
416 const MachineRegisterInfo &MRI) {
lib/CodeGen/IfConversion.cpp 194 MachineRegisterInfo *MRI;
lib/CodeGen/InlineSpiller.cpp 93 MachineRegisterInfo &MRI;
166 MachineRegisterInfo &MRI;
290 for (MachineRegisterInfo::reg_instr_nodbg_iterator
330 for (MachineRegisterInfo::reg_instr_iterator
447 for (MachineRegisterInfo::use_instr_nodbg_iterator
647 for (MachineRegisterInfo::reg_bundle_iterator
967 for (MachineRegisterInfo::reg_bundle_iterator
1093 for (MachineRegisterInfo::reg_instr_iterator
lib/CodeGen/LiveDebugVariables.cpp 299 MachineRegisterInfo &MRI, LiveIntervals &LIS);
303 void computeIntervals(MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI,
764 MachineRegisterInfo &MRI, LiveIntervals &LIS) {
833 void UserValue::computeIntervals(MachineRegisterInfo &MRI,
1183 const MachineRegisterInfo &MRI = MF.getRegInfo();
lib/CodeGen/LiveInterval.cpp 969 const MachineRegisterInfo &MRI,
1076 void LiveInterval::verify(const MachineRegisterInfo *MRI) const {
1353 MachineRegisterInfo &MRI) {
1355 for (MachineRegisterInfo::reg_iterator RI = MRI.reg_begin(LI.reg),
lib/CodeGen/LiveIntervals.cpp 946 const MachineRegisterInfo& MRI;
954 HMEditor(LiveIntervals& LIS, const MachineRegisterInfo& MRI,
lib/CodeGen/LivePhysRegs.cpp 143 bool LivePhysRegs::available(const MachineRegisterInfo &MRI,
178 const MachineRegisterInfo &MRI = MF.getRegInfo();
249 const MachineRegisterInfo &MRI = MF.getRegInfo();
260 const MachineRegisterInfo &MRI = MF.getRegInfo();
281 const MachineRegisterInfo &MRI = MF.getRegInfo();
lib/CodeGen/LiveRangeShrink.cpp 111 MachineRegisterInfo &MRI = MF.getRegInfo();
lib/CodeGen/LiveRegUnits.cpp 94 const MachineRegisterInfo &MRI = MF.getRegInfo();
lib/CodeGen/LiveVariables.cpp 722 MachineRegisterInfo &MRI) {
lib/CodeGen/MIRCanonicalizerPass.cpp 224 MachineRegisterInfo *MRI = &MBB->getParent()->getRegInfo();
308 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
401 MachineRegisterInfo &MRI = MF.getRegInfo();
479 MachineRegisterInfo &MRI = MF.getRegInfo();
lib/CodeGen/MIRParser/MIParser.cpp 326 MachineRegisterInfo &MRI = MF.getRegInfo();
1422 MachineRegisterInfo &MRI = MF.getRegInfo();
lib/CodeGen/MIRParser/MIRParser.cpp 307 const MachineRegisterInfo &MRI = MF.getRegInfo();
338 const MachineRegisterInfo &MRI = MF.getRegInfo();
479 MachineRegisterInfo &MRI = MF.getRegInfo();
496 MachineRegisterInfo &RegInfo = MF.getRegInfo();
577 MachineRegisterInfo &MRI = MF.getRegInfo();
lib/CodeGen/MIRPrinter.cpp 122 void convert(yaml::MachineFunction &MF, const MachineRegisterInfo &RegInfo,
264 const MachineRegisterInfo &RegInfo,
287 const MachineRegisterInfo &RegInfo,
667 const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
707 const auto &MRI = MF->getRegInfo();
lib/CodeGen/MIRVRegNamerUtils.cpp 53 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
87 const MachineRegisterInfo &MRI = MF.getRegInfo();
159 MachineRegisterInfo &MRI, NamedVRegCursor &NVC) {
227 MachineRegisterInfo &MRI) {
258 MachineRegisterInfo &MRI = MF.getRegInfo();
lib/CodeGen/MIRVRegNamerUtils.h 37 MachineRegisterInfo &MRI;
60 NamedVRegCursor(MachineRegisterInfo &MRI, unsigned SkipGapSize = 1000)
lib/CodeGen/MachineBasicBlock.cpp 96 MachineRegisterInfo &RegInfo = MF.getRegInfo();
339 const MachineRegisterInfo &MRI = MF->getRegInfo();
502 MachineRegisterInfo &MRI = getParent()->getRegInfo();
1046 MachineRegisterInfo *MRI = &getParent()->getRegInfo();
lib/CodeGen/MachineCSE.cpp 69 MachineRegisterInfo *MRI;
267 const MachineRegisterInfo &MRI = MF.getRegInfo();
lib/CodeGen/MachineCombiner.cpp 65 MachineRegisterInfo *MRI;
231 MachineRegisterInfo::reg_iterator RI = MRI->reg_begin(MO.getReg());
lib/CodeGen/MachineCopyPropagation.cpp 186 const MachineRegisterInfo *MRI;
lib/CodeGen/MachineFrameInfo.cpp 123 const MachineRegisterInfo &MRI = MF.getRegInfo();
lib/CodeGen/MachineFunction.cpp 158 RegInfo = new (Allocator) MachineRegisterInfo(this);
501 for (MachineRegisterInfo::livein_iterator
585 MachineRegisterInfo &MRI = getRegInfo();
lib/CodeGen/MachineInstr.cpp 90 const MachineRegisterInfo *&MRI,
152 MachineRegisterInfo *MachineInstr::getRegInfo() {
161 void MachineInstr::RemoveRegOperandsFromUseLists(MachineRegisterInfo &MRI) {
170 void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &MRI) {
187 unsigned NumOps, MachineRegisterInfo *MRI) {
238 MachineRegisterInfo *MRI = getRegInfo();
306 MachineRegisterInfo *MRI = getRegInfo();
681 MachineRegisterInfo &MRI = MF->getRegInfo();
1424 const MachineRegisterInfo &MRI) const {
1478 const MachineRegisterInfo *MRI = nullptr;
2129 auto *MRI = getRegInfo();
lib/CodeGen/MachineLICM.cpp 98 MachineRegisterInfo *MRI;
800 static bool isOperandKill(const MachineOperand &MO, MachineRegisterInfo *MRI) {
914 const MachineRegisterInfo *MRI) {
947 const MachineRegisterInfo *MRI,
lib/CodeGen/MachineLoopUtils.cpp 28 MachineRegisterInfo &MRI,
lib/CodeGen/MachineOperand.cpp 63 MachineRegisterInfo &MRI = MF->getRegInfo();
106 MachineRegisterInfo &MRI = MF->getRegInfo();
236 MachineRegisterInfo *RegInfo = nullptr;
772 const MachineRegisterInfo *MRI = nullptr;
790 const MachineRegisterInfo &MRI = MF->getRegInfo();
lib/CodeGen/MachinePipeliner.cpp 349 MachineRegisterInfo &MRI = MF->getRegInfo();
775 for (MachineRegisterInfo::use_instr_iterator
1547 MachineRegisterInfo &MRI = MF.getRegInfo();
2068 MachineRegisterInfo &MRI = MF.getRegInfo();
2107 MachineRegisterInfo &MRI = MI->getMF()->getRegInfo();
lib/CodeGen/MachineRegisterInfo.cpp 69 constrainRegClass(MachineRegisterInfo &MRI, unsigned Reg,
547 MachineRegisterInfo::use_instr_iterator nextI;
lib/CodeGen/MachineSink.cpp 87 MachineRegisterInfo *MRI; // Machine register information
765 const MachineRegisterInfo &MRI = MI.getMF()->getRegInfo();
992 const MachineRegisterInfo &MRI = MI.getMF()->getRegInfo();
lib/CodeGen/MachineTraceMetrics.cpp 635 DataDep(const MachineRegisterInfo *MRI, unsigned VirtReg, unsigned UseOp)
638 MachineRegisterInfo::def_iterator DefI = MRI->def_begin(VirtReg);
652 const MachineRegisterInfo *MRI) {
683 const MachineRegisterInfo *MRI) {
lib/CodeGen/MachineVerifier.cpp 97 const MachineRegisterInfo *MRI;
lib/CodeGen/ModuloSchedule.cpp 84 for (MachineRegisterInfo::use_iterator UI = MRI.use_begin(Reg),
335 MachineRegisterInfo &MRI,
337 for (MachineRegisterInfo::use_iterator I = MRI.use_begin(FromReg),
352 MachineRegisterInfo &MRI) {
353 for (MachineRegisterInfo::use_iterator I = MRI.use_begin(Reg),
738 for (MachineRegisterInfo::use_iterator UI = MRI.use_begin(reg),
792 for (MachineRegisterInfo::use_instr_iterator I = MRI.use_instr_begin(Def),
923 MachineRegisterInfo &MRI = MF.getRegInfo();
1143 for (MachineRegisterInfo::use_iterator UI = MRI.use_begin(OldReg),
1216 void EliminateDeadPhis(MachineBasicBlock *MBB, MachineRegisterInfo &MRI,
1249 MachineRegisterInfo &MRI;
1518 MachineRegisterInfo &MRI;
1524 KernelOperandInfo(MachineOperand *MO, MachineRegisterInfo &MRI,
lib/CodeGen/OptimizePHIs.cpp 37 MachineRegisterInfo *MRI;
lib/CodeGen/PHIElimination.cpp 68 MachineRegisterInfo *MRI; // Machine register information
222 const MachineRegisterInfo &MRI) {
231 const MachineRegisterInfo &MRI) {
lib/CodeGen/PHIEliminationUtils.cpp 35 MachineRegisterInfo& MRI = MBB->getParent()->getRegInfo();
lib/CodeGen/PeepholeOptimizer.cpp 156 MachineRegisterInfo *MRI;
378 const MachineRegisterInfo &MRI;
418 const MachineRegisterInfo &MRI,
755 insertPHI(MachineRegisterInfo &MRI, const TargetInstrInfo &TII,
1111 getNewSource(MachineRegisterInfo *MRI, const TargetInstrInfo *TII,
2098 MachineRegisterInfo::def_iterator DI = MRI.def_begin(Reg);
lib/CodeGen/ProcessImplicitDefs.cpp 30 MachineRegisterInfo *MRI;
lib/CodeGen/PrologEpilogInserter.cpp 505 MachineRegisterInfo &MRI = MF.getRegInfo();
lib/CodeGen/RegAllocBase.cpp 119 for (MachineRegisterInfo::reg_instr_iterator
lib/CodeGen/RegAllocBase.h 65 MachineRegisterInfo *MRI = nullptr;
lib/CodeGen/RegAllocFast.cpp 71 MachineRegisterInfo *MRI;
361 MachineRegisterInfo::reg_nodbg_iterator I = MRI->reg_nodbg_begin(MO.getReg());
lib/CodeGen/RegAllocGreedy.cpp 2512 static bool hasTiedDef(MachineRegisterInfo *MRI, unsigned reg) {
lib/CodeGen/RegAllocPBQP.cpp 557 const MachineRegisterInfo &MRI = MF.getRegInfo();
582 const MachineRegisterInfo &MRI = G.getMetadata().MF.getRegInfo();
745 MachineRegisterInfo &MRI = MF.getRegInfo();
879 const MachineRegisterInfo &MRI = G.getMetadata().MF.getRegInfo();
lib/CodeGen/RegUsageInfoCollector.cpp 102 MachineRegisterInfo *MRI = &MF.getRegInfo();
lib/CodeGen/RegisterCoalescer.cpp 125 MachineRegisterInfo* MRI;
417 const MachineRegisterInfo &MRI = MI->getMF()->getRegInfo();
859 for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(IntA.reg),
1671 for (MachineRegisterInfo::reg_instr_iterator
3512 const MachineRegisterInfo *MRI) {
lib/CodeGen/RegisterPressure.cpp 51 const MachineRegisterInfo &MRI, unsigned Reg,
65 const MachineRegisterInfo &MRI, unsigned Reg,
225 void LiveRegSet::init(const MachineRegisterInfo &MRI) {
422 const MachineRegisterInfo &MRI, bool TrackLaneMasks, unsigned RegUnit,
450 const MachineRegisterInfo &MRI,
472 const MachineRegisterInfo &MRI;
477 const MachineRegisterInfo &MRI, bool IgnoreDead)
570 const MachineRegisterInfo &MRI,
600 const MachineRegisterInfo &MRI,
659 const MachineRegisterInfo &MRI) {
671 const MachineRegisterInfo *MRI) {
1224 const MachineRegisterInfo &MRI,
lib/CodeGen/RegisterScavenging.cpp 623 static Register scavengeVReg(MachineRegisterInfo &MRI, RegScavenger &RS,
654 MachineRegisterInfo::def_iterator FirstDef =
677 static bool scavengeFrameVirtualRegsInBlock(MachineRegisterInfo &MRI,
755 MachineRegisterInfo &MRI = MF.getRegInfo();
lib/CodeGen/RenameIndependentSubregs.cpp 104 MachineRegisterInfo *MRI;
215 for (MachineRegisterInfo::reg_nodbg_iterator I = MRI->reg_nodbg_begin(Reg),
lib/CodeGen/ScheduleDAGInstrs.cpp 1086 static void toggleKills(const MachineRegisterInfo &MRI, LivePhysRegs &LiveRegs,
lib/CodeGen/SelectionDAG/FastISel.cpp 2359 MachineRegisterInfo::reg_iterator RI = MRI.reg_begin(LoadReg);
lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp 520 MachineRegisterInfo &MRI = MF->getRegInfo();
lib/CodeGen/SelectionDAG/InstrEmitter.h 30 MachineRegisterInfo *MRI;
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp 957 const MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
5511 MachineRegisterInfo &RegInfo = MF.getRegInfo();
7967 MachineRegisterInfo &RegInfo = MF.getRegInfo();
8269 MachineRegisterInfo &RegInfo =
9766 MachineRegisterInfo& RegInfo = MF.getRegInfo();
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp 513 MachineRegisterInfo &MRI = MF->getRegInfo();
612 for (MachineRegisterInfo::use_instr_iterator
lib/CodeGen/SelectionDAG/TargetLowering.cpp 74 bool TargetLowering::parametersInCSRMatch(const MachineRegisterInfo &MRI,
2593 const APInt &DemandedElts, const MachineRegisterInfo &MRI,
lib/CodeGen/SplitKit.cpp 175 const MachineRegisterInfo &MRI = MF.getRegInfo();
1315 for (MachineRegisterInfo::reg_iterator RI = MRI.reg_begin(Edit->getReg()),
lib/CodeGen/SplitKit.h 262 MachineRegisterInfo &MRI;
lib/CodeGen/TailDuplicator.cpp 209 MachineRegisterInfo::use_iterator UI = MRI->use_begin(VReg);
289 const MachineRegisterInfo *MRI) {
lib/CodeGen/TargetFrameLoweringImpl.cpp 119 const MachineRegisterInfo &MRI = MF.getRegInfo();
lib/CodeGen/TargetInstrInfo.cpp 420 const MachineRegisterInfo *MRI) const {
451 const MachineRegisterInfo &MRI = MI.getMF()->getRegInfo();
671 const MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
689 const MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
778 MachineRegisterInfo &MRI = MF->getRegInfo();
860 MachineRegisterInfo &MRI = Root.getMF()->getRegInfo();
885 const MachineRegisterInfo &MRI = MF.getRegInfo();
lib/CodeGen/TargetRegisterInfo.cpp 90 unsigned SubIdx, const MachineRegisterInfo *MRI) {
153 Printable printRegClassOrBank(unsigned Reg, const MachineRegisterInfo &RegInfo,
389 const MachineRegisterInfo &MRI = MF.getRegInfo();
473 const MachineRegisterInfo &MRI) const {
496 const MachineRegisterInfo *MRI) const {
lib/CodeGen/TwoAddressInstructionPass.cpp 97 MachineRegisterInfo *MRI;
344 const MachineRegisterInfo *MRI) {
470 const MachineRegisterInfo *MRI,
484 MachineRegisterInfo::def_iterator Begin = MRI->def_begin(Reg);
520 MachineRegisterInfo *MRI,
lib/CodeGen/UnreachableBlockElim.cpp 183 MachineRegisterInfo &MRI = F.getRegInfo();
lib/CodeGen/VirtRegMap.cpp 179 MachineRegisterInfo *MRI;
lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp 110 MachineRegisterInfo *MRI;
lib/Target/AArch64/AArch64AdvSIMDScalarPass.cpp 66 MachineRegisterInfo *MRI;
105 const MachineRegisterInfo *MRI) {
114 const MachineRegisterInfo *MRI) {
128 const MachineRegisterInfo *MRI,
209 MachineRegisterInfo::def_instr_iterator Def =
222 MachineRegisterInfo::def_instr_iterator Def =
241 for (MachineRegisterInfo::use_instr_nodbg_iterator
302 MachineRegisterInfo::def_instr_iterator Def =
321 MachineRegisterInfo::def_instr_iterator Def =
lib/Target/AArch64/AArch64CallLowering.cpp 56 IncomingArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
108 FormalArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
119 CallReturnHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
131 OutgoingArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
221 const DataLayout &DL, MachineRegisterInfo &MRI, CallingConv::ID CallConv) const {
269 MachineRegisterInfo &MRI = MF.getRegInfo();
421 MachineRegisterInfo &MRI = MF.getRegInfo();
598 MachineRegisterInfo &MRI = MF.getRegInfo();
783 MachineRegisterInfo &MRI = MF.getRegInfo();
925 MachineRegisterInfo &MRI = MF.getRegInfo();
lib/Target/AArch64/AArch64CallLowering.h 64 const DataLayout &DL, MachineRegisterInfo &MRI,
lib/Target/AArch64/AArch64CleanupLocalDynamicTLSPass.cpp 121 MachineRegisterInfo &RegInfo = MF->getRegInfo();
lib/Target/AArch64/AArch64CondBrTuning.cpp 51 MachineRegisterInfo *MRI;
lib/Target/AArch64/AArch64ConditionOptimizer.cpp 96 const MachineRegisterInfo *MRI;
lib/Target/AArch64/AArch64ConditionalCompares.cpp 141 MachineRegisterInfo *MRI;
768 MachineRegisterInfo *MRI;
lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp 38 const MachineRegisterInfo *MRI;
lib/Target/AArch64/AArch64FalkorHWPFFix.cpp 708 MachineRegisterInfo &MRI = Fn.getRegInfo();
lib/Target/AArch64/AArch64FrameLowering.cpp 400 const MachineRegisterInfo &MRI = MF->getRegInfo();
1958 const MachineRegisterInfo &MRI = MF.getRegInfo();
2230 const MachineRegisterInfo &MRI = MF.getRegInfo();
lib/Target/AArch64/AArch64ISelLowering.cpp 3668 const MachineRegisterInfo &MRI = MF.getRegInfo();
12383 MachineRegisterInfo *MRI = &Entry->getParent()->getRegInfo();
lib/Target/AArch64/AArch64InstrInfo.cpp 417 static unsigned removeCopies(const MachineRegisterInfo &MRI, unsigned VReg) {
430 static unsigned canFoldIntoCSel(const MachineRegisterInfo &MRI, unsigned VReg,
502 const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
543 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
1054 MachineRegisterInfo *MRI = &MF->getRegInfo();
1183 int CmpValue, const MachineRegisterInfo *MRI) const {
1442 const MachineRegisterInfo *MRI) const {
3237 const MachineRegisterInfo &MRI = MF.getRegInfo();
3597 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
3983 genFusedMultiply(MachineFunction &MF, MachineRegisterInfo &MRI,
4062 static MachineInstr *genMaddR(MachineFunction &MF, MachineRegisterInfo &MRI,
4104 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
4785 MachineRegisterInfo *MRI = &MF->getRegInfo();
lib/Target/AArch64/AArch64InstrInfo.h 209 const MachineRegisterInfo *MRI) const override;
289 const MachineRegisterInfo *MRI) const;
lib/Target/AArch64/AArch64InstructionSelector.cpp 79 bool earlySelectSHL(MachineInstr &I, MachineRegisterInfo &MRI) const;
83 MachineRegisterInfo &MRI) const;
86 MachineRegisterInfo &MRI) const;
88 MachineRegisterInfo &MRI) const;
91 MachineRegisterInfo &MRI) const;
93 bool selectVectorASHR(MachineInstr &I, MachineRegisterInfo &MRI) const;
94 bool selectVectorSHL(MachineInstr &I, MachineRegisterInfo &MRI) const;
113 bool selectInsertElt(MachineInstr &I, MachineRegisterInfo &MRI) const;
114 bool selectBuildVector(MachineInstr &I, MachineRegisterInfo &MRI) const;
115 bool selectMergeValues(MachineInstr &I, MachineRegisterInfo &MRI) const;
116 bool selectUnmergeValues(MachineInstr &I, MachineRegisterInfo &MRI) const;
118 bool selectShuffleVector(MachineInstr &I, MachineRegisterInfo &MRI) const;
119 bool selectExtractElt(MachineInstr &I, MachineRegisterInfo &MRI) const;
120 bool selectConcatVectors(MachineInstr &I, MachineRegisterInfo &MRI) const;
122 MachineRegisterInfo &MRI) const;
124 MachineRegisterInfo &MRI) const;
125 bool selectIntrinsic(MachineInstr &I, MachineRegisterInfo &MRI) const;
126 bool selectVectorICmp(MachineInstr &I, MachineRegisterInfo &MRI) const;
127 bool selectIntrinsicTrunc(MachineInstr &I, MachineRegisterInfo &MRI) const;
128 bool selectIntrinsicRound(MachineInstr &I, MachineRegisterInfo &MRI) const;
129 bool selectJumpTable(MachineInstr &I, MachineRegisterInfo &MRI) const;
130 bool selectBrJT(MachineInstr &I, MachineRegisterInfo &MRI) const;
131 bool selectTLSGlobalValue(MachineInstr &I, MachineRegisterInfo &MRI) const;
159 MachineRegisterInfo &MRI) const;
204 const MachineRegisterInfo &MRI) const;
404 const MachineRegisterInfo &MRI,
556 const MachineRegisterInfo &MRI,
592 static bool selectSubregisterCopy(MachineInstr &I, MachineRegisterInfo &MRI,
618 MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI,
643 MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI,
831 static unsigned selectSelectOpc(MachineInstr &I, MachineRegisterInfo &MRI,
845 static unsigned selectFCMPOpc(MachineInstr &I, MachineRegisterInfo &MRI) {
953 MachineInstr &I, MachineFunction &MF, MachineRegisterInfo &MRI) const {
1010 MachineInstr &I, MachineRegisterInfo &MRI) const {
1040 MachineInstr &I, MachineRegisterInfo &MRI) const {
1084 MachineInstr &I, MachineFunction &MF, MachineRegisterInfo &MRI) const {
1089 MachineInstr &I, MachineFunction &MF, MachineRegisterInfo &MRI) const {
1119 MachineRegisterInfo &MRI = MF.getRegInfo();
1157 MachineRegisterInfo &MRI = MF.getRegInfo();
1199 MachineInstr &I, MachineRegisterInfo &MRI) const {
1234 MachineInstr &I, MachineRegisterInfo &MRI) const {
1281 MachineRegisterInfo &MRI = MF.getRegInfo();
1322 MachineRegisterInfo &MRI = MF.getRegInfo();
2333 MachineRegisterInfo &MRI) const {
2353 MachineInstr &I, MachineRegisterInfo &MRI) const {
2370 MachineInstr &I, MachineRegisterInfo &MRI) const {
2401 MachineInstr &I, MachineRegisterInfo &MRI) const {
2456 MachineInstr &I, MachineRegisterInfo &MRI) const {
2511 MachineInstr &I, MachineRegisterInfo &MRI) const {
2710 MachineInstr &I, MachineRegisterInfo &MRI) const {
2807 MachineRegisterInfo &MRI = *MIRBuilder.getMRI();
2865 MachineInstr &I, MachineRegisterInfo &MRI) const {
2905 MachineInstr &I, MachineRegisterInfo &MRI) const {
2935 MachineInstr &I, MachineRegisterInfo &MRI) const {
3050 MachineInstr &I, MachineRegisterInfo &MRI) const {
3149 MachineRegisterInfo &MRI = MIRBuilder.getMF().getRegInfo();
3173 MachineRegisterInfo &MRI = MIRBuilder.getMF().getRegInfo();
3198 MachineRegisterInfo &MRI = MIRBuilder.getMF().getRegInfo();
3227 MachineRegisterInfo &MRI = MIRBuilder.getMF().getRegInfo();
3278 MachineRegisterInfo &MRI = MIRBuilder.getMF().getRegInfo();
3332 MachineInstr &I, MachineRegisterInfo &MRI) const {
3380 MachineRegisterInfo &MRI = *MIB.getMRI();
3480 MachineRegisterInfo &MRI = *MIRBuilder.getMRI();
3582 MachineRegisterInfo &MRI = *MIB.getMRI();
3648 MachineInstr &I, MachineRegisterInfo &MRI) const {
3748 MachineRegisterInfo &MRI = *MIRBuilder.getMRI();
3774 MachineInstr &I, MachineRegisterInfo &MRI) const {
3850 MachineInstr &I, MachineRegisterInfo &MRI) const {
3937 MachineInstr &I, MachineRegisterInfo &MRI) const {
3963 MachineInstr &I, MachineRegisterInfo &MRI) const {
4132 MachineRegisterInfo &MRI = Root.getParent()->getMF()->getRegInfo();
4149 MachineInstr &MI, const MachineRegisterInfo &MRI) const {
4181 MachineRegisterInfo &MRI = Root.getParent()->getMF()->getRegInfo();
4283 MachineRegisterInfo &MRI = Root.getParent()->getMF()->getRegInfo();
4316 MachineRegisterInfo &MRI = Root.getParent()->getMF()->getRegInfo();
4341 MachineRegisterInfo &MRI =
4385 MachineRegisterInfo &MRI =
4460 MachineRegisterInfo &MRI =
4497 getExtendTypeForInst(MachineInstr &MI, MachineRegisterInfo &MRI) {
4554 MachineRegisterInfo &MRI = *MIB.getMRI();
4574 MachineRegisterInfo &MRI =
4637 const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
4670 const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
lib/Target/AArch64/AArch64LegalizerInfo.cpp 620 MachineRegisterInfo &MRI,
642 MachineInstr &MI, MachineRegisterInfo &MRI,
660 MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &MIRBuilder,
684 MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &MIRBuilder,
723 MachineRegisterInfo &MRI,
lib/Target/AArch64/AArch64LegalizerInfo.h 30 bool legalizeCustom(MachineInstr &MI, MachineRegisterInfo &MRI,
34 bool legalizeIntrinsic(MachineInstr &MI, MachineRegisterInfo &MRI,
38 bool legalizeVaArg(MachineInstr &MI, MachineRegisterInfo &MRI,
40 bool legalizeLoadStore(MachineInstr &MI, MachineRegisterInfo &MRI,
43 bool legalizeShlAshrLshr(MachineInstr &MI, MachineRegisterInfo &MRI,
lib/Target/AArch64/AArch64RedundantCopyElimination.cpp 70 const MachineRegisterInfo *MRI;
lib/Target/AArch64/AArch64RegisterBankInfo.cpp 273 const MachineRegisterInfo &MRI = MF.getRegInfo();
422 const MachineRegisterInfo &MRI = MF.getRegInfo();
461 const MachineInstr &MI, const MachineRegisterInfo &MRI,
480 const MachineRegisterInfo &MRI,
494 const MachineInstr &MI, const MachineRegisterInfo &MRI,
523 const MachineRegisterInfo &MRI = MF.getRegInfo();
lib/Target/AArch64/AArch64RegisterBankInfo.h 118 bool hasFPConstraints(const MachineInstr &MI, const MachineRegisterInfo &MRI,
122 bool onlyUsesFP(const MachineInstr &MI, const MachineRegisterInfo &MRI,
126 bool onlyDefinesFP(const MachineInstr &MI, const MachineRegisterInfo &MRI,
lib/Target/AArch64/AArch64RegisterInfo.cpp 417 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
lib/Target/AArch64/AArch64SIMDInstrOpt.cpp 70 MachineRegisterInfo *MRI;
426 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
lib/Target/AArch64/AArch64StackTaggingPreRA.cpp 59 MachineRegisterInfo *MRI;
lib/Target/AArch64/AArch64StorePairSuppress.cpp 33 const MachineRegisterInfo *MRI;
lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp 591 static bool hasAnyNonFlatUseOfReg(const MachineRegisterInfo &MRI,
620 const MachineRegisterInfo &MRI = MF.getRegInfo();
lib/Target/AMDGPU/AMDGPUCallLowering.cpp 34 OutgoingValueHandler(MachineIRBuilder &B, MachineRegisterInfo &MRI,
78 IncomingArgHandler(MachineIRBuilder &B, MachineRegisterInfo &MRI,
138 FormalArgHandler(MachineIRBuilder &B, MachineRegisterInfo &MRI,
155 const DataLayout &DL, MachineRegisterInfo &MRI, CallingConv::ID CallConv,
226 MachineRegisterInfo &MRI = MF.getRegInfo();
273 MachineRegisterInfo &MRI = MF.getRegInfo();
296 MachineRegisterInfo &MRI = MF.getRegInfo();
346 MachineRegisterInfo &MRI = MF.getRegInfo();
411 MachineRegisterInfo &MRI = MF.getRegInfo();
442 MachineRegisterInfo &MRI = MF.getRegInfo();
566 MachineRegisterInfo &MRI = MF.getRegInfo();
lib/Target/AMDGPU/AMDGPUCallLowering.h 37 const DataLayout &DL, MachineRegisterInfo &MRI,
lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp 551 MachineRegisterInfo &MRI = CurDAG->getMachineFunction().getRegInfo();
lib/Target/AMDGPU/AMDGPUISelLowering.cpp 4092 MachineRegisterInfo &MRI = MF.getRegInfo();
lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp 72 static bool isSCC(Register Reg, const MachineRegisterInfo &MRI) {
95 const MachineRegisterInfo &MRI) const {
399 MachineRegisterInfo &MRI = MF->getRegInfo();
775 static bool isZero(Register Reg, MachineRegisterInfo &MRI) {
802 getBaseWithConstantOffset(MachineRegisterInfo &MRI, Register Reg) {
1371 MachineRegisterInfo &MRI = MF->getRegInfo();
1475 const MachineRegisterInfo &MRI, SmallVectorImpl<GEPInfo> &AddrInfo) const {
2091 bool AMDGPUInstructionSelector::isDSOffsetLegal(const MachineRegisterInfo &MRI,
2179 const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
lib/Target/AMDGPU/AMDGPUInstructionSelector.h 47 MachineRegisterInfo *MRI;
70 bool isVCC(Register Reg, const MachineRegisterInfo &MRI) const;
104 void getAddrModeInfo(const MachineInstr &Load, const MachineRegisterInfo &MRI,
160 bool isDSOffsetLegal(const MachineRegisterInfo &MRI,
lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp 1091 MachineRegisterInfo &MRI,
1138 MachineRegisterInfo &MRI,
1211 MachineInstr &MI, MachineRegisterInfo &MRI,
1317 MachineInstr &MI, MachineRegisterInfo &MRI,
1344 MachineInstr &MI, MachineRegisterInfo &MRI,
1389 MachineInstr &MI, MachineRegisterInfo &MRI,
1435 MachineInstr &MI, MachineRegisterInfo &MRI,
1467 MachineInstr &MI, MachineRegisterInfo &MRI,
1491 MachineInstr &MI, MachineRegisterInfo &MRI,
1520 MachineInstr &MI, MachineRegisterInfo &MRI,
1550 MachineInstr &MI, MachineRegisterInfo &MRI,
1635 MachineInstr &MI, MachineRegisterInfo &MRI,
1705 MachineInstr &MI, MachineRegisterInfo &MRI,
1717 MachineInstr &MI, MachineRegisterInfo &MRI,
1738 MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const {
1766 MachineRegisterInfo &MRI) {
1776 Register AMDGPULegalizerInfo::getLiveInRegister(MachineRegisterInfo &MRI,
1794 MachineRegisterInfo &MRI = *B.getMRI();
1836 MachineRegisterInfo &MRI,
1860 MachineRegisterInfo &MRI,
1877 MachineRegisterInfo &MRI,
1937 MachineRegisterInfo &MRI,
1970 MachineRegisterInfo &MRI,
2006 MachineRegisterInfo &MRI,
2040 MachineRegisterInfo &MRI,
2053 MachineRegisterInfo &MRI,
2075 MachineRegisterInfo &MRI,
2108 MachineRegisterInfo &MRI,
lib/Target/AMDGPU/AMDGPULegalizerInfo.h 35 bool legalizeCustom(MachineInstr &MI, MachineRegisterInfo &MRI,
40 MachineRegisterInfo &MRI,
43 bool legalizeAddrSpaceCast(MachineInstr &MI, MachineRegisterInfo &MRI,
45 bool legalizeFrint(MachineInstr &MI, MachineRegisterInfo &MRI,
47 bool legalizeFceil(MachineInstr &MI, MachineRegisterInfo &MRI,
49 bool legalizeIntrinsicTrunc(MachineInstr &MI, MachineRegisterInfo &MRI,
51 bool legalizeITOFP(MachineInstr &MI, MachineRegisterInfo &MRI,
53 bool legalizeMinNumMaxNum(MachineInstr &MI, MachineRegisterInfo &MRI,
55 bool legalizeExtractVectorElt(MachineInstr &MI, MachineRegisterInfo &MRI,
57 bool legalizeInsertVectorElt(MachineInstr &MI, MachineRegisterInfo &MRI,
59 bool legalizeSinCos(MachineInstr &MI, MachineRegisterInfo &MRI,
66 bool legalizeGlobalValue(MachineInstr &MI, MachineRegisterInfo &MRI,
68 bool legalizeLoad(MachineInstr &MI, MachineRegisterInfo &MRI,
72 bool legalizeFMad(MachineInstr &MI, MachineRegisterInfo &MRI,
75 bool legalizeAtomicCmpXChg(MachineInstr &MI, MachineRegisterInfo &MRI,
78 Register getLiveInRegister(MachineRegisterInfo &MRI,
84 MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B,
87 bool legalizeFDIV(MachineInstr &MI, MachineRegisterInfo &MRI,
89 bool legalizeFDIV16(MachineInstr &MI, MachineRegisterInfo &MRI,
91 bool legalizeFastUnsafeFDIV(MachineInstr &MI, MachineRegisterInfo &MRI,
93 bool legalizeFDIVFastIntrin(MachineInstr &MI, MachineRegisterInfo &MRI,
96 bool legalizeImplicitArgPtr(MachineInstr &MI, MachineRegisterInfo &MRI,
98 bool legalizeIsAddrSpace(MachineInstr &MI, MachineRegisterInfo &MRI,
101 Register handleD16VData(MachineIRBuilder &B, MachineRegisterInfo &MRI,
103 bool legalizeRawBufferStore(MachineInstr &MI, MachineRegisterInfo &MRI,
105 bool legalizeIntrinsic(MachineInstr &MI, MachineRegisterInfo &MRI,
lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp 94 void dump(MachineRegisterInfo *MRI);
265 LLVM_DUMP_METHOD void PHILinearize::dump(MachineRegisterInfo *MRI) {
345 MachineInstr *DefInstr, const MachineRegisterInfo *MRI,
350 const MachineRegisterInfo *MRI,
354 void storeMBBLiveOuts(MachineBasicBlock *MBB, const MachineRegisterInfo *MRI,
358 void storeLiveOuts(MachineBasicBlock *MBB, const MachineRegisterInfo *MRI,
361 void storeLiveOuts(RegionMRT *Region, const MachineRegisterInfo *MRI,
367 LinearizedRegion(MachineBasicBlock *MBB, const MachineRegisterInfo *MRI,
400 MachineRegisterInfo *MRI, bool ReplaceInside,
405 MachineRegisterInfo *MRI);
409 MachineRegisterInfo *MRI);
429 bool hasNoDef(unsigned Reg, MachineRegisterInfo *MRI);
431 void removeFalseRegisterKills(MachineRegisterInfo *MRI);
433 void initLiveOut(RegionMRT *Region, const MachineRegisterInfo *MRI,
475 MachineRegisterInfo *MRI);
618 MachineRegisterInfo *MRI) {
637 const SIInstrInfo *TII, MachineRegisterInfo *MRI) {
694 const MachineRegisterInfo *MRI,
734 const MachineRegisterInfo *MRI,
751 const MachineRegisterInfo *MRI,
794 const MachineRegisterInfo *MRI,
813 const MachineRegisterInfo *MRI,
910 MachineRegisterInfo *MRI,
934 for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(Register),
972 MachineRegisterInfo *MRI) {
979 MachineRegisterInfo *MRI) {
1011 bool LinearizedRegion::hasNoDef(unsigned Reg, MachineRegisterInfo *MRI) {
1017 void LinearizedRegion::removeFalseRegisterKills(MachineRegisterInfo *MRI) {
1062 const MachineRegisterInfo *MRI,
1069 const MachineRegisterInfo *MRI,
1092 MachineRegisterInfo *MRI;
1234 MachineRegisterInfo *MRI,
2230 for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(Register),
2831 MachineRegisterInfo *MRI,
lib/Target/AMDGPU/AMDGPUMacroFusion.cpp 45 const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp 43 MachineRegisterInfo &MRI;
48 ApplyRegBankMapping(MachineRegisterInfo &MRI_, const RegisterBank *RB)
342 const MachineRegisterInfo &MRI = MF.getRegInfo();
608 MachineRegisterInfo *MRI = B.getMRI();
625 static void setRegsToType(MachineRegisterInfo &MRI, ArrayRef<Register> Regs,
963 MachineRegisterInfo &MRI, ArrayRef<unsigned> OpIndices) const {
977 MachineIRBuilder &B, MachineInstr &MI, MachineRegisterInfo &MRI,
992 MachineInstr &MI, MachineRegisterInfo &MRI,
1000 MachineInstr &MI, MachineRegisterInfo &MRI, unsigned OpIdx) const {
1025 static MachineInstr *getOtherVRegDef(const MachineRegisterInfo &MRI,
1039 MachineRegisterInfo &MRI) const {
1112 MachineRegisterInfo &MRI, int RsrcIdx) const {
1150 MachineRegisterInfo &MRI,
1174 getBaseWithConstantOffset(MachineRegisterInfo &MRI, Register Reg) {
1231 static bool isZero(Register Reg, MachineRegisterInfo &MRI) {
1251 MachineRegisterInfo &MRI = *B.getMRI();
1330 MachineRegisterInfo &MRI = OpdMapper.getMRI();
1905 const MachineRegisterInfo &MRI = MF.getRegInfo();
1924 const MachineRegisterInfo &MRI = MF.getRegInfo();
1939 const MachineRegisterInfo &MRI = MF.getRegInfo();
1975 const MachineRegisterInfo &MRI = MF.getRegInfo();
1992 AMDGPURegisterBankInfo::getImageMapping(const MachineRegisterInfo &MRI,
2034 const MachineRegisterInfo &MRI = MF.getRegInfo();
2072 const MachineRegisterInfo &MRI,
2088 const MachineRegisterInfo &MRI,
2099 const MachineRegisterInfo &MRI,
2114 const MachineRegisterInfo &MRI = MF.getRegInfo();
lib/Target/AMDGPU/AMDGPURegisterBankInfo.h 50 MachineRegisterInfo &MRI,
61 MachineRegisterInfo &MRI,
64 MachineRegisterInfo &MRI,
67 void constrainOpWithReadfirstlane(MachineInstr &MI, MachineRegisterInfo &MRI,
71 MachineRegisterInfo &MRI) const;
75 MachineRegisterInfo &MRI, int RSrcIdx) const;
77 Register handleD16VData(MachineIRBuilder &B, MachineRegisterInfo &MRI,
92 unsigned getRegBankID(Register Reg, const MachineRegisterInfo &MRI,
98 const MachineRegisterInfo &MRI,
103 const MachineRegisterInfo &MRI,
121 addMappingFromTable(const MachineInstr &MI, const MachineRegisterInfo &MRI,
127 const MachineInstr &MI, const MachineRegisterInfo &MRI) const;
131 const MachineInstr &MI, const MachineRegisterInfo &MRI) const;
139 const InstructionMapping &getImageMapping(const MachineRegisterInfo &MRI,
lib/Target/AMDGPU/GCNDPPCombine.cpp 67 MachineRegisterInfo *MRI;
lib/Target/AMDGPU/GCNHazardRecognizer.cpp 719 const MachineRegisterInfo &MRI) {
748 const MachineRegisterInfo &MRI = MF.getRegInfo();
770 const MachineRegisterInfo &MRI = MF.getRegInfo();
787 const MachineRegisterInfo &MRI = MF.getRegInfo();
lib/Target/AMDGPU/GCNHazardRecognizer.h 82 int checkVALUHazardsHelper(const MachineOperand &Def, const MachineRegisterInfo &MRI);
lib/Target/AMDGPU/GCNIterativeScheduler.cpp 96 const auto &MRI = BB->getParent()->getRegInfo();
lib/Target/AMDGPU/GCNNSAReassign.cpp 71 const MachineRegisterInfo *MRI;
lib/Target/AMDGPU/GCNRegBankReassign.cpp 139 const MachineRegisterInfo *MRI;
lib/Target/AMDGPU/GCNRegPressure.cpp 38 const MachineRegisterInfo &MRI) {
86 const MachineRegisterInfo &MRI) {
100 const MachineRegisterInfo &MRI) {
199 const MachineRegisterInfo &MRI) {
211 const MachineRegisterInfo &MRI,
259 const MachineRegisterInfo &MRI) {
277 const MachineRegisterInfo &MRI) {
498 const MachineRegisterInfo &MRI) {
lib/Target/AMDGPU/GCNRegPressure.h 62 const MachineRegisterInfo &MRI);
85 static unsigned getRegKind(unsigned Reg, const MachineRegisterInfo &MRI);
107 mutable const MachineRegisterInfo *MRI = nullptr;
133 const MachineRegisterInfo &MRI);
190 const MachineRegisterInfo &MRI);
194 const MachineRegisterInfo &MRI);
213 auto &MRI = (*R.begin())->getParent()->getParent()->getRegInfo();
253 GCNRegPressure getRegPressure(const MachineRegisterInfo &MRI,
266 const MachineRegisterInfo &MRI);
lib/Target/AMDGPU/R600ISelLowering.cpp 293 MachineRegisterInfo &MRI = MF->getRegInfo();
lib/Target/AMDGPU/R600ISelLowering.h 67 MachineRegisterInfo & MRI, unsigned dword_offset) const;
lib/Target/AMDGPU/R600InstrInfo.cpp 1180 const MachineRegisterInfo &MRI = MF.getRegInfo();
lib/Target/AMDGPU/R600MachineScheduler.h 31 MachineRegisterInfo *MRI = nullptr;
lib/Target/AMDGPU/R600OptimizeVectorRegisters.cpp 59 static bool isImplicitlyDef(MachineRegisterInfo &MRI, unsigned Reg) {
75 RegSeqInfo(MachineRegisterInfo &MRI, MachineInstr *MI) : Instr(MI) {
98 MachineRegisterInfo *MRI;
235 for (MachineRegisterInfo::use_instr_iterator It = MRI->use_instr_begin(Reg),
283 for (MachineRegisterInfo::use_instr_iterator It = MRI->use_instr_begin(Reg),
354 for (MachineRegisterInfo::def_instr_iterator
lib/Target/AMDGPU/SIAddIMGInit.cpp 63 MachineRegisterInfo &MRI = MF.getRegInfo();
lib/Target/AMDGPU/SIFixSGPRCopies.cpp 116 MachineRegisterInfo *MRI;
154 const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
169 const MachineRegisterInfo &MRI) {
204 MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
242 MachineRegisterInfo &MRI) {
422 const MachineRegisterInfo &MRI,
lib/Target/AMDGPU/SIFixupVectorISel.cpp 88 MachineRegisterInfo &MRI,
157 MachineRegisterInfo &MRI,
223 MachineRegisterInfo &MRI = MF.getRegInfo();
lib/Target/AMDGPU/SIFoldOperands.cpp 89 MachineRegisterInfo *MRI;
249 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
404 MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
451 const SIInstrInfo *TII, const MachineRegisterInfo &MRI) {
513 MachineRegisterInfo &MRI = UseMI->getParent()->getParent()->getRegInfo();
565 MachineRegisterInfo::use_iterator Next;
566 for (MachineRegisterInfo::use_iterator
627 MachineRegisterInfo::use_iterator NextUse;
629 for (MachineRegisterInfo::use_iterator
943 static MachineOperand *getImmOrMaterializedImm(MachineRegisterInfo &MRI,
965 static bool tryConstantFoldOp(MachineRegisterInfo &MRI,
1128 MachineRegisterInfo::use_iterator NextUse;
1129 for (MachineRegisterInfo::use_iterator
1191 SmallVector <MachineRegisterInfo::use_iterator, 4> UsesToProcess;
1192 for (MachineRegisterInfo::use_iterator
1283 static bool hasOneNonDBGUseInst(const MachineRegisterInfo &MRI, unsigned Reg) {
lib/Target/AMDGPU/SIFormMemoryClauses.cpp 74 const MachineRegisterInfo *MRI;
lib/Target/AMDGPU/SIFrameLowering.cpp 50 static unsigned findScratchNonCalleeSaveRegister(MachineRegisterInfo &MRI,
82 static MCPhysReg findUnusedSGPRNonCalleeSaved(MachineRegisterInfo &MRI) {
212 MachineRegisterInfo &MRI = MF.getRegInfo();
275 MachineRegisterInfo &MRI = MF.getRegInfo();
322 MachineRegisterInfo &MRI = MF.getRegInfo();
407 MachineRegisterInfo &MRI = MF.getRegInfo();
691 MachineRegisterInfo &MRI = MF.getRegInfo();
836 MachineRegisterInfo &MRI = MF.getRegInfo();
lib/Target/AMDGPU/SIISelLowering.cpp 1411 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
1618 MachineRegisterInfo &MRI = MF.getRegInfo();
1787 MachineRegisterInfo &MRI = MF.getRegInfo();
1911 MachineRegisterInfo &MRI = MF.getRegInfo();
1992 MachineRegisterInfo *MRI = &Entry->getParent()->getRegInfo();
2651 const MachineRegisterInfo &MRI = MF.getRegInfo();
3119 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
3281 MachineRegisterInfo &MRI = MF->getRegInfo();
3333 MachineRegisterInfo &MRI,
3395 MachineRegisterInfo &MRI = MF->getRegInfo();
3486 MachineRegisterInfo &MRI = MF->getRegInfo();
3600 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
3677 MachineRegisterInfo &MRI = MF->getRegInfo();
3749 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
10258 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
10328 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
10390 MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
10675 MachineRegisterInfo &MRI = MF.getRegInfo();
10834 const MachineRegisterInfo &MRI = MF->getRegInfo();
11029 MachineRegisterInfo &MRI = MF.getRegInfo();
lib/Target/AMDGPU/SIInsertWaitcnts.cpp 264 const MachineRegisterInfo *MRI,
279 const MachineRegisterInfo *MRI, WaitEventType E,
347 const SIRegisterInfo *TRI, const MachineRegisterInfo *MRI,
371 const MachineRegisterInfo *MRI = nullptr;
461 const MachineRegisterInfo *MRI,
474 const MachineRegisterInfo &MRIA = *MRI;
504 const MachineRegisterInfo *MRI, unsigned OpNo,
518 const MachineRegisterInfo *MRI,
520 const MachineRegisterInfo &MRIA = *MRI;
989 const MachineRegisterInfo &MRIA = *MRI;
1025 const MachineRegisterInfo &MRIA = *MRI;
lib/Target/AMDGPU/SIInstrInfo.cpp 475 const MachineRegisterInfo &MRI =
755 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
818 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
944 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
957 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
1073 MachineRegisterInfo &MRI = MF->getRegInfo();
1097 MachineRegisterInfo &MRI = MF->getRegInfo();
1198 MachineRegisterInfo &MRI = MF->getRegInfo();
1216 MachineRegisterInfo &MRI = MF->getRegInfo();
1570 MachineRegisterInfo &MRI = MF->getRegInfo();
1778 MachineRegisterInfo &MRI = MF->getRegInfo();
2125 const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2139 const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2167 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2307 unsigned Reg, MachineRegisterInfo *MRI) const {
2597 const MachineRegisterInfo &MRI = MF->getRegInfo();
2785 bool SIInstrInfo::mayReadEXEC(const MachineRegisterInfo &MRI,
2988 const MachineRegisterInfo &MRI) const {
3099 bool SIInstrInfo::usesConstantBus(const MachineRegisterInfo &MRI,
3197 const MachineRegisterInfo &MRI = MF->getRegInfo();
3738 const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
3809 const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
3828 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
3913 bool SIInstrInfo::isLegalRegOperand(const MachineRegisterInfo &MRI,
3938 bool SIInstrInfo::isLegalVSrcOperand(const MachineRegisterInfo &MRI,
3952 const MachineRegisterInfo &MRI = MF.getRegInfo();
4012 void SIInstrInfo::legalizeOperandsVOP2(MachineRegisterInfo &MRI,
4124 void SIInstrInfo::legalizeOperandsVOP3(MachineRegisterInfo &MRI,
4212 MachineRegisterInfo &MRI) const {
4253 void SIInstrInfo::legalizeOperandsSMRD(MachineRegisterInfo &MRI,
4319 emitLoadSRsrcFromVGPRLoop(const SIInstrInfo &TII, MachineRegisterInfo &MRI,
4408 MachineRegisterInfo &MRI = MF.getRegInfo();
4475 MachineRegisterInfo &MRI = MF.getRegInfo();
4516 MachineRegisterInfo &MRI = MF.getRegInfo();
4824 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
5109 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
5139 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
5166 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
5232 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
5261 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
5290 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
5346 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
5416 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
5480 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
5521 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
5558 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
5618 MachineRegisterInfo &MRI,
5620 for (MachineRegisterInfo::use_iterator I = MRI.use_begin(DstReg),
5653 MachineRegisterInfo &MRI,
5801 const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
6072 MachineRegisterInfo &MRI = IfEntry->getParent()->getRegInfo();
6098 MachineRegisterInfo &MRI = LoopEnd->getParent()->getRegInfo();
6196 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
6417 MachineRegisterInfo &MRI) {
6451 bool llvm::execMayBeModifiedBeforeUse(const MachineRegisterInfo &MRI,
6484 bool llvm::execMayBeModifiedBeforeAnyUse(const MachineRegisterInfo &MRI,
lib/Target/AMDGPU/SIInstrInfo.h 117 MachineRegisterInfo &MRI,
120 void addUsersToMoveToVALUWorklist(unsigned Reg, MachineRegisterInfo &MRI,
319 MachineRegisterInfo *MRI) const final;
674 const MachineRegisterInfo &MRI = MF.getRegInfo();
680 const MachineRegisterInfo &MRI = MF.getRegInfo();
691 bool mayReadEXEC(const MachineRegisterInfo &MRI, const MachineInstr &MI) const;
770 bool usesConstantBus(const MachineRegisterInfo &MRI,
783 const MachineRegisterInfo &MRI) const;
850 bool isLegalVSrcOperand(const MachineRegisterInfo &MRI,
856 bool isLegalRegOperand(const MachineRegisterInfo &MRI,
862 void legalizeOperandsVOP2(MachineRegisterInfo &MRI, MachineInstr &MI) const;
865 void legalizeOperandsVOP3(MachineRegisterInfo &MRI, MachineInstr &MI) const;
872 MachineRegisterInfo &MRI) const;
874 void legalizeOperandsSMRD(MachineRegisterInfo &MRI, MachineInstr &MI) const;
1035 MachineRegisterInfo &MRI) {
1058 MachineRegisterInfo &MRI);
1063 bool execMayBeModifiedBeforeUse(const MachineRegisterInfo &MRI,
1071 bool execMayBeModifiedBeforeAnyUse(const MachineRegisterInfo &MRI,
lib/Target/AMDGPU/SILoadStoreOptimizer.cpp 159 bool hasMergeableAddress(const MachineRegisterInfo &MRI) {
208 MachineRegisterInfo *MRI = nullptr;
lib/Target/AMDGPU/SILowerControlFlow.cpp 83 MachineRegisterInfo *MRI = nullptr;
147 static bool isSimpleIf(const MachineInstr &MI, const MachineRegisterInfo *MRI,
418 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
lib/Target/AMDGPU/SILowerI1Copies.cpp 57 MachineRegisterInfo *MRI = nullptr;
429 MachineRegisterInfo &MRI = MF.getRegInfo();
494 const MachineRegisterInfo &MRI,
lib/Target/AMDGPU/SILowerSGPRSpills.cpp 185 MachineRegisterInfo &MRI = MF.getRegInfo();
251 MachineRegisterInfo &MRI = MF.getRegInfo();
lib/Target/AMDGPU/SIMachineFunctionInfo.cpp 272 MachineRegisterInfo &MRI = MF.getRegInfo();
327 MachineRegisterInfo &MRI = MF.getRegInfo();
lib/Target/AMDGPU/SIMachineScheduler.cpp 310 const MachineRegisterInfo *MRI,
312 for (MachineRegisterInfo::def_instr_iterator
330 MachineRegisterInfo *MRI = DAG->getMRI();
lib/Target/AMDGPU/SIMachineScheduler.h 459 MachineRegisterInfo *getMRI() { return &MRI; }
lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp 39 MachineRegisterInfo *MRI;
122 const MachineRegisterInfo &MRI,
190 MachineRegisterInfo &MRI,
302 MachineRegisterInfo &MRI = MF.getRegInfo();
lib/Target/AMDGPU/SIPeepholeSDWA.cpp 72 MachineRegisterInfo *MRI;
127 MachineRegisterInfo *getMRI() const {
295 const MachineRegisterInfo *MRI) {
317 const MachineRegisterInfo *MRI) {
446 MachineRegisterInfo *MRI = getMRI();
lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp 39 MachineRegisterInfo *MRI;
lib/Target/AMDGPU/SIRegisterInfo.cpp 361 MachineRegisterInfo &MRI = MF->getRegInfo();
560 MachineRegisterInfo &MRI = MF->getRegInfo();
1505 SIRegisterInfo::findUnusedRegister(const MachineRegisterInfo &MRI,
1690 SIRegisterInfo::getRegClassForReg(const MachineRegisterInfo &MRI,
1698 bool SIRegisterInfo::isVGPR(const MachineRegisterInfo &MRI,
1705 bool SIRegisterInfo::isAGPR(const MachineRegisterInfo &MRI,
1778 const MachineRegisterInfo &MRI) const {
1835 const MachineRegisterInfo &MRI) const {
1866 MachineRegisterInfo &MRI,
lib/Target/AMDGPU/SIRegisterInfo.h 138 bool isSGPRReg(const MachineRegisterInfo &MRI, unsigned Reg) const {
194 unsigned findUnusedRegister(const MachineRegisterInfo &MRI,
202 const TargetRegisterClass *getRegClassForReg(const MachineRegisterInfo &MRI,
204 bool isVGPR(const MachineRegisterInfo &MRI, unsigned Reg) const;
205 bool isAGPR(const MachineRegisterInfo &MRI, unsigned Reg) const;
206 bool isVectorRegister(const MachineRegisterInfo &MRI, unsigned Reg) const {
252 const MachineRegisterInfo &MRI) const;
257 const MachineRegisterInfo &MRI) const {
263 const MachineRegisterInfo &MRI) const override;
282 MachineRegisterInfo &MRI,
lib/Target/AMDGPU/SIShrinkInstructions.cpp 72 MachineRegisterInfo &MRI, bool TryToCommute = true) {
316 MachineRegisterInfo &MRI,
424 const SIRegisterInfo &TRI, const MachineRegisterInfo &MRI) {
455 static MachineInstr* matchSwap(MachineInstr &MovT, MachineRegisterInfo &MRI,
553 MachineRegisterInfo &MRI = MF.getRegInfo();
lib/Target/AMDGPU/SIWholeQuadMode.cpp 152 MachineRegisterInfo *MRI;
lib/Target/ARC/ARCISelLowering.cpp 452 MachineRegisterInfo &RegInfo = MF.getRegInfo();
lib/Target/ARC/ARCOptAddrMode.cpp 60 MachineRegisterInfo *MRI = nullptr;
140 MachineRegisterInfo *MRI) {
lib/Target/ARM/A15SDOptimizer.cpp 59 MachineRegisterInfo *MRI;
626 for (MachineRegisterInfo::use_iterator I = MRI->use_begin(DPRDefReg),
lib/Target/ARM/ARMAsmPrinter.cpp 1073 const MachineRegisterInfo &MachineRegInfo = MF.getRegInfo();
lib/Target/ARM/ARMBaseInstrInfo.cpp 1746 const MachineRegisterInfo *MRI) const {
2177 ARMBaseInstrInfo::canFoldIntoMOVCC(unsigned Reg, const MachineRegisterInfo &MRI,
2239 MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
2905 int CmpValue, const MachineRegisterInfo *MRI) const {
2914 for (MachineRegisterInfo::use_instr_iterator
3203 MachineRegisterInfo *MRI) const {
4695 const MachineRegisterInfo *MRI,
lib/Target/ARM/ARMBaseInstrInfo.h 239 const MachineRegisterInfo *MRI) const override;
300 const MachineRegisterInfo *MRI) const override;
313 MachineRegisterInfo *MRI) const override;
389 const MachineRegisterInfo *MRI,
407 MachineInstr *canFoldIntoMOVCC(unsigned Reg, const MachineRegisterInfo &MRI,
lib/Target/ARM/ARMBaseRegisterInfo.cpp 307 const MachineRegisterInfo &MRI = MF.getRegInfo();
357 MachineRegisterInfo *MRI = &MF.getRegInfo();
417 const MachineRegisterInfo *MRI = &MF.getRegInfo();
643 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
845 const MachineRegisterInfo &MRI = MF->getRegInfo();
lib/Target/ARM/ARMCallLowering.cpp 89 OutgoingValueHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
286 IncomingValueHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
404 FormalArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
474 CallReturnHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
509 MachineRegisterInfo &MRI = MF.getRegInfo();
lib/Target/ARM/ARMConstantIslandPass.cpp 925 MachineRegisterInfo &MRI = MF->getRegInfo();
lib/Target/ARM/ARMFrameLowering.cpp 998 const MachineRegisterInfo &MRI = MF.getRegInfo();
1654 MachineRegisterInfo &MRI = MF.getRegInfo();
lib/Target/ARM/ARMISelDAGToDAG.cpp 4712 MachineRegisterInfo &MRI = MF->getRegInfo();
lib/Target/ARM/ARMISelLowering.cpp 2509 MachineFrameInfo &MFI, const MachineRegisterInfo *MRI,
2634 const MachineRegisterInfo *MRI = &MF.getRegInfo();
2668 const MachineRegisterInfo &MRI = MF.getRegInfo();
9345 MachineRegisterInfo *MRI = &MF->getRegInfo();
9469 MachineRegisterInfo *MRI = &MF->getRegInfo();
10024 MachineRegisterInfo &MRI = MF->getRegInfo();
10300 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
10626 MachineRegisterInfo &MRI = Fn->getRegInfo();
10696 MachineRegisterInfo &MRI = MF->getRegInfo();
17104 MachineRegisterInfo *MRI = &Entry->getParent()->getRegInfo();
lib/Target/ARM/ARMInstructionSelector.cpp 47 MachineRegisterInfo &MRI) const;
59 bool selectGlobal(MachineInstrBuilder &MIB, MachineRegisterInfo &MRI) const;
60 bool selectSelect(MachineInstrBuilder &MIB, MachineRegisterInfo &MRI) const;
65 bool validOpRegPair(MachineRegisterInfo &MRI, unsigned LHS, unsigned RHS,
69 bool validReg(MachineRegisterInfo &MRI, unsigned Reg, unsigned ExpectedSize,
185 MachineRegisterInfo &MRI,
211 MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI,
232 MachineRegisterInfo &MRI,
263 MachineRegisterInfo &MRI,
500 bool ARMInstructionSelector::validOpRegPair(MachineRegisterInfo &MRI,
509 bool ARMInstructionSelector::validReg(MachineRegisterInfo &MRI, unsigned Reg,
527 MachineRegisterInfo &MRI) const {
609 MachineRegisterInfo &MRI) const {
767 MachineRegisterInfo &MRI) const {
842 auto &MRI = MF.getRegInfo();
lib/Target/ARM/ARMLegalizerInfo.cpp 361 MachineRegisterInfo &MRI,
lib/Target/ARM/ARMLegalizerInfo.h 31 bool legalizeCustom(MachineInstr &MI, MachineRegisterInfo &MRI,
lib/Target/ARM/ARMLoadStoreOptimizer.cpp 2041 MachineRegisterInfo *MRI;
lib/Target/ARM/ARMLowOverheadLoops.cpp 39 MachineRegisterInfo *MRI = nullptr;
lib/Target/ARM/ARMRegisterBankInfo.cpp 225 const MachineRegisterInfo &MRI = MF.getRegInfo();
lib/Target/ARM/MLxExpansionPass.cpp 52 MachineRegisterInfo *MRI;
lib/Target/ARM/Thumb1FrameLowering.cpp 849 const MachineRegisterInfo &MRI = MF.getRegInfo();
lib/Target/ARM/Thumb2InstrInfo.cpp 163 MachineRegisterInfo *MRI = &MF.getRegInfo();
204 MachineRegisterInfo *MRI = &MF.getRegInfo();
656 MachineRegisterInfo *MRI = &MF.getRegInfo();
lib/Target/AVR/AVRExpandPseudoInsts.cpp 71 MachineRegisterInfo &getRegInfo(Block &MBB) { return MBB.getParent()->getRegInfo(); }
lib/Target/AVR/AVRISelDAGToDAG.cpp 209 MachineRegisterInfo &RI = MF->getRegInfo();
lib/Target/AVR/AVRISelLowering.cpp 1442 MachineRegisterInfo &RI = F->getRegInfo();
lib/Target/BPF/BPFISelLowering.cpp 219 MachineRegisterInfo &RegInfo = MF.getRegInfo();
572 MachineRegisterInfo &RegInfo = F->getRegInfo();
590 MachineRegisterInfo &MRI = MF->getRegInfo();
lib/Target/BPF/BPFMIPeephole.cpp 44 MachineRegisterInfo *MRI;
300 MachineRegisterInfo *MRI;
lib/Target/BPF/BPFMISimplifyPatchable.cpp 76 MachineRegisterInfo *MRI = &MF->getRegInfo();
lib/Target/Hexagon/BitTracker.h 114 MachineRegisterInfo &MRI;
392 MachineEvaluator(const TargetRegisterInfo &T, MachineRegisterInfo &M)
490 MachineRegisterInfo &MRI;
lib/Target/Hexagon/HexagonBitSimplify.cpp 209 MachineRegisterInfo &MRI);
211 unsigned &Begin, unsigned &Width, MachineRegisterInfo &MRI);
213 unsigned NewSR, MachineRegisterInfo &MRI);
215 unsigned NewR, unsigned NewSR, MachineRegisterInfo &MRI);
218 const MachineRegisterInfo &MRI);
226 const BitTracker::RegisterRef &RR, MachineRegisterInfo &MRI);
228 const BitTracker::RegisterRef &RS, MachineRegisterInfo &MRI);
234 static bool hasTiedUse(unsigned Reg, MachineRegisterInfo &MRI,
355 MachineRegisterInfo &MRI) {
368 unsigned NewSR, MachineRegisterInfo &MRI) {
384 unsigned NewR, unsigned NewSR, MachineRegisterInfo &MRI) {
405 unsigned &Begin, unsigned &Width, MachineRegisterInfo &MRI) {
433 const MachineRegisterInfo &MRI) {
895 const BitTracker::RegisterRef &RR, MachineRegisterInfo &MRI) {
926 const BitTracker::RegisterRef &RS, MachineRegisterInfo &MRI) {
938 bool HexagonBitSimplify::hasTiedUse(unsigned Reg, MachineRegisterInfo &MRI,
967 MachineRegisterInfo &MRI;
1052 const HexagonRegisterInfo &hri, MachineRegisterInfo &mri)
1069 MachineRegisterInfo &MRI;
1375 MachineRegisterInfo &mri)
1386 MachineRegisterInfo &MRI;
1497 const HexagonRegisterInfo &hri, MachineRegisterInfo &mri)
1508 MachineRegisterInfo &MRI;
1517 CopyPropagation(const HexagonRegisterInfo &hri, MachineRegisterInfo &mri)
1528 MachineRegisterInfo &MRI;
1741 MachineRegisterInfo &mri, MachineFunction &mf)
1785 MachineRegisterInfo &MRI;
2767 MachineRegisterInfo &MRI = MF.getRegInfo();
2901 MachineRegisterInfo *MRI = nullptr;
lib/Target/Hexagon/HexagonBitTracker.cpp 41 MachineRegisterInfo &mri,
lib/Target/Hexagon/HexagonBitTracker.h 31 HexagonEvaluator(const HexagonRegisterInfo &tri, MachineRegisterInfo &mri,
lib/Target/Hexagon/HexagonBlockRanges.cpp 233 const MachineBasicBlock &B, const MachineRegisterInfo &MRI,
262 RegisterRef R, const MachineRegisterInfo &MRI,
295 MachineRegisterInfo &MRI = B.getParent()->getRegInfo();
473 auto &MRI = MF.getRegInfo();
lib/Target/Hexagon/HexagonBlockRanges.h 147 const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI);
162 const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI);
lib/Target/Hexagon/HexagonConstExtenders.cpp 384 MachineRegisterInfo *MRI = nullptr;
lib/Target/Hexagon/HexagonConstPropagation.cpp 263 MachineRegisterInfo *MRI;
1877 MachineRegisterInfo *MRI;
lib/Target/Hexagon/HexagonEarlyIfConv.cpp 216 MachineRegisterInfo *MRI = nullptr;
lib/Target/Hexagon/HexagonExpandCondsets.cpp 167 MachineRegisterInfo *MRI = nullptr;
lib/Target/Hexagon/HexagonFrameLowering.cpp 1397 MachineRegisterInfo &MRI = MF.getRegInfo();
1885 MachineRegisterInfo &MRI = MF.getRegInfo();
1952 MachineRegisterInfo &MRI = MF.getRegInfo();
1982 auto &MRI = MF.getRegInfo();
2013 auto &MRI = MF.getRegInfo();
lib/Target/Hexagon/HexagonGenInsert.cpp 567 MachineRegisterInfo *MRI;
1300 using use_iterator = MachineRegisterInfo::use_nodbg_iterator;
lib/Target/Hexagon/HexagonGenPredicate.cpp 108 MachineRegisterInfo *MRI = nullptr;
227 using use_iterator = MachineRegisterInfo::use_iterator;
lib/Target/Hexagon/HexagonHardwareLoops.cpp 102 MachineRegisterInfo *MRI;
1045 using use_nodbg_iterator = MachineRegisterInfo::use_nodbg_iterator;
1096 MachineRegisterInfo::use_iterator nextI;
1097 for (MachineRegisterInfo::use_iterator I = MRI->use_begin(Reg),
1454 for (MachineRegisterInfo::use_instr_nodbg_iterator I = MRI->use_instr_nodbg_begin(Reg),
lib/Target/Hexagon/HexagonISelLowering.cpp 285 auto &MRI = DAG.getMachineFunction().getRegInfo();
697 MachineRegisterInfo &MRI = MF.getRegInfo();
lib/Target/Hexagon/HexagonInstrInfo.cpp 1024 MachineRegisterInfo &MRI = MF.getRegInfo();
1606 MachineRegisterInfo &MRI = B.getParent()->getRegInfo();
1984 MachineRegisterInfo &MRI = MF->getRegInfo();
lib/Target/Hexagon/HexagonNewValueJump.cpp 292 MachineRegisterInfo &MRI = MF.getRegInfo();
lib/Target/Hexagon/HexagonOptAddrMode.cpp 81 MachineRegisterInfo *MRI = nullptr;
lib/Target/Hexagon/HexagonPeephole.cpp 84 const MachineRegisterInfo *MRI;
lib/Target/Hexagon/HexagonRDFOpt.cpp 81 MachineRegisterInfo *MRI;
91 HexagonDCE(DataFlowGraph &G, MachineRegisterInfo &MRI)
lib/Target/Hexagon/HexagonRegisterInfo.cpp 219 auto &MRI = MF.getRegInfo();
lib/Target/Hexagon/HexagonSplitDouble.cpp 87 MachineRegisterInfo *MRI;
lib/Target/Hexagon/HexagonStoreWidening.cpp 66 const MachineRegisterInfo *MRI;
lib/Target/Hexagon/HexagonVExtract.cpp 57 MachineRegisterInfo &MRI);
67 MachineRegisterInfo &MRI) {
104 MachineRegisterInfo &MRI = MF.getRegInfo();
lib/Target/Hexagon/RDFDeadCode.h 35 DeadCodeElimination(DataFlowGraph &dfg, MachineRegisterInfo &mri)
53 MachineRegisterInfo &MRI;
lib/Target/Hexagon/RDFGraph.cpp 894 MachineRegisterInfo &MRI = MF.getRegInfo();
lib/Target/Hexagon/RDFLiveness.h 54 Liveness(MachineRegisterInfo &mri, const DataFlowGraph &g)
lib/Target/Lanai/LanaiISelLowering.cpp 443 MachineRegisterInfo &RegInfo = MF.getRegInfo();
lib/Target/Lanai/LanaiInstrInfo.cpp 285 int CmpValue, const MachineRegisterInfo *MRI) const {
458 const MachineRegisterInfo &MRI) {
497 MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
lib/Target/Lanai/LanaiInstrInfo.h 106 const MachineRegisterInfo *MRI) const override;
lib/Target/MSP430/MSP430ISelLowering.cpp 608 MachineRegisterInfo &RegInfo = MF.getRegInfo();
1413 MachineRegisterInfo &RI = F->getRegInfo();
lib/Target/Mips/Mips16ISelDAGToDAG.cpp 72 MachineRegisterInfo &RegInfo = MF.getRegInfo();
lib/Target/Mips/MipsCallLowering.cpp 92 IncomingValueHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI)
122 CallReturnHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
227 OutgoingValueHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
lib/Target/Mips/MipsCallLowering.h 28 MipsHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI)
43 MachineRegisterInfo &MRI;
lib/Target/Mips/MipsISelLowering.cpp 1426 MachineRegisterInfo &RegInfo = MF->getRegInfo();
1555 MachineRegisterInfo &RegInfo = MF->getRegInfo();
1574 MachineRegisterInfo &RegInfo = MF->getRegInfo();
1731 MachineRegisterInfo &MRI = MF->getRegInfo();
1783 MachineRegisterInfo &RegInfo = MF->getRegInfo();
lib/Target/Mips/MipsInstructionSelector.cpp 44 bool selectCopy(MachineInstr &I, MachineRegisterInfo &MRI) const;
49 MachineRegisterInfo &MRI) const;
88 MachineRegisterInfo &MRI) const {
166 MachineRegisterInfo &MRI) const {
233 MachineRegisterInfo &MRI = MF.getRegInfo();
lib/Target/Mips/MipsLegalizerInfo.cpp 242 MachineRegisterInfo &MRI,
338 MachineRegisterInfo &MRI,
lib/Target/Mips/MipsLegalizerInfo.h 28 bool legalizeCustom(MachineInstr &MI, MachineRegisterInfo &MRI,
32 bool legalizeIntrinsic(MachineInstr &MI, MachineRegisterInfo &MRI,
lib/Target/Mips/MipsMachineFunction.cpp 68 MachineRegisterInfo &RegInfo = MF.getRegInfo();
lib/Target/Mips/MipsOptimizePICCall.cpp 280 MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
lib/Target/Mips/MipsRegisterBankInfo.cpp 172 Register Reg, const MachineRegisterInfo &MRI) {
187 Register Reg, const MachineRegisterInfo &MRI) {
198 const MachineRegisterInfo &MRI = MF.getRegInfo();
212 const MachineRegisterInfo &MRI = MF.getRegInfo();
225 const MachineRegisterInfo &MRI = MI->getMF()->getRegInfo();
340 const MachineRegisterInfo &MRI = MF.getRegInfo();
405 const MachineRegisterInfo &MRI = MF.getRegInfo();
626 MachineRegisterInfo &MRI) const {
666 MachineRegisterInfo &MRI = OpdMapper.getMRI();
lib/Target/Mips/MipsRegisterBankInfo.h 50 void setRegBank(MachineInstr &MI, MachineRegisterInfo &MRI) const;
82 void addDefUses(Register Reg, const MachineRegisterInfo &MRI);
83 void addUseDef(Register Reg, const MachineRegisterInfo &MRI);
lib/Target/Mips/MipsSEFrameLowering.cpp 90 MachineRegisterInfo &MRI;
lib/Target/Mips/MipsSEISelDAGToDAG.cpp 82 bool MipsSEDAGToDAGISel::replaceUsesWithZeroReg(MachineRegisterInfo *MRI,
105 for (MachineRegisterInfo::use_iterator U = MRI->use_begin(DstReg),
157 MachineRegisterInfo *MRI = &MF.getRegInfo();
lib/Target/Mips/MipsSEISelDAGToDAG.h 37 bool replaceUsesWithZeroReg(MachineRegisterInfo *MRI, const MachineInstr&);
lib/Target/Mips/MipsSEISelLowering.cpp 3036 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3105 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3172 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3218 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3247 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3283 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3329 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3443 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3478 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3512 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3567 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3666 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3771 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3820 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3849 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
lib/Target/Mips/MipsSEInstrInfo.cpp 614 MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo();
lib/Target/Mips/MipsSERegisterInfo.cpp 224 MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo();
lib/Target/NVPTX/NVPTXAsmPrinter.h 247 const MachineRegisterInfo *MRI;
lib/Target/NVPTX/NVPTXFrameLowering.cpp 37 MachineRegisterInfo &MR = MF.getRegInfo();
lib/Target/NVPTX/NVPTXInstrInfo.cpp 36 const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
lib/Target/NVPTX/NVPTXPeephole.cpp 82 const auto &MRI = MF.getRegInfo();
107 const auto &MRI = MF.getRegInfo();
146 const auto &MRI = MF.getRegInfo();
lib/Target/NVPTX/NVPTXReplaceImageHandles.cpp 134 const MachineRegisterInfo &MRI = MF.getRegInfo();
lib/Target/PowerPC/PPCBranchCoalescing.cpp 151 MachineRegisterInfo *MRI;
lib/Target/PowerPC/PPCFrameLowering.cpp 344 const MachineRegisterInfo &MRI = MF->getRegInfo();
451 MachineRegisterInfo::def_iterator RI = MF.getRegInfo().def_begin(LR);
2219 const MachineRegisterInfo &MRI = MF->getRegInfo();
lib/Target/PowerPC/PPCISelLowering.cpp10353 MachineRegisterInfo &RegInfo = F->getRegInfo();
10457 MachineRegisterInfo &RegInfo = F->getRegInfo();
10617 MachineRegisterInfo &MRI = MF->getRegInfo();
10758 MachineRegisterInfo &MRI = MF->getRegInfo();
11023 MachineRegisterInfo &RegInfo = F->getRegInfo();
11272 MachineRegisterInfo &RegInfo = F->getRegInfo();
11439 MachineRegisterInfo &RegInfo = F->getRegInfo();
11465 MachineRegisterInfo &RegInfo = F->getRegInfo();
11478 MachineRegisterInfo &RegInfo = F->getRegInfo();
11528 MachineRegisterInfo &RegInfo = F->getRegInfo();
11588 MachineRegisterInfo &RegInfo = F->getRegInfo();
15032 MachineRegisterInfo *MRI = &Entry->getParent()->getRegInfo();
lib/Target/PowerPC/PPCInstrInfo.cpp 190 const MachineRegisterInfo *MRI =
768 const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
801 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
1325 unsigned Reg, MachineRegisterInfo *MRI) const {
1638 const MachineRegisterInfo *MRI) const {
1698 for (MachineRegisterInfo::use_instr_iterator
1724 for (MachineRegisterInfo::use_instr_iterator
1874 for (MachineRegisterInfo::use_instr_iterator
2346 MachineRegisterInfo *MRI = &MI.getParent()->getParent()->getRegInfo();
2455 const MachineRegisterInfo &MRI =
2556 MachineRegisterInfo *MRI = &MF->getRegInfo();
2755 MachineRegisterInfo *MRI = &MF->getRegInfo();
3453 MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
3514 const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
3635 MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
3717 MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
3997 const MachineRegisterInfo *MRI = &MF->getRegInfo();
4240 MachineRegisterInfo &MRI = MF->getRegInfo();
lib/Target/PowerPC/PPCInstrInfo.h 308 MachineRegisterInfo *MRI) const override;
358 const MachineRegisterInfo *MRI) const override;
lib/Target/PowerPC/PPCMIPeephole.cpp 85 MachineRegisterInfo *MRI;
146 MachineRegisterInfo *MRI) {
917 MachineBasicBlock *BB2, MachineRegisterInfo *MRI) {
939 MachineRegisterInfo *MRI) {
lib/Target/PowerPC/PPCReduceCRLogicals.cpp 56 MachineBasicBlock *NewMBB, MachineRegisterInfo *MRI) {
87 MachineRegisterInfo *MRI) {
145 MachineRegisterInfo *MRI = &MF->getRegInfo();
380 MachineRegisterInfo *MRI;
lib/Target/PowerPC/PPCRegisterInfo.cpp 1234 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
1260 MachineRegisterInfo &MRI = MF.getRegInfo();
lib/Target/PowerPC/PPCVSXCopy.cpp 52 MachineRegisterInfo &MRI) {
62 bool IsVSReg(unsigned Reg, MachineRegisterInfo &MRI) {
66 bool IsVRReg(unsigned Reg, MachineRegisterInfo &MRI) {
70 bool IsF8Reg(unsigned Reg, MachineRegisterInfo &MRI) {
74 bool IsVSFReg(unsigned Reg, MachineRegisterInfo &MRI) {
78 bool IsVSSReg(unsigned Reg, MachineRegisterInfo &MRI) {
86 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
lib/Target/PowerPC/PPCVSXFMAMutate.cpp 73 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
lib/Target/PowerPC/PPCVSXSwapRemoval.cpp 101 MachineRegisterInfo *MRI;
lib/Target/RISCV/RISCVFrameLowering.cpp 67 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
lib/Target/RISCV/RISCVISelLowering.cpp 1121 MachineRegisterInfo &RegInfo = MF.getRegInfo();
1690 MachineRegisterInfo &RegInfo = MF.getRegInfo();
1776 MachineRegisterInfo &RegInfo = MF.getRegInfo();
1948 MachineRegisterInfo &RegInfo = MF.getRegInfo();
lib/Target/RISCV/RISCVInstrInfo.cpp 166 MachineRegisterInfo &MRI = MF->getRegInfo();
383 MachineRegisterInfo &MRI = MF->getRegInfo();
lib/Target/RISCV/RISCVMergeBaseOffset.cpp 61 MachineRegisterInfo *MRI;
lib/Target/RISCV/RISCVRegisterInfo.cpp 109 MachineRegisterInfo &MRI = MF.getRegInfo();
lib/Target/Sparc/LeonPasses.h 42 int getUnusedFPRegister(MachineRegisterInfo &MRI);
lib/Target/Sparc/SparcAsmPrinter.cpp 277 const MachineRegisterInfo &MRI = MF->getRegInfo();
lib/Target/Sparc/SparcFrameLowering.cpp 306 static bool LLVM_ATTRIBUTE_UNUSED verifyLeafProcRegUse(MachineRegisterInfo *MRI)
323 MachineRegisterInfo &MRI = MF.getRegInfo();
333 MachineRegisterInfo &MRI = MF.getRegInfo();
lib/Target/Sparc/SparcISelDAGToDAG.cpp 227 MachineRegisterInfo &MRI = MF->getRegInfo();
lib/Target/Sparc/SparcISelLowering.cpp 388 MachineRegisterInfo &RegInfo = MF.getRegInfo();
lib/Target/Sparc/SparcInstrInfo.cpp 481 MachineRegisterInfo &RegInfo = MF->getRegInfo();
lib/Target/SystemZ/SystemZISelLowering.cpp 1299 MachineRegisterInfo &MRI = MF.getRegInfo();
6509 MachineRegisterInfo &MRI = MF.getRegInfo();
6811 MachineRegisterInfo &MRI = MF.getRegInfo();
6930 MachineRegisterInfo &MRI = MF.getRegInfo();
7045 MachineRegisterInfo &MRI = MF.getRegInfo();
7169 MachineRegisterInfo &MRI = MF.getRegInfo();
7197 MachineRegisterInfo &MRI = MF.getRegInfo();
7227 MachineRegisterInfo &MRI = MF.getRegInfo();
7407 MachineRegisterInfo &MRI = MF.getRegInfo();
7512 MachineRegisterInfo *MRI = &MF.getRegInfo();
lib/Target/SystemZ/SystemZInstrInfo.cpp 545 const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
572 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
610 MachineRegisterInfo *MRI) const {
lib/Target/SystemZ/SystemZInstrInfo.h 230 MachineRegisterInfo *MRI) const override;
lib/Target/SystemZ/SystemZLDCleanup.cpp 134 MachineRegisterInfo &RegInfo = MF->getRegInfo();
lib/Target/SystemZ/SystemZRegisterInfo.cpp 31 const MachineRegisterInfo *MRI) {
62 const MachineRegisterInfo *MRI) {
83 const MachineRegisterInfo *MRI = &MF.getRegInfo();
lib/Target/WebAssembly/WebAssemblyAsmPrinter.h 25 const MachineRegisterInfo *MRI;
lib/Target/WebAssembly/WebAssemblyCFGStackify.cpp 713 MachineRegisterInfo &MRI) {
728 MachineRegisterInfo &MRI = MF.getRegInfo();
lib/Target/WebAssembly/WebAssemblyExplicitLocals.cpp 169 MachineRegisterInfo &MRI,
196 MachineRegisterInfo &MRI = MF.getRegInfo();
lib/Target/WebAssembly/WebAssemblyFixIrreducibleControlFlow.cpp 361 MachineRegisterInfo &MRI = MF.getRegInfo();
lib/Target/WebAssembly/WebAssemblyFrameLowering.cpp 164 auto &MRI = MF.getRegInfo();
231 auto &MRI = MF.getRegInfo();
lib/Target/WebAssembly/WebAssemblyISelLowering.cpp 336 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp 61 auto &MRI = MBB.getParent()->getRegInfo();
195 auto &MRI = MF.getRegInfo();
225 auto &MRI = MF.getRegInfo();
lib/Target/WebAssembly/WebAssemblyLateEHPrepare.cpp 128 MachineRegisterInfo &MRI = MF.getRegInfo();
237 MachineRegisterInfo &MRI = MF.getRegInfo();
lib/Target/WebAssembly/WebAssemblyLowerBrUnless.cpp 63 auto &MRI = MF.getRegInfo();
lib/Target/WebAssembly/WebAssemblyMCInstLower.cpp 239 const MachineRegisterInfo &MRI =
lib/Target/WebAssembly/WebAssemblyMemIntrinsicResults.cpp 86 const MachineRegisterInfo &MRI,
150 const MachineRegisterInfo &MRI,
183 MachineRegisterInfo &MRI = MF.getRegInfo();
lib/Target/WebAssembly/WebAssemblyOptimizeLiveIntervals.cpp 73 MachineRegisterInfo &MRI = MF.getRegInfo();
lib/Target/WebAssembly/WebAssemblyPeephole.cpp 62 MachineRegisterInfo &MRI) {
77 MachineRegisterInfo &MRI,
138 MachineRegisterInfo &MRI = MF.getRegInfo();
lib/Target/WebAssembly/WebAssemblyPrepareForLiveIntervals.cpp 65 static bool hasArgumentDef(unsigned Reg, const MachineRegisterInfo &MRI) {
80 MachineRegisterInfo &MRI = MF.getRegInfo();
lib/Target/WebAssembly/WebAssemblyRegColoring.cpp 65 static float computeWeight(const MachineRegisterInfo *MRI,
88 MachineRegisterInfo *MRI = &MF.getRegInfo();
lib/Target/WebAssembly/WebAssemblyRegNumbering.cpp 67 MachineRegisterInfo &MRI = MF.getRegInfo();
lib/Target/WebAssembly/WebAssemblyRegStackify.cpp 99 MachineRegisterInfo &MRI,
270 const MachineRegisterInfo &MRI,
287 static bool hasOneUse(unsigned Reg, MachineInstr *Def, MachineRegisterInfo &MRI,
317 AliasAnalysis &AA, const MachineRegisterInfo &MRI) {
402 const MachineRegisterInfo &MRI,
487 MachineRegisterInfo &MRI) {
599 MachineRegisterInfo &MRI, const WebAssemblyInstrInfo *TII) {
774 MachineRegisterInfo &MRI = MF.getRegInfo();
lib/Target/WebAssembly/WebAssemblyRegisterInfo.cpp 61 MachineRegisterInfo &MRI = MF.getRegInfo();
lib/Target/WebAssembly/WebAssemblyReplacePhysRegs.cpp 69 MachineRegisterInfo &MRI = MF.getRegInfo();
lib/Target/X86/X86AvoidStoreForwardingBlocks.cpp 86 MachineRegisterInfo *MRI;
lib/Target/X86/X86CallFrameOptimization.cpp 121 MachineRegisterInfo *MRI;
lib/Target/X86/X86CallLowering.cpp 56 MachineRegisterInfo &MRI,
99 OutgoingValueHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
197 MachineRegisterInfo &MRI = MF.getRegInfo();
230 IncomingValueHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
302 FormalArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
313 CallReturnHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
338 MachineRegisterInfo &MRI = MF.getRegInfo();
382 MachineRegisterInfo &MRI = MF.getRegInfo();
lib/Target/X86/X86CallLowering.h 46 const DataLayout &DL, MachineRegisterInfo &MRI,
lib/Target/X86/X86CmovConversion.cpp 114 MachineRegisterInfo *MRI;
lib/Target/X86/X86DomainReassignment.cpp 103 MachineRegisterInfo *MRI) const = 0;
107 MachineRegisterInfo *MRI) const = 0;
118 MachineRegisterInfo *MRI) const override {
124 MachineRegisterInfo *MRI) const override {
152 MachineRegisterInfo *MRI) const override {
164 MachineRegisterInfo *MRI) const override {
180 MachineRegisterInfo *MRI) const override {
200 MachineRegisterInfo *MRI) const override {
237 MachineRegisterInfo *MRI) const override {
268 MachineRegisterInfo *MRI) const override {
277 MachineRegisterInfo *MRI) const override {
352 LLVM_DUMP_METHOD void dump(const MachineRegisterInfo *MRI) const {
377 MachineRegisterInfo *MRI;
lib/Target/X86/X86FixupSetCC.cpp 57 MachineRegisterInfo *MRI;
lib/Target/X86/X86FlagsCopyLowering.cpp 90 MachineRegisterInfo *MRI;
lib/Target/X86/X86FloatingPoint.cpp 330 const MachineRegisterInfo &MRI = MF.getRegInfo();
lib/Target/X86/X86FrameLowering.cpp 585 MachineRegisterInfo &MRI = MF.getRegInfo();
2084 const MachineRegisterInfo &MRI = MF.getRegInfo();
2743 auto &MRI = MBB.getParent()->getRegInfo();
lib/Target/X86/X86ISelLowering.cpp 3529 MachineRegisterInfo &MRI = MF.getRegInfo();
4209 MachineFrameInfo &MFI, const MachineRegisterInfo *MRI,
4426 const MachineRegisterInfo *MRI = &MF.getRegInfo();
4471 const MachineRegisterInfo &MRI = MF.getRegInfo();
22231 MachineRegisterInfo &MRI = MF.getRegInfo();
29211 MachineRegisterInfo &MRI = MF->getRegInfo();
29294 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
30048 MachineRegisterInfo &MRI = MF->getRegInfo();
30427 MachineRegisterInfo &MRI = MF->getRegInfo();
30471 MachineRegisterInfo &MRI = MF->getRegInfo();
30630 MachineRegisterInfo &MRI = MF->getRegInfo();
30806 MachineRegisterInfo &MRI = MF->getRegInfo();
30889 MachineRegisterInfo *MRI = &MF->getRegInfo();
30938 MachineRegisterInfo *MRI = &MF->getRegInfo();
31376 MachineRegisterInfo &MRI = MF->getRegInfo();
46183 MachineRegisterInfo *MRI = &Entry->getParent()->getRegInfo();
lib/Target/X86/X86InstrInfo.cpp 466 static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) {
471 for (MachineRegisterInfo::def_instr_iterator I = MRI.def_instr_begin(BaseReg),
612 const MachineRegisterInfo &MRI = MF.getRegInfo();
632 const MachineRegisterInfo &MRI = MF.getRegInfo();
764 MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo();
2843 const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2870 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
3555 const MachineRegisterInfo *MRI) const {
3834 const MachineRegisterInfo *MRI,
4635 MachineRegisterInfo &MRI = MF.getRegInfo();
4816 MachineRegisterInfo &RegInfo = MF.getRegInfo();
6028 MachineRegisterInfo &RegInfo = MF->getRegInfo();
7226 const MachineRegisterInfo *MRI,
7763 MachineRegisterInfo &RegInfo = MF.getRegInfo();
7926 MachineRegisterInfo &RegInfo = MF->getRegInfo();
lib/Target/X86/X86InstrInfo.h 452 const MachineRegisterInfo *MRI,
481 const MachineRegisterInfo *MRI) const override;
491 const MachineRegisterInfo *MRI,
lib/Target/X86/X86InstructionSelector.cpp 75 bool selectLoadStoreOp(MachineInstr &I, MachineRegisterInfo &MRI,
77 bool selectFrameIndexOrGep(MachineInstr &I, MachineRegisterInfo &MRI,
79 bool selectGlobalValue(MachineInstr &I, MachineRegisterInfo &MRI,
81 bool selectConstant(MachineInstr &I, MachineRegisterInfo &MRI,
83 bool selectTruncOrPtrToInt(MachineInstr &I, MachineRegisterInfo &MRI,
85 bool selectZext(MachineInstr &I, MachineRegisterInfo &MRI,
87 bool selectAnyext(MachineInstr &I, MachineRegisterInfo &MRI,
89 bool selectCmp(MachineInstr &I, MachineRegisterInfo &MRI,
91 bool selectFCmp(MachineInstr &I, MachineRegisterInfo &MRI,
93 bool selectUadde(MachineInstr &I, MachineRegisterInfo &MRI,
95 bool selectCopy(MachineInstr &I, MachineRegisterInfo &MRI) const;
96 bool selectUnmergeValues(MachineInstr &I, MachineRegisterInfo &MRI,
98 bool selectMergeValues(MachineInstr &I, MachineRegisterInfo &MRI,
100 bool selectInsert(MachineInstr &I, MachineRegisterInfo &MRI,
102 bool selectExtract(MachineInstr &I, MachineRegisterInfo &MRI,
104 bool selectCondBranch(MachineInstr &I, MachineRegisterInfo &MRI,
106 bool selectTurnIntoCOPY(MachineInstr &I, MachineRegisterInfo &MRI,
111 bool materializeFP(MachineInstr &I, MachineRegisterInfo &MRI,
113 bool selectImplicitDefOrPHI(MachineInstr &I, MachineRegisterInfo &MRI) const;
114 bool selectDivRem(MachineInstr &I, MachineRegisterInfo &MRI,
116 bool selectIntrinsicWSideEffects(MachineInstr &I, MachineRegisterInfo &MRI,
121 MachineRegisterInfo &MRI, MachineFunction &MF) const;
124 MachineRegisterInfo &MRI, MachineFunction &MF) const;
128 MachineRegisterInfo &MRI) const;
197 MachineRegisterInfo &MRI) const {
231 MachineRegisterInfo &MRI) const {
313 MachineRegisterInfo &MRI = MF.getRegInfo();
473 const MachineRegisterInfo &MRI,
499 MachineRegisterInfo &MRI,
559 MachineRegisterInfo &MRI,
587 MachineRegisterInfo &MRI,
633 MachineRegisterInfo &MRI,
690 MachineInstr &I, MachineRegisterInfo &MRI, const unsigned DstReg,
705 MachineRegisterInfo &MRI,
771 MachineRegisterInfo &MRI,
882 MachineRegisterInfo &MRI,
937 MachineRegisterInfo &MRI,
988 MachineRegisterInfo &MRI,
1079 MachineRegisterInfo &MRI,
1138 MachineRegisterInfo &MRI,
1196 MachineRegisterInfo &MRI,
1234 MachineRegisterInfo &MRI,
1271 MachineRegisterInfo &MRI,
1329 MachineInstr &I, MachineRegisterInfo &MRI, MachineFunction &MF) {
1354 MachineInstr &I, MachineRegisterInfo &MRI, MachineFunction &MF) {
1403 MachineRegisterInfo &MRI,
1424 MachineRegisterInfo &MRI,
1490 MachineInstr &I, MachineRegisterInfo &MRI) const {
1517 MachineRegisterInfo &MRI,
1718 MachineInstr &I, MachineRegisterInfo &MRI, MachineFunction &MF) const {
lib/Target/X86/X86LegalizerInfo.cpp 89 MachineRegisterInfo &MRI,
lib/Target/X86/X86LegalizerInfo.h 35 bool legalizeIntrinsic(MachineInstr &MI, MachineRegisterInfo &MRI,
lib/Target/X86/X86OptimizeLEAs.cpp 297 MachineRegisterInfo *MRI;
lib/Target/X86/X86RegisterBankInfo.cpp 111 const MachineInstr &MI, const MachineRegisterInfo &MRI, const bool isFP,
147 const MachineRegisterInfo &MRI = MF.getRegInfo();
163 const MachineRegisterInfo &MRI = MF.getRegInfo();
282 const MachineRegisterInfo &MRI = MF.getRegInfo();
lib/Target/X86/X86RegisterBankInfo.h 54 const MachineRegisterInfo &MRI, const bool isFP,
lib/Target/X86/X86RegisterInfo.cpp 653 const MachineRegisterInfo *MRI = &MF.getRegInfo();
lib/Target/X86/X86SpeculativeLoadHardening.cpp 162 MachineRegisterInfo *MRI;
lib/Target/X86/X86VZeroUpper.cpp 133 static bool checkFnHasLiveInYmmOrZmm(MachineRegisterInfo &MRI) {
285 MachineRegisterInfo &MRI = MF.getRegInfo();
lib/Target/X86/X86WinAllocaExpander.cpp 57 MachineRegisterInfo *MRI;
79 static int64_t getWinAllocaAmount(MachineInstr *MI, MachineRegisterInfo *MRI) {
lib/Target/XCore/XCoreFrameLowering.cpp 541 const MachineRegisterInfo &MRI = MF.getRegInfo();
lib/Target/XCore/XCoreISelLowering.cpp 1265 MachineRegisterInfo &RegInfo = MF.getRegInfo();
unittests/CodeGen/GlobalISel/GISelMITest.h 159 MachineRegisterInfo *MRI;
usr/include/c++/7.4.0/type_traits 1554 { typedef _Tp type; };
1563 { typedef _Tp type; };
1574 remove_const<typename remove_volatile<_Tp>::type>::type type;