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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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Declarations
include/llvm/CodeGen/FastISel.h 49 class MachineOperand;
include/llvm/CodeGen/GlobalISel/CallLowering.h 34 class MachineOperand;
include/llvm/CodeGen/GlobalISel/CombinerHelper.h 29 class MachineOperand;
include/llvm/CodeGen/GlobalISel/InstructionSelector.h 38 class MachineOperand;
include/llvm/CodeGen/GlobalISel/RegBankSelect.h 81 class MachineOperand;
include/llvm/CodeGen/GlobalISel/Utils.h 27 class MachineOperand;
include/llvm/CodeGen/LivePhysRegs.h 42 class MachineOperand;
include/llvm/CodeGen/LiveRangeEdit.h 40 class MachineOperand;
include/llvm/CodeGen/MachineSSAUpdater.h 21 class MachineOperand;
include/llvm/CodeGen/ScheduleDAGInstrs.h 43 class MachineOperand;
lib/CodeGen/AggressiveAntiDepBreaker.h 32 class MachineOperand;
lib/CodeGen/AsmPrinter/DwarfUnit.h 31 class MachineOperand;
lib/CodeGen/CriticalAntiDepBreaker.h 29 class MachineOperand;
lib/Target/AArch64/AArch64MCInstLower.h 24 class MachineOperand;
lib/Target/AMDGPU/AMDGPUInstructionSelector.h 39 class MachineOperand;
lib/Target/AMDGPU/GCNHazardRecognizer.h 26 class MachineOperand;
lib/Target/ARM/ARMAsmPrinter.h 21 class MachineOperand;
lib/Target/AVR/AVRMCInstLower.h 18 class MachineOperand;
lib/Target/BPF/BPFMCInstLower.h 22 class MachineOperand;
lib/Target/Hexagon/HexagonInstrInfo.h 35 class MachineOperand;
lib/Target/Hexagon/RDFGraph.h 253 class MachineOperand;
lib/Target/Lanai/LanaiMCInstLower.h 22 class MachineOperand;
lib/Target/MSP430/MSP430MCInstLower.h 22 class MachineOperand;
lib/Target/Mips/MipsAsmPrinter.h 35 class MachineOperand;
lib/Target/Mips/MipsInstrInfo.h 36 class MachineOperand;
lib/Target/PowerPC/PPC.h 27 class MachineOperand;
lib/Target/RISCV/RISCV.h 30 class MachineOperand;
lib/Target/SystemZ/SystemZMCInstLower.h 20 class MachineOperand;
lib/Target/WebAssembly/WebAssemblyMCInstLower.h 27 class MachineOperand;
References
gen/lib/Target/ARM/ARMGenGlobalISel.inc 756 const auto &MO = MI.getOperand(1);
766 const auto &MO = MI.getOperand(1);
776 const auto &MO = MI.getOperand(1);
include/llvm/ADT/ArrayRef.h 43 using iterator = const T *;
44 using const_iterator = const T *;
50 const T *Data = nullptr;
66 /*implicit*/ ArrayRef(const T &OneElt)
70 /*implicit*/ ArrayRef(const T *data, size_t length)
74 ArrayRef(const T *begin, const T *end)
74 ArrayRef(const T *begin, const T *end)
81 /*implicit*/ ArrayRef(const SmallVectorTemplateCommon<T, U> &Vec)
87 /*implicit*/ ArrayRef(const std::vector<T, A> &Vec)
92 /*implicit*/ constexpr ArrayRef(const std::array<T, N> &Arr)
97 /*implicit*/ constexpr ArrayRef(const T (&Arr)[N]) : Data(Arr), Length(N) {}
100 /*implicit*/ ArrayRef(const std::initializer_list<T> &Vec)
145 const T *data() const { return Data; }
151 const T &front() const {
157 const T &back() const {
163 template <typename Allocator> ArrayRef<T> copy(Allocator &A) {
178 ArrayRef<T> slice(size_t N, size_t M) const {
184 ArrayRef<T> slice(size_t N) const { return slice(N, size() - N); }
187 ArrayRef<T> drop_front(size_t N = 1) const {
193 ArrayRef<T> drop_back(size_t N = 1) const {
200 template <class PredicateT> ArrayRef<T> drop_while(PredicateT Pred) const {
206 template <class PredicateT> ArrayRef<T> drop_until(PredicateT Pred) const {
211 ArrayRef<T> take_front(size_t N = 1) const {
218 ArrayRef<T> take_back(size_t N = 1) const {
226 template <class PredicateT> ArrayRef<T> take_while(PredicateT Pred) const {
232 template <class PredicateT> ArrayRef<T> take_until(PredicateT Pred) const {
239 const T &operator[](size_t Index) const {
249 typename std::enable_if<std::is_same<U, T>::value, ArrayRef<T>>::type &
257 typename std::enable_if<std::is_same<U, T>::value, ArrayRef<T>>::type &
263 std::vector<T> vec() const {
270 operator std::vector<T>() const {
include/llvm/ADT/DenseMap.h 40 struct DenseMapPair : public std::pair<KeyT, ValueT> {
43 KeyT &getFirst() { return std::pair<KeyT, ValueT>::first; }
44 const KeyT &getFirst() const { return std::pair<KeyT, ValueT>::first; }
65 using key_type = KeyT;
69 using iterator = DenseMapIterator<KeyT, ValueT, KeyInfoT, BucketT>;
71 DenseMapIterator<KeyT, ValueT, KeyInfoT, BucketT, true>;
145 size_type count(const_arg_type_t<KeyT> Val) const {
156 const_iterator find(const_arg_type_t<KeyT> Val) const {
185 ValueT lookup(const_arg_type_t<KeyT> Val) const {
272 bool erase(const KeyT &Val) {
291 value_type& FindAndConstruct(const KeyT &Key) {
299 ValueT &operator[](const KeyT &Key) {
303 value_type& FindAndConstruct(KeyT &&Key) {
311 ValueT &operator[](KeyT &&Key) {
334 const KeyT EmptyKey = getEmptyKey(), TombstoneKey = getTombstoneKey();
349 const KeyT EmptyKey = getEmptyKey();
351 ::new (&B->getFirst()) KeyT(EmptyKey);
369 const KeyT EmptyKey = getEmptyKey();
370 const KeyT TombstoneKey = getTombstoneKey();
392 const DenseMapBase<OtherBaseT, KeyT, ValueT, KeyInfoT, BucketT> &other) {
414 static unsigned getHashValue(const KeyT &Val) {
419 static unsigned getHashValue(const LookupKeyT &Val) {
423 static const KeyT getEmptyKey() {
429 static const KeyT getTombstoneKey() {
437 if (shouldReverseIterate<KeyT>()) {
515 BucketT *InsertIntoBucket(BucketT *TheBucket, KeyArg &&Key,
525 BucketT *InsertIntoBucketWithLookup(BucketT *TheBucket, KeyT &&Key,
535 BucketT *InsertIntoBucketImpl(const KeyT &Key, const LookupKeyT &Lookup,
535 BucketT *InsertIntoBucketImpl(const KeyT &Key, const LookupKeyT &Lookup,
566 const KeyT EmptyKey = getEmptyKey();
578 bool LookupBucketFor(const LookupKeyT &Val,
590 const KeyT EmptyKey = getEmptyKey();
591 const KeyT TombstoneKey = getTombstoneKey();
629 bool LookupBucketFor(const LookupKeyT &Val, BucketT *&FoundBucket) {
684 class DenseMap : public DenseMapBase<DenseMap<KeyT, ValueT, KeyInfoT, BucketT>,
685 KeyT, ValueT, KeyInfoT, BucketT> {
690 using BaseT = DenseMapBase<DenseMap, KeyT, ValueT, KeyInfoT, BucketT>;
1163 using ConstIterator = DenseMapIterator<KeyT, ValueT, KeyInfoT, Bucket, true>;
1186 if (shouldReverseIterate<KeyT>()) {
1199 const DenseMapIterator<KeyT, ValueT, KeyInfoT, Bucket, IsConstSrc> &I)
1210 if (shouldReverseIterate<KeyT>())
1249 const KeyT Empty = KeyInfoT::getEmptyKey();
1250 const KeyT Tombstone = KeyInfoT::getTombstoneKey();
1259 const KeyT Empty = KeyInfoT::getEmptyKey();
1260 const KeyT Tombstone = KeyInfoT::getTombstoneKey();
include/llvm/ADT/DenseMapInfo.h 39 static inline T* getEmptyKey() {
41 Val <<= PointerLikeTypeTraits<T*>::NumLowBitsAvailable;
45 static inline T* getTombstoneKey() {
47 Val <<= PointerLikeTypeTraits<T*>::NumLowBitsAvailable;
51 static unsigned getHashValue(const T *PtrVal) {
56 static bool isEqual(const T *LHS, const T *RHS) { return LHS == RHS; }
56 static bool isEqual(const T *LHS, const T *RHS) { return LHS == RHS; }
include/llvm/ADT/Hashing.h 371 typename std::enable_if<!is_hashable_data<T>::value, size_t>::type
372 get_hashable_data(const T &value) {
554 const T &arg, const Ts &...args) {
554 const T &arg, const Ts &...args) {
600 template <typename ...Ts> hash_code hash_combine(const Ts &...args) {
include/llvm/ADT/MapVector.h 83 std::pair<KeyT, ValueT> &front() { return Vector.front(); }
84 const std::pair<KeyT, ValueT> &front() const { return Vector.front(); }
85 std::pair<KeyT, ValueT> &back() { return Vector.back(); }
86 const std::pair<KeyT, ValueT> &back() const { return Vector.back(); }
98 ValueT &operator[](const KeyT &Key) {
110 ValueT lookup(const KeyT &Key) const {
117 std::pair<iterator, bool> insert(const std::pair<KeyT, ValueT> &KV) {
129 std::pair<iterator, bool> insert(std::pair<KeyT, ValueT> &&KV) {
131 std::pair<KeyT, typename MapType::mapped_type> Pair = std::make_pair(KV.first, 0);
142 size_type count(const KeyT &Key) const {
147 iterator find(const KeyT &Key) {
153 const_iterator find(const KeyT &Key) const {
192 size_type erase(const KeyT &Key) {
include/llvm/ADT/Optional.h 144 T value;
172 T &getValue() LLVM_LVALUE_FUNCTION noexcept {
176 T const &getValue() const LLVM_LVALUE_FUNCTION noexcept {
181 T &&getValue() && noexcept {
206 ::new ((void *)std::addressof(value)) T(std::move(y));
216 optional_detail::OptionalStorage<T> Storage;
219 using value_type = T;
224 Optional(const T &y) : Storage(optional_detail::in_place_t{}, y) {}
227 Optional(T &&y) : Storage(optional_detail::in_place_t{}, std::move(y)) {}
230 Optional &operator=(T &&y) {
241 static inline Optional create(const T *y) {
245 Optional &operator=(const T &y) {
253 const T *getPointer() const { return &Storage.getValue(); }
254 T *getPointer() { return &Storage.getValue(); }
255 const T &getValue() const LLVM_LVALUE_FUNCTION { return Storage.getValue(); }
256 T &getValue() LLVM_LVALUE_FUNCTION { return Storage.getValue(); }
260 const T *operator->() const { return getPointer(); }
261 T *operator->() { return getPointer(); }
262 const T &operator*() const LLVM_LVALUE_FUNCTION { return getValue(); }
263 T &operator*() LLVM_LVALUE_FUNCTION { return getValue(); }
266 constexpr T getValueOr(U &&value) const LLVM_LVALUE_FUNCTION {
271 T &&getValue() && { return std::move(Storage.getValue()); }
272 T &&operator*() && { return std::move(Storage.getValue()); }
275 T getValueOr(U &&value) && {
include/llvm/ADT/SmallVector.h 75 AlignedCharArrayUnion<T> FirstEl;
114 using value_type = T;
115 using iterator = T *;
116 using const_iterator = const T *;
121 using reference = T &;
122 using const_reference = const T &;
123 using pointer = T *;
124 using const_pointer = const T *;
259 class SmallVectorTemplateBase<T, true> : public SmallVectorTemplateCommon<T> {
264 static void destroy_range(T *, T *) {}
264 static void destroy_range(T *, T *) {}
286 T1 *I, T1 *E, T2 *Dest,
286 T1 *I, T1 *E, T2 *Dest,
286 T1 *I, T1 *E, T2 *Dest,
287 typename std::enable_if<std::is_same<typename std::remove_const<T1>::type,
288 T2>::value>::type * = nullptr) {
294 memcpy(reinterpret_cast<void *>(Dest), I, (E - I) * sizeof(T));
299 void grow(size_t MinSize = 0) { this->grow_pod(MinSize, sizeof(T)); }
302 void push_back(const T &Elt) {
305 memcpy(reinterpret_cast<void *>(this->end()), &Elt, sizeof(T));
315 class SmallVectorImpl : public SmallVectorTemplateBase<T> {
316 using SuperClass = SmallVectorTemplateBase<T>;
357 void resize(size_type N, const T &NV) {
374 LLVM_NODISCARD T pop_back_val() {
397 void append(size_type NumInputs, const T &Elt) {
405 void append(std::initializer_list<T> IL) {
412 void assign(size_type NumElts, const T &Elt) {
429 void assign(std::initializer_list<T> IL) {
467 iterator insert(iterator I, T &&Elt) {
497 iterator insert(iterator I, const T &Elt) {
526 iterator insert(iterator I, size_type NumToInsert, const T &Elt) {
637 void insert(iterator I, std::initializer_list<T> IL) {
820 AlignedCharArrayUnion<T> InlineElts[N];
837 class SmallVector : public SmallVectorImpl<T>, SmallVectorStorage<T, N> {
837 class SmallVector : public SmallVectorImpl<T>, SmallVectorStorage<T, N> {
846 explicit SmallVector(size_t Size, const T &Value = T())
865 SmallVector(std::initializer_list<T> IL) : SmallVectorImpl<T>(N) {
884 SmallVector(SmallVectorImpl<T> &&RHS) : SmallVectorImpl<T>(N) {
include/llvm/CodeGen/AsmPrinter.h 609 virtual void PrintSymbolOperand(const MachineOperand &MO, raw_ostream &OS);
include/llvm/CodeGen/FastISel.h 589 bool addStackMapLiveVars(SmallVectorImpl<MachineOperand> &Ops,
include/llvm/CodeGen/GlobalISel/CSEInfo.h 190 addNodeIDMachineOperand(const MachineOperand &MO) const;
include/llvm/CodeGen/GlobalISel/CallLowering.h 77 MachineOperand Callee = MachineOperand::CreateImm(0);
77 MachineOperand Callee = MachineOperand::CreateImm(0);
include/llvm/CodeGen/GlobalISel/CombinerHelper.h 57 void replaceRegOpWith(MachineRegisterInfo &MRI, MachineOperand &FromRegOp,
include/llvm/CodeGen/GlobalISel/InstructionSelector.h 487 bool isOperandImmEqual(const MachineOperand &MO, int64_t Value,
493 bool isBaseWithConstantOffset(const MachineOperand &Root,
include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h 93 MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx);
191 MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx);
484 MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx);
526 MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx);
544 MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx);
574 MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx);
617 MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx);
642 MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx);
659 MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx);
674 MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx);
793 MachineOperand &MO = State.MIs[OldInsnID]->getOperand(OpIdx);
include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h 83 auto &CstVal = SrcMI->getOperand(1);
124 auto &CstVal = SrcMI->getOperand(1);
174 auto &CstVal = SrcMI->getOperand(1);
include/llvm/CodeGen/GlobalISel/Localizer.h 58 static bool isLocalUse(MachineOperand &MOUse, const MachineInstr &Def,
include/llvm/CodeGen/GlobalISel/MIPatternMatch.h 64 bool match(const MachineRegisterInfo &MRI, MachineOperand *MO) {
include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h 70 DstOp(const MachineOperand &Op) : Reg(Op.getReg()), Ty(DstType::Ty_Reg) {}
131 SrcOp(const MachineOperand &Op) : Reg(Op.getReg()), Ty(SrcType::Ty_Reg) {}
include/llvm/CodeGen/GlobalISel/RegBankSelect.h 562 bool repairReg(MachineOperand &MO,
574 getRepairCost(const MachineOperand &MO,
606 const MachineOperand &MO,
include/llvm/CodeGen/GlobalISel/Utils.h 64 const MachineOperand &RegMO, unsigned OpIdx);
81 const MachineOperand &RegMO, unsigned OpIdx);
include/llvm/CodeGen/LivePhysRegs.h 97 void removeRegsInMask(const MachineOperand &MO,
98 SmallVectorImpl<std::pair<MCPhysReg, const MachineOperand*>> *Clobbers =
129 SmallVectorImpl<std::pair<MCPhysReg, const MachineOperand*>> &Clobbers);
include/llvm/CodeGen/LiveRangeEdit.h 121 bool useIsKill(const LiveInterval &LI, const MachineOperand &MO) const;
include/llvm/CodeGen/LiveVariables.h 154 void HandleRegMask(const MachineOperand&);
216 MachineOperand &MO = MI.getOperand(i);
252 MachineOperand &MO = MI.getOperand(i);
include/llvm/CodeGen/MachineFunction.h 266 ArrayRecycler<MachineOperand> OperandRecycler;
781 using OperandCapacity = ArrayRecycler<MachineOperand>::Capacity;
785 MachineOperand *allocateOperandArray(OperandCapacity Cap) {
792 void deallocateOperandArray(OperandCapacity Cap, MachineOperand *Array) {
include/llvm/CodeGen/MachineInstr.h 116 MachineOperand *Operands = nullptr; // Pointer to the first operand.
118 using OperandCapacity = ArrayRecycler<MachineOperand>::Capacity;
431 const MachineOperand& getOperand(unsigned i) const {
435 MachineOperand& getOperand(unsigned i) {
449 const MachineOperand &MO = getOperand(I);
483 using mop_iterator = MachineOperand *;
484 using const_mop_iterator = const MachineOperand *;
1250 MachineOperand *findRegisterUseOperand(Register Reg, bool isKill = false,
1256 const MachineOperand *findRegisterUseOperand(
1275 MachineOperand *
1283 const MachineOperand *
1368 const MachineOperand &MO = getOperand(DefOpIdx);
1381 const MachineOperand &MO = getOperand(UseOpIdx);
1548 void addOperand(MachineFunction &MF, const MachineOperand &Op);
1555 void addOperand(const MachineOperand &Op);
1644 MachineOperand &MO = getOperand(OpIdx);
include/llvm/CodeGen/MachineInstrBuilder.h 92 MI->addOperand(*MF, MachineOperand::CreateReg(RegNo,
123 MI->addOperand(*MF, MachineOperand::CreateImm(Val));
128 MI->addOperand(*MF, MachineOperand::CreateCImm(Val));
133 MI->addOperand(*MF, MachineOperand::CreateFPImm(Val));
139 MI->addOperand(*MF, MachineOperand::CreateMBB(MBB, TargetFlags));
144 MI->addOperand(*MF, MachineOperand::CreateFI(Idx));
151 MI->addOperand(*MF, MachineOperand::CreateCPI(Idx, Offset, TargetFlags));
157 MI->addOperand(*MF, MachineOperand::CreateTargetIndex(Idx, Offset,
164 MI->addOperand(*MF, MachineOperand::CreateJTI(Idx, TargetFlags));
171 MI->addOperand(*MF, MachineOperand::CreateGA(GV, Offset, TargetFlags));
177 MI->addOperand(*MF, MachineOperand::CreateES(FnName, TargetFlags));
184 MI->addOperand(*MF, MachineOperand::CreateBA(BA, Offset, TargetFlags));
189 MI->addOperand(*MF, MachineOperand::CreateRegMask(Mask));
215 const MachineInstrBuilder &add(const MachineOperand &MO) const {
220 const MachineInstrBuilder &add(ArrayRef<MachineOperand> MOs) const {
221 for (const MachineOperand &MO : MOs) {
228 MI->addOperand(*MF, MachineOperand::CreateMetadata(MD));
239 MI->addOperand(*MF, MachineOperand::CreateCFIIndex(CFIIndex));
244 MI->addOperand(*MF, MachineOperand::CreateIntrinsicID(ID));
249 MI->addOperand(*MF, MachineOperand::CreatePredicate(Pred));
254 MI->addOperand(*MF, MachineOperand::CreateShuffleMask(Val));
260 MI->addOperand(*MF, MachineOperand::CreateMCSymbol(Sym, TargetFlags));
275 const MachineInstrBuilder &addDisp(const MachineOperand &Disp, int64_t off,
287 case MachineOperand::MO_Immediate:
289 case MachineOperand::MO_ConstantPoolIndex:
292 case MachineOperand::MO_GlobalAddress:
295 case MachineOperand::MO_BlockAddress:
441 MachineOperand &MO, const MDNode *Variable,
458 MachineOperand &MO, const MDNode *Variable,
496 inline unsigned getRegState(const MachineOperand &RegOp) {
include/llvm/CodeGen/MachineInstrBundle.h 130 MachineOperand &deref() const { return *OpI; }
225 MachineOperand &operator* () const { return deref(); }
226 MachineOperand *operator->() const { return &deref(); }
235 const MachineOperand &operator* () const { return deref(); }
236 const MachineOperand *operator->() const { return &deref(); }
245 MachineOperand &operator* () const { return deref(); }
246 MachineOperand *operator->() const { return &deref(); }
256 const MachineOperand &operator* () const { return deref(); }
257 const MachineOperand *operator->() const { return &deref(); }
include/llvm/CodeGen/MachineOperand.h 181 MachineOperand *Prev; // Access list for register. See MRI.
182 MachineOperand *Next;
202 static_assert(alignof(MachineOperand) <= alignof(int64_t),
206 static_assert(sizeof(MachineOperand) <=
256 static void printTargetFlags(raw_ostream& OS, const MachineOperand &Op);
708 bool isIdenticalTo(const MachineOperand &Other) const;
716 friend hash_code hash_value(const MachineOperand &MO);
756 static MachineOperand CreateImm(int64_t Val) {
757 MachineOperand Op(MachineOperand::MO_Immediate);
757 MachineOperand Op(MachineOperand::MO_Immediate);
762 static MachineOperand CreateCImm(const ConstantInt *CI) {
763 MachineOperand Op(MachineOperand::MO_CImmediate);
763 MachineOperand Op(MachineOperand::MO_CImmediate);
768 static MachineOperand CreateFPImm(const ConstantFP *CFP) {
769 MachineOperand Op(MachineOperand::MO_FPImmediate);
769 MachineOperand Op(MachineOperand::MO_FPImmediate);
774 static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp = false,
783 MachineOperand Op(MachineOperand::MO_Register);
783 MachineOperand Op(MachineOperand::MO_Register);
799 static MachineOperand CreateMBB(MachineBasicBlock *MBB,
801 MachineOperand Op(MachineOperand::MO_MachineBasicBlock);
801 MachineOperand Op(MachineOperand::MO_MachineBasicBlock);
806 static MachineOperand CreateFI(int Idx) {
807 MachineOperand Op(MachineOperand::MO_FrameIndex);
807 MachineOperand Op(MachineOperand::MO_FrameIndex);
811 static MachineOperand CreateCPI(unsigned Idx, int Offset,
813 MachineOperand Op(MachineOperand::MO_ConstantPoolIndex);
813 MachineOperand Op(MachineOperand::MO_ConstantPoolIndex);
819 static MachineOperand CreateTargetIndex(unsigned Idx, int64_t Offset,
821 MachineOperand Op(MachineOperand::MO_TargetIndex);
821 MachineOperand Op(MachineOperand::MO_TargetIndex);
827 static MachineOperand CreateJTI(unsigned Idx, unsigned TargetFlags = 0) {
828 MachineOperand Op(MachineOperand::MO_JumpTableIndex);
828 MachineOperand Op(MachineOperand::MO_JumpTableIndex);
833 static MachineOperand CreateGA(const GlobalValue *GV, int64_t Offset,
835 MachineOperand Op(MachineOperand::MO_GlobalAddress);
835 MachineOperand Op(MachineOperand::MO_GlobalAddress);
841 static MachineOperand CreateES(const char *SymName,
843 MachineOperand Op(MachineOperand::MO_ExternalSymbol);
843 MachineOperand Op(MachineOperand::MO_ExternalSymbol);
849 static MachineOperand CreateBA(const BlockAddress *BA, int64_t Offset,
851 MachineOperand Op(MachineOperand::MO_BlockAddress);
851 MachineOperand Op(MachineOperand::MO_BlockAddress);
869 static MachineOperand CreateRegMask(const uint32_t *Mask) {
871 MachineOperand Op(MachineOperand::MO_RegisterMask);
871 MachineOperand Op(MachineOperand::MO_RegisterMask);
875 static MachineOperand CreateRegLiveOut(const uint32_t *Mask) {
877 MachineOperand Op(MachineOperand::MO_RegisterLiveOut);
877 MachineOperand Op(MachineOperand::MO_RegisterLiveOut);
881 static MachineOperand CreateMetadata(const MDNode *Meta) {
882 MachineOperand Op(MachineOperand::MO_Metadata);
882 MachineOperand Op(MachineOperand::MO_Metadata);
887 static MachineOperand CreateMCSymbol(MCSymbol *Sym,
889 MachineOperand Op(MachineOperand::MO_MCSymbol);
889 MachineOperand Op(MachineOperand::MO_MCSymbol);
896 static MachineOperand CreateCFIIndex(unsigned CFIIndex) {
897 MachineOperand Op(MachineOperand::MO_CFIIndex);
897 MachineOperand Op(MachineOperand::MO_CFIIndex);
902 static MachineOperand CreateIntrinsicID(Intrinsic::ID ID) {
903 MachineOperand Op(MachineOperand::MO_IntrinsicID);
903 MachineOperand Op(MachineOperand::MO_IntrinsicID);
908 static MachineOperand CreatePredicate(unsigned Pred) {
909 MachineOperand Op(MachineOperand::MO_Predicate);
909 MachineOperand Op(MachineOperand::MO_Predicate);
914 static MachineOperand CreateShuffleMask(const Constant *C) {
915 MachineOperand Op(MachineOperand::MO_ShuffleMask);
915 MachineOperand Op(MachineOperand::MO_ShuffleMask);
950 static MachineOperand getEmptyKey() {
952 MachineOperand::MO_Empty));
954 static MachineOperand getTombstoneKey() {
956 MachineOperand::MO_Tombstone));
958 static unsigned getHashValue(const MachineOperand &MO) {
961 static bool isEqual(const MachineOperand &LHS, const MachineOperand &RHS) {
961 static bool isEqual(const MachineOperand &LHS, const MachineOperand &RHS) {
963 MachineOperand::MO_Empty) ||
965 MachineOperand::MO_Tombstone))
971 inline raw_ostream &operator<<(raw_ostream &OS, const MachineOperand &MO) {
978 hash_code hash_value(const MachineOperand &MO);
include/llvm/CodeGen/MachinePipeliner.h 78 SmallVector<MachineOperand, 4> BrCond;
584 MachineOperand &MO);
include/llvm/CodeGen/MachineRegisterInfo.h 74 IndexedMap<std::pair<RegClassOrRegBank, MachineOperand *>,
106 std::unique_ptr<MachineOperand *[]> PhysRegUseDefLists;
110 MachineOperand *&getRegUseDefListHead(Register RegNo) {
116 MachineOperand *getRegUseDefListHead(Register RegNo) const {
123 static MachineOperand *getNextOperandForReg(const MachineOperand *MO) {
123 static MachineOperand *getNextOperandForReg(const MachineOperand *MO) {
247 void addRegOperandToUseList(MachineOperand *MO);
250 void removeRegOperandFromUseList(MachineOperand *MO);
253 void moveOperands(MachineOperand *Dst, MachineOperand *Src, unsigned NumOps);
253 void moveOperands(MachineOperand *Dst, MachineOperand *Src, unsigned NumOps);
974 MachineOperand *Op = nullptr;
976 explicit defusechain_iterator(MachineOperand *op) : Op(op) {
1057 MachineOperand &operator*() const {
1062 MachineOperand *operator->() const {
1080 MachineOperand *Op = nullptr;
1082 explicit defusechain_instr_iterator(MachineOperand *op) : Op(op) {
include/llvm/CodeGen/MachineSSAUpdater.h 104 void RewriteUse(MachineOperand &U);
include/llvm/CodeGen/ScheduleDAGInstrs.h 373 void toggleKillFlag(MachineInstr &MI, MachineOperand &MO);
377 LaneBitmask getLaneMaskForMO(const MachineOperand &MO) const;
380 bool deadDefHasNoUse(const MachineOperand &MO);
include/llvm/CodeGen/StackMaps.h 90 const MachineOperand &getMetaOper(unsigned Pos) const {
109 const MachineOperand &getCallTarget() const {
185 const MachineOperand &getCallTarget() const {
include/llvm/CodeGen/TargetInstrInfo.h 65 using ParamLoadedValue = std::pair<MachineOperand, DIExpression*>;
582 SmallVectorImpl<MachineOperand> &Cond,
601 MachineOperand LHS = MachineOperand::CreateImm(0);
601 MachineOperand LHS = MachineOperand::CreateImm(0);
602 MachineOperand RHS = MachineOperand::CreateImm(0);
602 MachineOperand RHS = MachineOperand::CreateImm(0);
653 ArrayRef<MachineOperand> Cond,
687 SmallVectorImpl<MachineOperand> &Cond) = 0;
726 SmallVectorImpl<MachineOperand> &Cond,
829 ArrayRef<MachineOperand> Cond, unsigned TrueReg,
876 SmallVectorImpl<MachineOperand> &Cond,
926 const MachineOperand *&Source,
927 const MachineOperand *&Destination) const {
937 bool isCopyInstr(const MachineInstr &MI, const MachineOperand *&Source,
938 const MachineOperand *&Destination) const {
1217 const MachineOperand *&BaseOp,
1243 virtual bool shouldClusterMemOps(const MachineOperand &BaseOp1,
1244 const MachineOperand &BaseOp2,
1252 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
1279 virtual bool canMakeTailCallConditional(SmallVectorImpl<MachineOperand> &Cond,
1286 SmallVectorImpl<MachineOperand> &Cond,
1294 ArrayRef<MachineOperand> Pred) const;
1298 virtual bool SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
1299 ArrayRef<MachineOperand> Pred2) const {
1307 std::vector<MachineOperand> &Pred) const {
include/llvm/CodeGen/TargetRegisterInfo.h 971 getConstrainedRegClassForOperand(const MachineOperand &MO,
include/llvm/Support/AlignOf.h 30 T t;
39 template <typename T> union SizerImpl<T> { char arr[sizeof(T)]; };
50 llvm::detail::SizerImpl<T, Ts...>)];
include/llvm/Support/ArrayRecycler.h 36 static_assert(sizeof(T) >= sizeof(FreeList), "Objects are too small");
43 T *pop(unsigned Idx) {
56 void push(unsigned Idx, T *Ptr) {
125 T *allocate(Capacity Cap, AllocatorType &Allocator) {
127 if (T *Ptr = pop(Cap.getBucket()))
130 return static_cast<T*>(Allocator.Allocate(sizeof(T)*Cap.getSize(), Align));
137 void deallocate(Capacity Cap, T *Ptr) {
include/llvm/Support/PointerLikeTypeTraits.h 56 static inline void *getAsVoidPointer(T *P) { return P; }
57 static inline T *getFromVoidPointer(void *P) { return static_cast<T *>(P); }
59 enum { NumLowBitsAvailable = detail::ConstantLog2<alignof(T)>::value };
91 typedef PointerLikeTypeTraits<T *> NonConst;
93 static inline const void *getAsVoidPointer(const T *P) {
96 static inline const T *getFromVoidPointer(const void *P) {
include/llvm/Support/type_traits.h 31 using UnderlyingT = typename std::remove_reference<T>::type;
65 using type = const T &;
91 T t;
122 static auto get(F*) -> decltype(std::declval<F &>() = std::declval<const F &>(), std::true_type{});
122 static auto get(F*) -> decltype(std::declval<F &>() = std::declval<const F &>(), std::true_type{});
122 static auto get(F*) -> decltype(std::declval<F &>() = std::declval<const F &>(), std::true_type{});
130 static auto get(F*) -> decltype(std::declval<F &>() = std::declval<F &&>(), std::true_type{});
130 static auto get(F*) -> decltype(std::declval<F &>() = std::declval<F &&>(), std::true_type{});
130 static auto get(F*) -> decltype(std::declval<F &>() = std::declval<F &&>(), std::true_type{});
145 std::is_copy_constructible<detail::trivial_helper<T>>::value;
147 !std::is_copy_constructible<T>::value;
151 std::is_move_constructible<detail::trivial_helper<T>>::value;
153 !std::is_move_constructible<T>::value;
157 is_copy_assignable<detail::trivial_helper<T>>::value;
159 !is_copy_assignable<T>::value;
163 is_move_assignable<detail::trivial_helper<T>>::value;
165 !is_move_assignable<T>::value;
169 std::is_destructible<detail::trivial_helper<T>>::value;
lib/CodeGen/AggressiveAntiDepBreaker.cpp 231 MachineOperand &MO) {
239 MachineOperand *Op = nullptr;
251 MachineOperand &MO = MI.getOperand(i);
366 MachineOperand &MO = MI.getOperand(i);
376 MachineOperand &MO = MI.getOperand(i);
419 MachineOperand &MO = MI.getOperand(i);
472 MachineOperand &MO = MI.getOperand(i);
507 MachineOperand &MO = MI.getOperand(i);
878 MachineOperand *AntiDepOp = MI.findRegisterDefOperand(AntiDepReg);
lib/CodeGen/AggressiveAntiDepBreaker.h 45 MachineOperand *Operand;
162 bool IsImplicitDefUse(MachineInstr &MI, MachineOperand &MO);
lib/CodeGen/AsmPrinter/AsmPrinter.cpp 809 const MachineOperand &Op = MI->getOperand(i);
lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp 529 const MachineOperand &MO = MI->getOperand(I);
603 void AsmPrinter::PrintSymbolOperand(const MachineOperand &MO, raw_ostream &OS) {
620 const MachineOperand &MO = MI->getOperand(OpNo);
lib/CodeGen/AsmPrinter/DbgEntityHistoryCalculator.cpp 270 for (const MachineOperand &MO : MI.operands()) {
lib/CodeGen/AsmPrinter/DwarfDebug.cpp 236 auto RegOp = MI->getOperand(0);
237 auto Op1 = MI->getOperand(1);
589 for (const MachineOperand &MO : MI.operands()) {
722 const MachineOperand &CalleeOp = MI.getOperand(0);
lib/CodeGen/AsmPrinter/DwarfUnit.cpp 510 void DwarfUnit::addConstantFPValue(DIE &Die, const MachineOperand &MO) {
542 void DwarfUnit::addConstantValue(DIE &Die, const MachineOperand &MO,
lib/CodeGen/AsmPrinter/DwarfUnit.h 199 void addConstantValue(DIE &Die, const MachineOperand &MO, const DIType *Ty);
207 void addConstantFPValue(DIE &Die, const MachineOperand &MO);
lib/CodeGen/AsmPrinter/EHStreamer.cpp 175 const MachineOperand &MO = MI->getOperand(I);
lib/CodeGen/BranchFolding.cpp 202 SmallVector<MachineOperand, 4> Cond;
232 for (const MachineOperand &Op : I.operands()) {
259 const MachineOperand &Op = MI.getOperand(i);
266 case MachineOperand::MO_Register:
269 case MachineOperand::MO_Immediate:
272 case MachineOperand::MO_MachineBasicBlock:
275 case MachineOperand::MO_FrameIndex:
276 case MachineOperand::MO_ConstantPoolIndex:
277 case MachineOperand::MO_JumpTableIndex:
280 case MachineOperand::MO_GlobalAddress:
281 case MachineOperand::MO_ExternalSymbol:
520 SmallVector<MachineOperand, 4> Cond;
876 MachineOperand &MO = MBBICommon->getOperand(I);
878 const MachineOperand &OtherMO = MBBI->getOperand(I);
1173 SmallVector<MachineOperand, 4> Cond;
1177 SmallVector<MachineOperand, 4> NewCond(Cond);
1446 SmallVector<MachineOperand, 4> PriorCond;
1528 SmallVector<MachineOperand, 4> NewPriorCond(PriorCond);
1563 SmallVector<MachineOperand, 4> NewPriorCond(PriorCond);
1591 SmallVector<MachineOperand, 4> PredCond;
1621 SmallVector<MachineOperand, 4> CurCond;
1634 SmallVector<MachineOperand, 4> NewCond(CurCond);
1706 SmallVector<MachineOperand, 4> NewCurCond;
1751 SmallVector<MachineOperand, 4> PredCond;
1812 SmallVector<MachineOperand, 4> PrevCond;
1879 for (const MachineOperand &MO : Loc->operands()) {
1914 for (const MachineOperand &MO : PI->operands()) {
1945 for (const MachineOperand &MO : PI->operands()) {
1969 SmallVector<MachineOperand, 4> Cond;
2013 for (MachineOperand &MO : TIB->operands()) {
2068 for (const MachineOperand &MO : TIB->operands()) {
2086 for (const MachineOperand &MO : TIB->operands()) {
lib/CodeGen/BranchRelaxation.cpp 305 SmallVector<MachineOperand, 4> Cond;
lib/CodeGen/BreakFalseDeps.cpp 109 MachineOperand &MO = MI->getOperand(OpIdx);
130 for (MachineOperand &CurrMO : MI->operands()) {
202 MachineOperand &MO = MI->getOperand(i);
lib/CodeGen/CFGuardLongjmp.cpp 82 for (MachineOperand &MO : MI.operands()) {
lib/CodeGen/CriticalAntiDepBreaker.cpp 188 MachineOperand &MO = MI.getOperand(i);
262 MachineOperand &MO = MI.getOperand(i);
304 MachineOperand &MO = MI.getOperand(i);
351 MachineOperand *RefOper = I->second;
362 const MachineOperand &CheckOper = MI->getOperand(i);
614 MachineOperand &MO = MI.getOperand(i);
641 std::pair<std::multimap<unsigned, MachineOperand *>::iterator,
642 std::multimap<unsigned, MachineOperand *>::iterator>
655 for (std::multimap<unsigned, MachineOperand *>::iterator
lib/CodeGen/CriticalAntiDepBreaker.h 56 std::multimap<unsigned, MachineOperand *> RegRefs;
59 std::multimap<unsigned, MachineOperand *>::const_iterator;
lib/CodeGen/DeadMachineInstructionElim.cpp 76 const MachineOperand &MO = MI->getOperand(i);
141 const MachineOperand &MO = MI->getOperand(i);
160 const MachineOperand &MO = MI->getOperand(i);
lib/CodeGen/DetectDeadLanes.cpp 75 void addUsedLanesOnOperand(const MachineOperand &MO, LaneBitmask UsedLanes);
85 void transferDefinedLanesStep(const MachineOperand &Use,
91 LaneBitmask transferDefinedLanes(const MachineOperand &Def, unsigned OpNum,
97 const MachineOperand &MO) const;
104 bool isUndefRegAtInput(const MachineOperand &MO,
107 bool isUndefInput(const MachineOperand &MO, bool *CrossCopy) const;
155 const MachineOperand &MO) {
193 void DetectDeadLanes::addUsedLanesOnOperand(const MachineOperand &MO,
221 for (const MachineOperand &MO : MI.uses()) {
231 const MachineOperand &MO) const {
252 const MachineOperand &Def = MI.getOperand(0);
274 void DetectDeadLanes::transferDefinedLanesStep(const MachineOperand &Use,
287 const MachineOperand &Def = *MI.defs().begin();
310 LaneBitmask DetectDeadLanes::transferDefinedLanes(const MachineOperand &Def,
358 const MachineOperand &Def = *MRI->def_begin(Reg);
377 for (const MachineOperand &MO : DefMI.uses()) {
392 const MachineOperand &MODef = *MRI->def_begin(MOReg);
419 for (const MachineOperand &MO : MRI->use_nodbg_operands(Reg)) {
430 const MachineOperand &Def = *UseMI.defs().begin();
458 bool DetectDeadLanes::isUndefRegAtInput(const MachineOperand &MO,
465 bool DetectDeadLanes::isUndefInput(const MachineOperand &MO,
472 const MachineOperand &Def = MI.getOperand(0);
514 MachineOperand &Def = *MRI->def_begin(Reg);
518 for (const MachineOperand &MO : MRI->use_nodbg_operands(Reg))
536 for (MachineOperand &MO : MI.operands()) {
lib/CodeGen/EarlyIfConversion.cpp 124 SmallVector<MachineOperand, 4> Cond;
255 for (const MachineOperand &MO : I->operands()) {
378 for (const MachineOperand &MO : I->operands()) {
688 SmallVector<MachineOperand, 0> EmptyCond;
lib/CodeGen/ExecutionDomainFix.cpp 241 MachineOperand &MO = MI->getOperand(i);
262 MachineOperand &mo = mi->getOperand(i);
272 MachineOperand &mo = mi->getOperand(i);
293 MachineOperand &mo = mi->getOperand(i);
383 for (MachineOperand &mo : mi->operands()) {
lib/CodeGen/ExpandPostRAPseudos.cpp 70 for (const MachineOperand &MO : MI->implicit_operands())
143 MachineOperand &DstMO = MI->getOperand(0);
144 MachineOperand &SrcMO = MI->getOperand(1);
lib/CodeGen/GlobalISel/CSEInfo.cpp 316 addNodeIDMachineOperand(MachineOperand::CreateReg(Reg, false));
334 const MachineOperand &MO) const {
lib/CodeGen/GlobalISel/CSEMIRBuilder.cpp 220 ProfBuilder.addNodeIDMachineOperand(MachineOperand::CreateCImm(&Val));
247 ProfBuilder.addNodeIDMachineOperand(MachineOperand::CreateFPImm(&Val));
lib/CodeGen/GlobalISel/CallLowering.cpp 54 Info.Callee = MachineOperand::CreateGA(F, 0);
56 Info.Callee = MachineOperand::CreateReg(GetCalleeReg(), false);
lib/CodeGen/GlobalISel/CombinerHelper.cpp 55 MachineOperand &FromRegOp,
112 for (const MachineOperand &MO : MI.operands()) {
124 for (const MachineOperand &BuildVecMO : Def->operands()) {
321 MachineIRBuilder &Builder, MachineInstr &DefMI, MachineOperand &UseMO,
331 MachineOperand *PredBB = std::next(&UseMO);
371 auto &LoadValue = MI.getOperand(0);
458 auto &LoadValue = MI.getOperand(0);
459 SmallVector<MachineOperand *, 4> Uses;
460 for (auto &UseMO : MRI.use_operands(LoadValue.getReg()))
463 for (auto *UseMO : Uses) {
471 MachineOperand &UseSrcMO = UseMI->getOperand(1);
lib/CodeGen/GlobalISel/GISelKnownBits.cpp 126 MachineOperand Dst = MI.getOperand(0);
127 MachineOperand Src = MI.getOperand(1);
lib/CodeGen/GlobalISel/InstructionSelector.cpp 49 const MachineOperand &MO, int64_t Value,
58 const MachineOperand &Root, const MachineRegisterInfo &MRI) const {
66 MachineOperand &RHS = RootI->getOperand(2);
lib/CodeGen/GlobalISel/LegalizerHelper.cpp 369 Info.Callee = MachineOperand::CreateES(Name);
435 Info.Callee = MachineOperand::CreateES(Name);
1000 MachineOperand &MO1 = MI.getOperand(1);
1004 MachineOperand &MO2 = MI.getOperand(0);
1083 MachineOperand &MO = MI.getOperand(OpIdx);
1090 MachineOperand &MO = MI.getOperand(OpIdx);
1098 MachineOperand &MO = MI.getOperand(OpIdx);
1107 MachineOperand &MO = MI.getOperand(OpIdx);
1116 MachineOperand &MO = MI.getOperand(OpIdx);
1125 MachineOperand &MO = MI.getOperand(OpIdx);
1676 MachineOperand &SrcMO = MI.getOperand(1);
1687 MachineOperand &SrcMO = MI.getOperand(1);
lib/CodeGen/GlobalISel/Localizer.cpp 98 bool Localizer::isLocalUse(MachineOperand &MOUse, const MachineInstr &Def,
130 MachineOperand &MOUse = *MOIt++;
lib/CodeGen/GlobalISel/RegBankSelect.cpp 134 MachineOperand &MO, const RegisterBankInfo::ValueMapping &ValMapping,
237 const MachineOperand &MO,
323 RegBankSelect::RepairingPlacement &RepairPt, const MachineOperand &MO,
468 const MachineOperand &MO = MI.getOperand(OpIdx);
594 MachineOperand &MO = MI.getOperand(OpIdx);
728 const MachineOperand &MO = MI.getOperand(OpIdx);
lib/CodeGen/GlobalISel/RegisterBankInfo.cpp 179 const MachineOperand &MO = MI.getOperand(OpIdx);
228 const MachineOperand &MO = MI.getOperand(OpIdx);
441 MachineOperand &MO = MI.getOperand(OpIdx);
604 const MachineOperand &MO = MI.getOperand(Idx);
lib/CodeGen/GlobalISel/Utils.cpp 44 const TargetRegisterClass &RegClass, const MachineOperand &RegMO,
74 const MachineOperand &RegMO, unsigned OpIdx) {
122 MachineOperand &MO = I.getOperand(OpI);
229 const MachineOperand &CstVal = MI.getOperand(1);
lib/CodeGen/IfConversion.cpp 149 SmallVector<MachineOperand, 4> BrCond;
150 SmallVector<MachineOperand, 4> Predicate;
254 bool FeasibilityAnalysis(BBInfo &BBI, SmallVectorImpl<MachineOperand> &Pred,
277 SmallVectorImpl<MachineOperand> &Cond,
751 std::vector<MachineOperand> PredDefs;
1031 SmallVector<MachineOperand, 4> RevCond(BBI.BrCond.begin(), BBI.BrCond.end());
1141 std::vector<MachineOperand> PredDefs;
1162 SmallVectorImpl<MachineOperand> &Pred,
1188 SmallVector<MachineOperand, 4> RevPred(Pred.begin(), Pred.end());
1189 SmallVector<MachineOperand, 4> Cond(BBI.BrCond.begin(), BBI.BrCond.end());
1278 SmallVector<MachineOperand, 4>
1468 SmallVector<MachineOperand, 0> NoCond;
1485 SmallVector<std::pair<MCPhysReg, const MachineOperand*>, 4> Clobbers;
1493 MachineOperand &Op = const_cast<MachineOperand&>(*Clobber.second);
1533 SmallVector<MachineOperand, 4> Cond(BBI.BrCond.begin(), BBI.BrCond.end());
1619 SmallVector<MachineOperand, 4> Cond(BBI.BrCond.begin(), BBI.BrCond.end());
1698 SmallVector<MachineOperand, 4> RevCond(CvtBBI->BrCond.begin(),
1790 SmallVector<MachineOperand, 4> RevCond(BBI.BrCond.begin(), BBI.BrCond.end());
1793 SmallVector<MachineOperand, 4> *Cond1 = &BBI.BrCond;
1794 SmallVector<MachineOperand, 4> *Cond2 = &RevCond;
1859 SmallVector<std::pair<MCPhysReg, const MachineOperand*>, 4> Dummy;
1945 for (const MachineOperand &MO : FI.operands()) {
2113 for (const MachineOperand &MO : MI.operands()) {
2172 SmallVectorImpl<MachineOperand> &Cond,
lib/CodeGen/ImplicitNullChecks.cpp 277 for (auto MOA : A->operands()) {
282 for (auto MOB : B->operands()) {
366 const MachineOperand *BaseOp;
415 for (auto &DependenceMO : DependenceMI->operands()) {
642 for (auto &MO : MI->uses()) {
644 MachineOperand NewMO = MO;
689 for (const MachineOperand &MO : FaultingInstr->operands()) {
699 for (auto &MO : DepMI->operands()) {
lib/CodeGen/InlineSpiller.cpp 558 MachineOperand &MO = MI.getOperand(i);
623 MachineOperand &MO = OpPair.first->getOperand(OpPair.second);
772 MachineOperand *MO = I->findRegisterDefOperand(VReg);
814 MachineOperand &MO = MI->getOperand(Idx);
883 MachineOperand &MO = FoldMI->getOperand(i - 1);
1043 MachineOperand &MO = OpPair.first->getOperand(OpPair.second);
1522 MachineOperand &MO = RMEnt->getOperand(i - 1);
lib/CodeGen/InterferenceCache.cpp 198 if (MachineOperand::clobbersPhysReg(RegMaskBits[i], PhysReg)) {
255 if (MachineOperand::clobbersPhysReg(RegMaskBits[i-1], PhysReg)) {
lib/CodeGen/LiveDebugValues.cpp 308 MachineOperand MO = MI.getOperand(0);
811 for (const MachineOperand &MO : MI.operands()) {
872 for (const MachineOperand &MO : MI.operands()) {
886 for (const MachineOperand &MONext : NextI->operands()) {
1000 const MachineOperand *SrcRegOp, *DestRegOp;
lib/CodeGen/LiveDebugVariables.cpp 192 SmallVector<MachineOperand, 4> locations;
227 unsigned getLocationNo(const MachineOperand &LocMO) {
257 void addDef(SlotIndex Idx, const MachineOperand &LocMO) {
651 MachineOperand MO = MachineOperand::CreateReg(0U, false);
651 MachineOperand MO = MachineOperand::CreateReg(0U, false);
773 for (MachineOperand &MO : MRI.use_nodbg_operands(LI->reg)) {
847 const MachineOperand &LocMO = locations[Loc.locNo()];
1043 MachineOperand MO = MachineOperand::CreateReg(LI->reg, false);
1043 MachineOperand MO = MachineOperand::CreateReg(LI->reg, false);
1122 const MachineOperand *Loc = &locations[LocNo];
1164 MapVector<MachineOperand, std::pair<bool, unsigned>> NewLocations;
1169 MachineOperand Loc = locations[I];
1191 Loc = MachineOperand::CreateFI(VRM.getStackSlot(VirtReg));
1295 MachineOperand MO = !Loc.isUndef() ?
1297 MachineOperand::CreateReg(/* Reg */ 0, /* isDef */ false, /* isImp */ false,
lib/CodeGen/LiveInterval.cpp 975 for (const MachineOperand &MO : MRI.def_operands(reg)) {
1357 MachineOperand &MO = *RI;
lib/CodeGen/LiveIntervals.cpp 226 for (const MachineOperand &MO : MI.operands()) {
551 for (MachineOperand &MO : MRI->use_nodbg_operands(Reg)) {
778 for (const MachineOperand &MO : MI->operands()) {
976 for (MachineOperand &MO : MI->operands()) {
1404 for (MachineOperand &MO : MRI.use_nodbg_operands(Reg)) {
1513 const MachineOperand &MO = *OI;
lib/CodeGen/LivePhysRegs.cpp 30 void LivePhysRegs::removeRegsInMask(const MachineOperand &MO,
31 SmallVectorImpl<std::pair<MCPhysReg, const MachineOperand*>> *Clobbers) {
85 SmallVectorImpl<std::pair<MCPhysReg, const MachineOperand*>> &Clobbers) {
113 MachineOperand::clobbersPhysReg(Reg.second->getRegMask(), Reg.first))
lib/CodeGen/LiveRangeCalc.cpp 65 LiveRange &LR, const MachineOperand &MO) {
82 for (const MachineOperand &MO : MRI->reg_nodbg_operands(Reg)) {
152 for (MachineOperand &MO : MRI->def_operands(Reg))
165 for (MachineOperand &MO : MRI->reg_nodbg_operands(Reg)) {
lib/CodeGen/LiveRangeEdit.cpp 112 const MachineOperand &MO = OrigMI->getOperand(i);
190 for (MachineOperand &MO : MRI.reg_nodbg_operands(LI->reg)) {
244 const MachineOperand &MO) const {
351 const MachineOperand &MO = MI->getOperand(i-1);
lib/CodeGen/LiveRangeShrink.cpp 140 for (const MachineOperand &MO : MI.operands()) {
165 const MachineOperand *DefMO = nullptr;
172 for (const MachineOperand &MO : MI.operands()) {
lib/CodeGen/LiveRegUnits.cpp 29 if (MachineOperand::clobbersPhysReg(RegMask, *RootReg))
38 if (MachineOperand::clobbersPhysReg(RegMask, *RootReg))
lib/CodeGen/LiveVariables.cpp 215 MachineOperand &MO = LastDef->getOperand(i);
247 LastPartialDef->addOperand(MachineOperand::CreateReg(Reg, true/*IsDef*/,
259 LastPartialDef->addOperand(MachineOperand::CreateReg(SubReg,
270 LastDef->addOperand(MachineOperand::CreateReg(Reg, true/*IsDef*/,
376 MachineOperand *MO = PhysRegDef[Reg]->findRegisterDefOperand(SubReg);
383 PhysRegDef[Reg]->addOperand(MachineOperand::CreateReg(SubReg,
400 LastPartDef->addOperand(MachineOperand::CreateReg(Reg, false/*IsDef*/,
403 MachineOperand *MO =
422 void LiveVariables::HandleRegMask(const MachineOperand &MO) {
516 MachineOperand &MO = MI.getOperand(i);
691 MachineOperand &MO = MI.getOperand(i);
lib/CodeGen/MIRCanonicalizerPass.cpp 169 MachineOperand &MO = II->getOperand(i);
189 MachineOperand &MO = II->getOperand(0);
225 for (auto &UO : MRI->use_nodbg_operands(MO.getReg())) {
340 std::vector<MachineOperand *> Uses;
343 for (auto *MO : Uses)
357 for (auto &MO : MI.operands()) {
432 std::vector<MachineOperand *> RenameMOs;
433 for (auto &MO : MRI.reg_operands(vRegToRename)) {
437 for (auto *MO : RenameMOs) {
lib/CodeGen/MIRParser/MIParser.cpp 351 MachineOperand Operand;
356 ParsedMachineOperand(const MachineOperand &Operand, StringRef::iterator Begin,
420 bool parseRegisterOperand(MachineOperand &Dest,
422 bool parseImmediateOperand(MachineOperand &Dest);
427 bool parseTypedImmediateOperand(MachineOperand &Dest);
428 bool parseFPImmediateOperand(MachineOperand &Dest);
430 bool parseMBBOperand(MachineOperand &Dest);
432 bool parseStackObjectOperand(MachineOperand &Dest);
434 bool parseFixedStackObjectOperand(MachineOperand &Dest);
436 bool parseGlobalAddressOperand(MachineOperand &Dest);
437 bool parseConstantPoolIndexOperand(MachineOperand &Dest);
438 bool parseSubRegisterIndexOperand(MachineOperand &Dest);
439 bool parseJumpTableIndexOperand(MachineOperand &Dest);
440 bool parseExternalSymbolOperand(MachineOperand &Dest);
441 bool parseMCSymbolOperand(MachineOperand &Dest);
445 bool parseMetadataOperand(MachineOperand &Dest);
449 bool parseCFIOperand(MachineOperand &Dest);
451 bool parseBlockAddressOperand(MachineOperand &Dest);
452 bool parseIntrinsicOperand(MachineOperand &Dest);
453 bool parsePredicateOperand(MachineOperand &Dest);
454 bool parseShuffleMaskOperand(MachineOperand &Dest);
455 bool parseTargetIndexOperand(MachineOperand &Dest);
456 bool parseCustomRegisterMaskOperand(MachineOperand &Dest);
457 bool parseLiveoutRegisterMaskOperand(MachineOperand &Dest);
458 bool parseMachineOperand(MachineOperand &Dest,
460 bool parseMachineOperandAndTargetFlags(MachineOperand &Dest,
465 bool parseOperandsOffset(MachineOperand &Op);
886 MachineOperand MO = MachineOperand::CreateImm(0);
886 MachineOperand MO = MachineOperand::CreateImm(0);
1075 static const char *printImplicitRegisterFlag(const MachineOperand &MO) {
1087 static bool isImplicitOperandIn(const MachineOperand &ImplicitOperand,
1104 SmallVector<MachineOperand, 4> ImplicitOperands;
1108 MachineOperand::CreateReg(*ImpDefs, true, true));
1112 MachineOperand::CreateReg(*ImpUses, false, true));
1116 for (const auto &I : ImplicitOperands) {
1370 const auto &DefOperand = Operands[DefIdx].Operand;
1393 bool MIParser::parseRegisterOperand(MachineOperand &Dest,
1469 Dest = MachineOperand::CreateReg(
1478 bool MIParser::parseImmediateOperand(MachineOperand &Dest) {
1483 Dest = MachineOperand::CreateImm(Int.getExtValue());
1593 bool MIParser::parseTypedImmediateOperand(MachineOperand &Dest) {
1614 Dest = MachineOperand::CreateCImm(cast<ConstantInt>(C));
1618 bool MIParser::parseFPImmediateOperand(MachineOperand &Dest) {
1627 Dest = MachineOperand::CreateFPImm(cast<ConstantFP>(C));
1671 bool MIParser::parseMBBOperand(MachineOperand &Dest) {
1675 Dest = MachineOperand::CreateMBB(MBB);
1701 bool MIParser::parseStackObjectOperand(MachineOperand &Dest) {
1705 Dest = MachineOperand::CreateFI(FI);
1723 bool MIParser::parseFixedStackObjectOperand(MachineOperand &Dest) {
1727 Dest = MachineOperand::CreateFI(FI);
1757 bool MIParser::parseGlobalAddressOperand(MachineOperand &Dest) {
1762 Dest = MachineOperand::CreateGA(GV, /*Offset=*/0);
1768 bool MIParser::parseConstantPoolIndexOperand(MachineOperand &Dest) {
1777 Dest = MachineOperand::CreateCPI(ID, /*Offset=*/0);
1783 bool MIParser::parseJumpTableIndexOperand(MachineOperand &Dest) {
1792 Dest = MachineOperand::CreateJTI(JumpTableEntryInfo->second);
1796 bool MIParser::parseExternalSymbolOperand(MachineOperand &Dest) {
1800 Dest = MachineOperand::CreateES(Symbol);
1806 bool MIParser::parseMCSymbolOperand(MachineOperand &Dest) {
1810 Dest = MachineOperand::CreateMCSymbol(Symbol);
1816 bool MIParser::parseSubRegisterIndexOperand(MachineOperand &Dest) {
1823 Dest = MachineOperand::CreateImm(SubRegIndex);
1994 bool MIParser::parseMetadataOperand(MachineOperand &Dest) {
2003 Dest = MachineOperand::CreateMetadata(Node);
2048 bool MIParser::parseCFIOperand(MachineOperand &Dest) {
2144 Dest = MachineOperand::CreateCFIIndex(CFIIndex);
2173 bool MIParser::parseBlockAddressOperand(MachineOperand &Dest) {
2198 Dest = MachineOperand::CreateBA(BlockAddress::get(F, BB), /*Offset=*/0);
2204 bool MIParser::parseIntrinsicOperand(MachineOperand &Dest) {
2228 Dest = MachineOperand::CreateIntrinsicID(ID);
2233 bool MIParser::parsePredicateOperand(MachineOperand &Dest) {
2284 Dest = MachineOperand::CreatePredicate(Pred);
2291 bool MIParser::parseShuffleMaskOperand(MachineOperand &Dest) {
2327 Dest = MachineOperand::CreateShuffleMask(C);
2329 Dest = MachineOperand::CreateShuffleMask(ConstantVector::get(ShufMask));
2334 bool MIParser::parseTargetIndexOperand(MachineOperand &Dest) {
2347 Dest = MachineOperand::CreateTargetIndex(unsigned(Index), /*Offset=*/0);
2353 bool MIParser::parseCustomRegisterMaskOperand(MachineOperand &Dest) {
2376 Dest = MachineOperand::CreateRegMask(Mask);
2380 bool MIParser::parseLiveoutRegisterMaskOperand(MachineOperand &Dest) {
2401 Dest = MachineOperand::CreateRegLiveOut(Mask);
2405 bool MIParser::parseMachineOperand(MachineOperand &Dest,
2487 Dest = MachineOperand::CreateRegMask(RegMask);
2502 MachineOperand &Dest, Optional<unsigned> &TiedDefIdx) {
2587 bool MIParser::parseOperandsOffset(MachineOperand &Op) {
lib/CodeGen/MIRParser/MIRParser.cpp 615 for (const MachineOperand &MO : MI.operands()) {
lib/CodeGen/MIRPrinter.cpp 557 for (const MachineOperand &MO : MI.operands()) {
777 MachineOperand::printSymbol(OS, *PreInstrSymbol);
784 MachineOperand::printSymbol(OS, *PostInstrSymbol);
814 MachineOperand::printStackObjectReference(OS, Operand.ID, Operand.IsFixed,
822 const MachineOperand &Op = MI.getOperand(OpIdx);
824 case MachineOperand::MO_Immediate:
826 MachineOperand::printTargetFlags(OS, Op);
827 MachineOperand::printSubRegIdx(OS, Op.getImm(), TRI);
831 case MachineOperand::MO_Register:
832 case MachineOperand::MO_CImmediate:
833 case MachineOperand::MO_FPImmediate:
834 case MachineOperand::MO_MachineBasicBlock:
835 case MachineOperand::MO_ConstantPoolIndex:
836 case MachineOperand::MO_TargetIndex:
837 case MachineOperand::MO_JumpTableIndex:
838 case MachineOperand::MO_ExternalSymbol:
839 case MachineOperand::MO_GlobalAddress:
840 case MachineOperand::MO_RegisterLiveOut:
841 case MachineOperand::MO_Metadata:
842 case MachineOperand::MO_MCSymbol:
843 case MachineOperand::MO_CFIIndex:
844 case MachineOperand::MO_IntrinsicID:
845 case MachineOperand::MO_Predicate:
846 case MachineOperand::MO_BlockAddress:
847 case MachineOperand::MO_ShuffleMask: {
856 case MachineOperand::MO_FrameIndex:
859 case MachineOperand::MO_RegisterMask: {
lib/CodeGen/MIRVRegNamerUtils.cpp 142 MachineOperand &MO = Def->getOperand(I);
236 std::vector<MachineOperand *> RenameMOs;
237 for (auto &MO : MRI.reg_operands(VReg)) {
241 for (auto *MO : RenameMOs) {
278 MachineOperand &MO = candidate->getOperand(i);
293 MachineOperand &MO = candidate->getOperand(i);
lib/CodeGen/MachineBasicBlock.cpp 539 SmallVector<MachineOperand, 4> Cond;
839 SmallVector<MachineOperand, 4> Cond;
968 SmallVector<MachineOperand, 4> Cond;
1031 MachineOperand &MO = I->getOperand(ni);
1123 SmallVector<MachineOperand, 4> Cond;
1220 MachineOperand &MO = MI.getOperand(i);
lib/CodeGen/MachineBlockPlacement.cpp 2560 SmallVector<MachineOperand, 4> Cond; // For AnalyzeBranch.
2707 SmallVector<MachineOperand, 4> Cond; // For AnalyzeBranch.
lib/CodeGen/MachineCSE.cpp 167 for (MachineOperand &MO : MI->operands()) {
234 for (const MachineOperand &MO : I->operands()) {
282 for (const MachineOperand &MO : MI->operands()) {
301 const MachineOperand &MO = MOP.value();
374 for (const MachineOperand &MO : I->operands()) {
465 for (const MachineOperand &MO : MI->operands()) {
595 MachineOperand &MO = MI->getOperand(i);
675 if (MachineOperand *MO = II->findRegisterUseOperand(
780 for (auto def : MI->defs())
784 for (auto use : MI->uses())
lib/CodeGen/MachineCombiner.cpp 87 MachineInstr *getOperandDef(const MachineOperand &MO);
137 MachineInstr *MachineCombiner::getOperandDef(const MachineOperand &MO) {
169 for (const MachineOperand &MO : InstrPtr->operands()) {
224 for (const MachineOperand &MO : NewRoot->operands()) {
lib/CodeGen/MachineCopyPropagation.cpp 170 for (const MachineOperand &MO : MI.operands())
218 bool hasImplicitOverlap(const MachineInstr &MI, const MachineOperand &Use);
370 const MachineOperand &Use) {
371 for (const MachineOperand &MIUse : MI.uses())
390 MachineOperand &MOUse = MI.getOperand(OpIdx);
414 const MachineOperand &CopySrc = Copy->getOperand(1);
504 for (const MachineOperand &MO : MI->implicit_operands()) {
527 for (const MachineOperand &MO : MI->implicit_operands()) {
542 for (const MachineOperand &MO : MI->operands())
557 const MachineOperand *RegMask = nullptr;
558 for (const MachineOperand &MO : MI->operands()) {
lib/CodeGen/MachineFunction.cpp 466 unsigned Size = MachineOperand::getRegMaskSize(NumRegs);
lib/CodeGen/MachineInstr.cpp 106 addOperand(MF, MachineOperand::CreateReg(*ImpDefs, true, true));
110 addOperand(MF, MachineOperand::CreateReg(*ImpUses, false, true));
142 for (const MachineOperand &MO : MI.operands())
162 for (MachineOperand &MO : operands())
171 for (MachineOperand &MO : operands())
176 void MachineInstr::addOperand(const MachineOperand &Op) {
186 static void moveOperands(MachineOperand *Dst, MachineOperand *Src,
186 static void moveOperands(MachineOperand *Dst, MachineOperand *Src,
192 std::memmove(Dst, Src, NumOps * sizeof(MachineOperand));
199 void MachineInstr::addOperand(MachineFunction &MF, const MachineOperand &Op) {
207 MachineOperand CopyOp(Op);
228 bool isDebugOp = Op.getType() == MachineOperand::MO_Metadata ||
229 Op.getType() == MachineOperand::MO_MCSymbol;
243 MachineOperand *OldOperands = Operands;
263 MachineOperand *NewMO = new (Operands + OpNo) MachineOperand(Op);
263 MachineOperand *NewMO = new (Operands + OpNo) MachineOperand(Op);
615 const MachineOperand &MO = getOperand(i);
616 const MachineOperand &OMO = Other.getOperand(i);
683 for (const MachineOperand &MO : MI->operands()) {
705 const MachineOperand &MO = getOperand(I);
724 const MachineOperand &MO = getOperand(I);
796 const MachineOperand &FlagMO = getOperand(i);
892 const MachineOperand &MO = getOperand(OpIdx);
903 const MachineOperand &MO = getOperand(OpIdx);
933 const MachineOperand &MO = getOperand(i);
946 const MachineOperand &MO = getOperand(i);
970 const MachineOperand &MO = getOperand(i);
996 const MachineOperand &MO = getOperand(i);
1051 MachineOperand &DefMO = getOperand(DefIdx);
1052 MachineOperand &UseMO = getOperand(UseIdx);
1076 const MachineOperand &MO = getOperand(OpIdx);
1090 const MachineOperand &UseMO = getOperand(i);
1104 const MachineOperand &FlagMO = getOperand(i);
1133 for (MachineOperand &MO : operands()) {
1145 for (MachineOperand &MO : operands()) {
1151 for (MachineOperand &MO : operands()) {
1387 for (const MachineOperand &MO : operands()) {
1402 const MachineOperand &MO = MI.getOperand(i);
1411 const auto &Operand = getOperand(I);
1425 const MachineOperand &Op = getOperand(OpIdx);
1490 const MachineOperand &MO = getOperand(OpIdx);
1500 const MachineOperand &MO = getOperand(StartOp);
1590 const MachineOperand &MO = getOperand(i);
1679 MachineOperand::printSubRegIdx(OS, MO.getImm(), TRI);
1694 MachineOperand::printSymbol(OS, *PreInstrSymbol);
1702 MachineOperand::printSymbol(OS, *PostInstrSymbol);
1793 MachineOperand &MO = getOperand(i);
1841 addOperand(MachineOperand::CreateReg(IncomingReg,
1854 for (MachineOperand &MO : operands()) {
1872 MachineOperand &MO = getOperand(i);
1908 addOperand(MachineOperand::CreateReg(Reg,
1917 for (MachineOperand &MO : operands()) {
1925 for (MachineOperand &MO : operands()) {
1935 MachineOperand *MO = findRegisterDefOperand(Reg, false, false, RegInfo);
1939 for (const MachineOperand &MO : operands()) {
1945 addOperand(MachineOperand::CreateReg(Reg,
1953 for (MachineOperand &MO : operands()) {
1982 for (const MachineOperand &MO : MI->operands()) {
2031 MachineOperand &MO, const MDNode *Variable,
2130 for (auto &MO : MRI->use_operands(DefReg)) {
lib/CodeGen/MachineInstrBundle.cpp 62 MachineOperand &MO = MII->getOperand(i);
146 SmallVector<MachineOperand*, 4> Defs;
149 MachineOperand &MO = MII->getOperand(i);
179 MachineOperand &MO = *Defs[i];
289 MachineOperand &MO = deref();
322 MachineOperand &MO = deref();
lib/CodeGen/MachineLICM.cpp 405 for (const MachineOperand &MO : MI->operands()) {
525 for (const MachineOperand &MO : TI->operands()) {
553 for (const MachineOperand &MO : MI->operands()) {
578 for (MachineOperand &MO : MI.operands()) {
768 const MachineOperand &MO = I->getOperand(0);
800 static bool isOperandKill(const MachineOperand &MO, MachineRegisterInfo *MRI) {
816 SmallVector<MachineOperand, 4> Cond;
851 const MachineOperand &MO = MI->getOperand(i);
922 for (const MachineOperand &MO : MI.operands()) {
1008 for (const MachineOperand &MO : I.operands()) {
1060 for (const MachineOperand &MO : MI->operands()) {
1103 const MachineOperand &MO = UseMI.getOperand(i);
1130 MachineOperand &DefMO = MI.getOperand(i);
1224 const MachineOperand &MO = MI.getOperand(i);
1376 const MachineOperand &MO = MI->getOperand(i);
1485 for (MachineOperand &MO : MI->operands())
lib/CodeGen/MachineLoopUtils.cpp 50 for (MachineOperand &MO : NewMI->defs()) {
62 SmallVector<MachineOperand *, 4> Uses;
63 for (auto &Use : MRI.use_operands(OrigR))
66 for (auto *Use : Uses) {
75 for (MachineOperand &MO : I->uses())
120 SmallVector<MachineOperand, 4> Cond;
lib/CodeGen/MachineOperand.cpp 40 static const MachineFunction *getMFIfAvailable(const MachineOperand &MO) {
47 static MachineFunction *getMFIfAvailable(MachineOperand &MO) {
274 bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
280 case MachineOperand::MO_Register:
283 case MachineOperand::MO_Immediate:
285 case MachineOperand::MO_CImmediate:
287 case MachineOperand::MO_FPImmediate:
289 case MachineOperand::MO_MachineBasicBlock:
291 case MachineOperand::MO_FrameIndex:
293 case MachineOperand::MO_ConstantPoolIndex:
294 case MachineOperand::MO_TargetIndex:
296 case MachineOperand::MO_JumpTableIndex:
298 case MachineOperand::MO_GlobalAddress:
300 case MachineOperand::MO_ExternalSymbol:
303 case MachineOperand::MO_BlockAddress:
306 case MachineOperand::MO_RegisterMask:
307 case MachineOperand::MO_RegisterLiveOut: {
326 case MachineOperand::MO_MCSymbol:
328 case MachineOperand::MO_CFIIndex:
330 case MachineOperand::MO_Metadata:
332 case MachineOperand::MO_IntrinsicID:
334 case MachineOperand::MO_Predicate:
336 case MachineOperand::MO_ShuffleMask:
343 hash_code llvm::hash_value(const MachineOperand &MO) {
345 case MachineOperand::MO_Register:
348 case MachineOperand::MO_Immediate:
350 case MachineOperand::MO_CImmediate:
352 case MachineOperand::MO_FPImmediate:
354 case MachineOperand::MO_MachineBasicBlock:
356 case MachineOperand::MO_FrameIndex:
358 case MachineOperand::MO_ConstantPoolIndex:
359 case MachineOperand::MO_TargetIndex:
362 case MachineOperand::MO_JumpTableIndex:
364 case MachineOperand::MO_ExternalSymbol:
367 case MachineOperand::MO_GlobalAddress:
370 case MachineOperand::MO_BlockAddress:
373 case MachineOperand::MO_RegisterMask:
374 case MachineOperand::MO_RegisterLiveOut:
376 case MachineOperand::MO_Metadata:
378 case MachineOperand::MO_MCSymbol:
380 case MachineOperand::MO_CFIIndex:
382 case MachineOperand::MO_IntrinsicID:
384 case MachineOperand::MO_Predicate:
386 case MachineOperand::MO_ShuffleMask:
394 static void tryToGetTargetInfo(const MachineOperand &MO,
456 MachineOperand::printIRSlotNumber(OS, *Slot);
480 MachineOperand::printIRSlotNumber(OS, Slot);
522 MachineOperand::printStackObjectReference(OS, FrameIndex, IsFixed, Name);
535 const MachineOperand &Op) {
626 MachineOperand::printSymbol(OS, *Label);
632 MachineOperand::printSymbol(OS, *Label);
637 MachineOperand::printSymbol(OS, *Label);
642 MachineOperand::printSymbol(OS, *Label);
649 MachineOperand::printSymbol(OS, *Label);
655 MachineOperand::printSymbol(OS, *Label);
661 MachineOperand::printSymbol(OS, *Label);
668 MachineOperand::printSymbol(OS, *Label);
675 MachineOperand::printSymbol(OS, *Label);
681 MachineOperand::printSymbol(OS, *Label);
687 MachineOperand::printSymbol(OS, *Label);
699 MachineOperand::printSymbol(OS, *Label);
705 MachineOperand::printSymbol(OS, *Label);
713 MachineOperand::printSymbol(OS, *Label);
718 MachineOperand::printSymbol(OS, *Label);
750 case MachineOperand::MO_Register: {
805 case MachineOperand::MO_Immediate:
808 case MachineOperand::MO_CImmediate:
811 case MachineOperand::MO_FPImmediate:
814 case MachineOperand::MO_MachineBasicBlock:
817 case MachineOperand::MO_FrameIndex: {
826 case MachineOperand::MO_ConstantPoolIndex:
830 case MachineOperand::MO_TargetIndex: {
840 case MachineOperand::MO_JumpTableIndex:
843 case MachineOperand::MO_GlobalAddress:
847 case MachineOperand::MO_ExternalSymbol: {
858 case MachineOperand::MO_BlockAddress: {
865 MachineOperand::printOperandOffset(OS, getOffset());
868 case MachineOperand::MO_RegisterMask: {
893 case MachineOperand::MO_RegisterLiveOut: {
912 case MachineOperand::MO_Metadata:
915 case MachineOperand::MO_MCSymbol:
918 case MachineOperand::MO_CFIIndex: {
925 case MachineOperand::MO_IntrinsicID: {
935 case MachineOperand::MO_Predicate: {
941 case MachineOperand::MO_ShuffleMask:
1157 MachineOperand::printOperandOffset(OS, getOffset());
lib/CodeGen/MachineOutliner.cpp 1247 for (MachineOperand &MOP : MI.operands()) {
1254 CallInst->addOperand(MachineOperand::CreateReg(
lib/CodeGen/MachinePipeliner.cpp 353 MachineOperand &DefOp = PI.getOperand(0);
358 MachineOperand &RegOp = PI.getOperand(i);
694 const MachineOperand *BaseOp1, *BaseOp2;
1554 for (const MachineOperand &MO : MI->operands())
1565 for (const MachineOperand &MO : SU->getInstr()->operands())
2058 const MachineOperand *BaseOp;
2236 const MachineOperand *BaseOpS, *BaseOpD;
2473 MachineOperand &MO = MI->getOperand(i);
2617 MachineInstr *Def, MachineOperand &MO) {
2629 MachineOperand &DMO = Def->getOperand(i);
2766 const MachineOperand &MO = MI->getOperand(i);
lib/CodeGen/MachineRegisterInfo.cpp 52 PhysRegUseDefLists.reset(new MachineOperand*[NumRegs]());
133 for (MachineOperand &MO : reg_nodbg_operands(Reg)) {
220 for (MachineOperand &M : reg_operands(Reg)) {
221 MachineOperand *MO = &M;
230 MachineOperand *MO0 = &MI->getOperand(0);
265 void MachineRegisterInfo::addRegOperandToUseList(MachineOperand *MO) {
267 MachineOperand *&HeadRef = getRegUseDefListHead(MO->getReg());
268 MachineOperand *const Head = HeadRef;
284 MachineOperand *Last = Head->Contents.Reg.Prev;
304 void MachineRegisterInfo::removeRegOperandFromUseList(MachineOperand *MO) {
306 MachineOperand *&HeadRef = getRegUseDefListHead(MO->getReg());
307 MachineOperand *const Head = HeadRef;
311 MachineOperand *Next = MO->Contents.Reg.Next;
312 MachineOperand *Prev = MO->Contents.Reg.Prev;
333 void MachineRegisterInfo::moveOperands(MachineOperand *Dst,
334 MachineOperand *Src,
348 new (Dst) MachineOperand(*Src);
352 MachineOperand *&Head = getRegUseDefListHead(Src->getReg());
353 MachineOperand *Prev = Src->Contents.Reg.Prev;
354 MachineOperand *Next = Src->Contents.Reg.Next;
387 MachineOperand &O = *I;
438 for (MachineOperand &MO : use_operands(Reg))
558 for (const MachineOperand &MO : MI.operands()) {
568 static bool isNoReturnDef(const MachineOperand &MO) {
592 for (const MachineOperand &MO : make_range(def_begin(*AI), def_end())) {
lib/CodeGen/MachineSSAUpdater.cpp 212 MachineOperand *U) {
223 void MachineSSAUpdater::RewriteUse(MachineOperand &U) {
lib/CodeGen/MachineScheduler.cpp 930 for (const MachineOperand &MO : MI.operands()) {
945 for (const MachineOperand &MO2 : MI.operands()) {
1471 const MachineOperand *BaseOp;
1474 MemOpInfo(SUnit *su, const MachineOperand *Op, int64_t ofs)
1560 const MachineOperand *BaseOp;
1691 const MachineOperand &SrcOp = Copy->getOperand(1);
1696 const MachineOperand &DstOp = Copy->getOperand(0);
2933 for (const MachineOperand &Op : MI->defs()) {
lib/CodeGen/MachineSink.cpp 265 for (MachineOperand &MO : MRI->use_nodbg_operands(Reg)) {
278 for (MachineOperand &MO : MRI->use_nodbg_operands(Reg)) {
410 MachineOperand &MO = MI.getOperand(0);
439 const MachineOperand &MO = MI.getOperand(i);
638 const MachineOperand &MO = MI.getOperand(i);
740 const MachineOperand *BaseOp;
799 MachineOperand DbgMO = DbgMI->getOperand(0);
802 const MachineOperand *SrcMO = nullptr, *DstMO = nullptr;
879 const MachineOperand &MO = MI.getOperand(I);
952 for (auto &MO : MI.operands()) {
975 for (MachineOperand &MO : MI.operands()) {
993 for (auto &MO : MI.operands()) {
1148 MachineOperand &MO = MI->getOperand(U);
1185 MachineOperand &MO = MI->getOperand(i);
1256 auto &MO = MI->getOperand(0);
1311 for (auto &MO : MI->operands()) {
lib/CodeGen/MachineTraceMetrics.cpp 660 const MachineOperand &MO = *I;
708 const MachineOperand &MO = *MI;
902 const MachineOperand &MO = *MOI;
lib/CodeGen/MachineVerifier.cpp 237 void visitMachineOperand(const MachineOperand *MO, unsigned MONum);
246 void report(const char *msg, const MachineOperand *MO, unsigned MONum,
263 void checkLiveness(const MachineOperand *MO, unsigned MONum);
264 void checkLivenessAtUse(const MachineOperand *MO, unsigned MONum,
267 void checkLivenessAtDef(const MachineOperand *MO, unsigned MONum,
440 const MachineOperand &Op = MI.getOperand(I);
509 void MachineVerifier::report(const char *msg, const MachineOperand *MO,
673 SmallVector<MachineOperand, 4> Cond;
872 const MachineOperand &MO = MI->getOperand(OpNo);
888 const MachineOperand &MO = MI->getOperand(OpNo);
935 const MachineOperand *MO = &MI->getOperand(I);
959 const MachineOperand *MO = &MI->getOperand(I);
1280 const MachineOperand &SrcOp = MI->getOperand(1);
1286 const MachineOperand &OffsetOp = MI->getOperand(2);
1302 const MachineOperand &SrcOp = MI->getOperand(2);
1308 const MachineOperand &OffsetOp = MI->getOperand(3);
1340 const auto &IdxOp = MI->getOperand(2);
1349 const MachineOperand &IntrIDOp = MI->getOperand(MI->getNumExplicitDefs());
1405 const MachineOperand &MaskOp = MI->getOperand(3);
1455 const MachineOperand &DstOp = MI->getOperand(0);
1456 const MachineOperand &AllocOp = MI->getOperand(1);
1457 const MachineOperand &AlignOp = MI->getOperand(2);
1542 const MachineOperand &DstOp = MI->getOperand(0);
1543 const MachineOperand &SrcOp = MI->getOperand(1);
1593 MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) {
1630 const MachineOperand &MOTied = MI->getOperand(TiedTo);
1646 case MachineOperand::MO_Register: {
1656 const MachineOperand &OtherMO = MI->getOperand(OtherIdx);
1818 case MachineOperand::MO_RegisterMask:
1822 case MachineOperand::MO_MachineBasicBlock:
1827 case MachineOperand::MO_FrameIndex:
1873 void MachineVerifier::checkLivenessAtUse(const MachineOperand *MO,
1895 void MachineVerifier::checkLivenessAtDef(const MachineOperand *MO,
1939 void MachineVerifier::checkLiveness(const MachineOperand *MO, unsigned MONum) {
2021 for (const MachineOperand &MOP : MI->uses()) {
2111 MachineOperand::clobbersPhysReg(Mask, *I))
2214 const MachineOperand &MODef = Phi.getOperand(0);
2227 const MachineOperand &MO0 = Phi.getOperand(I);
2236 const MachineOperand &MO1 = Phi.getOperand(I + 1);
lib/CodeGen/ModuloSchedule.cpp 77 MachineOperand &Op = MI->getOperand(i);
87 MachineOperand &UseOp = *UI;
240 SmallVector<MachineOperand, 0> Cond;
256 SmallVector<MachineOperand, 4> Cond;
326 SmallVector<MachineOperand, 4> Cond1;
340 MachineOperand &O = *I;
624 MachineOperand &MO = BBI->getOperand(i);
867 SmallVector<MachineOperand, 4> Cond;
913 const MachineOperand *BaseOp;
985 const auto &MO = OldMI->getOperand(i);
1026 MachineOperand &MO = NewMI->getOperand(i);
1146 MachineOperand &UseOp = *UI;
1319 for (MachineOperand &MO : MI.uses()) {
1339 for (MachineOperand &Def : MI->defs()) {
1520 MachineOperand *Source;
1521 MachineOperand *Target;
1524 KernelOperandInfo(MachineOperand *MO, MachineRegisterInfo &MRI,
1561 bool isRegInLoop(MachineOperand *MO) {
1643 MI.addOperand(MachineOperand::CreateReg(Reg, /*isDef=*/false));
1644 MI.addOperand(MachineOperand::CreateMBB(*PI));
1700 SmallVector<MachineOperand, 4> Cond;
1742 for (MachineOperand &DefMO : MI->defs()) {
1774 SmallVector<MachineOperand, 4> Cond;
lib/CodeGen/PHIElimination.cpp 233 const MachineOperand &MO = MPhi.getOperand(I);
lib/CodeGen/PatchableFunction.cpp 77 for (auto &MO : FirstActualI->operands())
lib/CodeGen/PeepholeOptimizer.cpp 493 SmallVector<MachineOperand*, 8> Uses;
496 SmallVector<MachineOperand*, 8> ExtendedUses;
499 for (MachineOperand &UseMO : MRI->use_nodbg_operands(SrcReg)) {
572 MachineOperand *UseMO = Uses[i];
631 SmallVector<MachineOperand, 4> Cond;
844 const MachineOperand &MOSrc = CopyLike.getOperand(1);
847 const MachineOperand &MODef = CopyLike.getOperand(0);
855 MachineOperand &MOSrc = CopyLike.getOperand(CurrentSrcIdx);
890 const MachineOperand &MODef = CopyLike.getOperand(CurrentSrcIdx);
927 const MachineOperand &MOInsertedReg = CopyLike.getOperand(2);
929 const MachineOperand &MODef = CopyLike.getOperand(0);
945 MachineOperand &MO = CopyLike.getOperand(CurrentSrcIdx);
974 const MachineOperand &MOExtractedReg = CopyLike.getOperand(1);
983 const MachineOperand &MODef = CopyLike.getOperand(0);
1050 const MachineOperand &MOInsertedReg = CopyLike.getOperand(CurrentSrcIdx);
1060 const MachineOperand &MODef = CopyLike.getOperand(0);
1072 MachineOperand &MO = CopyLike.getOperand(CurrentSrcIdx);
1149 const MachineOperand &MODef = NewPHI.getOperand(0);
1171 const MachineOperand &MODef = MI.getOperand(0);
1355 MachineOperand &MO = MI.getOperand(i);
1487 static bool isVirtualRegisterOperand(MachineOperand &MO) {
1520 MachineOperand &DefOp = MI.getOperand(0);
1567 MachineOperand &MO = PHI.getOperand(Idx);
1660 for (const MachineOperand &MO : MI->operands()) {
1678 if (MachineOperand::clobbersPhysReg(RegMask, Def)) {
1758 const MachineOperand &MOp = MI->getOperand(i);
1822 const MachineOperand &Src = Def->getOperand(1);
1838 const MachineOperand DefOp = Def->getOperand(DefIdx);
1847 const MachineOperand &MO = Def->getOperand(OpIdx);
1872 const MachineOperand &Src = Def->getOperand(SrcIdx);
1955 const MachineOperand &MODef = Def->getOperand(DefIdx);
2036 const MachineOperand &MO = Def->getOperand(i);
lib/CodeGen/ProcessImplicitDefs.cpp 68 for (const MachineOperand &MO : MI->operands())
81 for (MachineOperand &MO : MRI->use_nodbg_operands(Reg)) {
100 for (MachineOperand &MO : UserMI->operands()) {
lib/CodeGen/PrologEpilogInserter.cpp 1254 MachineOperand &Offset = MI.getOperand(i + 1);
lib/CodeGen/ReachingDefAnalysis.cpp 105 MachineOperand &MO = MI->getOperand(i);
lib/CodeGen/RegAllocFast.cpp 188 bool isLastUseOfLocalReg(const MachineOperand &MO) const;
196 void usePhysReg(MachineOperand &MO);
211 void allocVirtRegUndef(MachineOperand &MO);
217 bool setPhysReg(MachineInstr &MI, MachineOperand &MO, MCPhysReg PhysReg);
354 bool RegAllocFast::isLastUseOfLocalReg(const MachineOperand &MO) const {
370 MachineOperand &MO = LR.LastUse->getOperand(LR.LastOpNum);
453 void RegAllocFast::usePhysReg(MachineOperand &MO) {
751 void RegAllocFast::allocVirtRegUndef(MachineOperand &MO) {
816 MachineOperand &MO = MI.getOperand(OpNum);
855 bool RegAllocFast::setPhysReg(MachineInstr &MI, MachineOperand &MO,
890 for (const MachineOperand &MO : MI.operands()) {
905 for (const MachineOperand &MO : MI.operands()) {
920 MachineOperand &MO = MI.getOperand(I);
946 const MachineOperand &MO = MI.getOperand(I);
961 for (const MachineOperand &MO : MI.operands()) {
1039 MachineOperand &MO = MI.getOperand(i);
1095 MachineOperand &MO = MI.getOperand(I);
1123 for (MachineOperand &MO : MI.uses()) {
1139 for (const MachineOperand &MO : MI.operands()) {
1166 const MachineOperand &MO = MI.getOperand(I);
1179 const MachineOperand &MO = MI.getOperand(I);
1211 MachineOperand &MO = MI.getOperand(0);
lib/CodeGen/RegAllocGreedy.cpp 2513 for (const MachineOperand &MO : MRI->def_operands(reg))
lib/CodeGen/RegUsageInfoCollector.cpp 128 unsigned RegMaskSize = MachineOperand::getRegMaskSize(TRI->getNumRegs());
lib/CodeGen/RegUsageInfoPropagate.cpp 70 for (MachineOperand &MO : MI.operands()) {
90 for (const MachineOperand &MO : MI.operands()) {
lib/CodeGen/RegisterCoalescer.cpp 282 MachineOperand &MO, unsigned SubRegIdx);
804 MachineOperand &NewDstMO = DefMI->getOperand(NewDstIdx);
816 for (MachineOperand &MO : MRI->use_nodbg_operands(IntA.reg)) {
862 MachineOperand &UseMO = *UI;
1193 for (const MachineOperand &Op : MI.operands()) {
1242 MachineOperand &DstOperand = CopyMI->getOperand(0);
1292 MachineOperand &DefMO = NewMI.getOperand(0);
1310 SmallVector<MachineOperand, 4> ImplicitOps;
1316 MachineOperand &MO = CopyMI->getOperand(I);
1336 MachineOperand &MO = NewMI.getOperand(i);
1434 NewMI.addOperand(MachineOperand::CreateReg(
1463 for (MachineOperand &MO : ImplicitOps)
1480 for (MachineOperand &UseMO : MRI->use_operands(SrcReg)) {
1499 for (MachineOperand &UseMO : MRI->use_nodbg_operands(SrcReg)) {
1554 MachineOperand &MO = CopyMI->getOperand(i-1);
1587 for (MachineOperand &MO : MRI->reg_nodbg_operands(DstReg)) {
1617 for (MachineOperand &MO : CopyMI->operands())
1626 MachineOperand &MO, unsigned SubRegIdx) {
1658 for (MachineOperand &MO : MRI->reg_operands(DstReg)) {
1695 MachineOperand &MO = UseMI->getOperand(Ops[i]);
2393 for (const MachineOperand &MO : DefMI->operands()) {
2827 for (const MachineOperand &MO : MI.operands()) {
2942 for (MachineOperand &MO :
lib/CodeGen/RegisterPressure.cpp 499 void collectOperand(const MachineOperand &MO) const {
530 void collectOperandLanes(const MachineOperand &MO) const {
1227 for (const MachineOperand &MO : MRI.use_nodbg_operands(Reg)) {
lib/CodeGen/RegisterScavenging.cpp 119 for (const MachineOperand &MO : MI.operands()) {
204 for (const MachineOperand &MO : MI.operands()) {
327 for (const MachineOperand &MO : MI->operands()) {
432 for (const MachineOperand &MO : MI.operands()) {
543 for (const MachineOperand &MO : MI.operands()) {
631 for (MachineOperand &MO : MRI.reg_nodbg_operands(VReg)) {
694 for (const MachineOperand &MO : NMI.operands()) {
716 for (const MachineOperand &MO : MI.operands()) {
739 for (const MachineOperand &MO : MBB.front().operands()) {
lib/CodeGen/RegisterUsageInfo.cpp 96 if (MachineOperand::clobbersPhysReg(&(FPRMPair->second[0]), PReg))
lib/CodeGen/RenameIndependentSubregs.cpp 178 for (const MachineOperand &MO : MRI->reg_nodbg_operands(Reg)) {
217 MachineOperand &MO = *I++;
344 for (MachineOperand &MO : MRI->reg_nodbg_operands(Reg)) {
lib/CodeGen/ScheduleDAGInstrs.cpp 205 for (const MachineOperand &MO : ExitMI->operands()) {
230 const MachineOperand &MO = SU->getInstr()->getOperand(OperIdx);
286 MachineOperand &MO = MI->getOperand(OperIdx);
361 LaneBitmask ScheduleDAGInstrs::getLaneMaskForMO(const MachineOperand &MO) const
375 bool ScheduleDAGInstrs::deadDefHasNoUse(const MachineOperand &MO) {
390 MachineOperand &MO = MI->getOperand(OperIdx);
408 const MachineOperand &OtherMO = MI->getOperand(I);
510 const MachineOperand &MO = MI->getOperand(OperIdx);
838 const MachineOperand &MO = MI.getOperand(j);
851 const MachineOperand &MO = MI.getOperand(j);
1088 for (MachineOperand &MO : MI.operands()) {
1118 const MachineOperand &MO = *O;
lib/CodeGen/SelectionDAG/FastISel.cpp 170 for (const MachineOperand &MO : MI.operands()) {
760 bool FastISel::addStackMapLiveVars(SmallVectorImpl<MachineOperand> &Ops,
766 Ops.push_back(MachineOperand::CreateImm(StackMaps::ConstantOp));
767 Ops.push_back(MachineOperand::CreateImm(C->getSExtValue()));
769 Ops.push_back(MachineOperand::CreateImm(StackMaps::ConstantOp));
770 Ops.push_back(MachineOperand::CreateImm(0));
777 Ops.push_back(MachineOperand::CreateFI(SI->second));
784 Ops.push_back(MachineOperand::CreateReg(Reg, /*isDef=*/false));
806 SmallVector<MachineOperand, 32> Ops;
812 Ops.push_back(MachineOperand::CreateImm(ID->getZExtValue()));
818 Ops.push_back(MachineOperand::CreateImm(NumBytes->getZExtValue()));
832 Ops.push_back(MachineOperand::CreateReg(
847 for (auto const &MO : Ops)
937 SmallVector<MachineOperand, 32> Ops;
944 Ops.push_back(MachineOperand::CreateReg(CLI.ResultReg, /*isDef=*/true));
951 Ops.push_back(MachineOperand::CreateImm(ID->getZExtValue()));
957 Ops.push_back(MachineOperand::CreateImm(NumBytes->getZExtValue()));
963 Ops.push_back(MachineOperand::CreateImm(CalleeConstAddr));
968 Ops.push_back(MachineOperand::CreateImm(CalleeConstAddr));
972 Ops.push_back(MachineOperand::CreateGA(GV, 0));
974 Ops.push_back(MachineOperand::CreateImm(0));
981 Ops.push_back(MachineOperand::CreateImm(NumCallRegArgs));
984 Ops.push_back(MachineOperand::CreateImm((unsigned)CC));
993 Ops.push_back(MachineOperand::CreateReg(Reg, /*isDef=*/false));
999 Ops.push_back(MachineOperand::CreateReg(Reg, /*isDef=*/false));
1006 Ops.push_back(MachineOperand::CreateRegMask(
1012 Ops.push_back(MachineOperand::CreateReg(
1018 Ops.push_back(MachineOperand::CreateReg(Reg, /*isDef=*/true,
1025 for (auto &MO : Ops)
1045 SmallVector<MachineOperand, 8> Ops;
1046 Ops.push_back(MachineOperand::CreateReg(getRegForValue(I->getArgOperand(0)),
1048 Ops.push_back(MachineOperand::CreateReg(getRegForValue(I->getArgOperand(1)),
1053 for (auto &MO : Ops)
1064 SmallVector<MachineOperand, 8> Ops;
1065 Ops.push_back(MachineOperand::CreateReg(getRegForValue(I->getArgOperand(0)),
1067 Ops.push_back(MachineOperand::CreateReg(getRegForValue(I->getArgOperand(1)),
1069 Ops.push_back(MachineOperand::CreateReg(getRegForValue(I->getArgOperand(2)),
1074 for (auto &MO : Ops)
1366 Optional<MachineOperand> Op;
1368 Op = MachineOperand::CreateReg(Reg, false);
1384 Op = MachineOperand::CreateReg(FuncInfo.InitializeRegForValue(Address),
lib/CodeGen/SelectionDAG/InstrEmitter.cpp 1138 MachineOperand *MO =
lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp 1327 if (!MachineOperand::clobbersPhysReg(RegMask, i)) continue;
2854 MachineOperand::clobbersPhysReg(RegMask, SuccPred.getReg()) &&
2896 if (SURegMask && MachineOperand::clobbersPhysReg(SURegMask, Reg))
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp 5497 Optional<MachineOperand> Op;
5501 Op = MachineOperand::CreateFI(FI);
5517 Op = MachineOperand::CreateReg(Reg, false);
5528 Op = MachineOperand::CreateFI(FINode->getIndex());
5561 Op = MachineOperand::CreateReg(VMI->second, false);
lib/CodeGen/SelectionDAG/TargetLowering.cpp 84 if (MachineOperand::clobbersPhysReg(CallerPreservedMask, Reg))
lib/CodeGen/ShrinkWrap.cpp 275 for (const MachineOperand &MO : MI.operands()) {
lib/CodeGen/SplitKit.cpp 176 for (MachineOperand &MO : MRI.use_nodbg_operands(CurLI->reg))
439 for (const MachineOperand &DefOp : DefMI->defs()) {
1305 ExtPoint(const MachineOperand &O, unsigned R, SlotIndex N)
1308 MachineOperand MO;
1317 MachineOperand &MO = *RI;
lib/CodeGen/StackColoring.cpp 571 const MachineOperand &MO = MI.getOperand(0);
604 for (const MachineOperand &MO : MI.operands()) {
680 for (const MachineOperand &MO : MI.operands()) {
985 for (MachineOperand &MO : I.operands()) {
1094 for (const MachineOperand &MO : I.operands()) {
lib/CodeGen/StackMapLivenessAnalysis.cpp 154 MachineOperand MO = MachineOperand::CreateRegLiveOut(Mask);
154 MachineOperand MO = MachineOperand::CreateRegLiveOut(Mask);
lib/CodeGen/StackSlotColoring.cpp 166 MachineOperand &MO = MI.getOperand(i);
400 MachineOperand &MO = MI.getOperand(i);
lib/CodeGen/TailDuplicator.cpp 211 MachineOperand &UseMO = *UI;
384 MachineOperand &MO = NewMI.getOperand(i);
471 MachineOperand &MO = MI.getOperand(i + 1);
479 MachineOperand &MO0 = MI.getOperand(Idx);
486 MachineOperand &MO = MI.getOperand(i + 1);
572 SmallVector<MachineOperand, 4> PredCond;
643 MachineOperand &PU = I.getOperand(Idx);
688 SmallVector<MachineOperand, 4> PredCond;
715 SmallVector<MachineOperand, 4> PredCond;
779 SmallVector<MachineOperand, 4> PredCond;
879 SmallVector<MachineOperand, 4> PriorCond;
lib/CodeGen/TargetInstrInfo.cpp 321 MachineInstr &MI, ArrayRef<MachineOperand> Pred) const {
333 MachineOperand &MO = MI.getOperand(i);
440 const MachineOperand &FoldOp = MI.getOperand(FoldIdx);
441 const MachineOperand &LiveOp = MI.getOperand(1 - FoldIdx);
509 MachineOperand &MO = MI.getOperand(i);
609 const MachineOperand &MO = MI.getOperand(1 - Ops[0]);
669 const MachineOperand &Op1 = Inst.getOperand(1);
670 const MachineOperand &Op2 = Inst.getOperand(2);
802 MachineOperand &OpA = Prev.getOperand(OpIdx[Row][0]);
803 MachineOperand &OpB = Root.getOperand(OpIdx[Row][1]);
804 MachineOperand &OpX = Prev.getOperand(OpIdx[Row][2]);
805 MachineOperand &OpY = Root.getOperand(OpIdx[Row][3]);
806 MachineOperand &OpC = Root.getOperand(0);
925 const MachineOperand &MO = MI.getOperand(i);
1126 const MachineOperand *Op = nullptr;
1128 const MachineOperand *SrcRegOp, *DestRegOp;
1180 const MachineOperand &MOReg = MI.getOperand(OpIdx);
1183 const MachineOperand &MOSubIdx = MI.getOperand(OpIdx + 1);
1205 const MachineOperand &MOReg = MI.getOperand(1);
1208 const MachineOperand &MOSubIdx = MI.getOperand(2);
1230 const MachineOperand &MOBaseReg = MI.getOperand(1);
1231 const MachineOperand &MOInsertedReg = MI.getOperand(2);
1234 const MachineOperand &MOSubIdx = MI.getOperand(3);
lib/CodeGen/TargetLoweringBase.cpp 1039 MachineOperand &MO = MI->getOperand(OperIdx);
lib/CodeGen/TargetSchedule.cpp 160 const MachineOperand &MO = MI->getOperand(i);
176 const MachineOperand &MO = MI->getOperand(i);
lib/CodeGen/TwoAddressInstructionPass.cpp 230 for (const MachineOperand &MO : MI->operands()) {
265 for (MachineOperand &UseMO : MRI->use_nodbg_operands(SavedReg)) {
286 MachineOperand *KillMO = nullptr;
299 MachineOperand &MO = OtherMI.getOperand(i);
388 for (MachineOperand &MO : MRI->reg_operands(Reg)) {
504 const MachineOperand &MO = MI.getOperand(i);
910 for (const MachineOperand &MO : MI->operands()) {
954 for (const MachineOperand &MO : OtherMI.operands()) {
1092 for (const MachineOperand &MO : KillMI->operands()) {
1129 for (const MachineOperand &MO : OtherMI.operands()) {
1399 MachineOperand &MO = MI.getOperand(i);
1427 for (const MachineOperand &MO : MI.operands()) {
1472 MachineOperand &SrcMO = MI->getOperand(SrcIdx);
1473 MachineOperand &DstMO = MI->getOperand(DstIdx);
1507 const MachineOperand &DstMO = MI->getOperand(TiedPairs[tpi].second);
1521 const MachineOperand &DstMO = MI->getOperand(DstIdx);
1591 MachineOperand &MO = MI->getOperand(SrcIdx);
1616 for (MachineOperand &MO : MI->operands()) {
1656 for (MachineOperand &MO : MI->operands()) {
1817 MachineOperand &UseMO = MI.getOperand(i);
lib/CodeGen/UnreachableBlockElim.cpp 175 const MachineOperand &Input = phi->getOperand(1);
176 const MachineOperand &Output = phi->getOperand(0);
lib/CodeGen/VirtRegMap.cpp 186 bool readsUndefSubreg(const MachineOperand &MO) const;
350 bool VirtRegRewriter::readsUndefSubreg(const MachineOperand &MO) const {
509 MachineOperand &MO = *MOI;
lib/CodeGen/XRayInstrumentation.cpp 110 for (auto &MO : T.operands())
lib/Target/AArch64/AArch64A53Fix835769.cpp 140 SmallVector<MachineOperand, 2> Cond;
lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp 145 void maybeKillChain(MachineOperand &MO, unsigned Idx,
553 for (auto &U : I.operands()) {
574 MachineOperand &MO = I.getOperand(0);
607 for (auto &I : MI->uses())
609 for (auto &I : MI->defs())
672 for (auto &I : MI->uses())
674 for (auto &I : MI->defs())
681 maybeKillChain(MachineOperand &MO, unsigned Idx,
lib/Target/AArch64/AArch64AdvSIMDScalarPass.cpp 127 static MachineOperand *getSrcFromCopy(MachineInstr *MI,
212 MachineOperand *MOSrc0 = getSrcFromCopy(&*Def, MRI, SubReg0);
225 MachineOperand *MOSrc1 = getSrcFromCopy(&*Def, MRI, SubReg1);
305 MachineOperand *MOSrc0 = getSrcFromCopy(&*Def, MRI, SubReg0);
324 MachineOperand *MOSrc1 = getSrcFromCopy(&*Def, MRI, SubReg1);
lib/Target/AArch64/AArch64AsmPrinter.cpp 83 bool lowerOperand(const MachineOperand &MO, MCOperand &MCOp) const {
152 bool printAsmMRegister(const MachineOperand &MO, char Mode, raw_ostream &O);
153 bool printAsmRegInClass(const MachineOperand &MO,
500 const MachineOperand &MO = MI->getOperand(OpNum);
504 case MachineOperand::MO_Register: {
511 case MachineOperand::MO_Immediate: {
515 case MachineOperand::MO_GlobalAddress: {
519 case MachineOperand::MO_BlockAddress: {
527 bool AArch64AsmPrinter::printAsmMRegister(const MachineOperand &MO, char Mode,
548 bool AArch64AsmPrinter::printAsmRegInClass(const MachineOperand &MO,
562 const MachineOperand &MO = MI->getOperand(OpNum);
660 const MachineOperand &MO = MI->getOperand(OpNum);
927 const MachineOperand &MO_Sym = MI->getOperand(1);
928 MachineOperand Hi_MOSym(MO_Sym), Lo_MOSym(MO_Sym);
1019 const MachineOperand &MO_Sym = MI->getOperand(0);
1020 MachineOperand MO_TLSDESC_LO12(MO_Sym), MO_TLSDESC(MO_Sym);
lib/Target/AArch64/AArch64CallLowering.cpp 621 if (MachineOperand::clobbersPhysReg(CallerPreservedMask, Reg))
lib/Target/AArch64/AArch64CollectLOH.cpp 165 case MachineOperand::MO_GlobalAddress:
166 case MachineOperand::MO_JumpTableIndex:
167 case MachineOperand::MO_ConstantPoolIndex:
168 case MachineOperand::MO_BlockAddress:
190 case MachineOperand::MO_GlobalAddress:
198 static bool isCandidateStore(const MachineInstr &MI, const MachineOperand &MO) {
291 static void handleUse(const MachineInstr &MI, const MachineOperand &MO,
456 if (!MachineOperand::clobbersPhysReg(RegMask, Reg))
465 for (const MachineOperand &MO : MI.operands()) {
484 for (const MachineOperand &MO : MI.uses()) {
532 const MachineOperand &Def = MI.getOperand(0);
533 const MachineOperand &Op = MI.getOperand(1);
544 const MachineOperand &Op0 = MI.getOperand(0);
lib/Target/AArch64/AArch64CondBrTuning.cpp 63 MachineInstr *getOperandDef(const MachineOperand &MO);
80 MachineInstr *AArch64CondBrTuning::getOperandDef(const MachineOperand &MO) {
93 MachineOperand &MO = MI.getOperand(I);
lib/Target/AArch64/AArch64ConditionOptimizer.cpp 304 static bool parseCond(ArrayRef<MachineOperand> Cond, AArch64CC::CondCode &CC) {
348 SmallVector<MachineOperand, 4> HeadCond;
359 SmallVector<MachineOperand, 4> TrueCond;
lib/Target/AArch64/AArch64ConditionalCompares.cpp 160 SmallVector<MachineOperand, 4> HeadCond;
166 SmallVector<MachineOperand, 4> CmpBBCond;
272 static bool parseCond(ArrayRef<MachineOperand> Cond, AArch64CC::CondCode &CC) {
lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp 65 for (const MachineOperand &MO : MI.uses())
143 MachineOperand &MO = MI.getOperand(I);
lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp 97 const MachineOperand &MO = OldMI.getOperand(i);
176 const MachineOperand &Dest = MI.getOperand(0);
255 MachineOperand &DestLo = MI.getOperand(0);
256 MachineOperand &DestHi = MI.getOperand(1);
479 const MachineOperand &MO1 = MI.getOperand(1);
564 auto Tag = MI.getOperand(1);
lib/Target/AArch64/AArch64FalkorHWPFFix.cpp 218 const MachineOperand *OffsetOpnd = nullptr;
745 MachineOperand &MO = MI.getOperand(OpI);
774 MachineOperand &BaseOpnd = MI.getOperand(LdI.BaseRegIdx);
lib/Target/AArch64/AArch64FastISel.cpp 2069 for (auto &Opnd : MI->uses()) {
lib/Target/AArch64/AArch64FrameLowering.cpp 195 for (const MachineOperand &MO : MI.operands()) {
605 MachineOperand *ImmOpnd = nullptr;
769 MachineOperand &OffsetOpnd = MI.getOperand(OffsetIdx);
1359 MachineOperand &StackAdjust = MBBI->getOperand(1);
1426 const MachineOperand &OffsetOp = Pop->getOperand(Pop->getNumOperands() - 1);
lib/Target/AArch64/AArch64InstrInfo.cpp 127 SmallVectorImpl<MachineOperand> &Cond) {
141 Cond.push_back(MachineOperand::CreateImm(-1));
142 Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
150 Cond.push_back(MachineOperand::CreateImm(-1));
151 Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
211 SmallVectorImpl<MachineOperand> &Cond,
296 SmallVectorImpl<MachineOperand> &Cond) const {
373 ArrayRef<MachineOperand> Cond) const {
390 ArrayRef<MachineOperand> Cond, const DebugLoc &DL, int *BytesAdded) const {
497 ArrayRef<MachineOperand> Cond,
934 const MachineOperand *BaseOpA = nullptr, *BaseOpB = nullptr;
1058 MachineOperand &MO = Instr.getOperand(OpIdx);
1981 const MachineOperand *&BaseOp,
1989 const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset,
2035 MachineOperand &
2038 MachineOperand &OfsOp = LdSt.getOperand(LdSt.getNumExplicitOperands() - 1);
2326 bool AArch64InstrInfo::shouldClusterMemOps(const MachineOperand &BaseOp1,
2327 const MachineOperand &BaseOp2,
3239 const MachineOperand &DstMO = MI.getOperand(0);
3240 const MachineOperand &SrcMO = MI.getOperand(1);
3342 MachineOperand &LoadDst = LoadMI.getOperand(0);
3414 const MachineOperand &ImmOpnd =
3594 static bool canCombine(MachineBasicBlock &MBB, MachineOperand &MO,
3623 static bool canCombineWithMUL(MachineBasicBlock &MBB, MachineOperand &MO,
3630 static bool canCombineWithFMUL(MachineBasicBlock &MBB, MachineOperand &MO,
4821 MachineOperand &MO = DefMI->getOperand(1);
5134 const MachineOperand *Base; // Filled with the base operand of MI.
5404 for (const MachineOperand &MOP : MI.operands()) {
5438 for (const MachineOperand &MOP : MI.operands()) {
5504 const MachineOperand *Base;
5518 MachineOperand &StackOffsetOperand = getMemOpBaseRegImmOfsOffsetOperand(MI);
5706 const MachineInstr &MI, const MachineOperand *&Source,
5707 const MachineOperand *&Destination) const {
lib/Target/AArch64/AArch64InstrInfo.h 110 const MachineOperand *&BaseOp,
115 const MachineOperand *&BaseOp,
120 MachineOperand &getMemOpBaseRegImmOfsOffsetOperand(MachineInstr &LdSt) const;
129 bool shouldClusterMemOps(const MachineOperand &BaseOp1,
130 const MachineOperand &BaseOp2,
177 SmallVectorImpl<MachineOperand> &Cond,
182 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
186 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
187 bool canInsertSelect(const MachineBasicBlock &, ArrayRef<MachineOperand> Cond,
275 bool isCopyInstrImpl(const MachineInstr &MI, const MachineOperand *&Source,
276 const MachineOperand *&Destination) const override;
287 ArrayRef<MachineOperand> Cond) const;
lib/Target/AArch64/AArch64InstructionSelector.cpp 141 MachineInstr *emitIntegerCompare(MachineOperand &LHS, MachineOperand &RHS,
141 MachineInstr *emitIntegerCompare(MachineOperand &LHS, MachineOperand &RHS,
142 MachineOperand &Predicate,
144 MachineInstr *emitADD(Register DefReg, MachineOperand &LHS, MachineOperand &RHS,
144 MachineInstr *emitADD(Register DefReg, MachineOperand &LHS, MachineOperand &RHS,
146 MachineInstr *emitCMN(MachineOperand &LHS, MachineOperand &RHS,
146 MachineInstr *emitCMN(MachineOperand &LHS, MachineOperand &RHS,
250 MachineInstr *tryFoldIntegerCompare(MachineOperand &LHS, MachineOperand &RHS,
250 MachineInstr *tryFoldIntegerCompare(MachineOperand &LHS, MachineOperand &RHS,
251 MachineOperand &Predicate,
601 MachineOperand &RegOp = I.getOperand(1);
730 MachineOperand &RegOp = I.getOperand(1);
1126 MovZ->addOperand(MF, MachineOperand::CreateImm(0));
1136 MovI->addOperand(MF, MachineOperand::CreateGA(
1140 MF, MachineOperand::CreateBA(cast<BlockAddress>(V),
1143 MovI->addOperand(MF, MachineOperand::CreateImm(Offset));
1204 const auto &MO = I.getOperand(2);
1553 MachineOperand &RegOp = I.getOperand(0);
1563 MachineOperand &ImmOp = I.getOperand(1);
1683 I.addOperand(MachineOperand::CreateImm(0));
1684 I.addOperand(MachineOperand::CreateImm(0));
1787 I.addOperand(MachineOperand::CreateImm(Offset));
2878 MachineOperand &LaneIdxOp = I.getOperand(2);
3145 AArch64InstructionSelector::emitADD(Register DefReg, MachineOperand &LHS,
3146 MachineOperand &RHS,
3170 AArch64InstructionSelector::emitCMN(MachineOperand &LHS, MachineOperand &RHS,
3170 AArch64InstructionSelector::emitCMN(MachineOperand &LHS, MachineOperand &RHS,
3224 MachineOperand &LHS, MachineOperand &RHS, MachineOperand &Predicate,
3224 MachineOperand &LHS, MachineOperand &RHS, MachineOperand &Predicate,
3224 MachineOperand &LHS, MachineOperand &RHS, MachineOperand &Predicate,
3335 MachineOperand &ImmOp = I.getOperand(1);
3476 MachineOperand &LHS, MachineOperand &RHS, MachineOperand &Predicate,
3476 MachineOperand &LHS, MachineOperand &RHS, MachineOperand &Predicate,
3476 MachineOperand &LHS, MachineOperand &RHS, MachineOperand &Predicate,
3910 MachineOperand &RegOp = I.getOperand(1);
4014 static Optional<uint64_t> getImmedFromMO(const MachineOperand &Root) {
4354 MachineOperand &OffImm = RootDef->getOperand(2);
4361 MachineOperand &RHSOp1 = RHS->getOperand(1);
4370 MachineOperand &Base = RootDef->getOperand(1);
4403 MachineOperand &LHS = RootDef->getOperand(1);
4404 MachineOperand &RHS = RootDef->getOperand(2);
4477 MachineOperand &ShiftRHS = ShiftInst->getOperand(2);
4484 MachineOperand &ShiftLHS = ShiftInst->getOperand(1);
4590 MachineOperand &RHS = RootDef->getOperand(2);
4598 MachineOperand &LHS = RootDef->getOperand(1);
lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp 602 static const MachineOperand &getLdStRegOp(const MachineInstr &MI,
609 static const MachineOperand &getLdStBaseOp(const MachineInstr &MI) {
614 static const MachineOperand &getLdStOffsetOp(const MachineInstr &MI) {
742 const MachineOperand &BaseRegOp =
811 const MachineOperand &BaseRegOp =
859 MachineOperand RegOp0 = getLdStRegOp(*RtMI);
860 MachineOperand RegOp1 = getLdStRegOp(*Rt2MI);
901 MachineOperand &DstMO = MIB->getOperand(SExtIdx);
950 const MachineOperand &StMO = getLdStRegOp(*StoreI);
lib/Target/AArch64/AArch64MCInstLower.cpp 37 AArch64MCInstLower::GetGlobalAddressSymbol(const MachineOperand &MO) const {
75 AArch64MCInstLower::GetExternalSymbolSymbol(const MachineOperand &MO) const {
79 MCOperand AArch64MCInstLower::lowerSymbolOperandDarwin(const MachineOperand &MO,
114 MCOperand AArch64MCInstLower::lowerSymbolOperandELF(const MachineOperand &MO,
191 MCOperand AArch64MCInstLower::lowerSymbolOperandCOFF(const MachineOperand &MO,
241 MCOperand AArch64MCInstLower::LowerSymbolOperand(const MachineOperand &MO,
252 bool AArch64MCInstLower::lowerOperand(const MachineOperand &MO,
257 case MachineOperand::MO_Register:
263 case MachineOperand::MO_RegisterMask:
266 case MachineOperand::MO_Immediate:
269 case MachineOperand::MO_MachineBasicBlock:
273 case MachineOperand::MO_GlobalAddress:
276 case MachineOperand::MO_ExternalSymbol:
279 case MachineOperand::MO_MCSymbol:
282 case MachineOperand::MO_JumpTableIndex:
285 case MachineOperand::MO_ConstantPoolIndex:
288 case MachineOperand::MO_BlockAddress:
299 for (const MachineOperand &MO : MI->operands()) {
lib/Target/AArch64/AArch64MCInstLower.h 37 bool lowerOperand(const MachineOperand &MO, MCOperand &MCOp) const;
40 MCOperand lowerSymbolOperandDarwin(const MachineOperand &MO,
42 MCOperand lowerSymbolOperandELF(const MachineOperand &MO,
44 MCOperand lowerSymbolOperandCOFF(const MachineOperand &MO,
46 MCOperand LowerSymbolOperand(const MachineOperand &MO, MCSymbol *Sym) const;
48 MCSymbol *GetGlobalAddressSymbol(const MachineOperand &MO) const;
49 MCSymbol *GetExternalSymbolSymbol(const MachineOperand &MO) const;
lib/Target/AArch64/AArch64RegisterInfo.cpp 154 unsigned RegMaskSize = MachineOperand::getRegMaskSize(getNumRegs());
478 MachineOperand &FI = MI.getOperand(FIOperandNum);
lib/Target/AArch64/AArch64SpeculationHardening.cpp 189 SmallVector<MachineOperand, 1> analyzeBranchCondCode;
498 for (MachineOperand Op : MI.defs())
509 for (auto Def : MI.defs()) {
522 for (auto Use : MI.uses()) {
570 for (MachineOperand Op : MI.defs())
631 for (MachineOperand Op : MI.uses())
lib/Target/AArch64/AArch64StorePairSuppress.cpp 150 const MachineOperand *BaseOp;
lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp 594 for (const MachineOperand &UseOp : MRI.reg_operands(Reg)) {
699 for (const MachineOperand &MO : MI.operands()) {
857 const MachineOperand *CalleeOp
1295 const MachineOperand &MO = MI->getOperand(OpNo);
lib/Target/AMDGPU/AMDGPUAsmPrinter.h 111 bool lowerOperand(const MachineOperand &MO, MCOperand &MCOp) const;
lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp 117 const MachineOperand &Src = I.getOperand(1);
118 MachineOperand &Dst = I.getOperand(0);
167 for (const MachineOperand &MO : I.operands()) {
214 MachineOperand
215 AMDGPUInstructionSelector::getSubOperand64(MachineOperand &MO,
229 return MachineOperand::CreateReg(DstReg, MO.isDef(), MO.isImplicit(),
243 return MachineOperand::CreateImm(Imm.getLoBits(32).getSExtValue());
245 return MachineOperand::CreateImm(Imm.getHiBits(32).getSExtValue());
263 MachineOperand &Dst = I.getOperand(0);
264 MachineOperand &Src0 = I.getOperand(1);
265 MachineOperand &Src1 = I.getOperand(2);
323 I.addOperand(*MF, MachineOperand::CreateImm(0));
324 I.addOperand(*MF, MachineOperand::CreateReg(AMDGPU::EXEC, false, true));
348 MachineOperand Lo1(getSubOperand64(I.getOperand(1), HalfRC, AMDGPU::sub0));
349 MachineOperand Lo2(getSubOperand64(I.getOperand(2), HalfRC, AMDGPU::sub0));
350 MachineOperand Hi1(getSubOperand64(I.getOperand(1), HalfRC, AMDGPU::sub1));
351 MachineOperand Hi2(getSubOperand64(I.getOperand(2), HalfRC, AMDGPU::sub1));
411 I.addOperand(*MF, MachineOperand::CreateReg(AMDGPU::EXEC, false, true));
412 I.addOperand(*MF, MachineOperand::CreateImm(0));
449 for (const MachineOperand &MO : Copy->operands()) {
482 MachineOperand &Src = MI.getOperand(I + 1);
503 MachineOperand &Src = MI.getOperand(NumDst);
527 MachineOperand &Dst = MI.getOperand(I);
546 const MachineOperand &MO = I.getOperand(0);
809 const MachineOperand &Op = Def->getOperand(1);
1099 const MachineOperand &CCOp = I.getOperand(1);
1400 MachineOperand &ImmOp = I.getOperand(1);
1487 const MachineOperand &GEPOp = PtrMI->getOperand(i);
1558 MachineOperand &CondOp = I.getOperand(0);
1606 I.addOperand(*MF, MachineOperand::CreateReg(AMDGPU::EXEC, false, true));
2045 const MachineOperand &LHS = RootDef->getOperand(1);
2046 const MachineOperand &RHS = RootDef->getOperand(2);
2092 const MachineOperand &Base,
2147 const MachineOperand &LHS = RootDef->getOperand(1);
2148 const MachineOperand &RHS = RootDef->getOperand(2);
lib/Target/AMDGPU/AMDGPUInstructionSelector.h 75 MachineOperand getSubOperand64(MachineOperand &MO,
75 MachineOperand getSubOperand64(MachineOperand &MO,
161 const MachineOperand &Base,
lib/Target/AMDGPU/AMDGPUMCInstLower.cpp 47 const MachineOperand &MO) const;
53 bool lowerOperand(const MachineOperand &MO, MCOperand &MCOp) const;
102 const MachineOperand &MO) const {
126 bool AMDGPUMCInstLower::lowerOperand(const MachineOperand &MO,
131 case MachineOperand::MO_Immediate:
134 case MachineOperand::MO_Register:
137 case MachineOperand::MO_MachineBasicBlock: {
148 case MachineOperand::MO_GlobalAddress: {
163 case MachineOperand::MO_ExternalSymbol: {
170 case MachineOperand::MO_RegisterMask:
209 for (const MachineOperand &MO : MI->explicit_operands()) {
220 bool AMDGPUAsmPrinter::lowerOperand(const MachineOperand &MO,
377 for (const MachineOperand &MO : MI->explicit_operands()) {
lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp 707 for (auto &UI : MRI->use_operands(Reg)) {
740 for (auto &UI : MRI->use_operands(Reg)) {
757 for (auto &RI : II.defs()) {
760 for (auto &IRI : II.implicit_operands()) {
799 for (auto &RI : II.defs()) {
803 for (auto &IRI : II.implicit_operands()) {
937 MachineOperand &O = *I;
1024 for (auto &RI : II.uses()) {
1046 MachineOperand *Def = &(*(MRI->def_begin(Reg)));
1047 MachineOperand *UseOperand = &(RI);
1182 void ensureCondIsNotKilled(SmallVector<MachineOperand, 1> Cond);
1284 for (auto &UI : TI.uses()) {
1316 for (auto &UI : TI.uses()) {
1881 MachineOperand RegOp = MachineOperand::CreateReg(Reg, false, false, true);
1881 MachineOperand RegOp = MachineOperand::CreateReg(Reg, false, false, true);
1882 ArrayRef<MachineOperand> Cond(RegOp);
1889 SmallVector<MachineOperand, 1> Cond) {
1906 SmallVector<MachineOperand, 1> Cond;
2108 MachineOperand *Def = &(*(MRI->def_begin(SourceReg)));
2121 MachineOperand *Def = &(*(MRI->def_begin(SourceReg)));
2233 MachineOperand &O = *I;
2329 SmallVector<MachineOperand, 1> ECond;
2340 MachineOperand RegOp =
2341 MachineOperand::CreateReg(Reg, false, false, true);
2342 ArrayRef<MachineOperand> Cond(RegOp);
2388 SmallVector<MachineOperand, 1> ECond;
2399 MachineOperand RegOp = MachineOperand::CreateReg(Reg, false, false, true);
2399 MachineOperand RegOp = MachineOperand::CreateReg(Reg, false, false, true);
2400 ArrayRef<MachineOperand> Cond(RegOp);
2558 for (auto &UI : Branch.uses()) {
lib/Target/AMDGPU/AMDGPUMacroFusion.cpp 47 const MachineOperand *Src2 = TII.getNamedOperand(SecondMI,
lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp 58 for (MachineOperand &Op : MI.operands()) {
686 for (MachineOperand &Def : MI.defs()) {
765 for (MachineOperand &Op : MI.uses()) {
1959 const MachineOperand &MO = MI.getOperand(OpdIdx);
1979 const MachineOperand &Op = MI.getOperand(I);
lib/Target/AMDGPU/GCNDPPCombine.cpp 72 MachineOperand *getOldOpndValue(MachineOperand &OldOpnd) const;
72 MachineOperand *getOldOpndValue(MachineOperand &OldOpnd) const;
77 MachineOperand *OldOpnd,
134 MachineOperand *GCNDPPCombine::getOldOpndValue(MachineOperand &OldOpnd) const {
134 MachineOperand *GCNDPPCombine::getOldOpndValue(MachineOperand &OldOpnd) const {
145 auto &Op1 = Def->getOperand(1);
171 auto *Dst = TII->getNamedOperand(OrigMI, AMDGPU::OpName::vdst);
192 if (auto *Mod0 = TII->getNamedOperand(OrigMI,
204 auto *Src0 = TII->getNamedOperand(MovMI, AMDGPU::OpName::src0);
215 if (auto *Mod1 = TII->getNamedOperand(OrigMI,
227 if (auto *Src1 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src1)) {
237 if (auto *Src2 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src2)) {
261 static bool isIdentityValue(unsigned OrigMIOp, MachineOperand *OldOpnd) {
316 MachineOperand *OldOpndValue,
320 auto *Src1 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src1);
342 auto *Imm = TII->getNamedOperand(MI, OpndName);
354 auto *DstOpnd = TII->getNamedOperand(MovMI, AMDGPU::OpName::vdst);
367 auto *RowMaskOpnd = TII->getNamedOperand(MovMI, AMDGPU::OpName::row_mask);
369 auto *BankMaskOpnd = TII->getNamedOperand(MovMI, AMDGPU::OpName::bank_mask);
374 auto *BCZOpnd = TII->getNamedOperand(MovMI, AMDGPU::OpName::bound_ctrl);
378 auto *OldOpnd = TII->getNamedOperand(MovMI, AMDGPU::OpName::old);
379 auto *SrcOpnd = TII->getNamedOperand(MovMI, AMDGPU::OpName::src0);
387 auto * const OldOpndValue = getOldOpndValue(*OldOpnd);
444 SmallVector<MachineOperand*, 16> Uses;
446 for (auto &Use : MRI->use_nodbg_operands(DPPMovReg)) {
451 MachineOperand *Use = Uses.pop_back_val();
479 for (auto &Op : MRI->use_nodbg_operands(FwdReg)) {
lib/Target/AMDGPU/GCNHazardRecognizer.cpp 126 const MachineOperand *RegOp = TII->getNamedOperand(RegInstr,
477 for (const MachineOperand &Op : Ops) {
554 for (const MachineOperand &Use : SMRD->uses()) {
591 for (const MachineOperand &Use : VMEM->uses()) {
613 for (const MachineOperand &Use : DPP->uses()) {
689 const MachineOperand *SOffset =
718 int GCNHazardRecognizer::checkVALUHazardsHelper(const MachineOperand &Def,
751 for (const MachineOperand &Def : VALU->defs()) {
775 const MachineOperand &Op = IA->getOperand(I);
789 const MachineOperand *LaneSelectOp =
834 for (const MachineOperand &Use : MI->uses()) {
893 auto *Src0 = TII->getNamedOperand(*MI, AMDGPU::OpName::src0);
921 for (const MachineOperand &Def : MI->defs()) {
922 MachineOperand *Op = I->findRegisterUseOperand(Def.getReg(), false, TRI);
967 const MachineOperand *SDST = TII->getNamedOperand(*MI, SDSTName);
969 for (const auto &MO : MI->implicit_operands()) {
1054 for (auto MO : MI->implicit_operands())
1146 const auto *Offset = TII->getNamedOperand(*MI, AMDGPU::OpName::offset);
1217 for (const MachineOperand &Use : MI->explicit_uses()) {
1239 for (const MachineOperand &Op : MI->explicit_operands()) {
1376 for (const MachineOperand &Op : MI->explicit_uses()) {
lib/Target/AMDGPU/GCNHazardRecognizer.h 82 int checkVALUHazardsHelper(const MachineOperand &Def, const MachineRegisterInfo &MRI);
lib/Target/AMDGPU/GCNIterativeScheduler.cpp 391 for (auto &Op : MI->operands())
lib/Target/AMDGPU/GCNNSAReassign.cpp 175 const MachineOperand &Op = MI.getOperand(VAddr0Idx + I);
202 for (auto U : MRI->use_nodbg_operands(Reg)) {
278 const MachineOperand &Op = MI->getOperand(VAddr0Idx + I);
lib/Target/AMDGPU/GCNRegBankReassign.cpp 361 for (const auto& Op : MI.explicit_uses()) {
433 for (auto U : MRI->use_nodbg_operands(Reg)) {
lib/Target/AMDGPU/GCNRegPressure.cpp 198 static LaneBitmask getDefRegMask(const MachineOperand &MO,
210 static LaneBitmask getUsedRegMask(const MachineOperand &MO,
233 for (const auto &MO : MI.operands()) {
330 for (const auto &MO : MI.defs()) {
406 for (const auto &MO : LastTrackedMI->defs()) {
lib/Target/AMDGPU/GCNSchedStrategy.cpp 409 for (auto &Op : MI->operands())
lib/Target/AMDGPU/R600AsmPrinter.cpp 57 const MachineOperand &MO = MI.getOperand(op_idx);
lib/Target/AMDGPU/R600ControlFlowFinalizer.cpp 302 const MachineOperand &MO = *I;
359 void getLiteral(MachineInstr &MI, std::vector<MachineOperand *> &Lits) const {
366 const SmallVector<std::pair<MachineOperand *, int64_t>, 3> Srcs =
372 std::vector<MachineOperand *>::iterator It =
378 MachineOperand &Operand = MI.getOperand(
422 std::vector<MachineOperand *>Literals;
428 for (MachineOperand &MO : BI->operands()) {
lib/Target/AMDGPU/R600EmitClauseMarkers.cpp 78 MachineOperand &MO = *It;
137 const SmallVectorImpl<std::pair<MachineOperand *, int64_t>> &Consts =
lib/Target/AMDGPU/R600ExpandSpecialInstrs.cpp 100 MachineOperand &DstOp = MI.getOperand(DstIdx);
lib/Target/AMDGPU/R600InstrInfo.cpp 277 SmallVector<std::pair<MachineOperand *, int64_t>, 3>
279 SmallVector<std::pair<MachineOperand *, int64_t>, 3> Result;
294 MachineOperand &MO =
298 MachineOperand &Sel =
318 MachineOperand &MO = MI.getOperand(SrcIdx);
321 MachineOperand &Sel =
327 MachineOperand &Operand =
677 SmallVectorImpl<MachineOperand> &Cond,
717 Cond.push_back(MachineOperand::CreateReg(R600::PRED_SEL_ONE, false));
737 Cond.push_back(MachineOperand::CreateReg(R600::PRED_SEL_ONE, false));
759 ArrayRef<MachineOperand> Cond,
933 R600InstrInfo::reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
934 MachineOperand &MO = Cond[1];
952 MachineOperand &MO2 = Cond[2];
967 std::vector<MachineOperand> &Pred) const {
972 ArrayRef<MachineOperand> Pred) const {
995 MachineOperand &PMO = MI.getOperand(PIdx);
1326 MachineOperand &Src0 = MI->getOperand(
1328 MachineOperand &Src1 = MI->getOperand(
1349 MachineOperand &MO = MI->getOperand(getOperandIdx(MI->getOpcode(),
1355 MachineOperand &MO = MI->getOperand(
1400 MachineOperand &R600InstrInfo::getFlagOp(MachineInstr &MI, unsigned SrcIdx,
1460 MachineOperand &FlagOp = MI.getOperand(FlagIndex);
1472 MachineOperand &FlagOp = getFlagOp(MI, Operand, Flag);
1481 MachineOperand &FlagOp = getFlagOp(MI, Operand);
1490 MachineOperand &FlagOp = getFlagOp(MI, Operand, Flag);
1493 MachineOperand &FlagOp = getFlagOp(MI);
lib/Target/AMDGPU/R600InstrInfo.h 119 SmallVector<std::pair<MachineOperand *, int64_t>, 3>
165 SmallVectorImpl<MachineOperand> &Cond) const override;
169 SmallVectorImpl<MachineOperand> &Cond,
173 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
198 std::vector<MachineOperand> &Pred) const override;
204 ArrayRef<MachineOperand> Pred) const override;
310 MachineOperand &getFlagOp(MachineInstr &MI, unsigned SrcIdx = 0,
lib/Target/AMDGPU/R600MachineScheduler.cpp 163 MachineOperand &MO = *It;
365 MachineOperand &MO = *It;
lib/Target/AMDGPU/R600OptimizeVectorRegisters.cpp 78 MachineOperand &MO = Instr->getOperand(i);
lib/Target/AMDGPU/SIAddIMGInit.cpp 79 MachineOperand *TFE = TII->getNamedOperand(MI, AMDGPU::OpName::tfe);
80 MachineOperand *LWE = TII->getNamedOperand(MI, AMDGPU::OpName::lwe);
81 MachineOperand *D16 = TII->getNamedOperand(MI, AMDGPU::OpName::d16);
102 MachineOperand *MO_Dmask =
lib/Target/AMDGPU/SIFixSGPRCopies.cpp 205 auto &Src = MI.getOperand(1);
212 for (const auto &MO : MRI.reg_nodbg_operands(DstReg)) {
333 const MachineOperand *ImmOp =
437 MachineOperand *Imm = nullptr;
438 for (auto &MO : MI.operands()) {
703 MachineOperand &Src0 = MI.getOperand(Src0Idx);
704 MachineOperand &Src1 = MI.getOperand(Src1Idx);
717 for (MachineOperand *MO : {&Src0, &Src1}) {
721 const MachineOperand &Def = DefMI->getOperand(0);
725 const MachineOperand &Copied = DefMI->getOperand(1);
768 for (const auto &Use : MRI->use_operands(Reg)) {
lib/Target/AMDGPU/SIFixVGPRCopies.cpp 60 MachineOperand::CreateReg(AMDGPU::EXEC, false, true));
lib/Target/AMDGPU/SIFixupVectorISel.cpp 85 static bool findSRegBaseAndIndex(MachineOperand *Op,
90 SmallVector<MachineOperand *, 8> Worklist;
93 MachineOperand *WOp = Worklist.pop_back_val();
177 MachineOperand *Op = TII->getNamedOperand(MI, AMDGPU::OpName::vaddr);
184 MachineOperand *VData = TII->getNamedOperand(MI, AMDGPU::OpName::vdata);
189 NewGlob->addOperand(MF, MachineOperand::CreateReg(IndexReg, false));
192 NewGlob->addOperand(MF, MachineOperand::CreateReg(BaseReg, false));
195 MachineOperand *Glc = TII->getNamedOperand(MI, AMDGPU::OpName::glc);
200 MachineOperand *DLC = TII->getNamedOperand(MI, AMDGPU::OpName::dlc);
206 MachineOperand *VDstInOp = TII->getNamedOperand(MI,
lib/Target/AMDGPU/SIFoldOperands.cpp 34 MachineOperand *OpToFold;
40 MachineOperand::MachineOperandType Kind;
43 FoldCandidate(MachineInstr *MI, unsigned OpNo, MachineOperand *FoldOp,
60 return Kind == MachineOperand::MO_FrameIndex;
64 return Kind == MachineOperand::MO_Immediate;
68 return Kind == MachineOperand::MO_Register;
71 bool isGlobal() const { return Kind == MachineOperand::MO_GlobalAddress; }
95 void foldOperand(MachineOperand &OpToFold,
101 void foldInstOperand(MachineInstr &MI, MachineOperand &OpToFold) const;
103 const MachineOperand *isClamp(const MachineInstr &MI) const;
106 std::pair<const MachineOperand *, int> isOMod(const MachineInstr &MI) const;
138 const MachineOperand &OpToFold) {
175 const MachineOperand &OpToFold) {
190 MachineOperand &Old = MI->getOperand(Fold.UseOpNo);
211 MachineOperand &Mod = MI->getOperand(ModIdx);
251 MachineOperand &Dst0 = MI->getOperand(0);
252 MachineOperand &Dst1 = MI->getOperand(1);
301 MachineOperand *New = Fold.OpToFold;
318 MachineOperand *FoldOp, bool Commuted = false,
331 MachineOperand *OpToFold,
409 MachineOperand &OtherOp = MI->getOperand(OtherIdx);
440 const MachineOperand &UseMO) {
449 SmallVectorImpl<std::pair<MachineOperand*, unsigned>> &Defs,
457 MachineOperand *Sub = &Def->getOperand(I);
464 MachineOperand *Op = &SubDef->getOperand(1);
482 const MachineOperand &OpToFold,
514 SmallVector<std::pair<MachineOperand*, unsigned>, 32> Defs;
520 const MachineOperand *Op = Defs[I].first;
542 MachineOperand &OpToFold,
547 const MachineOperand &UseOp = UseMI->getOperand(UseOpIdx);
593 MachineOperand *SOff = TII->getNamedOperand(*UseMI, AMDGPU::OpName::soffset);
686 SmallVector<std::pair<MachineOperand*, unsigned>, 32> Defs;
701 MachineOperand *Def = Defs[I].first;
860 MachineOperand ImmOp = MachineOperand::CreateImm(Imm.getSExtValue());
860 MachineOperand ImmOp = MachineOperand::CreateImm(Imm.getSExtValue());
943 static MachineOperand *getImmOrMaterializedImm(MachineRegisterInfo &MRI,
944 MachineOperand &Op) {
953 MachineOperand &ImmSrc = Def->getOperand(1);
968 MachineOperand *ImmOp) {
982 MachineOperand *Src0 = getImmOrMaterializedImm(MRI, MI->getOperand(Src0Idx));
983 MachineOperand *Src1 = getImmOrMaterializedImm(MRI, MI->getOperand(Src1Idx));
1086 const MachineOperand *Src0 = TII->getNamedOperand(*MI, AMDGPU::OpName::src0);
1087 const MachineOperand *Src1 = TII->getNamedOperand(*MI, AMDGPU::OpName::src1);
1114 MachineOperand &OpToFold) const {
1120 MachineOperand &Dst = MI.getOperand(0);
1125 MachineOperand *NonInlineUse = nullptr;
1240 const MachineOperand *SIFoldOperands::isClamp(const MachineInstr &MI) const {
1251 const MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0);
1252 const MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1);
1296 const MachineOperand *ClampSrc = isClamp(MI);
1306 MachineOperand *DefClamp = TII->getNamedOperand(*Def, AMDGPU::OpName::clamp);
1354 std::pair<const MachineOperand *, int>
1365 const MachineOperand *RegOp = nullptr;
1366 const MachineOperand *ImmOp = nullptr;
1367 const MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0);
1368 const MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1);
1396 const MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0);
1397 const MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1);
1416 const MachineOperand *RegOp;
1425 MachineOperand *DefOMod = TII->getNamedOperand(*Def, AMDGPU::OpName::omod);
1462 MachineOperand *CurrentKnownM0Val = nullptr;
1486 MachineOperand &NewM0Val = MI.getOperand(1);
1498 MachineOperand &OpToFold = MI.getOperand(1);
1515 MachineOperand &Dst = MI.getOperand(0);
lib/Target/AMDGPU/SIFormMemoryClauses.cpp 122 for (const MachineOperand &ResMO : MI.defs()) {
124 for (const MachineOperand &MO : MI.uses()) {
135 static unsigned getMopState(const MachineOperand &MO) {
210 for (const MachineOperand &MO : MI.operands()) {
265 for (const MachineOperand &MO : MI.operands()) {
369 for (MachineOperand &MO : BI->defs())
lib/Target/AMDGPU/SIISelLowering.cpp 3126 if (MachineOperand *Src = TII->getNamedOperand(MI, AMDGPU::OpName::data0))
3302 const MachineOperand *Idx = TII->getNamedOperand(MI, AMDGPU::OpName::idx);
3342 const MachineOperand *Idx = TII->getNamedOperand(MI, AMDGPU::OpName::idx);
3489 const MachineOperand *SrcVec = TII->getNamedOperand(MI, AMDGPU::OpName::src);
3490 const MachineOperand *Idx = TII->getNamedOperand(MI, AMDGPU::OpName::idx);
3491 const MachineOperand *Val = TII->getNamedOperand(MI, AMDGPU::OpName::val);
3606 MachineOperand &Dest = MI.getOperand(0);
3607 MachineOperand &Src0 = MI.getOperand(1);
3608 MachineOperand &Src1 = MI.getOperand(2);
3613 MachineOperand Src0Sub0 = TII->buildExtractSubRegOrImm(MI, MRI,
3616 MachineOperand Src0Sub1 = TII->buildExtractSubRegOrImm(MI, MRI,
3620 MachineOperand Src1Sub0 = TII->buildExtractSubRegOrImm(MI, MRI,
3623 MachineOperand Src1Sub1 = TII->buildExtractSubRegOrImm(MI, MRI,
10406 MachineOperand &Op = MI.getOperand(I);
lib/Target/AMDGPU/SIInsertSkips.cpp 277 const MachineOperand &Op = MI.getOperand(0);
371 MachineOperand &Op1 = A->getOperand(1);
372 MachineOperand &Op2 = A->getOperand(2);
lib/Target/AMDGPU/SIInsertWaitcnts.cpp 464 const MachineOperand &Op = MI->getOperand(OpNo);
572 const MachineOperand &Op = Inst.getOperand(I);
619 MachineOperand &DefMO = Inst.getOperand(I);
628 MachineOperand &MO = Inst.getOperand(I);
988 const MachineOperand &Op = MI.getOperand(I);
1024 MachineOperand &Def = MI.getOperand(I);
lib/Target/AMDGPU/SIInstrInfo.cpp 260 const MachineOperand *&BaseOp,
266 const MachineOperand *OffsetImm =
285 const MachineOperand *Offset0Imm =
287 const MachineOperand *Offset1Imm =
320 const MachineOperand *SOffset = getNamedOperand(LdSt, AMDGPU::OpName::soffset);
324 const MachineOperand *AddrReg = getNamedOperand(LdSt, AMDGPU::OpName::vaddr);
328 const MachineOperand *RSrc = getNamedOperand(LdSt, AMDGPU::OpName::srsrc);
334 const MachineOperand *OffsetImm =
341 const MachineOperand *AddrReg = getNamedOperand(LdSt, AMDGPU::OpName::vaddr);
345 const MachineOperand *OffsetImm =
359 const MachineOperand *OffsetImm =
364 const MachineOperand *SBaseReg = getNamedOperand(LdSt, AMDGPU::OpName::sbase);
373 const MachineOperand *VAddr = getNamedOperand(LdSt, AMDGPU::OpName::vaddr);
395 const MachineOperand &BaseOp1,
397 const MachineOperand &BaseOp2) {
429 bool SIInstrInfo::shouldClusterMemOps(const MachineOperand &BaseOp1,
430 const MachineOperand &BaseOp2,
438 const MachineOperand *FirstDst = nullptr;
439 const MachineOperand *SecondDst = nullptr;
622 MachineOperand &DefOp = Def->getOperand(1);
868 MachineOperand RegOp = Cond[1];
882 MachineOperand RegOp = Cond[1];
1423 const MachineOperand &SrcOp = MI.getOperand(1);
1551 for (MachineOperand &MO : I->operands())
1587 const MachineOperand &SrcOp = MI.getOperand(I);
1622 MachineOperand &Src0,
1624 MachineOperand &Src1,
1626 MachineOperand *Src0Mods = getNamedOperand(MI, Src0OpName);
1630 MachineOperand *Src1Mods = getNamedOperand(MI, Src1OpName);
1643 MachineOperand &RegOp,
1644 MachineOperand &NonRegOp) {
1681 MachineOperand &Src0 = MI.getOperand(Src0Idx);
1682 MachineOperand &Src1 = MI.getOperand(Src1Idx);
1924 Cond.push_back(MachineOperand::CreateImm(Pred));
1946 SmallVectorImpl<MachineOperand> &Cond,
2039 static void preserveCondRegFlags(MachineOperand &CondReg,
2040 const MachineOperand &OrigCond) {
2048 ArrayRef<MachineOperand> Cond,
2093 MachineOperand &CondReg = CondBr->getOperand(1);
2104 SmallVectorImpl<MachineOperand> &Cond) const {
2118 ArrayRef<MachineOperand> Cond,
2325 const MachineOperand *ImmOp = getNamedOperand(DefMI, AMDGPU::OpName::src0);
2358 MachineOperand *Src0 = getNamedOperand(UseMI, AMDGPU::OpName::src0);
2368 MachineOperand *Src1 = getNamedOperand(UseMI, AMDGPU::OpName::src1);
2369 MachineOperand *Src2 = getNamedOperand(UseMI, AMDGPU::OpName::src2);
2521 const MachineOperand *BaseOp0, *BaseOp1;
2593 static int64_t getFoldableImm(const MachineOperand* MO) {
2631 const MachineOperand *Src0 = &MI.getOperand(Src0Idx);
2642 const MachineOperand *Dst = getNamedOperand(MI, AMDGPU::OpName::vdst);
2643 const MachineOperand *Src0 = getNamedOperand(MI, AMDGPU::OpName::src0);
2644 const MachineOperand *Src0Mods =
2646 const MachineOperand *Src1 = getNamedOperand(MI, AMDGPU::OpName::src1);
2647 const MachineOperand *Src1Mods =
2649 const MachineOperand *Src2 = getNamedOperand(MI, AMDGPU::OpName::src2);
2650 const MachineOperand *Clamp = getNamedOperand(MI, AMDGPU::OpName::clamp);
2651 const MachineOperand *Omod = getNamedOperand(MI, AMDGPU::OpName::omod);
2830 bool SIInstrInfo::isInlineConstant(const MachineOperand &MO,
2891 bool SIInstrInfo::isLiteralConstantLike(const MachineOperand &MO,
2894 case MachineOperand::MO_Register:
2896 case MachineOperand::MO_Immediate:
2898 case MachineOperand::MO_FrameIndex:
2899 case MachineOperand::MO_MachineBasicBlock:
2900 case MachineOperand::MO_ExternalSymbol:
2901 case MachineOperand::MO_GlobalAddress:
2902 case MachineOperand::MO_MCSymbol:
2909 static bool compareMachineOp(const MachineOperand &Op0,
2910 const MachineOperand &Op1) {
2915 case MachineOperand::MO_Register:
2917 case MachineOperand::MO_Immediate:
2925 const MachineOperand &MO) const {
2975 const MachineOperand *Mods = getNamedOperand(MI, OpName);
2989 const MachineOperand *Src2 = getNamedOperand(MI, AMDGPU::OpName::src2);
3004 const MachineOperand *Src1
3025 const MachineOperand *Src1 = getNamedOperand(MI, AMDGPU::OpName::src1);
3047 const MachineOperand &Orig) {
3049 for (MachineOperand &Use : MI.implicit_operands()) {
3078 const MachineOperand *Src1 = getNamedOperand(MI, AMDGPU::OpName::src1);
3082 const MachineOperand *Src2 = getNamedOperand(MI, AMDGPU::OpName::src2);
3100 const MachineOperand &MO,
3133 for (const MachineOperand &MO : MI.implicit_operands()) {
3181 const MachineOperand &SuperVec,
3182 const MachineOperand &SubReg) {
3219 const MachineOperand &Op = MI.getOperand(I);
3263 const MachineOperand &MO = MI.getOperand(i);
3314 const MachineOperand &MO = MI.getOperand(OpIdx);
3333 const MachineOperand *OMod = getNamedOperand(MI, AMDGPU::OpName::omod);
3345 const MachineOperand &Dst = MI.getOperand(DstIdx);
3352 const MachineOperand *Clamp = getNamedOperand(MI, AMDGPU::OpName::clamp);
3359 const MachineOperand *OMod = getNamedOperand(MI, AMDGPU::OpName::omod);
3367 const MachineOperand *DstUnused = getNamedOperand(MI, AMDGPU::OpName::dst_unused);
3370 const MachineOperand &Dst = MI.getOperand(DstIdx);
3376 const MachineOperand &TiedMO =
3394 const MachineOperand *DMask = getNamedOperand(MI, AMDGPU::OpName::dmask);
3399 const MachineOperand *TFE = getNamedOperand(MI, AMDGPU::OpName::tfe);
3400 const MachineOperand *LWE = getNamedOperand(MI, AMDGPU::OpName::lwe);
3401 const MachineOperand *D16 = getNamedOperand(MI, AMDGPU::OpName::d16);
3413 const MachineOperand &Dst = MI.getOperand(DstIdx);
3450 const MachineOperand &MO = MI.getOperand(OpIdx);
3497 const MachineOperand &MO = MI.getOperand(OpIdx);
3516 const MachineOperand &Src0 = MI.getOperand(Src0Idx);
3517 const MachineOperand &Src1 = MI.getOperand(Src1Idx);
3518 const MachineOperand &Src2 = MI.getOperand(Src2Idx);
3529 const MachineOperand &Src0 = MI.getOperand(Src0Idx);
3530 const MachineOperand &Src1 = MI.getOperand(Src1Idx);
3588 const MachineOperand *Dst = getNamedOperand(MI, AMDGPU::OpName::vdst);
3603 const MachineOperand &Src0 = MI.getOperand(Src0Idx);
3604 const MachineOperand &ImpUse
3626 const MachineOperand *Soff = getNamedOperand(MI, AMDGPU::OpName::soff);
3635 const MachineOperand *Offset = getNamedOperand(MI, AMDGPU::OpName::offset);
3643 const MachineOperand *DimOp = getNamedOperand(MI, AMDGPU::OpName::dim);
3689 const MachineOperand *DppCt = getNamedOperand(MI, AMDGPU::OpName::dpp_ctrl);
3827 MachineOperand &MO = MI.getOperand(OpIdx);
3884 MachineOperand SIInstrInfo::buildExtractSubRegOrImm(
3893 return MachineOperand::CreateImm(static_cast<int32_t>(Op.getImm()));
3895 return MachineOperand::CreateImm(static_cast<int32_t>(Op.getImm() >> 32));
3902 return MachineOperand::CreateReg(SubReg, false);
3908 MachineOperand Op1 = Inst.getOperand(1);
3915 const MachineOperand &MO) const {
3940 const MachineOperand &MO) const {
3950 const MachineOperand *MO) const {
3974 const MachineOperand &Op = MI.getOperand(i);
4018 MachineOperand &Src0 = MI.getOperand(Src0Idx);
4021 MachineOperand &Src1 = MI.getOperand(Src1Idx);
4137 MachineOperand &Src1 = MI.getOperand(VOP3Idx[1]);
4138 MachineOperand &Src2 = MI.getOperand(VOP3Idx[2]);
4168 MachineOperand &MO = MI.getOperand(Idx);
4260 MachineOperand *SBase = getNamedOperand(MI, AMDGPU::OpName::sbase);
4265 MachineOperand *SOff = getNamedOperand(MI, AMDGPU::OpName::soff);
4312 Copy->addOperand(MachineOperand::CreateReg(AMDGPU::EXEC, false, true));
4321 const DebugLoc &DL, MachineOperand &Rsrc) {
4403 MachineOperand &Rsrc, MachineDominatorTree *MDT) {
4422 for (auto &MO : MI.uses()) {
4472 extractRsrcPtr(const SIInstrInfo &TII, MachineInstr &MI, MachineOperand &Rsrc) {
4578 MachineOperand &Op = MI.getOperand(I);
4603 MachineOperand &Op = MI.getOperand(I);
4629 MachineOperand &Op = MI.getOperand(1);
4637 MachineOperand &Src = MI.getOperand(0);
4651 MachineOperand *SRsrc = getNamedOperand(MI, AMDGPU::OpName::srsrc);
4657 MachineOperand *SSamp = getNamedOperand(MI, AMDGPU::OpName::ssamp);
4670 MachineOperand *Rsrc = &MI.getOperand(RsrcIdx);
4694 MachineOperand *VAddr = getNamedOperand(MI, AMDGPU::OpName::vaddr);
4745 MachineOperand *VData = getNamedOperand(MI, AMDGPU::OpName::vdata);
4746 MachineOperand *Offset = getNamedOperand(MI, AMDGPU::OpName::offset);
4747 MachineOperand *SOffset = getNamedOperand(MI, AMDGPU::OpName::soffset);
4752 MachineOperand *VDataIn = getNamedOperand(MI, AMDGPU::OpName::vdata_in);
4766 if (const MachineOperand *GLC =
4770 if (const MachineOperand *DLC =
4777 if (const MachineOperand *TFE =
5013 MachineOperand &Op = Inst.getOperand(i);
5026 Inst.addOperand(MachineOperand::CreateImm(0));
5027 Inst.addOperand(MachineOperand::CreateImm(Size));
5032 Inst.addOperand(MachineOperand::CreateImm(0));
5039 const MachineOperand &OffsetWidthOp = Inst.getOperand(2);
5049 Inst.addOperand(MachineOperand::CreateImm(Offset));
5050 Inst.addOperand(MachineOperand::CreateImm(BitWidth));
5124 Inst.addOperand(MachineOperand::CreateImm(0)); // clamp bit
5143 MachineOperand &Dest = Inst.getOperand(0);
5144 MachineOperand &Src = Inst.getOperand(1);
5170 MachineOperand &Dest = Inst.getOperand(0);
5171 MachineOperand &Src0 = Inst.getOperand(1);
5172 MachineOperand &Src1 = Inst.getOperand(2);
5236 MachineOperand &Dest = Inst.getOperand(0);
5237 MachineOperand &Src0 = Inst.getOperand(1);
5238 MachineOperand &Src1 = Inst.getOperand(2);
5265 MachineOperand &Dest = Inst.getOperand(0);
5266 MachineOperand &Src0 = Inst.getOperand(1);
5267 MachineOperand &Src1 = Inst.getOperand(2);
5292 MachineOperand &Dest = Inst.getOperand(0);
5293 MachineOperand &Src0 = Inst.getOperand(1);
5305 MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
5315 MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
5356 MachineOperand &Dest = Inst.getOperand(0);
5357 MachineOperand &Src0 = Inst.getOperand(1);
5358 MachineOperand &Src1 = Inst.getOperand(2);
5367 MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
5369 MachineOperand SrcReg1Sub0 = buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC,
5373 MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
5375 MachineOperand SrcReg1Sub1 = buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC,
5418 MachineOperand &Dest = Inst.getOperand(0);
5419 MachineOperand &Src0 = Inst.getOperand(1);
5420 MachineOperand &Src1 = Inst.getOperand(2);
5437 MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
5439 MachineOperand SrcReg1Sub0 = buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC,
5441 MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
5443 MachineOperand SrcReg1Sub1 = buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC,
5482 MachineOperand &Dest = Inst.getOperand(0);
5483 MachineOperand &Src0 = Inst.getOperand(1);
5484 MachineOperand &Src1 = Inst.getOperand(2);
5493 MachineOperand* Op0;
5494 MachineOperand* Op1;
5526 MachineOperand &Dest = Inst.getOperand(0);
5527 MachineOperand &Src = Inst.getOperand(1);
5539 MachineOperand SrcRegSub0 = buildExtractSubRegOrImm(MII, MRI, Src, SrcRC,
5541 MachineOperand SrcRegSub1 = buildExtractSubRegOrImm(MII, MRI, Src, SrcRC,
5562 MachineOperand &Dest = Inst.getOperand(0);
5598 MachineOperand &Src = Inst.getOperand(1);
5657 MachineOperand &Src0 = Inst.getOperand(1);
5658 MachineOperand &Src1 = Inst.getOperand(2);
5709 MachineOperand &Dest = Inst.getOperand(0);
5714 void SIInstrInfo::addSCCDefUsersToVALUWorklist(MachineOperand &Op,
5808 const MachineOperand &MO = MI.getOperand(Idx);
5852 MachineOperand *SIInstrInfo::getNamedOperand(MachineInstr &MI,
5921 const MachineOperand *Addr = getNamedOperand(MI, AMDGPU::OpName::vaddr);
5934 const MachineOperand *Addr = getNamedOperand(MI, AMDGPU::OpName::addr);
6250 for (auto &Op : MI.implicit_operands()) {
6372 TargetInstrInfo::RegSubRegPair getRegOrUndef(const MachineOperand &RegOpnd) {
6383 auto &RegOp = MI.getOperand(1 + 2 * I);
6429 auto &Op1 = MI->getOperand(1);
lib/Target/AMDGPU/SIInstrInfo.h 73 MachineOperand buildExtractSubRegOrImm(MachineBasicBlock::iterator MI,
123 void addSCCDefUsersToVALUWorklist(MachineOperand &Op,
137 MachineOperand &Src0, unsigned Src0OpName,
138 MachineOperand &Src1, unsigned Src1OpName) const;
183 const MachineOperand *&BaseOp,
187 bool shouldClusterMemOps(const MachineOperand &BaseOp1,
188 const MachineOperand &BaseOp2,
279 SmallVectorImpl<MachineOperand> &Cond,
286 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
291 SmallVectorImpl<MachineOperand> &Cond) const override;
294 ArrayRef<MachineOperand> Cond,
695 bool isInlineConstant(const MachineOperand &MO, uint8_t OperandType) const;
697 bool isInlineConstant(const MachineOperand &MO,
705 const MachineOperand &UseMO,
706 const MachineOperand &DefMO) const {
719 const MachineOperand &MO = MI.getOperand(OpIdx);
724 const MachineOperand &MO) const {
740 bool isInlineConstant(const MachineOperand &MO) const {
745 bool isLiteralConstant(const MachineOperand &MO,
751 const MachineOperand &MO = MI.getOperand(OpIdx);
759 bool isLiteralConstantLike(const MachineOperand &MO,
763 const MachineOperand &MO) const;
771 const MachineOperand &MO,
818 const MachineOperand &MO = MI.getOperand(OpNo);
845 const MachineOperand *MO = nullptr) const;
852 const MachineOperand &MO) const;
858 const MachineOperand &MO) const;
907 MachineOperand *getNamedOperand(MachineInstr &MI, unsigned OperandName) const;
910 const MachineOperand *getNamedOperand(const MachineInstr &MI,
1045 TargetInstrInfo::RegSubRegPair getRegSubRegPair(const MachineOperand &O) {
lib/Target/AMDGPU/SILoadStoreOptimizer.cpp 134 const MachineOperand *AddrReg[5];
139 const MachineOperand &AddrRegNext = MI.getOperand(AddrIdx[i]);
161 const MachineOperand *AddrOp = AddrReg[i];
236 MachineOperand createRegOrImm(int32_t Val, MachineInstr &MI) const;
237 Optional<int32_t> extractConstOffset(const MachineOperand &Op) const;
238 void processBaseWithConstOffset(const MachineOperand &Base, MemAddress &Addr) const;
562 for (const MachineOperand &Op : MI.operands()) {
586 for (MachineOperand &Use : MI.operands()) {
642 const auto *TFEOp = TII.getNamedOperand(*CI.I, AMDGPU::OpName::tfe);
643 const auto *LWEOp = TII.getNamedOperand(*CI.I, AMDGPU::OpName::lwe);
877 const auto *AddrReg = TII->getNamedOperand(*CI.I, AMDGPU::OpName::addr);
879 const auto *Dest0 = TII->getNamedOperand(*CI.I, AMDGPU::OpName::vdst);
880 const auto *Dest1 = TII->getNamedOperand(*CI.Paired, AMDGPU::OpName::vdst);
976 const MachineOperand *AddrReg =
978 const MachineOperand *Data0 =
980 const MachineOperand *Data1 =
1074 const auto *Dest0 = TII->getNamedOperand(*CI.I, AMDGPU::OpName::vdata);
1075 const auto *Dest1 = TII->getNamedOperand(*CI.Paired, AMDGPU::OpName::vdata);
1124 const auto *Dest0 = TII->getNamedOperand(*CI.I, AMDGPU::OpName::sdst);
1125 const auto *Dest1 = TII->getNamedOperand(*CI.Paired, AMDGPU::OpName::sdst);
1186 const auto *Dest0 = TII->getNamedOperand(*CI.I, AMDGPU::OpName::vdata);
1187 const auto *Dest1 = TII->getNamedOperand(*CI.Paired, AMDGPU::OpName::vdata);
1310 const auto *Src0 = TII->getNamedOperand(*CI.I, AMDGPU::OpName::vdata);
1311 const auto *Src1 = TII->getNamedOperand(*CI.Paired, AMDGPU::OpName::vdata);
1354 MachineOperand
1358 return MachineOperand::CreateImm(Val);
1367 return MachineOperand::CreateReg(Reg, false);
1386 MachineOperand OffsetLo = createRegOrImm(static_cast<int32_t>(Addr.Offset), MI);
1387 MachineOperand OffsetHi =
1437 SILoadStoreOptimizer::extractConstOffset(const MachineOperand &Op) const {
1462 void SILoadStoreOptimizer::processBaseWithConstOffset(const MachineOperand &Base,
1472 MachineOperand BaseLo = Def->getOperand(1);
1473 MachineOperand BaseHi = Def->getOperand(3);
1484 const auto *Src0 = TII->getNamedOperand(*BaseLoDef, AMDGPU::OpName::src0);
1485 const auto *Src1 = TII->getNamedOperand(*BaseLoDef, AMDGPU::OpName::src1);
1541 MachineOperand &Base = *TII->getNamedOperand(MI, AMDGPU::OpName::vaddr);
1603 const MachineOperand &BaseNext =
lib/Target/AMDGPU/SILowerControlFlow.cpp 104 SmallVectorImpl<MachineOperand> &Src) const;
139 MachineOperand &ImpDefSCC = MI.getOperand(3);
182 MachineOperand &SaveExec = MI->getOperand(0);
203 MachineOperand& Cond = MI.getOperand(1);
206 MachineOperand &ImpDefSCC = MI.getOperand(4);
442 SmallVectorImpl<MachineOperand> &Src) const {
443 MachineOperand &Op = MI.getOperand(OpNo);
462 for (const auto &SrcOp : Def->explicit_operands())
474 SmallVector<MachineOperand, 4> Ops;
lib/Target/AMDGPU/SILowerI1Copies.cpp 774 for (const MachineOperand &MO : MI.operands()) {
lib/Target/AMDGPU/SIMachineScheduler.cpp 1959 const MachineOperand *BaseLatOp;
lib/Target/AMDGPU/SIMemoryLegalizer.cpp 109 MachineOperand &Bit = MI->getOperand(BitIdx);
lib/Target/AMDGPU/SIOptimizeExecMasking.cpp 66 const MachineOperand &Src = MI.getOperand(1);
82 const MachineOperand &Dst = MI.getOperand(0);
109 const MachineOperand &Src1 = MI.getOperand(1);
112 const MachineOperand &Src2 = MI.getOperand(2);
125 const MachineOperand &Src1 = MI.getOperand(1);
128 const MachineOperand &Src2 = MI.getOperand(2);
388 MachineOperand &Src0 = SaveExecInst->getOperand(1);
389 MachineOperand &Src1 = SaveExecInst->getOperand(2);
391 MachineOperand *OtherOp = nullptr;
lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp 213 MachineOperand *AndCC = &And->getOperand(1);
230 MachineOperand *Op1 = TII->getNamedOperand(*Cmp, AMDGPU::OpName::src0);
231 MachineOperand *Op2 = TII->getNamedOperand(*Cmp, AMDGPU::OpName::src1);
248 MachineOperand *CC = TII->getNamedOperand(*Sel, AMDGPU::OpName::src2);
356 for (auto &Op : I->operands()) {
397 for (auto &Op : Lead->operands()) {
lib/Target/AMDGPU/SIPeepholeSDWA.cpp 80 Optional<int64_t> foldToImm(const MachineOperand &Op) const;
108 MachineOperand *Target; // Operand that would be used in converted instruction
109 MachineOperand *Replaced; // Operand that would be replace by Target
112 SDWAOperand(MachineOperand *TargetOp, MachineOperand *ReplacedOp)
112 SDWAOperand(MachineOperand *TargetOp, MachineOperand *ReplacedOp)
123 MachineOperand *getTargetOperand() const { return Target; }
124 MachineOperand *getReplacedOperand() const { return Replaced; }
147 SDWASrcOperand(MachineOperand *TargetOp, MachineOperand *ReplacedOp,
147 SDWASrcOperand(MachineOperand *TargetOp, MachineOperand *ReplacedOp,
162 const MachineOperand *SrcOp) const;
176 SDWADstOperand(MachineOperand *TargetOp, MachineOperand *ReplacedOp,
176 SDWADstOperand(MachineOperand *TargetOp, MachineOperand *ReplacedOp,
193 MachineOperand *Preserve;
196 SDWADstPreserveOperand(MachineOperand *TargetOp, MachineOperand *ReplacedOp,
196 SDWADstPreserveOperand(MachineOperand *TargetOp, MachineOperand *ReplacedOp,
197 MachineOperand *PreserveOp, SdwaSel DstSel_ = DWORD)
203 MachineOperand *getPreservedOperand() const { return Preserve; }
275 static void copyRegOperand(MachineOperand &To, const MachineOperand &From) {
275 static void copyRegOperand(MachineOperand &To, const MachineOperand &From) {
287 static bool isSameReg(const MachineOperand &LHS, const MachineOperand &RHS) {
287 static bool isSameReg(const MachineOperand &LHS, const MachineOperand &RHS) {
294 static MachineOperand *findSingleRegUse(const MachineOperand *Reg,
294 static MachineOperand *findSingleRegUse(const MachineOperand *Reg,
299 MachineOperand *ResMO = nullptr;
300 for (MachineOperand &UseMO : MRI->use_nodbg_operands(Reg->getReg())) {
316 static MachineOperand *findSingleRegDef(const MachineOperand *Reg,
316 static MachineOperand *findSingleRegDef(const MachineOperand *Reg,
325 for (auto &DefMO : DefInstr->defs()) {
335 const MachineOperand *SrcOp) const {
362 MachineOperand *PotentialMO = findSingleRegUse(getReplacedOperand(), getMRI());
373 MachineOperand *Src = TII->getNamedOperand(MI, AMDGPU::OpName::src0);
374 MachineOperand *SrcSel = TII->getNamedOperand(MI, AMDGPU::OpName::src0_sel);
375 MachineOperand *SrcMods =
392 MachineOperand *Dst = TII->getNamedOperand(MI, AMDGPU::OpName::vdst);
393 MachineOperand *DstUnused =
449 MachineOperand *PotentialMO = findSingleRegDef(getReplacedOperand(), MRI);
474 MachineOperand *Operand = TII->getNamedOperand(MI, AMDGPU::OpName::vdst);
479 MachineOperand *DstSel= TII->getNamedOperand(MI, AMDGPU::OpName::dst_sel);
482 MachineOperand *DstUnused= TII->getNamedOperand(MI, AMDGPU::OpName::dst_unused);
497 for (MachineOperand &MO : MI.uses()) {
522 Optional<int64_t> SIPeepholeSDWA::foldToImm(const MachineOperand &Op) const {
530 for (const MachineOperand &Def : MRI->def_operands(Op.getReg())) {
538 const MachineOperand &Copied = DefInst->getOperand(1);
567 MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0);
575 MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1);
576 MachineOperand *Dst = TII->getNamedOperand(MI, AMDGPU::OpName::vdst);
608 MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0);
613 MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1);
614 MachineOperand *Dst = TII->getNamedOperand(MI, AMDGPU::OpName::vdst);
648 MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1);
653 MachineOperand *Src2 = TII->getNamedOperand(MI, AMDGPU::OpName::src2);
677 MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0);
678 MachineOperand *Dst = TII->getNamedOperand(MI, AMDGPU::OpName::vdst);
694 MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0);
695 MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1);
707 MachineOperand *Dst = TII->getNamedOperand(MI, AMDGPU::OpName::vdst);
728 using CheckRetType = Optional<std::pair<MachineOperand *, MachineOperand *>>;
728 using CheckRetType = Optional<std::pair<MachineOperand *, MachineOperand *>>;
734 MachineOperand *Op1Def = findSingleRegDef(Op1, MRI);
742 MachineOperand *Op2Def = findSingleRegDef(Op2, MRI);
749 MachineOperand *OrSDWA = TII->getNamedOperand(MI, AMDGPU::OpName::src0);
750 MachineOperand *OrOther = TII->getNamedOperand(MI, AMDGPU::OpName::src1);
762 MachineOperand *OrSDWADef = Res->first;
763 MachineOperand *OrOtherDef = Res->second;
840 MachineOperand *OrDst = TII->getNamedOperand(MI, AMDGPU::OpName::vdst);
891 const MachineOperand *Sdst = TII->getNamedOperand(MI, AMDGPU::OpName::sdst);
894 MachineOperand *NextOp = findSingleRegUse(Sdst, MRI);
903 MachineOperand *CarryIn = TII->getNamedOperand(MISucc, AMDGPU::OpName::src2);
906 MachineOperand *CarryOut = TII->getNamedOperand(MISucc, AMDGPU::OpName::sdst);
956 const MachineOperand *SDst = TII->getNamedOperand(MI, AMDGPU::OpName::sdst);
1013 MachineOperand *Dst = TII->getNamedOperand(MI, AMDGPU::OpName::vdst);
1028 MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0);
1033 if (auto *Mod = TII->getNamedOperand(MI, AMDGPU::OpName::src0_modifiers))
1040 MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1);
1045 if (auto *Mod = TII->getNamedOperand(MI, AMDGPU::OpName::src1_modifiers))
1057 MachineOperand *Src2 = TII->getNamedOperand(MI, AMDGPU::OpName::src2);
1064 MachineOperand *Clamp = TII->getNamedOperand(MI, AMDGPU::OpName::clamp);
1073 MachineOperand *OMod = TII->getNamedOperand(MI, AMDGPU::OpName::omod);
1083 MachineOperand *DstSel = TII->getNamedOperand(MI, AMDGPU::OpName::dst_sel);
1093 MachineOperand *DstUnused = TII->getNamedOperand(MI, AMDGPU::OpName::dst_unused);
1103 MachineOperand *Src0Sel = TII->getNamedOperand(MI, AMDGPU::OpName::src0_sel);
1113 MachineOperand *Src1Sel = TII->getNamedOperand(MI, AMDGPU::OpName::src1_sel);
1134 auto Tied = MI.getOperand(TiedIdx);
1177 for (MachineOperand &Op : MI.explicit_uses()) {
lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp 67 bool processDef(MachineOperand &MO);
89 bool SIPreAllocateWWMRegs::processDef(MachineOperand &MO) {
123 for (MachineOperand &MO : MI.operands()) {
210 for (MachineOperand &DefOpnd : MI.defs()) {
lib/Target/AMDGPU/SIRegisterInfo.cpp 384 for (const MachineOperand &MO: MI.operands()) {
394 MachineOperand *FIOp = TII->getNamedOperand(MI, AMDGPU::OpName::vaddr);
405 MachineOperand *OffsetOp = TII->getNamedOperand(MI, AMDGPU::OpName::offset);
590 const MachineOperand *Reg = TII->getNamedOperand(*MI, AMDGPU::OpName::vdata);
607 const MachineOperand *VDataIn = TII->getNamedOperand(*MI,
995 MachineOperand &FIOp = MI->getOperand(FIOperandNum);
1041 const MachineOperand *VData = TII->getNamedOperand(*MI,
1071 const MachineOperand *VData = TII->getNamedOperand(*MI,
1834 SIRegisterInfo::getConstrainedRegClassForOperand(const MachineOperand &MO,
lib/Target/AMDGPU/SIRegisterInfo.h 262 getConstrainedRegClassForOperand(const MachineOperand &MO,
lib/Target/AMDGPU/SIShrinkInstructions.cpp 78 MachineOperand &Src0 = MI.getOperand(Src0Idx);
84 MachineOperand &MovSrc = Def->getOperand(1);
128 static bool isKImmOperand(const SIInstrInfo *TII, const MachineOperand &Src) {
134 static bool isKUImmOperand(const SIInstrInfo *TII, const MachineOperand &Src) {
141 const MachineOperand &Src,
159 const MachineOperand &Src,
176 const MachineOperand &MO = MI.getOperand(i);
188 const MachineOperand &Src1 = MI.getOperand(1);
253 const MachineOperand &Op = MI.getOperand(VAddr0Idx + i);
320 const MachineOperand *Dest = &MI.getOperand(0);
321 MachineOperand *Src0 = &MI.getOperand(1);
322 MachineOperand *Src1 = &MI.getOperand(2);
323 MachineOperand *SrcReg = Src0;
324 MachineOperand *SrcImm = Src1;
392 for (const MachineOperand &MO : R) {
462 MachineOperand &Xop = MovT.getOperand(1);
475 for (MachineOperand &YTop : MRI.use_nodbg_operands(T)) {
578 MachineOperand &Src = MI.getOperand(1);
632 const MachineOperand *Dest = &MI.getOperand(0);
633 MachineOperand *Src0 = &MI.getOperand(1);
634 MachineOperand *Src1 = &MI.getOperand(2);
669 const MachineOperand &Dst = MI.getOperand(0);
670 MachineOperand &Src = MI.getOperand(1);
740 const MachineOperand *Src2 =
754 const MachineOperand *SDst = TII->getNamedOperand(MI,
758 const MachineOperand *Src2 = TII->getNamedOperand(MI,
lib/Target/AMDGPU/SIWholeQuadMode.cpp 272 for (const MachineOperand &Use : MI.uses()) {
359 MachineOperand &Inactive = MI.getOperand(2);
389 for (const MachineOperand &MO : MI.defs()) {
543 const MachineOperand &Op = MI.getOperand(0);
869 MI->addOperand(MachineOperand::CreateReg(AMDGPU::EXEC, false, true));
lib/Target/ARC/ARCInstrInfo.cpp 49 static bool isZeroImm(const MachineOperand &Op) {
173 SmallVectorImpl<MachineOperand> &Cond,
351 SmallVectorImpl<MachineOperand> &Cond) const {
373 ArrayRef<MachineOperand> Cond,
lib/Target/ARC/ARCInstrInfo.h 55 SmallVectorImpl<MachineOperand> &Cond,
59 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
82 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
lib/Target/ARC/ARCMCInstLower.cpp 29 MCOperand ARCMCInstLower::LowerSymbolOperand(const MachineOperand &MO,
36 case MachineOperand::MO_MachineBasicBlock:
39 case MachineOperand::MO_GlobalAddress:
43 case MachineOperand::MO_BlockAddress:
47 case MachineOperand::MO_ExternalSymbol:
51 case MachineOperand::MO_JumpTableIndex:
54 case MachineOperand::MO_ConstantPoolIndex:
76 MCOperand ARCMCInstLower::LowerOperand(const MachineOperand &MO,
83 case MachineOperand::MO_Register:
88 case MachineOperand::MO_Immediate:
90 case MachineOperand::MO_MachineBasicBlock:
91 case MachineOperand::MO_GlobalAddress:
92 case MachineOperand::MO_ExternalSymbol:
93 case MachineOperand::MO_JumpTableIndex:
94 case MachineOperand::MO_ConstantPoolIndex:
95 case MachineOperand::MO_BlockAddress:
97 case MachineOperand::MO_RegisterMask:
108 const MachineOperand &MO = MI->getOperand(i);
lib/Target/ARC/ARCMCInstLower.h 27 using MachineOperandType = MachineOperand::MachineOperandType;
34 MCOperand LowerOperand(const MachineOperand &MO, unsigned offset = 0) const;
37 MCOperand LowerSymbolOperand(const MachineOperand &MO,
lib/Target/ARC/ARCOptAddrMode.cpp 89 MachineOperand &Incr, unsigned BaseReg);
100 unsigned NewBase, MachineOperand &NewOffset);
174 const MachineOperand &MO = MI.getOperand(OffPos);
198 MachineOperand &Base = Ldst.getOperand(BasePos);
199 MachineOperand &Offset = Ldst.getOperand(OffsetPos);
342 MachineOperand &Incr, unsigned BaseReg) {
375 MachineOperand &MO = MI->getOperand(OffPos);
405 for (auto &O : Ldst->explicit_operands()) {
442 MachineOperand &NewOffset) {
445 MachineOperand Src = MachineOperand::CreateImm(0xDEADBEEF);
445 MachineOperand Src = MachineOperand::CreateImm(0xDEADBEEF);
459 Ldst.addOperand(MachineOperand::CreateReg(NewBase, true));
462 Ldst.addOperand(MachineOperand::CreateReg(BaseReg, false));
lib/Target/ARC/ARCRegisterInfo.cpp 170 MachineOperand &FrameOp = MI.getOperand(FIOperandNum);
lib/Target/ARM/A15SDOptimizer.cpp 97 bool usesRegClass(MachineOperand &MO, const TargetRegisterClass *TRC);
132 bool A15SDOptimizer::usesRegClass(MachineOperand &MO,
159 MachineOperand *MO = MI->findRegisterDefOperand(SReg);
191 for (MachineOperand &MO : MI->operands()) {
197 MachineOperand *Op = MI->findRegisterDefOperand(Reg);
213 for (MachineOperand &MODef : Def->operands()) {
403 for (MachineOperand &MO : MI->operands()) {
624 SmallVector<MachineOperand*, 8> Uses;
635 for (SmallVectorImpl<MachineOperand *>::const_iterator I = Uses.begin(),
lib/Target/ARM/ARMAsmPrinter.cpp 187 void ARMAsmPrinter::PrintSymbolOperand(const MachineOperand &MO,
201 const MachineOperand &MO = MI->getOperand(OpNum);
205 case MachineOperand::MO_Register: {
217 case MachineOperand::MO_Immediate: {
227 case MachineOperand::MO_MachineBasicBlock:
230 case MachineOperand::MO_GlobalAddress: {
234 case MachineOperand::MO_ConstantPoolIndex:
304 const MachineOperand &MO = MI->getOperand(OpNum);
337 const MachineOperand &FlagsOP = MI->getOperand(OpNum - 1);
377 const MachineOperand &MO = MI->getOperand(OpNum);
391 const MachineOperand &MO = MI->getOperand(RegOp);
417 const MachineOperand &MO = MI->getOperand(OpNum);
454 const MachineOperand &MO = MI->getOperand(OpNum);
938 const MachineOperand &MO1 = MI->getOperand(1);
984 const MachineOperand &MO1 = MI->getOperand(1);
1014 const MachineOperand &MO1 = MI->getOperand(1);
1120 const MachineOperand &MO = MI->getOperand(i);
1380 const MachineOperand &Op = MI->getOperand(0);
lib/Target/ARM/ARMAsmPrinter.h 78 void PrintSymbolOperand(const MachineOperand &MO, raw_ostream &O) override;
106 bool lowerOperand(const MachineOperand &MO, MCOperand &MCOp);
145 MCOperand GetSymbolRef(const MachineOperand &MO, const MCSymbol *Symbol);
lib/Target/ARM/ARMBaseInstrInfo.cpp 172 const MachineOperand &WB = isLoad ? MI.getOperand(1) : MI.getOperand(0);
173 const MachineOperand &Base = MI.getOperand(2);
174 const MachineOperand &Offset = MI.getOperand(NumOps - 3);
278 MachineOperand &MO = MI.getOperand(i);
314 SmallVectorImpl<MachineOperand> &Cond,
431 ArrayRef<MachineOperand> Cond,
476 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
499 MachineInstr &MI, ArrayRef<MachineOperand> Pred) const {
511 MachineOperand &PMO = MI.getOperand(PIdx);
519 bool ARMBaseInstrInfo::SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
520 ArrayRef<MachineOperand> Pred2) const {
546 MachineInstr &MI, std::vector<MachineOperand> &Pred) const {
549 const MachineOperand &MO = MI.getOperand(i);
561 for (const auto &MO : MI.operands())
569 const MachineOperand &Offset = MI.getOperand(Op + 1);
577 const MachineOperand &Offset = MI.getOperand(Op + 1);
578 const MachineOperand &Opc = MI.getOperand(Op + 2);
589 const MachineOperand &Opc = MI.getOperand(Op + 2);
597 const MachineOperand &Opc = MI.getOperand(Op + 2);
684 const MachineOperand &MO = MI->getOperand(i);
997 const MachineOperand *&Src,
998 const MachineOperand *&Dest) const {
1523 MachineOperand LDWb(MI->getOperand(1));
1533 MachineOperand STWb(MI->getOperand(0));
1542 MachineOperand LDBase(MI->getOperand(3));
1545 MachineOperand STBase(MI->getOperand(2));
1763 const MachineOperand &MO0 = MI0.getOperand(1);
1764 const MachineOperand &MO1 = MI1.getOperand(1);
1819 const MachineOperand &MO0 = MI0.getOperand(i);
1820 const MachineOperand &MO1 = MI1.getOperand(i);
2192 const MachineOperand &MO = MI->getOperand(i);
2213 SmallVectorImpl<MachineOperand> &Cond,
2248 MachineOperand FalseReg = MI.getOperand(Invert ? 2 : 1);
2448 SmallVector<MachineOperand, 4> RegList;
2456 MachineOperand &MO = MI->getOperand(i);
2476 RegList.push_back(MachineOperand::CreateReg(CurReg, false, false,
2498 RegList.push_back(MachineOperand::CreateReg(CurReg, true, false, false,
2636 MachineOperand &ImmOp = MI.getOperand(ImmIdx);
3049 SmallVector<std::pair<MachineOperand*, ARMCC::CondCodes>, 4>
3058 const MachineOperand &MO = Instr.getOperand(IO);
3218 const MachineOperand &MO = DefMI.getOperand(NumOps - 1);
3791 const auto &Op = MI.getOperand(i);
4262 const MachineOperand &DefMO = DefMI.getOperand(DefIdx);
4292 const MachineOperand &DefMO, unsigned Reg, const MachineInstr &UseMI,
5145 const MachineOperand &MO = MI.getOperand(OpNum);
5202 const MachineOperand &MO = MI.getOperand(OpNum);
5262 const MachineOperand *MOReg = &MI.getOperand(1);
5288 const MachineOperand &MOReg = MI.getOperand(2);
5308 const MachineOperand &MOBaseReg = MI.getOperand(1);
5309 const MachineOperand &MOInsertedReg = MI.getOperand(2);
5312 const MachineOperand &MOIndex = MI.getOperand(3);
lib/Target/ARM/ARMBaseInstrInfo.h 106 bool isCopyInstrImpl(const MachineInstr &MI, const MachineOperand *&Source,
107 const MachineOperand *&Destination) const override;
135 SmallVectorImpl<MachineOperand> &Cond,
140 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
145 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
157 ArrayRef<MachineOperand> Pred) const override;
159 bool SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
160 ArrayRef<MachineOperand> Pred2) const override;
163 std::vector<MachineOperand> &Pred) const override;
303 SmallVectorImpl<MachineOperand> &Cond, unsigned &TrueOp,
375 const MachineOperand &DefMO, unsigned Reg,
463 static inline std::array<MachineOperand, 2> predOps(ARMCC::CondCodes Pred,
465 return {{MachineOperand::CreateImm(static_cast<int64_t>(Pred)),
466 MachineOperand::CreateReg(PredReg, false)}};
471 static inline MachineOperand condCodeOp(unsigned CCReg = 0) {
472 return MachineOperand::CreateReg(CCReg, false);
478 static inline MachineOperand t1CondCodeOp(bool isDead = false) {
479 return MachineOperand::CreateReg(ARM::CPSR,
lib/Target/ARM/ARMBaseRegisterInfo.cpp 513 const MachineOperand &OffOp = MI->getOperand(Idx+1);
lib/Target/ARM/ARMConstantIslandPass.cpp 592 MachineOperand JTOp =
631 SmallVector<MachineOperand, 4> Cond;
2061 const MachineOperand &MO = I->getOperand(K);
2080 const MachineOperand &MO = I->getOperand(K);
2141 const MachineOperand &MO = J->getOperand(K);
2172 MachineOperand JTOP = MI->getOperand(JTOpIdx);
2366 MachineOperand JTOP = MI->getOperand(JTOpIdx);
2401 SmallVector<MachineOperand, 4> Cond;
2402 SmallVector<MachineOperand, 4> CondPrior;
lib/Target/ARM/ARMExpandPseudoInsts.cpp 97 const MachineOperand &MO = OldMI.getOperand(i);
527 const MachineOperand &AM6Offset = MI.getOperand(OpIdx++);
564 MachineOperand MO = MI.getOperand(SrcOpIdx);
608 const MachineOperand &AM6Offset = MI.getOperand(OpIdx++);
709 MachineOperand MO = MI.getOperand(OpIdx++);
758 MachineOperand VdSrc(MI.getOperand(OpIdx++));
769 MachineOperand VmSrc(MI.getOperand(OpIdx++));
783 static bool IsAnAddressOperand(const MachineOperand &MO) {
788 case MachineOperand::MO_Register:
789 case MachineOperand::MO_Immediate:
790 case MachineOperand::MO_CImmediate:
791 case MachineOperand::MO_FPImmediate:
792 case MachineOperand::MO_ShuffleMask:
794 case MachineOperand::MO_MachineBasicBlock:
796 case MachineOperand::MO_FrameIndex:
798 case MachineOperand::MO_ConstantPoolIndex:
799 case MachineOperand::MO_TargetIndex:
800 case MachineOperand::MO_JumpTableIndex:
801 case MachineOperand::MO_ExternalSymbol:
802 case MachineOperand::MO_GlobalAddress:
803 case MachineOperand::MO_BlockAddress:
805 case MachineOperand::MO_RegisterMask:
806 case MachineOperand::MO_RegisterLiveOut:
808 case MachineOperand::MO_Metadata:
809 case MachineOperand::MO_MCSymbol:
811 case MachineOperand::MO_CFIIndex:
813 case MachineOperand::MO_IntrinsicID:
814 case MachineOperand::MO_Predicate:
820 static MachineOperand makeImplicit(const MachineOperand &MO) {
820 static MachineOperand makeImplicit(const MachineOperand &MO) {
821 MachineOperand NewMO = MO;
835 const MachineOperand &MO = MI.getOperand(isCC ? 2 : 1);
884 case MachineOperand::MO_Immediate: {
892 case MachineOperand::MO_ExternalSymbol: {
935 const MachineOperand &Dest = MI.getOperand(0);
1035 static void addExclusiveRegPair(MachineInstrBuilder &MIB, MachineOperand &Reg,
1054 MachineOperand &Dest = MI.getOperand(0);
1061 MachineOperand New = MI.getOperand(4);
1174 MachineOperand &JumpTarget = MBBI->getOperand(0);
1474 const MachineOperand &MO1 = MI.getOperand(1);
1532 const MachineOperand &MO1 = MI.getOperand(1);
1628 MachineOperand Dst(MI.getOperand(OpIdx++));
lib/Target/ARM/ARMFastISel.cpp 255 for (const MachineOperand &MO : MI->operands()) {
lib/Target/ARM/ARMISelLowering.cpp10411 MachineOperand Def(MI.getOperand(1));
10745 MI.addOperand(MachineOperand::CreateReg(0, /*isDef=*/true));
10756 const MachineOperand& op = MI.getOperand(i);
10764 MI.addOperand(MachineOperand::CreateImm(ARMCC::AL));
10765 MI.addOperand(MachineOperand::CreateReg(0, /*isDef=*/false));
10784 const MachineOperand &MO = MI.getOperand(i);
10808 MachineOperand &MO = MI.getOperand(ccOutIdx);
lib/Target/ARM/ARMInstructionSelector.cpp 966 auto &Val = I.getOperand(1);
lib/Target/ARM/ARMLoadStoreOptimizer.cpp 204 for (const auto &MO : MI.operands()) {
244 static const MachineOperand &getLoadStoreBaseOp(const MachineInstr &MI) {
248 static const MachineOperand &getLoadStoreRegOp(const MachineInstr &MI) {
506 MachineOperand &MO =
523 MachineOperand &MO =
861 const MachineOperand &MO = getLoadStoreRegOp(*MI);
873 for (const MachineOperand &MO : MI->implicit_operands()) {
938 for (MachineOperand &MO : MI.implicit_operands()) {
956 for (MachineOperand &MO : MI.uses()) {
1007 const MachineOperand &PMO = getLoadStoreRegOp(*MI);
1054 const MachineOperand &MO = getLoadStoreRegOp(*MemOps[I].MI);
1263 const MachineOperand &BaseOP = MI->getOperand(0);
1440 MachineOperand &MO = MI->getOperand(0);
1476 MachineOperand &MO = MI->getOperand(0);
1514 const MachineOperand &BaseOp = MI.getOperand(2);
1516 const MachineOperand &Reg0Op = MI.getOperand(0);
1517 const MachineOperand &Reg1Op = MI.getOperand(1);
1555 for (const MachineOperand &MO : MI.implicit_operands())
1657 const MachineOperand &BaseOp = MI->getOperand(2);
1785 const MachineOperand &MO = MBBI->getOperand(0);
1943 MachineOperand &MO = PrevMI.getOperand(PrevMI.getNumOperands() - 1);
1981 for (auto Use : Prev->uses())
2121 MachineOperand &MO = I->getOperand(j);
lib/Target/ARM/ARMLowOverheadLoops.cpp 122 for (auto &MO : MI.operands()) {
135 for (auto &MO : MI.operands()) {
293 for (auto &MO : MI.operands()) {
lib/Target/ARM/ARMMCInstLower.cpp 38 MCOperand ARMAsmPrinter::GetSymbolRef(const MachineOperand &MO,
72 bool ARMAsmPrinter::lowerOperand(const MachineOperand &MO,
76 case MachineOperand::MO_Register:
83 case MachineOperand::MO_Immediate:
86 case MachineOperand::MO_MachineBasicBlock:
90 case MachineOperand::MO_GlobalAddress:
94 case MachineOperand::MO_ExternalSymbol:
98 case MachineOperand::MO_JumpTableIndex:
101 case MachineOperand::MO_ConstantPoolIndex:
106 case MachineOperand::MO_BlockAddress:
109 case MachineOperand::MO_FPImmediate: {
116 case MachineOperand::MO_RegisterMask:
155 for (const MachineOperand &MO : MI->operands()) {
lib/Target/ARM/ARMRegisterBankInfo.cpp 455 const MachineOperand &MaybeReg = MI.getOperand(0);
lib/Target/ARM/Thumb1FrameLowering.cpp 641 for (auto MO: MBBI->operands())
756 for (auto MO: MBBI->operands())
978 for (auto Op : Terminator->implicit_operands()) {
lib/Target/ARM/Thumb2ITBlockPass.cpp 87 for (auto &MO : MI->operands()) {
114 for (MachineOperand &MO : MI->operands()) {
218 MI->addOperand(MachineOperand::CreateReg(ARM::ITSTATE, false/*ifDef*/,
247 NMI->addOperand(MachineOperand::CreateReg(ARM::ITSTATE, false/*ifDef*/,
lib/Target/ARM/Thumb2InstrInfo.cpp 514 MI.addOperand(MachineOperand::CreateReg(0, false));
545 MI.addOperand(MachineOperand::CreateReg(0, false));
585 const MachineOperand &OffOp = MI.getOperand(FrameRegIdx+1);
599 const MachineOperand &OffOp = MI.getOperand(FrameRegIdx+1);
643 MachineOperand &ImmOp = MI.getOperand(FrameRegIdx+1);
lib/Target/ARM/Thumb2SizeReduction.cpp 300 for (const MachineOperand &MO : CPSRDef->operands()) {
309 for (const MachineOperand &MO : Use->operands()) {
380 const MachineOperand &MO = MI->getOperand(i);
869 const MachineOperand &MO = MI->getOperand(i);
951 const MachineOperand &MO = MI->getOperand(i);
974 for (const MachineOperand &MO : MI.operands()) {
989 for (const MachineOperand &MO : MI.operands()) {
1090 MachineOperand *MO = BundleMI->findRegisterDefOperand(ARM::CPSR);
lib/Target/ARM/ThumbRegisterInfo.cpp 394 MachineOperand &ImmOp = MI.getOperand(ImmIdx);
lib/Target/AVR/AVRAsmPrinter.cpp 62 const MachineOperand &MO = MI->getOperand(OpNo);
65 case MachineOperand::MO_Register:
68 case MachineOperand::MO_Immediate:
71 case MachineOperand::MO_GlobalAddress:
74 case MachineOperand::MO_ExternalSymbol:
77 case MachineOperand::MO_MachineBasicBlock:
96 const MachineOperand &RegOp = MI->getOperand(OpNum);
143 const MachineOperand &MO = MI->getOperand(OpNum);
lib/Target/AVR/AVRExpandPseudoInsts.cpp 290 case MachineOperand::MO_GlobalAddress: {
298 case MachineOperand::MO_Immediate: {
501 case MachineOperand::MO_GlobalAddress: {
510 case MachineOperand::MO_BlockAddress: {
514 MIBLO.add(MachineOperand::CreateBA(BA, TF | AVRII::MO_LO));
515 MIBHI.add(MachineOperand::CreateBA(BA, TF | AVRII::MO_HI));
518 case MachineOperand::MO_Immediate: {
550 case MachineOperand::MO_GlobalAddress: {
559 case MachineOperand::MO_Immediate: {
826 auto Op1 = MI.getOperand(0);
827 auto Op2 = MI.getOperand(1);
846 auto Op1 = MI.getOperand(0);
847 auto Op2 = MI.getOperand(1);
875 for (MachineOperand &MO : MI.operands()) {
982 case MachineOperand::MO_GlobalAddress: {
991 case MachineOperand::MO_Immediate: {
lib/Target/AVR/AVRFrameLowering.cpp 469 for (const MachineOperand &MO : MI.operands()) {
lib/Target/AVR/AVRInstrInfo.cpp 266 SmallVectorImpl<MachineOperand> &Cond,
371 Cond.push_back(MachineOperand::CreateImm(BranchCode));
401 ArrayRef<MachineOperand> Cond,
467 SmallVectorImpl<MachineOperand> &Cond) const {
lib/Target/AVR/AVRInstrInfo.h 94 SmallVectorImpl<MachineOperand> &Cond,
97 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
103 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
lib/Target/AVR/AVRMCInstLower.cpp 26 MCOperand AVRMCInstLower::lowerSymbolOperand(const MachineOperand &MO,
65 for (MachineOperand const &MO : MI.operands()) {
72 case MachineOperand::MO_Register:
78 case MachineOperand::MO_Immediate:
81 case MachineOperand::MO_GlobalAddress:
84 case MachineOperand::MO_ExternalSymbol:
88 case MachineOperand::MO_MachineBasicBlock:
92 case MachineOperand::MO_RegisterMask:
94 case MachineOperand::MO_BlockAddress:
98 case MachineOperand::MO_JumpTableIndex:
101 case MachineOperand::MO_ConstantPoolIndex:
lib/Target/AVR/AVRMCInstLower.h 32 MCOperand lowerSymbolOperand(const MachineOperand &MO, MCSymbol *Sym) const;
lib/Target/AVR/AVRRelaxMemOperations.cpp 91 MachineOperand &Ptr = MI.getOperand(0);
92 MachineOperand &Src = MI.getOperand(2);
lib/Target/BPF/BPFAsmPrinter.cpp 74 const MachineOperand &MO = MI->getOperand(OpNum);
77 case MachineOperand::MO_Register:
81 case MachineOperand::MO_Immediate:
85 case MachineOperand::MO_MachineBasicBlock:
89 case MachineOperand::MO_GlobalAddress:
93 case MachineOperand::MO_BlockAddress: {
99 case MachineOperand::MO_ExternalSymbol:
103 case MachineOperand::MO_JumpTableIndex:
104 case MachineOperand::MO_ConstantPoolIndex:
123 const MachineOperand &BaseMO = MI->getOperand(OpNum);
124 const MachineOperand &OffsetMO = MI->getOperand(OpNum + 1);
lib/Target/BPF/BPFInstrInfo.cpp 167 SmallVectorImpl<MachineOperand> &Cond,
222 ArrayRef<MachineOperand> Cond,
lib/Target/BPF/BPFInstrInfo.h 50 SmallVectorImpl<MachineOperand> &Cond,
56 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
lib/Target/BPF/BPFMCInstLower.cpp 27 BPFMCInstLower::GetGlobalAddressSymbol(const MachineOperand &MO) const {
32 BPFMCInstLower::GetExternalSymbolSymbol(const MachineOperand &MO) const {
36 MCOperand BPFMCInstLower::LowerSymbolOperand(const MachineOperand &MO,
51 const MachineOperand &MO = MI->getOperand(i);
58 case MachineOperand::MO_Register:
64 case MachineOperand::MO_Immediate:
67 case MachineOperand::MO_MachineBasicBlock:
71 case MachineOperand::MO_RegisterMask:
73 case MachineOperand::MO_ExternalSymbol:
76 case MachineOperand::MO_GlobalAddress:
lib/Target/BPF/BPFMCInstLower.h 36 MCOperand LowerSymbolOperand(const MachineOperand &MO, MCSymbol *Sym) const;
38 MCSymbol *GetGlobalAddressSymbol(const MachineOperand &MO) const;
39 MCSymbol *GetExternalSymbolSymbol(const MachineOperand &MO) const;
lib/Target/BPF/BPFMIChecking.cpp 112 for (const MachineOperand &MO : MI.operands()) {
lib/Target/BPF/BPFMIPeephole.cpp 90 MachineOperand &opnd = DefInsn->getOperand(i);
103 MachineOperand &opnd = DefInsn->getOperand(1);
417 MachineOperand &opnd = DefMI->getOperand(i);
lib/Target/BPF/BPFMISimplifyPatchable.cpp 109 const MachineOperand &MO = DefInst->getOperand(1);
lib/Target/BPF/BTFDebug.cpp 988 const MachineOperand &MO = MI->getOperand(1);
1125 const MachineOperand &MO = MI->getOperand(1);
lib/Target/Hexagon/BitTracker.cpp 803 const MachineOperand &MD = PI.getOperand(0);
855 const MachineOperand &MO = MI.getOperand(i);
872 for (const MachineOperand &MO : MI.operands()) {
lib/Target/Hexagon/BitTracker.h 143 RegisterRef(const MachineOperand &MO)
lib/Target/Hexagon/HexagonAsmPrinter.cpp 77 const MachineOperand &MO = MI->getOperand(OpNo);
82 case MachineOperand::MO_Register:
85 case MachineOperand::MO_Immediate:
88 case MachineOperand::MO_MachineBasicBlock:
91 case MachineOperand::MO_ConstantPoolIndex:
94 case MachineOperand::MO_GlobalAddress:
128 const MachineOperand &MO = MI->getOperand(OpNo);
162 const MachineOperand &Base = MI->getOperand(OpNo);
163 const MachineOperand &Offset = MI->getOperand(OpNo+1);
216 const MachineOperand &MO = MI.getOperand(1);
lib/Target/Hexagon/HexagonBitSimplify.cpp 1015 for (auto &Op : MI->operands()) {
1325 for (auto &Op : MI->uses()) {
1918 MachineOperand &ValOp = MI->getOperand(2);
1955 MachineOperand &OffOp = MI->getOperand(1);
2004 MI->addOperand(MachineOperand::CreateImm(V));
2139 for (auto &Op : MI->uses()) {
2280 MachineOperand &Op1 = In->getOperand(1);
2286 MachineOperand &Op0 = In->getOperand(0);
2534 const MachineOperand &SrcOp = MI->getOperand(1);
2580 MachineOperand &CmpOp = MI->getOperand(2);
2663 MachineOperand &Src1 = InpDef->getOperand(2);
2664 MachineOperand &Src2 = InpDef->getOperand(3);
2722 const MachineOperand &Op0 = MI->getOperand(0);
2948 const MachineOperand &OpB = P.getOperand(i+1);
3011 const MachineOperand &Op = MI->getOperand(i);
3088 const MachineOperand &Op = SI->getOperand(j);
lib/Target/Hexagon/HexagonBitTracker.cpp 168 const MachineOperand &MO = MI.getOperand(i);
195 for (const MachineOperand &MO : MI.operands()) {
244 for (const MachineOperand &MO : MI.operands()) {
268 const MachineOperand &Op = MI.getOperand(N);
1042 for (const MachineOperand &Op : MI.operands()) {
1189 const MachineOperand &MD = MI.getOperand(0);
lib/Target/Hexagon/HexagonBlockRanges.cpp 320 for (auto &Op : In.operands()) {
336 for (auto &Op : In.operands()) {
350 for (auto &Op : In.operands()) {
lib/Target/Hexagon/HexagonBranchRelaxation.cpp 162 SmallVector<MachineOperand, 4> Cond;
212 MachineOperand &MO = MI.getOperand(ExtOpNum);
lib/Target/Hexagon/HexagonConstExtenders.cpp 232 Register(const MachineOperand &Op)
234 Register &operator=(const MachineOperand &Op) {
250 operator MachineOperand() const {
252 return MachineOperand::CreateReg(Reg, /*Def*/false, /*Imp*/false,
257 return MachineOperand::CreateFI(FI);
330 MachineOperand &getOp() {
333 const MachineOperand &getOp() const {
350 ExtRoot(const MachineOperand &Op);
363 ExtValue(const MachineOperand &Op);
373 explicit operator MachineOperand() const;
411 const MachineOperand &Op) const;
412 const MachineOperand &getPredicateOp(const MachineInstr &MI) const;
413 const MachineOperand &getLoadResultOp(const MachineInstr &MI) const;
414 const MachineOperand &getStoredValueOp(const MachineInstr &MI) const;
510 case MachineOperand::MO_Immediate:
513 case MachineOperand::MO_FPImmediate:
516 case MachineOperand::MO_ExternalSymbol:
519 case MachineOperand::MO_GlobalAddress:
522 case MachineOperand::MO_BlockAddress:
525 case MachineOperand::MO_TargetIndex:
528 case MachineOperand::MO_ConstantPoolIndex:
531 case MachineOperand::MO_JumpTableIndex:
695 HCE::ExtRoot::ExtRoot(const MachineOperand &Op) {
721 case MachineOperand::MO_Immediate:
722 case MachineOperand::MO_TargetIndex:
723 case MachineOperand::MO_ConstantPoolIndex:
724 case MachineOperand::MO_JumpTableIndex:
726 case MachineOperand::MO_FPImmediate: {
731 case MachineOperand::MO_ExternalSymbol:
733 case MachineOperand::MO_GlobalAddress:
740 case MachineOperand::MO_BlockAddress: {
752 HCE::ExtValue::ExtValue(const MachineOperand &Op) : ExtRoot(Op) {
771 HCE::ExtValue::operator MachineOperand() const {
773 case MachineOperand::MO_Immediate:
774 return MachineOperand::CreateImm(V.ImmVal + Offset);
775 case MachineOperand::MO_FPImmediate:
777 return MachineOperand::CreateFPImm(V.CFP);
778 case MachineOperand::MO_ExternalSymbol:
780 return MachineOperand::CreateES(V.SymbolName, TF);
781 case MachineOperand::MO_GlobalAddress:
782 return MachineOperand::CreateGA(V.GV, Offset, TF);
783 case MachineOperand::MO_BlockAddress:
784 return MachineOperand::CreateBA(V.BA, Offset, TF);
785 case MachineOperand::MO_TargetIndex:
786 return MachineOperand::CreateTargetIndex(V.ImmVal, Offset, TF);
787 case MachineOperand::MO_ConstantPoolIndex:
788 return MachineOperand::CreateCPI(V.ImmVal, Offset, TF);
789 case MachineOperand::MO_JumpTableIndex:
791 return MachineOperand::CreateJTI(V.ImmVal, TF);
1055 const MachineOperand &Op1 = MI.getOperand(1), &Op2 = MI.getOperand(2);
1129 for (const MachineOperand &Op : MRI->use_operands(Rd.Reg)) {
1151 for (MachineOperand &Op : MI.operands())
1221 if (ER.Kind == MachineOperand::MO_GlobalAddress)
1533 MachineOperand ExtOp(EV);
1759 const MachineOperand &RegOp = MI.getOperand(IsAddi ? 1 : 2);
1760 const MachineOperand &ImmOp = MI.getOperand(IsAddi ? 2 : 1);
1858 for (MachineOperand &Op : MRI->use_operands(ED.Rd.Reg)) {
1877 MachineOperand &ImmOp = P.first->getOperand(J+1);
1915 const MachineOperand &Op) const {
1922 const MachineOperand &HCE::getPredicateOp(const MachineInstr &MI) const {
1924 for (const MachineOperand &Op : MI.operands()) {
1934 const MachineOperand &HCE::getLoadResultOp(const MachineInstr &MI) const {
1939 const MachineOperand &HCE::getStoredValueOp(const MachineInstr &MI) const {
lib/Target/Hexagon/HexagonConstPropagation.cpp 89 explicit RegisterSubReg(const MachineOperand &MO)
624 const MachineOperand &MD = PN.getOperand(0);
651 const MachineOperand &SO = PN.getOperand(i);
692 for (const MachineOperand &MO : MI.operands()) {
1850 const MachineOperand &MO);
1858 bool evaluateHexCompare2(uint32_t Cmp, const MachineOperand &Src1,
1859 const MachineOperand &Src2, const CellMap &Inputs, bool &Result);
1922 const MachineOperand &MD = MI.getOperand(0);
1953 const MachineOperand &OpLo = LoIs1 ? MI.getOperand(1) : MI.getOperand(3);
1954 const MachineOperand &OpHi = LoIs1 ? MI.getOperand(3) : MI.getOperand(1);
1976 const MachineOperand &VO = MI.getOperand(1);
2284 const MachineOperand &MD = BrI.getOperand(0);
2459 const MachineOperand &MO) {
2567 const MachineOperand &Src1 = MI.getOperand(1);
2568 const MachineOperand &Src2 = MI.getOperand(2);
2590 const MachineOperand &Src1, const MachineOperand &Src2,
2590 const MachineOperand &Src1, const MachineOperand &Src2,
2624 const MachineOperand &Src1 = MI.getOperand(1);
2625 const MachineOperand &Src2 = MI.getOperand(2);
2683 const MachineOperand &ValOp = MI.getOperand(TakeOp);
2792 for (const MachineOperand &MO : MI.operands()) {
2813 for (const MachineOperand &MO : MI.operands()) {
2831 for (const MachineOperand &MO : MI.operands()) {
2977 MachineOperand &Acc = MI.getOperand(1);
3000 const MachineOperand &OpR2 = Swap ? MI.getOperand(3)
3013 const MachineOperand &Src1 = MI.getOperand(1);
3043 MachineOperand &SO = MI.getOperand(CopyOf);
3075 MachineOperand &SO = MI.getOperand(CopyOf);
3094 for (MachineOperand &MO : NewMI->operands())
3117 MachineOperand &O = *I;
3159 for (auto &Op : NI->operands())
lib/Target/Hexagon/HexagonCopyToCombine.cpp 132 const MachineOperand &Op0 = MI.getOperand(0);
133 const MachineOperand &Op1 = MI.getOperand(1);
145 const MachineOperand &Op0 = MI.getOperand(0);
146 const MachineOperand &Op1 = MI.getOperand(1);
175 const MachineOperand &Op = I.getOperand(1);
239 MachineOperand &Op = MI.getOperand(I);
257 static Register UseReg(const MachineOperand& MO) {
406 MachineOperand &Op = MI.getOperand(OpdIdx);
441 for (MachineOperand &Op : MI.operands()) {
604 MachineOperand &LoOperand = IsI1Loreg ? I1.getOperand(1) : I2.getOperand(1);
605 MachineOperand &HiOperand = IsI1Loreg ? I2.getOperand(1) : I1.getOperand(1);
lib/Target/Hexagon/HexagonEarlyIfConv.cpp 384 for (const MachineOperand &MO : MI.operands()) {
401 for (const MachineOperand &MO : MI->operands()) {
471 const MachineOperand &RA = MI.getOperand(1);
472 const MachineOperand &RB = MI.getOperand(3);
491 for (const MachineOperand &MO : MI.operands()) {
729 for (const MachineOperand &MO : make_range(MOI, MI->operands_end()))
819 const MachineOperand &RO = PN->getOperand(i), &BO = PN->getOperand(i+1);
852 PN->addOperand(MachineOperand::CreateReg(MuxR, false, false, false, false,
854 PN->addOperand(MachineOperand::CreateMBB(FP.SplitB));
990 MachineOperand &UO = PN->getOperand(1);
lib/Target/Hexagon/HexagonExpandCondsets.cpp 177 RegisterRef(const MachineOperand &Op) : Reg(Op.getReg()),
211 unsigned getCondTfrOpcode(const MachineOperand &SO, bool Cond);
212 MachineInstr *genCondTfrFor(MachineOperand &SrcOp,
223 void predicateAt(const MachineOperand &DefOp, MachineInstr &MI,
319 MachineOperand &Op = MI->getOperand(i);
473 for (auto &Op : DefI->operands()) {
497 MachineOperand &Op = DefI->getOperand(i);
577 unsigned HexagonExpandCondsets::getCondTfrOpcode(const MachineOperand &SO,
603 case MachineOperand::MO_Immediate:
604 case MachineOperand::MO_FPImmediate:
605 case MachineOperand::MO_ConstantPoolIndex:
606 case MachineOperand::MO_TargetIndex:
607 case MachineOperand::MO_JumpTableIndex:
608 case MachineOperand::MO_ExternalSymbol:
609 case MachineOperand::MO_GlobalAddress:
610 case MachineOperand::MO_BlockAddress:
622 MachineInstr *HexagonExpandCondsets::genCondTfrFor(MachineOperand &SrcOp,
671 MachineOperand &MD = MI.getOperand(0); // Definition
672 MachineOperand &MP = MI.getOperand(1); // Predicate register
687 MachineOperand &ST = MI.getOperand(2);
688 MachineOperand &SF = MI.getOperand(3);
728 for (auto &Op : MI->operands()) {
764 for (auto &Op : MI->operands()) {
798 for (auto &Op : MI.operands()) {
853 void HexagonExpandCondsets::predicateAt(const MachineOperand &DefOp,
877 MachineOperand &MO = MI.getOperand(Ox);
888 MachineOperand &MO = MI.getOperand(Ox);
899 for (auto &Op : NewI->operands())
920 for (auto &Op : MI->operands()) {
943 MachineOperand &MD = TfrI.getOperand(0);
944 MachineOperand &MP = TfrI.getOperand(1);
945 MachineOperand &MS = TfrI.getOperand(2);
991 for (auto &Op : MI->operands()) {
1081 for (auto &Op : I->operands())
1193 MachineOperand &S1 = MI->getOperand(2), &S2 = MI->getOperand(3);
1203 MachineOperand &S1 = CI->getOperand(2), &S2 = CI->getOperand(3);
1283 for (MachineOperand &Op : MI->operands())
lib/Target/Hexagon/HexagonFrameLowering.cpp 297 for (const MachineOperand &MO : MI->operands()) {
538 RetI->addOperand(MachineOperand::CreateReg(R.getReg(), false, true));
820 RetI.addOperand(MachineOperand::CreateReg(R.getReg(), false, true));
1741 SmallVector<std::pair<MCPhysReg, const MachineOperand*>,2> Clobbers;
2116 const MachineOperand &Op = In.getOperand(i);
2251 MachineOperand &SrcOp = SI.getOperand(2);
2351 MachineOperand &RdOp = AI->getOperand(0);
2352 MachineOperand &RsOp = AI->getOperand(1);
2413 MI->addOperand(MachineOperand::CreateReg(R.getReg(), IsDef, true, IsKill));
lib/Target/Hexagon/HexagonGenInsert.cpp 607 const MachineOperand &MO = MI->getOperand(i);
724 const MachineOperand &MO = MI->getOperand(i);
737 const MachineOperand &MO = MI->getOperand(i);
1477 for (const MachineOperand &MO : MI->operands()) {
lib/Target/Hexagon/HexagonGenMux.cpp 109 MachineOperand *SrcT, *SrcF;
134 unsigned getMuxOpcode(const MachineOperand &Src1,
135 const MachineOperand &Src2) const;
171 for (const MachineOperand &MO : MI->operands()) {
208 unsigned HexagonGenMux::getMuxOpcode(const MachineOperand &Src1,
209 const MachineOperand &Src2) const {
245 MachineOperand &PredOp = MI->getOperand(1);
305 MachineOperand *Src1 = &Def1.getOperand(2), *Src2 = &Def2.getOperand(2);
323 MachineOperand *SrcT = (MinX == CI.TrueX) ? Src1 : Src2;
324 MachineOperand *SrcF = (MinX == CI.FalseX) ? Src1 : Src2;
364 for (MachineOperand &Op : I->operands()) {
lib/Target/Hexagon/HexagonGenPredicate.cpp 53 RegisterSubReg(const MachineOperand &MO) : R(MO.getReg()), S(MO.getSubReg()) {}
353 for (const MachineOperand &MO : DefI->operands())
374 MachineOperand &MO = MI->getOperand(i);
413 MachineOperand &Op0 = MI->getOperand(0);
lib/Target/Hexagon/HexagonHardwareLoops.cpp 187 MachineOperand *InitialValue,
188 const MachineOperand *Endvalue,
204 CountValue *computeCount(MachineLoop *Loop, const MachineOperand *Start,
205 const MachineOperand *End, unsigned IVReg,
238 const MachineOperand *MO,
243 bool phiMayWrapOrUnderflow(MachineInstr *Phi, const MachineOperand *EndVal,
249 bool loopCountMayWrapOrUnderFlow(const MachineOperand *InitVal,
250 const MachineOperand *EndVal,
257 bool checkForImmediate(const MachineOperand &MO, int64_t &Val) const;
260 bool isImmediate(const MachineOperand &MO) const {
266 int64_t getImmediate(const MachineOperand &MO) const {
276 void setImmediate(MachineOperand &MO, int64_t Val);
445 MachineOperand &Opnd2 = DI->getOperand(2);
455 SmallVector<MachineOperand,2> Cond;
508 MachineOperand *InitialValue,
509 const MachineOperand *EndValue,
603 MachineOperand *InitialValue = nullptr;
616 SmallVector<MachineOperand,2> Cond;
629 SmallVector<MachineOperand,2> LCond;
672 const MachineOperand &Op1 = CondI->getOperand(1);
673 const MachineOperand &Op2 = CondI->getOperand(2);
674 const MachineOperand *EndValue = nullptr;
725 const MachineOperand *Start,
726 const MachineOperand *End,
1037 const MachineOperand &MO = MI->getOperand(i);
1057 const MachineOperand &OPO = OnePhi->getOperand(j);
1066 MachineOperand &Use = *J;
1092 const MachineOperand &MO = MI->getOperand(i);
1100 MachineOperand &Use = *I;
1224 SmallVector<MachineOperand, 2> Cond;
1293 SmallVector<MachineOperand, 0> Cond;
1342 MachineOperand &MO = In->getOperand(i);
1366 const MachineOperand *MO,
1387 MachineInstr *Phi, const MachineOperand *EndVal, MachineBasicBlock *MBB,
1415 const MachineOperand *InitVal, const MachineOperand *EndVal,
1415 const MachineOperand *InitVal, const MachineOperand *EndVal,
1464 SmallVector<MachineOperand, 2> Cond;
1497 bool HexagonHardwareLoops::checkForImmediate(const MachineOperand &MO,
1533 const MachineOperand &S1 = DI->getOperand(1);
1534 const MachineOperand &S2 = DI->getOperand(2);
1542 const MachineOperand &S1 = DI->getOperand(1);
1543 const MachineOperand &S3 = DI->getOperand(3);
1578 void HexagonHardwareLoops::setImmediate(MachineOperand &MO, int64_t Val) {
1644 MachineOperand &Opnd2 = DI->getOperand(2);
1658 SmallVector<MachineOperand,2> Cond;
1666 SmallVector<MachineOperand,2> LCond;
1712 MachineOperand *CmpImmOp = nullptr;
1719 MachineOperand &MO = PredDef->getOperand(i);
1764 MachineOperand *IndMO = nullptr;
1765 MachineOperand *nonIndMO = nullptr;
1768 MachineOperand &MO = PredDef->getOperand(i);
1835 MachineOperand &MO = PredDef->getOperand(i);
1876 SmallVector<MachineOperand,2> Tmp1;
1909 NewPN->addOperand(MachineOperand::CreateReg(NewPR, true));
1920 MachineOperand MO = MachineOperand::CreateReg(PredR, false);
1920 MachineOperand MO = MachineOperand::CreateReg(PredR, false);
1923 NewPN->addOperand(MachineOperand::CreateMBB(PredB));
1935 PN->addOperand(MachineOperand::CreateReg(NewPR, false));
1936 PN->addOperand(MachineOperand::CreateMBB(NewPH));
1950 MachineOperand &MO = PN->getOperand(i+1);
1960 SmallVector<MachineOperand,1> Tmp2;
1961 SmallVector<MachineOperand,1> EmptyCond;
lib/Target/Hexagon/HexagonHazardRecognizer.cpp 50 MachineOperand &MO = MI->getOperand(MI->getNumOperands() - 1);
115 for (const MachineOperand &MO : MI->operands())
lib/Target/Hexagon/HexagonInstrInfo.cpp 191 const MachineOperand &MO = MI.getOperand(i);
254 const MachineOperand OpFI = MI.getOperand(1);
257 const MachineOperand OpOff = MI.getOperand(2);
268 const MachineOperand OpFI = MI.getOperand(2);
271 const MachineOperand OpOff = MI.getOperand(3);
302 const MachineOperand &OpFI = MI.getOperand(0);
305 const MachineOperand &OpOff = MI.getOperand(1);
320 const MachineOperand &OpFI = MI.getOperand(1);
323 const MachineOperand &OpOff = MI.getOperand(2);
388 SmallVectorImpl<MachineOperand> &Cond,
483 Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
489 Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
496 Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
513 Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode()));
524 Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode()));
544 Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode()));
581 ArrayRef<MachineOperand> Cond,
603 SmallVector<MachineOperand, 4> Cond;
644 const MachineOperand &RO = Cond[1];
668 const MachineOperand &RO = Cond[1];
707 SmallVectorImpl<MachineOperand> &Cond) override {
715 Cond.push_back(MachineOperand::CreateImm(Hexagon::J2_jumpf));
1045 MachineOperand &MD = MI.getOperand(0);
1046 MachineOperand &MS = MI.getOperand(1);
1228 const MachineOperand &Op0 = MI.getOperand(0);
1229 const MachineOperand &Op1 = MI.getOperand(1);
1230 const MachineOperand &Op2 = MI.getOperand(2);
1231 const MachineOperand &Op3 = MI.getOperand(3);
1252 const MachineOperand &Op0 = MI.getOperand(0);
1253 const MachineOperand &Op1 = MI.getOperand(1);
1254 const MachineOperand &Op2 = MI.getOperand(2);
1255 const MachineOperand &Op3 = MI.getOperand(3);
1286 MachineOperand &Op0 = MI.getOperand(0);
1287 MachineOperand &Op1 = MI.getOperand(1);
1288 MachineOperand &Op2 = MI.getOperand(2);
1289 MachineOperand &Op3 = MI.getOperand(3);
1523 SmallVectorImpl<MachineOperand> &Cond) const {
1561 MachineInstr &MI, ArrayRef<MachineOperand> Cond) const {
1582 MachineOperand &Op = MI.getOperand(NOp);
1611 bool HexagonInstrInfo::SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
1612 ArrayRef<MachineOperand> Pred2) const {
1618 std::vector<MachineOperand> &Pred) const {
1622 MachineOperand MO = MI.getOperand(oper);
1841 const MachineOperand &Op2 = MI.getOperand(2);
1883 const MachineOperand &BaseA = MIa.getOperand(BasePosA);
1891 const MachineOperand &BaseB = MIb.getOperand(BasePosB);
1903 const MachineOperand &OffA = MIa.getOperand(OffsetPosA);
1904 const MachineOperand &OffB = MIb.getOperand(OffsetPosB);
1932 const MachineOperand &OffsetOp = MI.getOperand(OffsetPos);
1938 const MachineOperand &AddOp = MI.getOperand(2);
2043 const MachineOperand &MO = MI.getOperand(ExtOpNum);
2163 case MachineOperand::MO_MachineBasicBlock:
2164 case MachineOperand::MO_GlobalAddress:
2165 case MachineOperand::MO_ExternalSymbol:
2166 case MachineOperand::MO_JumpTableIndex:
2167 case MachineOperand::MO_ConstantPoolIndex:
2168 case MachineOperand::MO_BlockAddress:
2204 for (const MachineOperand &MO : MI.operands())
2940 const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset,
2954 const MachineOperand &Op = Second.getOperand(0);
2963 const MachineOperand &Stored =
2968 const MachineOperand &Op = First.getOperand(i);
3097 for (const MachineOperand &MO : MI.operands()) {
3141 bool HexagonInstrInfo::predOpcodeHasNot(ArrayRef<MachineOperand> Cond) const {
3156 MachineOperand *HexagonInstrInfo::getBaseAndOffset(const MachineInstr &MI,
3176 const MachineOperand &OffsetOp = MI.getOperand(OffsetPos);
3182 const MachineOperand &BaseOp = MI.getOperand(BasePos);
3392 const MachineOperand &CmpOp = GA.getOperand(2);
3575 const MachineOperand &BrTarget = MI.getOperand(1);
3632 for (const MachineOperand &Op : NextIt->operands()) {
4101 const MachineOperand &DefMO = DefMI.getOperand(DefIdx);
4114 const MachineOperand &UseMO = UseMI.getOperand(UseIdx);
4140 SmallVectorImpl<MachineOperand> &Cond) const {
4259 bool HexagonInstrInfo::getPredReg(ArrayRef<MachineOperand> Cond,
4357 MachineOperand &MO = MI.getOperand(ExtOpNum);
4426 bool HexagonInstrInfo::validateBranchCond(const ArrayRef<MachineOperand> &Cond)
4434 MachineOperand &Operand = MIB->getOperand(0);
4438 MIB->addOperand(MachineOperand::CreateImm(memShufDisabledMask));
4443 const MachineOperand &Operand = MIB.getOperand(0);
lib/Target/Hexagon/HexagonInstrInfo.h 108 SmallVectorImpl<MachineOperand> &Cond,
128 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
208 const MachineOperand *&BaseOp,
214 bool reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond)
230 ArrayRef<MachineOperand> Cond) const override;
234 bool SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
235 ArrayRef<MachineOperand> Pred2) const override;
241 std::vector<MachineOperand> &Pred) const override;
427 bool predOpcodeHasNot(ArrayRef<MachineOperand> Cond) const;
430 MachineOperand *getBaseAndOffset(const MachineInstr &MI, int64_t &Offset,
452 bool getInvertedPredSense(SmallVectorImpl<MachineOperand> &Cond) const;
458 bool getPredReg(ArrayRef<MachineOperand> Cond, unsigned &PredReg,
479 bool validateBranchCond(const ArrayRef<MachineOperand> &Cond) const;
lib/Target/Hexagon/HexagonMCInstLower.cpp 41 static MCOperand GetSymbolRef(const MachineOperand &MO, const MCSymbol *Symbol,
113 const MachineOperand &MO = MI->getOperand(i);
121 case MachineOperand::MO_RegisterMask:
123 case MachineOperand::MO_Register:
129 case MachineOperand::MO_FPImmediate: {
141 case MachineOperand::MO_Immediate: {
148 case MachineOperand::MO_MachineBasicBlock: {
156 case MachineOperand::MO_GlobalAddress:
159 case MachineOperand::MO_ExternalSymbol:
163 case MachineOperand::MO_JumpTableIndex:
166 case MachineOperand::MO_ConstantPoolIndex:
169 case MachineOperand::MO_BlockAddress:
lib/Target/Hexagon/HexagonNewValueJump.cpp 150 for (const MachineOperand &Op : II->operands()) {
250 const MachineOperand &Op2 = MI.getOperand(2);
651 for (MachineOperand &MO : MI.operands()) {
658 for (MachineOperand &Op : I->operands()) {
lib/Target/Hexagon/HexagonOptAddrMode.cpp 106 bool changeStore(MachineInstr *OldMI, MachineOperand ImmOp,
108 bool changeLoad(MachineInstr *OldMI, MachineOperand ImmOp, unsigned ImmOpNum);
110 const MachineOperand &ImmOp, unsigned ImmOpNum);
132 MachineOperand StOp = MI.getOperand(MI.getNumOperands() - 1);
161 const MachineOperand &OffsetOp = MI.getOperand(3);
204 for (auto &Mo : UseMI.operands())
362 MachineOperand BaseOp = MID.mayLoad() ? MI->getOperand(1)
368 MachineOperand OffsetOp = MID.mayLoad() ? MI->getOperand(2)
412 const MachineOperand ImmOp = AddMI->getOperand(2);
413 const MachineOperand AddRegOp = AddMI->getOperand(1);
417 MachineOperand &BaseOp = MID.mayLoad() ? UseMI->getOperand(1)
419 MachineOperand &OffsetOp = MID.mayLoad() ? UseMI->getOperand(2)
482 bool HexagonOptAddrMode::changeLoad(MachineInstr *OldMI, MachineOperand ImmOp,
543 bool HexagonOptAddrMode::changeStore(MachineInstr *OldMI, MachineOperand ImmOp,
604 const MachineOperand &ImmOp,
670 const MachineOperand ImmOp = TfrMI->getOperand(1);
755 const MachineOperand &op = UseMI->getOperand(j);
lib/Target/Hexagon/HexagonPeephole.cpp 137 MachineOperand &Dst = MI.getOperand(0);
138 MachineOperand &Src = MI.getOperand(1);
155 MachineOperand &Dst = MI.getOperand(0);
156 MachineOperand &Src1 = MI.getOperand(1);
157 MachineOperand &Src2 = MI.getOperand(2);
172 MachineOperand &Dst = MI.getOperand(0);
173 MachineOperand &Src1 = MI.getOperand(1);
174 MachineOperand &Src2 = MI.getOperand(2);
186 MachineOperand &Dst = MI.getOperand(0);
187 MachineOperand &Src = MI.getOperand(1);
204 MachineOperand &Dst = MI.getOperand(0);
205 MachineOperand &Src = MI.getOperand(1);
219 MI.addOperand(MachineOperand::CreateReg(PeepholeSrc, false));
226 MI.addOperand(MachineOperand::CreateReg(
239 MachineOperand &Op0 = MI.getOperand(0);
lib/Target/Hexagon/HexagonRDFOpt.cpp 120 const MachineOperand &DstOp = MI->getOperand(0);
121 const MachineOperand &HiOp = MI->getOperand(1);
122 const MachineOperand &LoOp = MI->getOperand(2);
131 const MachineOperand &A = MI->getOperand(2);
137 const MachineOperand &DstOp = MI->getOperand(0);
138 const MachineOperand &SrcOp = MI->getOperand(1);
256 MachineOperand &Op = MI.getOperand(OpNum);
lib/Target/Hexagon/HexagonSplitDouble.cpp 252 MachineOperand &Op = *U;
257 MachineOperand &MO = UseI->getOperand(i);
320 for (const auto &Op : MI->operands())
345 const MachineOperand &Op1 = MI->getOperand(1);
346 const MachineOperand &Op2 = MI->getOperand(2);
357 const MachineOperand &OpX = MI->getOperand(ImmX);
442 for (auto &Op : UseI->operands()) {
487 SmallVector<MachineOperand,2> Cond;
537 const MachineOperand &MD = MI.getOperand(0);
600 for (auto &Op : MI->operands()) {
621 auto CO = MachineOperand::CreateReg(R, Op.isDef(), Op.isImplicit(), isKill,
621 auto CO = MachineOperand::CreateReg(R, Op.isDef(), Op.isImplicit(), isKill,
641 MachineOperand &AdrOp = MI->getOperand(AdrX);
643 MachineOperand &ValOp = Load ? MI->getOperand(0)
675 MachineOperand &UpdOp = Load ? MI->getOperand(1) : MI->getOperand(0);
702 MachineOperand &Op0 = MI->getOperand(0);
703 MachineOperand &Op1 = MI->getOperand(1);
729 MachineOperand &Op0 = MI->getOperand(0);
730 MachineOperand &Op1 = MI->getOperand(1);
731 MachineOperand &Op2 = MI->getOperand(2);
759 MachineOperand &Op0 = MI->getOperand(0);
760 MachineOperand &Op1 = MI->getOperand(1);
781 MachineOperand &Op0 = MI->getOperand(0);
782 MachineOperand &Op1 = MI->getOperand(1);
783 MachineOperand &Op2 = MI->getOperand(2);
905 MachineOperand &Op0 = MI->getOperand(0);
906 MachineOperand &Op1 = MI->getOperand(1);
907 MachineOperand &Op2 = MI->getOperand(2);
908 MachineOperand &Op3 = MI->getOperand(3);
1079 for (auto &Op : MI->operands()) {
1104 for (auto &Op : MI->operands()) {
lib/Target/Hexagon/HexagonStoreWidening.cpp 122 const MachineOperand &MO = MI->getOperand(0);
135 const MachineOperand &MO = MI->getOperand(1);
405 MachineOperand &SO = MI->getOperand(2); // Source.
431 MachineOperand &MR = FirstSt->getOperand(0);
454 MachineOperand &MR = FirstSt->getOperand(0);
lib/Target/Hexagon/HexagonSubtarget.cpp 239 const MachineOperand &MO = MI->getOperand(i);
279 MachineOperand *BaseOp0 = HII.getBaseAndOffset(L0, Offset0, Size0);
292 MachineOperand *BaseOp1 = HII.getBaseAndOffset(L1, Offset1, Size1);
351 const MachineOperand &MO = DDst->getOperand(OpNum);
426 const MachineOperand &MO = SrcI->getOperand(OpNum);
434 const MachineOperand &MO = DstI->getOperand(OpNum);
lib/Target/Hexagon/HexagonVLIWPacketizer.cpp 311 for (const MachineOperand MO : MI.operands())
386 for (auto &MO : BI->operands())
428 for (auto &MO : MJ.operands())
481 MachineOperand &Off = MI.getOperand(1);
502 MachineOperand &Off = MI.getOperand(1);
568 static const MachineOperand &getPostIncrementOperand(const MachineInstr &MI,
602 static const MachineOperand& getStoreValueOperand(const MachineInstr &MI) {
621 static const MachineOperand &getAbsSetOperand(const MachineInstr &MI) {
650 const MachineOperand &Val = getStoreValueOperand(MI);
777 const MachineOperand &MO = MI.getOperand(opNum);
946 for (auto &Op : MI.operands()) {
1268 for (const MachineOperand &OpJ : J.operands()) {
1272 for (const MachineOperand &OpI : I.operands()) {
1353 const MachineOperand &NOp0 = NextMI.getOperand(0);
1354 const MachineOperand &NOp1 = NextMI.getOperand(1);
1379 const MachineOperand &OpR = secondRegMatch ? NOp0 : NOp1;
1587 for (const MachineOperand &Op : I.operands()) {
lib/Target/Hexagon/RDFCopy.cpp 44 const MachineOperand &Dst = MI->getOperand(0);
45 const MachineOperand &Src = MI->getOperand(1);
170 MachineOperand &Op = UA.Addr->getOp();
lib/Target/Hexagon/RDFGraph.cpp 426 void RefNode::setRegRef(MachineOperand *Op, DataFlowGraph &G) {
606 const MachineOperand &Op = In.getOperand(OpNum);
623 for (const MachineOperand &O : In.operands())
630 const MachineOperand &Op = In.getOperand(OpNum);
807 MachineOperand &Op, uint16_t Flags) {
823 MachineOperand &Op, uint16_t Flags) {
973 RegisterRef DataFlowGraph::makeRegRef(const MachineOperand &Op) const {
1256 for (const MachineOperand &Op : In.operands())
1271 for (const MachineOperand &Op : In.operands()) {
1291 MachineOperand &Op = In.getOperand(OpN);
1319 MachineOperand &Op = In.getOperand(OpN);
1336 MachineOperand &Op = In.getOperand(OpN);
1365 MachineOperand &Op = In.getOperand(OpN);
lib/Target/Hexagon/RDFGraph.h 495 MachineOperand *Op; // Non-phi refs point to a machine operand.
520 MachineOperand &getOp() {
526 void setRegRef(MachineOperand *Op, DataFlowGraph &G);
751 RegisterRef makeRegRef(const MachineOperand &Op) const;
825 MachineOperand &Op, uint16_t Flags = NodeAttrs::None);
830 MachineOperand &Op, uint16_t Flags = NodeAttrs::None);
lib/Target/Hexagon/RDFLiveness.cpp 885 for (auto &Op : MI->operands()) {
898 for (auto &Op : MI->operands()) {
lib/Target/Hexagon/RDFRegisters.cpp 79 for (const MachineOperand &Op : In.operands())
lib/Target/Lanai/LanaiAsmPrinter.cpp 66 const MachineOperand &MO = MI->getOperand(OpNum);
69 case MachineOperand::MO_Register:
73 case MachineOperand::MO_Immediate:
77 case MachineOperand::MO_MachineBasicBlock:
81 case MachineOperand::MO_GlobalAddress:
85 case MachineOperand::MO_BlockAddress: {
91 case MachineOperand::MO_ExternalSymbol:
95 case MachineOperand::MO_JumpTableIndex:
100 case MachineOperand::MO_ConstantPoolIndex:
123 const MachineOperand &FlagsOP = MI->getOperand(OpNo - 1);
133 const MachineOperand &MO = MI->getOperand(RegOp);
lib/Target/Lanai/LanaiDelaySlotFiller.cpp 204 const MachineOperand &MO = MI->getOperand(I);
233 const MachineOperand &MO = MI->getOperand(I);
lib/Target/Lanai/LanaiInstrInfo.cpp 103 const MachineOperand *BaseOpA = nullptr, *BaseOpB = nullptr;
351 SmallVector<std::pair<MachineOperand *, LPCC::CondCode>, 4>
359 const MachineOperand &MO = Instr.getOperand(IO);
439 SmallVectorImpl<MachineOperand> &Cond,
472 const MachineOperand &MO = MI->getOperand(i);
506 MachineOperand FalseReg = MI.getOperand(Invert ? 1 : 2);
565 SmallVectorImpl<MachineOperand> &Condition,
631 Condition.push_back(MachineOperand::CreateImm(BranchCond));
647 SmallVectorImpl<llvm::MachineOperand> &Condition) const {
663 ArrayRef<MachineOperand> Condition,
758 const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset,
797 const MachineOperand *&BaseOp,
lib/Target/Lanai/LanaiInstrInfo.h 71 const MachineOperand *&BaseOp,
76 const MachineOperand *&BaseOp,
88 SmallVectorImpl<MachineOperand> &Condition,
119 SmallVectorImpl<MachineOperand> &Cond, unsigned &TrueOp,
136 SmallVectorImpl<MachineOperand> &Condition) const override;
140 ArrayRef<MachineOperand> Condition,
lib/Target/Lanai/LanaiMCInstLower.cpp 33 LanaiMCInstLower::GetGlobalAddressSymbol(const MachineOperand &MO) const {
38 LanaiMCInstLower::GetBlockAddressSymbol(const MachineOperand &MO) const {
43 LanaiMCInstLower::GetExternalSymbolSymbol(const MachineOperand &MO) const {
47 MCSymbol *LanaiMCInstLower::GetJumpTableSymbol(const MachineOperand &MO) const {
57 LanaiMCInstLower::GetConstantPoolIndexSymbol(const MachineOperand &MO) const {
66 MCOperand LanaiMCInstLower::LowerSymbolOperand(const MachineOperand &MO,
97 const MachineOperand &MO = MI->getOperand(I);
101 case MachineOperand::MO_Register:
107 case MachineOperand::MO_Immediate:
110 case MachineOperand::MO_MachineBasicBlock:
114 case MachineOperand::MO_RegisterMask:
116 case MachineOperand::MO_GlobalAddress:
119 case MachineOperand::MO_BlockAddress:
122 case MachineOperand::MO_ExternalSymbol:
125 case MachineOperand::MO_JumpTableIndex:
128 case MachineOperand::MO_ConstantPoolIndex:
lib/Target/Lanai/LanaiMCInstLower.h 36 MCOperand LowerSymbolOperand(const MachineOperand &MO, MCSymbol *Sym) const;
38 MCSymbol *GetGlobalAddressSymbol(const MachineOperand &MO) const;
39 MCSymbol *GetBlockAddressSymbol(const MachineOperand &MO) const;
40 MCSymbol *GetExternalSymbolSymbol(const MachineOperand &MO) const;
41 MCSymbol *GetJumpTableSymbol(const MachineOperand &MO) const;
42 MCSymbol *GetConstantPoolIndexSymbol(const MachineOperand &MO) const;
lib/Target/Lanai/LanaiMemAluCombiner.cpp 170 bool isSameOperand(const MachineOperand &Op1, const MachineOperand &Op2) {
170 bool isSameOperand(const MachineOperand &Op1, const MachineOperand &Op2) {
175 case MachineOperand::MO_Register:
177 case MachineOperand::MO_Immediate:
184 bool isZeroOperand(const MachineOperand &Op) {
241 MachineOperand Dest = MemInstr->getOperand(0);
242 MachineOperand Base = MemInstr->getOperand(1);
243 MachineOperand MemOffset = MemInstr->getOperand(2);
244 MachineOperand AluOffset = AluInstr->getOperand(2);
292 MachineOperand &Dest = AluIter->getOperand(0);
293 MachineOperand &Op1 = AluIter->getOperand(1);
294 MachineOperand &Op2 = AluIter->getOperand(2);
331 MachineOperand *Base = &MemInstr->getOperand(1);
332 MachineOperand *Offset = &MemInstr->getOperand(2);
372 MachineOperand AluOperand = MBBIter->getOperand(3);
lib/Target/MSP430/MSP430AsmPrinter.cpp 51 void PrintSymbolOperand(const MachineOperand &MO, raw_ostream &O) override;
66 void MSP430AsmPrinter::PrintSymbolOperand(const MachineOperand &MO,
80 const MachineOperand &MO = MI->getOperand(OpNum);
83 case MachineOperand::MO_Register:
86 case MachineOperand::MO_Immediate:
91 case MachineOperand::MO_MachineBasicBlock:
94 case MachineOperand::MO_GlobalAddress: {
109 const MachineOperand &Base = MI->getOperand(OpNum);
110 const MachineOperand &Disp = MI->getOperand(OpNum+1);
lib/Target/MSP430/MSP430BranchSelector.cpp 191 SmallVector<MachineOperand, 1> Cond;
lib/Target/MSP430/MSP430InstrInfo.cpp 132 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
178 SmallVectorImpl<MachineOperand> &Cond,
240 Cond.push_back(MachineOperand::CreateImm(BranchCode));
268 ArrayRef<MachineOperand> Cond,
lib/Target/MSP430/MSP430InstrInfo.h 58 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
62 SmallVectorImpl<MachineOperand> &Cond,
68 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
lib/Target/MSP430/MSP430MCInstLower.cpp 31 GetGlobalAddressSymbol(const MachineOperand &MO) const {
41 GetExternalSymbolSymbol(const MachineOperand &MO) const {
51 GetJumpTableSymbol(const MachineOperand &MO) const {
68 GetConstantPoolIndexSymbol(const MachineOperand &MO) const {
85 GetBlockAddressSymbol(const MachineOperand &MO) const {
95 LowerSymbolOperand(const MachineOperand &MO, MCSymbol *Sym) const {
119 const MachineOperand &MO = MI->getOperand(i);
126 case MachineOperand::MO_Register:
131 case MachineOperand::MO_Immediate:
134 case MachineOperand::MO_MachineBasicBlock:
138 case MachineOperand::MO_GlobalAddress:
141 case MachineOperand::MO_ExternalSymbol:
144 case MachineOperand::MO_JumpTableIndex:
147 case MachineOperand::MO_ConstantPoolIndex:
150 case MachineOperand::MO_BlockAddress:
153 case MachineOperand::MO_RegisterMask:
lib/Target/MSP430/MSP430MCInstLower.h 35 MCOperand LowerSymbolOperand(const MachineOperand &MO, MCSymbol *Sym) const;
37 MCSymbol *GetGlobalAddressSymbol(const MachineOperand &MO) const;
38 MCSymbol *GetExternalSymbolSymbol(const MachineOperand &MO) const;
39 MCSymbol *GetJumpTableSymbol(const MachineOperand &MO) const;
40 MCSymbol *GetConstantPoolIndexSymbol(const MachineOperand &MO) const;
41 MCSymbol *GetBlockAddressSymbol(const MachineOperand &MO) const;
lib/Target/Mips/MicroMipsSizeReduction.cpp 286 static bool IsSP(const MachineOperand &MO) {
293 static bool isMMThreeBitGPRegister(const MachineOperand &MO) {
300 static bool isMMSourceRegister(const MachineOperand &MO) {
lib/Target/Mips/Mips16InstrInfo.cpp 100 const MachineOperand *&Src,
101 const MachineOperand *&Dest) const {
359 MachineOperand &MO = II->getOperand(i);
375 MachineOperand &MO = II->getOperand(i);
lib/Target/Mips/Mips16InstrInfo.h 109 bool isCopyInstrImpl(const MachineInstr &MI, const MachineOperand *&Source,
110 const MachineOperand *&Destination) const override;
lib/Target/Mips/MipsAsmPrinter.cpp 106 bool MipsAsmPrinter::lowerOperand(const MachineOperand &MO, MCOperand &MCOp) {
168 MachineOperand MO = MI.getOperand(I);
520 const MachineOperand &MO = MI->getOperand(OpNum);
526 if ((MO.getType()) != MachineOperand::MO_Immediate)
531 if ((MO.getType()) != MachineOperand::MO_Immediate)
536 if ((MO.getType()) != MachineOperand::MO_Immediate)
541 if ((MO.getType()) != MachineOperand::MO_Immediate)
546 if ((MO.getType()) != MachineOperand::MO_Immediate)
554 if (MO.getType() == MachineOperand::MO_Immediate && MO.getImm() == 0) {
566 const MachineOperand &FlagsOP = MI->getOperand(OpNum - 1);
598 const MachineOperand &MO = MI->getOperand(RegOp);
624 const MachineOperand &BaseMO = MI->getOperand(OpNum);
625 const MachineOperand &OffsetMO = MI->getOperand(OpNum + 1);
657 const MachineOperand &MO = MI->getOperand(opNum);
683 case MachineOperand::MO_Register:
688 case MachineOperand::MO_Immediate:
692 case MachineOperand::MO_MachineBasicBlock:
696 case MachineOperand::MO_GlobalAddress:
700 case MachineOperand::MO_BlockAddress: {
706 case MachineOperand::MO_ConstantPoolIndex:
755 const MachineOperand &MO = MI->getOperand(opNum);
lib/Target/Mips/MipsAsmPrinter.h 82 bool lowerOperand(const MachineOperand &MO, MCOperand &MCOp);
lib/Target/Mips/MipsBranchExpansion.cpp 227 const MachineOperand &MO = Br.getOperand(I);
343 MachineOperand &MO = Br->getOperand(I);
714 I.Br->addOperand(MachineOperand::CreateMBB(LongBrMBB));
lib/Target/Mips/MipsConstantIslandPass.cpp 1652 MachineOperand& Literal = I->getOperand(1);
1665 I->addOperand(MachineOperand::CreateCPI(index, 0));
1666 I->addOperand(MachineOperand::CreateImm(4));
lib/Target/Mips/MipsDelaySlotFiller.cpp 328 const MachineOperand &MO = Filler->getOperand(I);
418 const MachineOperand &MO = MI.getOperand(I);
855 SmallVector<MachineOperand, 2> Cond;
lib/Target/Mips/MipsISelLowering.cpp 1273 MachineOperand &Divisor = MI.getOperand(2);
3008 MI.addOperand(MachineOperand::CreateMCSymbol(S, MipsII::MO_JALR));
lib/Target/Mips/MipsInstrInfo.cpp 50 bool MipsInstrInfo::isZeroImm(const MachineOperand &op) const {
81 SmallVectorImpl<MachineOperand> &Cond) const {
88 Cond.push_back(MachineOperand::CreateImm(Opc));
97 SmallVectorImpl<MachineOperand> &Cond,
107 ArrayRef<MachineOperand> Cond) const {
123 ArrayRef<MachineOperand> Cond,
183 SmallVectorImpl<MachineOperand> &Cond) const {
192 SmallVectorImpl<MachineOperand> &Cond, bool AllowModify,
660 const MachineOperand &MO = I->getOperand(J);
728 MachineOperand MOPos = MI.getOperand(2);
739 MachineOperand MOSize = MI.getOperand(3);
lib/Target/Mips/MipsInstrInfo.h 65 SmallVectorImpl<MachineOperand> &Cond,
72 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
77 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
81 SmallVectorImpl<MachineOperand> &Cond,
165 bool isZeroImm(const MachineOperand &op) const;
175 SmallVectorImpl<MachineOperand> &Cond) const;
178 const DebugLoc &DL, ArrayRef<MachineOperand> Cond) const;
lib/Target/Mips/MipsInstructionSelector.cpp 392 MachineOperand BaseAddr = I.getOperand(1);
lib/Target/Mips/MipsMCInstLower.cpp 35 MCOperand MipsMCInstLower::LowerSymbolOperand(const MachineOperand &MO,
124 case MachineOperand::MO_MachineBasicBlock:
128 case MachineOperand::MO_GlobalAddress:
133 case MachineOperand::MO_BlockAddress:
138 case MachineOperand::MO_ExternalSymbol:
143 case MachineOperand::MO_MCSymbol:
148 case MachineOperand::MO_JumpTableIndex:
152 case MachineOperand::MO_ConstantPoolIndex:
179 MCOperand MipsMCInstLower::LowerOperand(const MachineOperand &MO,
185 case MachineOperand::MO_Register:
189 case MachineOperand::MO_Immediate:
191 case MachineOperand::MO_MachineBasicBlock:
192 case MachineOperand::MO_GlobalAddress:
193 case MachineOperand::MO_ExternalSymbol:
194 case MachineOperand::MO_MCSymbol:
195 case MachineOperand::MO_JumpTableIndex:
196 case MachineOperand::MO_ConstantPoolIndex:
197 case MachineOperand::MO_BlockAddress:
199 case MachineOperand::MO_RegisterMask:
279 const MachineOperand &MO = MI->getOperand(I);
324 const MachineOperand &MO = MI->getOperand(i);
lib/Target/Mips/MipsMCInstLower.h 28 using MachineOperandType = MachineOperand::MachineOperandType;
38 MCOperand LowerOperand(const MachineOperand& MO, unsigned offset = 0) const;
41 MCOperand LowerSymbolOperand(const MachineOperand &MO,
lib/Target/Mips/MipsOptimizePICCall.cpp 124 static MachineOperand *getCallTargetRegOpnd(MachineInstr &MI) {
128 MachineOperand &MO = MI.getOperand(0);
171 MachineOperand &MO = MI.getOperand(I);
271 MachineOperand *MO = getCallTargetRegOpnd(MI);
lib/Target/Mips/MipsRegisterBankInfo.cpp 421 for (const MachineOperand &Op : MI.operands()) {
lib/Target/Mips/MipsSEFrameLowering.cpp 345 const MachineOperand &Op1 = I->getOperand(1);
346 const MachineOperand &Op2 = I->getOperand(2);
lib/Target/Mips/MipsSEISelDAGToDAG.cpp 107 MachineOperand &MO = *U;
171 MI.addOperand(MachineOperand::CreateReg(Mips::SP, false, true));
178 MI.addOperand(MachineOperand::CreateReg(Mips::SP, false, true));
lib/Target/Mips/MipsSEInstrInfo.cpp 225 const MachineOperand *&Src,
226 const MachineOperand *&Dest) const {
689 for (auto & MO : I->operands()) {
730 const MachineOperand &SrcLo = I->getOperand(1), &SrcHi = I->getOperand(2);
753 const MachineOperand &Dst = I->getOperand(0), &Src = I->getOperand(1);
lib/Target/Mips/MipsSEInstrInfo.h 82 bool isCopyInstrImpl(const MachineInstr &MI, const MachineOperand *&Source,
83 const MachineOperand *&Destination) const override;
lib/Target/Mips/MipsSERegisterInfo.cpp 66 MachineOperand MO) {
lib/Target/NVPTX/NVPTXAsmPrinter.cpp 153 const MachineOperand &MO = MI->getOperand(OpNo);
216 const MachineOperand &MO = MI->getOperand(0);
224 const MachineOperand &MO = MI->getOperand(i);
239 bool NVPTXAsmPrinter::lowerOperand(const MachineOperand &MO,
243 case MachineOperand::MO_Register:
246 case MachineOperand::MO_Immediate:
249 case MachineOperand::MO_MachineBasicBlock:
253 case MachineOperand::MO_ExternalSymbol:
256 case MachineOperand::MO_GlobalAddress:
259 case MachineOperand::MO_FPImmediate: {
2210 const MachineOperand &MO = MI->getOperand(opNum);
2212 case MachineOperand::MO_Register:
2223 case MachineOperand::MO_Immediate:
2227 case MachineOperand::MO_FPImmediate:
2231 case MachineOperand::MO_GlobalAddress:
2235 case MachineOperand::MO_MachineBasicBlock:
lib/Target/NVPTX/NVPTXAsmPrinter.h 211 bool lowerOperand(const MachineOperand &MO, MCOperand &MCOp);
lib/Target/NVPTX/NVPTXInstrInfo.cpp 98 SmallVectorImpl<MachineOperand> &Cond,
183 ArrayRef<MachineOperand> Cond,
lib/Target/NVPTX/NVPTXInstrInfo.h 58 SmallVectorImpl<MachineOperand> &Cond,
63 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
lib/Target/NVPTX/NVPTXPeephole.cpp 81 auto &Op = Root.getOperand(1);
96 auto &BaseAddrOp = GenericAddrDef->getOperand(1);
lib/Target/NVPTX/NVPTXProxyRegErasure.cpp 56 void replaceRegisterUsage(MachineInstr &Instr, MachineOperand &From,
57 MachineOperand &To);
96 auto &InOp = *MI.uses().begin();
97 auto &OutOp = *MI.defs().begin();
110 MachineOperand &From,
111 MachineOperand &To) {
112 for (auto &Op : Instr.uses()) {
lib/Target/NVPTX/NVPTXReplaceImageHandles.cpp 44 void replaceImageHandle(MachineOperand &Op, MachineFunction &MF);
45 bool findIndexForHandle(MachineOperand &Op, MachineFunction &MF,
86 MachineOperand &TexHandle = MI.getOperand(4);
90 MachineOperand &SampHandle = MI.getOperand(5);
100 MachineOperand &SurfHandle = MI.getOperand(VecSize);
107 MachineOperand &SurfHandle = MI.getOperand(0);
114 MachineOperand &Handle = MI.getOperand(1);
125 replaceImageHandle(MachineOperand &Op, MachineFunction &MF) {
133 findIndexForHandle(MachineOperand &Op, MachineFunction &MF, unsigned &Idx) {
lib/Target/PowerPC/PPC.h 54 bool LowerPPCMachineOperandToMCOperand(const MachineOperand &MO,
lib/Target/PowerPC/PPCAsmPrinter.cpp 107 void PrintSymbolOperand(const MachineOperand &MO, raw_ostream &O) override;
181 void PPCAsmPrinter::PrintSymbolOperand(const MachineOperand &MO,
208 const MachineOperand &MO = MI->getOperand(OpNo);
211 case MachineOperand::MO_Register: {
222 case MachineOperand::MO_Immediate:
226 case MachineOperand::MO_MachineBasicBlock:
229 case MachineOperand::MO_ConstantPoolIndex:
233 case MachineOperand::MO_BlockAddress:
236 case MachineOperand::MO_GlobalAddress: {
384 const MachineOperand &CalleeMO = Opers.getCallTarget();
504 const MachineOperand &MO = MI->getOperand(2);
517 static MCSymbol *getMCSymbolForTOCPseudoMO(const MachineOperand &MO,
520 case MachineOperand::MO_GlobalAddress:
522 case MachineOperand::MO_ConstantPoolIndex:
524 case MachineOperand::MO_JumpTableIndex:
526 case MachineOperand::MO_BlockAddress:
547 for (const MachineOperand &MO: MI->operands()) {
686 const MachineOperand &MO = MI->getOperand(1);
744 const MachineOperand &MO = MI->getOperand(1);
773 const MachineOperand &MO = MI->getOperand(2);
803 const MachineOperand &MO = MI->getOperand(1);
834 const MachineOperand &MO = MI->getOperand(2);
874 const MachineOperand &MO = MI->getOperand(1);
906 const MachineOperand &MO = MI->getOperand(2);
924 const MachineOperand &MO = MI->getOperand(2);
943 const MachineOperand &MO = MI->getOperand(1);
1003 const MachineOperand &MO = MI->getOperand(2);
1021 const MachineOperand &MO = MI->getOperand(2);
1048 const MachineOperand &MO = MI->getOperand(2);
1066 const MachineOperand &MO = MI->getOperand(2);
1095 const MachineOperand &MO = MI->getOperand(2);
1115 const MachineOperand &MO = MI->getOperand(2);
1171 const MachineOperand &MO = MI->getOperand(OpNum);
1228 for (const auto &MO :
lib/Target/PowerPC/PPCBranchCoalescing.cpp 140 SmallVector<MachineOperand, 4> Cond;
155 bool identicalOperands(ArrayRef<MachineOperand> OperandList1,
156 ArrayRef<MachineOperand> OperandList2) const;
327 ArrayRef<MachineOperand> OpList1, ArrayRef<MachineOperand> OpList2) const {
327 ArrayRef<MachineOperand> OpList1, ArrayRef<MachineOperand> OpList2) const {
335 const MachineOperand &Op1 = OpList1[i];
336 const MachineOperand &Op2 = OpList2[i];
403 MachineOperand &MO = PHIInst.getOperand(i);
539 for (auto &Def : I->defs())
lib/Target/PowerPC/PPCCTRLoops.cpp 115 const MachineOperand &MO = MI.getOperand(i);
lib/Target/PowerPC/PPCExpandISEL.cpp 87 bool useSameRegister(const MachineOperand &Op1, const MachineOperand &Op2) {
87 bool useSameRegister(const MachineOperand &Op1, const MachineOperand &Op2) {
205 MachineOperand &Dest = (*I)->getOperand(0);
206 MachineOperand &TrueValue = (*I)->getOperand(1);
207 MachineOperand &FalseValue = (*I)->getOperand(2);
272 MachineOperand &Dest = (*MI)->getOperand(0);
273 MachineOperand &TrueValue = (*MI)->getOperand(1);
274 MachineOperand &FalseValue = (*MI)->getOperand(2);
394 SmallVector<std::pair<MCPhysReg, const MachineOperand *>, 2> Clobbers;
439 MachineOperand &Dest = MI->getOperand(0); // location to store to
440 MachineOperand &TrueValue = MI->getOperand(1); // Value to store if
442 MachineOperand &FalseValue = MI->getOperand(2); // Value to store if
444 MachineOperand &ConditionRegister = MI->getOperand(3); // Condition
462 .add(MachineOperand::CreateImm(0));
487 .add(MachineOperand::CreateImm(0));
lib/Target/PowerPC/PPCFrameLowering.cpp 366 const MachineOperand &MO = Ret.getOperand(I);
573 MachineOperand &MO = MBBI->getOperand(I);
1476 MachineOperand &StackAdjust = MBBI->getOperand(1);
1737 MachineOperand &JumpTarget = MBBI->getOperand(0);
1746 MachineOperand &JumpTarget = MBBI->getOperand(0);
1750 MachineOperand &JumpTarget = MBBI->getOperand(0);
1759 MachineOperand &JumpTarget = MBBI->getOperand(0);
lib/Target/PowerPC/PPCISelLowering.cpp10865 MI.addOperand(MachineOperand::CreateReg(PPC::X2, false, true));
10891 SmallVector<MachineOperand, 2> Cond;
10896 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_SET));
11587 MachineOperand SrcOp = MI.getOperand(1);
lib/Target/PowerPC/PPCInstrInfo.cpp 161 const MachineOperand &MO = MI.getOperand(i);
185 const MachineOperand &DefMO = DefMI.getOperand(DefIdx);
498 SmallVectorImpl<MachineOperand> &Cond,
547 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_SET));
555 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_UNSET));
565 Cond.push_back(MachineOperand::CreateImm(1));
566 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
576 Cond.push_back(MachineOperand::CreateImm(0));
577 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
610 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_SET));
620 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_UNSET));
633 Cond.push_back(MachineOperand::CreateImm(1));
634 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
647 Cond.push_back(MachineOperand::CreateImm(0));
648 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
705 ArrayRef<MachineOperand> Cond,
756 ArrayRef<MachineOperand> Cond,
1314 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
1438 ArrayRef<MachineOperand> Pred) const {
1523 bool PPCInstrInfo::SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
1524 ArrayRef<MachineOperand> Pred2) const {
1555 std::vector<MachineOperand> &Pred) const {
1568 const MachineOperand &MO = MI.getOperand(i);
1736 SmallVector<std::pair<MachineOperand*, PPC::Predicate>, 4> PredsToUpdate;
1737 SmallVector<std::pair<MachineOperand*, unsigned>, 4> SubRegsToUpdate;
1984 MachineOperand::CreateReg(*ImpDefs, true, true));
1990 MachineOperand::CreateReg(*ImpUses, false, true));
2128 static bool isAnImmediateOperand(const MachineOperand &MO) {
2285 MachineOperand &MO = MI.getOperand(UseOpIdx);
2393 MachineOperand &MO = MI.getOperand(i);
2467 MachineOperand &MO = MI.getOperand(Index);
2493 MachineOperand *MO = nullptr;
2689 MachineOperand ImmOperand = MI.getOperand(III.ImmOpNo);
2690 MachineOperand RegOperand = MI.getOperand(III.OpNoForForwarding);
2712 MachineOperand &MO = ADDMI->getOperand(Index);
3412 MachineOperand MOp1 = MI.getOperand(MinOp);
3413 MachineOperand MOp2 = MI.getOperand(MaxOp);
3425 SmallVector<MachineOperand, 2> MOps;
3487 MachineOperand *&ImmMO,
3488 MachineOperand *&RegMO) const {
3505 const MachineOperand &RegMO, const MachineInstr &DefMI,
3543 bool PPCInstrInfo::isImmElgibleForForwarding(const MachineOperand &ImmMO,
3615 MachineOperand *ImmMO = nullptr;
3616 MachineOperand *RegMO = nullptr;
3672 SmallVector<MachineOperand, 2> MOps;
3683 for (auto &MO : MOps)
4186 SmallVectorImpl<MachineOperand> &Cond) override {
4190 Cond.push_back(MachineOperand::CreateImm(0));
4191 Cond.push_back(MachineOperand::CreateReg(
4265 const MachineOperand *&BaseReg,
4301 const MachineOperand *BaseOpA = nullptr, *BaseOpB = nullptr;
lib/Target/PowerPC/PPCInstrInfo.h 149 MachineOperand *&ImmMO,
150 MachineOperand *&RegMO) const;
151 bool isImmElgibleForForwarding(const MachineOperand &ImmMO,
155 bool isRegElgibleForForwarding(const MachineOperand &RegMO,
265 SmallVectorImpl<MachineOperand> &Cond,
270 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
275 bool canInsertSelect(const MachineBasicBlock &, ArrayRef<MachineOperand> Cond,
305 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
341 ArrayRef<MachineOperand> Pred) const override;
343 bool SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
344 ArrayRef<MachineOperand> Pred2) const override;
347 std::vector<MachineOperand> &Pred) const override;
365 const MachineOperand *&BaseOp,
lib/Target/PowerPC/PPCMCInstLower.cpp 36 static MCSymbol *GetSymbolFromOperand(const MachineOperand &MO,
81 static MCOperand GetSymbolRef(const MachineOperand &MO, const MCSymbol *Symbol,
162 bool llvm::LowerPPCMachineOperandToMCOperand(const MachineOperand &MO,
168 case MachineOperand::MO_Register:
175 case MachineOperand::MO_Immediate:
178 case MachineOperand::MO_MachineBasicBlock:
182 case MachineOperand::MO_GlobalAddress:
183 case MachineOperand::MO_ExternalSymbol:
186 case MachineOperand::MO_JumpTableIndex:
189 case MachineOperand::MO_ConstantPoolIndex:
192 case MachineOperand::MO_BlockAddress:
196 case MachineOperand::MO_MCSymbol:
199 case MachineOperand::MO_RegisterMask:
lib/Target/PowerPC/PPCMIPeephole.cpp 145 static MachineInstr *getVRegDefOrNull(MachineOperand *Op,
751 MachineOperand Op1 = MI.getOperand(1);
752 MachineOperand Op2 = MI.getOperand(2);
905 MachineOperand &MO = Phi->getOperand(I);
961 for (MachineOperand &MO : CMPI->operands())
1343 MachineOperand MOpSHSrc = SrcMI->getOperand(2);
1344 MachineOperand MOpMBSrc = SrcMI->getOperand(3);
1345 MachineOperand MOpSHMI = MI.getOperand(2);
1346 MachineOperand MOpMEMI = MI.getOperand(3);
1405 MachineOperand MOpSHMI = MI.getOperand(2);
1406 MachineOperand MOpMEMI = MI.getOperand(3);
lib/Target/PowerPC/PPCPreEmitPeephole.cpp 98 MachineOperand *DeadOrKillToUnset = nullptr;
260 ArrayRef<MachineOperand> NoCond;
lib/Target/PowerPC/PPCReduceCRLogicals.cpp 63 MachineOperand &MO = MI.getOperand(i);
96 MachineOperand &MO = MI.getOperand(i);
lib/Target/PowerPC/PPCTOCRegDeps.cpp 102 for (const MachineOperand &MO : MI.operands()) {
121 MI.addOperand(MachineOperand::CreateReg(TOCReg,
lib/Target/PowerPC/PPCVSXCopy.cpp 91 MachineOperand &DstMO = MI.getOperand(0);
92 MachineOperand &SrcMO = MI.getOperand(1);
lib/Target/PowerPC/PPCVSXFMAMutate.cpp 284 MachineOperand &UseMO = *UI;
lib/Target/PowerPC/PPCVSXSwapRemoval.cpp 253 for (const MachineOperand &MO : MI.operands()) {
600 for (const MachineOperand &MO : MI->operands()) {
lib/Target/RISCV/RISCV.h 35 bool LowerRISCVMachineOperandToMCOperand(const MachineOperand &MO,
lib/Target/RISCV/RISCVAsmPrinter.cpp 55 bool lowerOperand(const MachineOperand &MO, MCOperand &MCOp) const {
90 const MachineOperand &MO = MI->getOperand(OpNo);
112 case MachineOperand::MO_Immediate:
115 case MachineOperand::MO_Register:
130 const MachineOperand &MO = MI->getOperand(OpNo);
lib/Target/RISCV/RISCVExpandPseudoInsts.cpp 633 const MachineOperand &Symbol = MI.getOperand(1);
lib/Target/RISCV/RISCVInstrInfo.cpp 204 SmallVectorImpl<MachineOperand> &Cond) {
209 Cond.push_back(MachineOperand::CreateImm(LastInst.getOpcode()));
236 SmallVectorImpl<MachineOperand> &Cond,
337 ArrayRef<MachineOperand> Cond, const DebugLoc &DL, int *BytesAdded) const {
415 SmallVectorImpl<MachineOperand> &Cond) const {
500 const MachineOperand &MO = MI.getOperand(OI.index());
lib/Target/RISCV/RISCVInstrInfo.h 60 SmallVectorImpl<MachineOperand> &Cond,
64 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
77 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
lib/Target/RISCV/RISCVMCInstLower.cpp 28 static MCOperand lowerSymbolOperand(const MachineOperand &MO, MCSymbol *Sym,
89 bool llvm::LowerRISCVMachineOperandToMCOperand(const MachineOperand &MO,
95 case MachineOperand::MO_Register:
101 case MachineOperand::MO_RegisterMask:
104 case MachineOperand::MO_Immediate:
107 case MachineOperand::MO_MachineBasicBlock:
110 case MachineOperand::MO_GlobalAddress:
113 case MachineOperand::MO_BlockAddress:
117 case MachineOperand::MO_ExternalSymbol:
121 case MachineOperand::MO_ConstantPoolIndex:
132 for (const MachineOperand &MO : MI->operands()) {
lib/Target/RISCV/RISCVMergeBaseOffset.cpp 84 HiLUI.getOperand(1).getType() != MachineOperand::MO_GlobalAddress ||
92 LoADDI->getOperand(2).getType() != MachineOperand::MO_GlobalAddress ||
150 MachineOperand &AddiImmOp = OffsetTail.getOperand(2);
156 MachineOperand &LuiImmOp = OffsetLui.getOperand(1);
238 MachineOperand &TailImmOp = Tail.getOperand(2);
244 MachineOperand &ImmOp = LoADDI.getOperand(2);
lib/Target/Sparc/DelaySlotFiller.cpp 252 const MachineOperand &MO = candidate->getOperand(i);
302 const MachineOperand &Reg = MI->getOperand(0);
307 const MachineOperand &Operand1 = MI->getOperand(1);
323 const MachineOperand &MO = MI->getOperand(i);
367 const MachineOperand &MO = I->getOperand(structSizeOpNum);
lib/Target/Sparc/LeonPasses.cpp 87 MachineOperand &MO = MI.getOperand(0);
lib/Target/Sparc/SparcAsmPrinter.cpp 175 const MachineOperand &MO = MI->getOperand(0);
294 const MachineOperand &MO = MI->getOperand (opNum);
350 case MachineOperand::MO_Register:
354 case MachineOperand::MO_Immediate:
357 case MachineOperand::MO_MachineBasicBlock:
360 case MachineOperand::MO_GlobalAddress:
363 case MachineOperand::MO_BlockAddress:
366 case MachineOperand::MO_ExternalSymbol:
369 case MachineOperand::MO_ConstantPoolIndex:
373 case MachineOperand::MO_Metadata:
lib/Target/Sparc/SparcInstrInfo.cpp 154 SmallVectorImpl<MachineOperand> &Cond) {
155 Cond.push_back(MachineOperand::CreateImm(LastInst->getOperand(1).getImm()));
162 SmallVectorImpl<MachineOperand> &Cond,
245 ArrayRef<MachineOperand> Cond,
298 SmallVectorImpl<MachineOperand> &Cond) const {
lib/Target/Sparc/SparcInstrInfo.h 69 SmallVectorImpl<MachineOperand> &Cond,
76 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
81 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
lib/Target/Sparc/SparcMCInstLower.cpp 30 const MachineOperand &MO,
39 case MachineOperand::MO_MachineBasicBlock:
43 case MachineOperand::MO_GlobalAddress:
47 case MachineOperand::MO_BlockAddress:
51 case MachineOperand::MO_ExternalSymbol:
55 case MachineOperand::MO_ConstantPoolIndex:
68 const MachineOperand &MO,
72 case MachineOperand::MO_Register:
77 case MachineOperand::MO_Immediate:
80 case MachineOperand::MO_MachineBasicBlock:
81 case MachineOperand::MO_GlobalAddress:
82 case MachineOperand::MO_BlockAddress:
83 case MachineOperand::MO_ExternalSymbol:
84 case MachineOperand::MO_ConstantPoolIndex:
87 case MachineOperand::MO_RegisterMask: break;
101 const MachineOperand &MO = MI->getOperand(i);
lib/Target/SystemZ/SystemZAsmPrinter.cpp 608 const MachineOperand &CalleeMO = Opers.getCallTarget();
lib/Target/SystemZ/SystemZElimCompare.cpp 153 const MachineOperand &MO = MI.getOperand(I);
231 MachineOperand Target(Branch->getOperand(2));
300 for (const auto &MO : MI.operands())
342 SmallVector<MachineOperand *, 4> AlterMasks;
535 MachineOperand CCMask(MBBI->getOperand(1));
539 MachineOperand Target(MBBI->getOperand(
lib/Target/SystemZ/SystemZISelLowering.cpp 69 static MachineOperand earlyUseOperand(MachineOperand Op) {
69 static MachineOperand earlyUseOperand(MachineOperand Op) {
6502 static Register forceReg(MachineInstr &MI, MachineOperand &Base,
6722 MachineOperand Base = MI.getOperand(1);
6817 MachineOperand Base = earlyUseOperand(MI.getOperand(1));
6819 MachineOperand Src2 = earlyUseOperand(MI.getOperand(3));
6935 MachineOperand Base = earlyUseOperand(MI.getOperand(1));
7049 MachineOperand Base = earlyUseOperand(MI.getOperand(1));
7230 MachineOperand DestBase = earlyUseOperand(MI.getOperand(0));
7232 MachineOperand SrcBase = earlyUseOperand(MI.getOperand(2));
7336 DestBase = MachineOperand::CreateReg(NextDestReg, false);
7337 SrcBase = MachineOperand::CreateReg(NextSrcReg, false);
7356 DestBase = MachineOperand::CreateReg(Reg, false);
7365 SrcBase = MachineOperand::CreateReg(Reg, false);
7487 MI.addOperand(MachineOperand::CreateReg(Reg, true, true));
7496 MI.addOperand(MachineOperand::CreateReg(Reg, true, true));
7501 MI.addOperand(MachineOperand::CreateReg(Reg, true, true));
lib/Target/SystemZ/SystemZInstrInfo.cpp 76 MachineOperand &HighRegOp = EarlierMI->getOperand(0);
77 MachineOperand &LowRegOp = MI->getOperand(0);
96 MachineOperand &HighOffsetOp = EarlierMI->getOperand(2);
97 MachineOperand &LowOffsetOp = MI->getOperand(2);
120 MachineOperand &OffsetMO = MI->getOperand(2);
356 SmallVectorImpl<MachineOperand> &Cond,
419 Cond.push_back(MachineOperand::CreateImm(Branch.CCValid));
420 Cond.push_back(MachineOperand::CreateImm(Branch.CCMask));
471 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
480 ArrayRef<MachineOperand> Cond,
534 ArrayRef<MachineOperand> Pred,
719 MachineInstr &MI, ArrayRef<MachineOperand> Pred) const {
740 MachineOperand FirstOp = MI.getOperand(0);
942 MachineOperand *CCDef = NewMI->findRegisterDefOperand(SystemZ::CC);
971 MachineOperand &Dest = MI.getOperand(0);
972 MachineOperand &Src = MI.getOperand(1);
985 MachineOperand &Op = MI.getOperand(I);
lib/Target/SystemZ/SystemZInstrInfo.h 112 const MachineOperand *Target;
125 const MachineOperand *target)
213 SmallVectorImpl<MachineOperand> &Cond,
218 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
223 bool canInsertSelect(const MachineBasicBlock&, ArrayRef<MachineOperand> Cond,
243 ArrayRef<MachineOperand> Pred) const override;
271 bool reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const
lib/Target/SystemZ/SystemZMCInstLower.cpp 36 SystemZMCInstLower::getExpr(const MachineOperand &MO,
41 case MachineOperand::MO_MachineBasicBlock:
46 case MachineOperand::MO_GlobalAddress:
50 case MachineOperand::MO_ExternalSymbol:
54 case MachineOperand::MO_JumpTableIndex:
59 case MachineOperand::MO_ConstantPoolIndex:
63 case MachineOperand::MO_BlockAddress:
79 MCOperand SystemZMCInstLower::lowerOperand(const MachineOperand &MO) const {
81 case MachineOperand::MO_Register:
84 case MachineOperand::MO_Immediate:
97 const MachineOperand &MO = MI->getOperand(I);
lib/Target/SystemZ/SystemZMCInstLower.h 35 MCOperand lowerOperand(const MachineOperand& MO) const;
38 const MCExpr *getExpr(const MachineOperand &MO,
lib/Target/SystemZ/SystemZPostRewrite.cpp 226 MachineOperand &SrcMO = MI.getOperand(1);
lib/Target/SystemZ/SystemZRegisterInfo.cpp 29 static const TargetRegisterClass *getRC32(MachineOperand &MO,
106 MachineOperand &TrueMO = Use.getOperand(1);
107 MachineOperand &FalseMO = Use.getOperand(2);
153 const MachineOperand *VRRegMO = nullptr;
154 const MachineOperand *OtherMO = nullptr;
155 const MachineOperand *CommuMO = nullptr;
388 for (const MachineOperand &MO : MII->operands())
lib/Target/SystemZ/SystemZShortenInst.cpp 160 MachineOperand Dest(MI.getOperand(0));
161 MachineOperand Src(MI.getOperand(1));
162 MachineOperand Suppress(MI.getOperand(2));
163 MachineOperand Mode(MI.getOperand(3));
351 MachineOperand &ImmMO = MI.getOperand(3);
lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp 69 std::string WebAssemblyAsmPrinter::regToString(const MachineOperand &MO) {
375 const MachineOperand &MO = MI->getOperand(OpNo);
377 case MachineOperand::MO_Immediate:
380 case MachineOperand::MO_Register:
386 case MachineOperand::MO_GlobalAddress:
389 case MachineOperand::MO_ExternalSymbol:
393 case MachineOperand::MO_MachineBasicBlock:
lib/Target/WebAssembly/WebAssemblyAsmPrinter.h 73 std::string regToString(const MachineOperand &MO);
lib/Target/WebAssembly/WebAssemblyCFGStackify.cpp 124 for (MachineOperand &MO : MI.explicit_operands())
660 SmallVector<MachineOperand, 4> Cond;
715 for (auto &MO : MI.explicit_uses()) {
1071 SmallVector<MachineOperand, 4> Cond;
1329 SmallVector<MachineOperand, 4> Ops(MI.operands());
1332 for (auto MO : Ops) {
1334 MO = MachineOperand::CreateImm(getDepth(Stack, MO.getMBB()));
lib/Target/WebAssembly/WebAssemblyCallIndirectFixup.cpp 120 SmallVector<MachineOperand, 8> Ops;
123 Ops.push_back(MachineOperand::CreateImm(0));
127 Ops.push_back(MachineOperand::CreateImm(0));
129 for (const MachineOperand &MO :
138 for (const MachineOperand &MO : Ops)
lib/Target/WebAssembly/WebAssemblyExplicitLocals.cpp 168 static MachineInstr *findStartOfTree(MachineOperand &MO,
176 for (MachineOperand &DefMO : Def->explicit_uses()) {
309 for (MachineOperand &MO : reverse(MI.explicit_uses())) {
388 for (const MachineOperand &MO : MI.explicit_operands()) {
lib/Target/WebAssembly/WebAssemblyFixIrreducibleControlFlow.cpp 454 for (auto &Op : Term.explicit_uses())
lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp 104 SmallVectorImpl<MachineOperand> &Cond,
122 Cond.push_back(MachineOperand::CreateImm(true));
130 Cond.push_back(MachineOperand::CreateImm(false));
144 Cond.push_back(MachineOperand::CreateImm(true));
181 ArrayRef<MachineOperand> Cond, const DebugLoc &DL, int *BytesAdded) const {
220 SmallVectorImpl<MachineOperand> &Cond) const {
230 Cond.front() = MachineOperand::CreateImm(!Cond.front().getImm());
lib/Target/WebAssembly/WebAssemblyInstrInfo.h 57 SmallVectorImpl<MachineOperand> &Cond,
62 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
66 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
lib/Target/WebAssembly/WebAssemblyLateEHPrepare.cpp 262 const MachineOperand &CalleeOp = MI.getOperand(0);
lib/Target/WebAssembly/WebAssemblyMCInstLower.cpp 48 WebAssemblyMCInstLower::GetGlobalAddressSymbol(const MachineOperand &MO) const {
71 const MachineOperand &MO) const {
125 MCOperand WebAssemblyMCInstLower::lowerSymbolOperand(const MachineOperand &MO,
212 const MachineOperand &MO = MI->getOperand(I);
219 case MachineOperand::MO_MachineBasicBlock:
222 case MachineOperand::MO_Register: {
232 case MachineOperand::MO_Immediate:
241 for (const MachineOperand &MO : MI->defs())
243 for (const MachineOperand &MO : MI->explicit_uses())
273 case MachineOperand::MO_FPImmediate: {
285 case MachineOperand::MO_GlobalAddress:
288 case MachineOperand::MO_ExternalSymbol:
295 case MachineOperand::MO_MCSymbol:
lib/Target/WebAssembly/WebAssemblyMCInstLower.h 34 MCSymbol *GetGlobalAddressSymbol(const MachineOperand &MO) const;
35 MCSymbol *GetExternalSymbolSymbol(const MachineOperand &MO) const;
36 MCOperand lowerSymbolOperand(const MachineOperand &MO, MCSymbol *Sym) const;
lib/Target/WebAssembly/WebAssemblyMemIntrinsicResults.cpp 101 MachineOperand &O = *I++;
154 MachineOperand &Op1 = MI.getOperand(1);
lib/Target/WebAssembly/WebAssemblyPeephole.cpp 61 MachineOperand &MO, WebAssemblyFunctionInfo &MFI,
91 for (auto &MO : MI.explicit_operands()) {
154 MachineOperand &Op1 = MI.getOperand(1);
162 const auto &Op2 = MI.getOperand(2);
166 MachineOperand &MO = MI.getOperand(0);
lib/Target/WebAssembly/WebAssemblyRegColoring.cpp 69 for (MachineOperand &MO : MRI->reg_nodbg_operands(VReg))
lib/Target/WebAssembly/WebAssemblyRegStackify.cpp 85 MI->addOperand(MachineOperand::CreateReg(WebAssembly::VALUE_STACK,
91 MI->addOperand(MachineOperand::CreateReg(WebAssembly::VALUE_STACK,
108 MI->addOperand(MachineOperand::CreateImm(0));
111 MI->addOperand(MachineOperand::CreateImm(0));
116 MI->addOperand(MachineOperand::CreateFPImm(Val));
121 MI->addOperand(MachineOperand::CreateFPImm(Val));
125 MI->addOperand(MachineOperand::CreateReg(TempReg, false));
143 const MachineOperand &MO = MI.getOperand(CalleeOpNo);
298 for (auto &I : MRI.use_nodbg_operands(Reg)) {
334 for (const MachineOperand &MO : Def->operands()) {
391 for (const MachineOperand &MO : I->operands())
400 static bool oneUseDominatesOtherUses(unsigned Reg, const MachineOperand &OneUse,
411 for (const MachineOperand &Use : MRI.use_nodbg_operands(Reg)) {
436 const MachineOperand &MO = UseInst->getOperand(0);
444 const MachineOperand &NewUse = *MRI.use_nodbg_begin(DefReg);
483 static MachineInstr *moveForSingleUse(unsigned Reg, MachineOperand &Op,
529 unsigned Reg, MachineOperand &Op, MachineInstr &Def, MachineBasicBlock &MBB,
597 unsigned Reg, MachineOperand &Op, MachineInstr *Def, MachineBasicBlock &MBB,
612 MachineOperand &DefMO = Def->getOperand(0);
666 MachineOperand &pop() {
668 MachineOperand &Op = *Range.begin();
711 for (const MachineOperand &MO : Range)
804 MachineOperand &Op = TreeWalker.pop();
915 for (MachineOperand &MO : reverse(MI.explicit_operands())) {
lib/Target/WebAssembly/WebAssemblyRegisterInfo.cpp 92 MachineOperand &OtherMO = MI.getOperand(3 - FIOperandNum);
102 MachineOperand &ImmMO = Def->getOperand(1);
lib/Target/WebAssembly/WebAssemblyReplacePhysRegs.cpp 89 MachineOperand &MO = *I++;
lib/Target/WebAssembly/WebAssemblyUtilities.cpp 32 const MachineOperand &MO = MI.getOperand(0);
52 const MachineOperand &MO = MI.getOperand(getCalleeOpNo(MI.getOpcode()));
lib/Target/X86/X86AsmPrinter.cpp 111 void X86AsmPrinter::PrintSymbolOperand(const MachineOperand &MO,
115 case MachineOperand::MO_ConstantPoolIndex:
119 case MachineOperand::MO_GlobalAddress: {
204 const MachineOperand &MO = MI->getOperand(OpNo);
208 case MachineOperand::MO_Register: {
215 case MachineOperand::MO_Immediate:
221 case MachineOperand::MO_GlobalAddress: {
227 case MachineOperand::MO_BlockAddress: {
240 const MachineOperand &MO = MI->getOperand(OpNo);
241 if (!Modifier || MO.getType() != MachineOperand::MO_Register)
260 const MachineOperand &MO = MI->getOperand(OpNo);
263 case MachineOperand::MO_Register:
267 case MachineOperand::MO_Immediate:
270 case MachineOperand::MO_GlobalAddress:
278 const MachineOperand &BaseReg = MI->getOperand(OpNo + X86::AddrBaseReg);
279 const MachineOperand &IndexReg = MI->getOperand(OpNo + X86::AddrIndexReg);
280 const MachineOperand &DispSpec = MI->getOperand(OpNo + X86::AddrDisp);
294 case MachineOperand::MO_Immediate: {
300 case MachineOperand::MO_GlobalAddress:
301 case MachineOperand::MO_ConstantPoolIndex:
331 const MachineOperand &Segment = MI->getOperand(OpNo + X86::AddrSegmentReg);
341 const MachineOperand &BaseReg = MI->getOperand(OpNo + X86::AddrBaseReg);
343 const MachineOperand &IndexReg = MI->getOperand(OpNo + X86::AddrIndexReg);
344 const MachineOperand &DispSpec = MI->getOperand(OpNo + X86::AddrDisp);
345 const MachineOperand &SegReg = MI->getOperand(OpNo + X86::AddrSegmentReg);
389 static bool printAsmMRegister(X86AsmPrinter &P, const MachineOperand &MO,
439 const MachineOperand &MO = MI->getOperand(OpNo);
449 case MachineOperand::MO_Immediate:
452 case MachineOperand::MO_ConstantPoolIndex:
453 case MachineOperand::MO_JumpTableIndex:
454 case MachineOperand::MO_ExternalSymbol:
456 case MachineOperand::MO_GlobalAddress:
461 case MachineOperand::MO_Register:
473 case MachineOperand::MO_Immediate:
476 case MachineOperand::MO_ConstantPoolIndex:
477 case MachineOperand::MO_JumpTableIndex:
478 case MachineOperand::MO_ExternalSymbol:
480 case MachineOperand::MO_GlobalAddress:
lib/Target/X86/X86AsmPrinter.h 105 void PrintSymbolOperand(const MachineOperand &MO, raw_ostream &O) override;
lib/Target/X86/X86AvoidStoreForwardingBlocks.cpp 297 static MachineOperand &getBaseOperand(MachineInstr *MI) {
302 static MachineOperand &getDispOperand(MachineInstr *MI) {
312 MachineOperand &Base = getBaseOperand(MI);
313 MachineOperand &Disp = getDispOperand(MI);
314 MachineOperand &Scale = MI->getOperand(AddrOffset + X86::AddrScaleAmt);
315 MachineOperand &Index = MI->getOperand(AddrOffset + X86::AddrIndexReg);
316 MachineOperand &Segment = MI->getOperand(AddrOffset + X86::AddrSegmentReg);
388 MachineOperand &LoadBase = getBaseOperand(LoadInst);
389 MachineOperand &StoreBase = getBaseOperand(StoreInst);
429 MachineOperand &StoreSrcVReg = StoreInst->getOperand(X86::AddrNumOperands);
498 MachineOperand &LoadBase = getBaseOperand(LoadInst);
499 MachineOperand &StoreBase = getBaseOperand(StoreInst);
546 MachineOperand &StoreMO = *UI++;
618 MachineOperand &LoadBase = getBaseOperand(LoadInst);
619 MachineOperand &StoreBase = getBaseOperand(StoreInst);
lib/Target/X86/X86CallFrameOptimization.cpp 291 MachineOperand ImmOp = MI->getOperand(X86::AddrNumOperands);
297 MachineOperand ImmOp = MI->getOperand(X86::AddrNumOperands);
335 for (const MachineOperand &MO : MI->operands()) {
453 for (const MachineOperand &MO : I->uses()) {
509 MachineOperand PushOp = Store->getOperand(X86::AddrNumOperands);
lib/Target/X86/X86CmovConversion.cpp 391 DenseMap<MachineOperand *, MachineInstr *> OperandToDefMap;
435 for (auto &MO : MI.uses()) {
456 for (auto &MO : MI.operands()) {
781 for (auto &MOp : NewMI->uses()) {
lib/Target/X86/X86CondBrFolding.cpp 192 MachineOperand &MO = MI->getOperand(i);
lib/Target/X86/X86DomainReassignment.cpp 158 for (auto &Op : MI->explicit_operands())
512 for (auto &MO : MRI->use_operands(Reg)) {
576 auto &Op = DefMI->getOperand(OpIdx);
592 for (auto &DefOp : UseMI.defs()) {
lib/Target/X86/X86EvexToVex.cpp 130 for (const MachineOperand &MO : MI.explicit_operands()) {
159 MachineOperand &Imm = MI.getOperand(MI.getNumExplicitOperands()-1);
174 MachineOperand &Imm = MI.getOperand(MI.getNumExplicitOperands()-1);
196 const MachineOperand &Imm = MI.getOperand(MI.getNumExplicitOperands()-1);
lib/Target/X86/X86ExpandPseudo.cpp 86 MachineOperand Selector = JTInst->getOperand(0);
196 MachineOperand &JumpTarget = MBBI->getOperand(0);
197 MachineOperand &StackAdjust = MBBI->getOperand(isMem ? X86::AddrNumOperands
287 MachineOperand &DestAddr = MBBI->getOperand(0);
350 const MachineOperand &InArg = MBBI->getOperand(6);
lib/Target/X86/X86FastISel.cpp 3939 SmallVector<MachineOperand, 8> AddrOps;
3956 MachineOperand &MO = *I;
lib/Target/X86/X86FixupBWInsts.cpp 249 for (auto &MO: OrigMI->implicit_operands()) {
301 auto &OldDest = MI->getOperand(0);
302 auto &OldSrc = MI->getOperand(1);
328 for (auto &Op : MI->implicit_operands())
lib/Target/X86/X86FixupLEAs.cpp 43 void seekLEAFixup(MachineOperand &p, MachineBasicBlock::iterator &I,
81 RegUsageState usesRegister(MachineOperand &p, MachineBasicBlock::iterator I);
132 const MachineOperand &Src = MI.getOperand(1);
133 const MachineOperand &Dest = MI.getOperand(0);
239 FixupLEAPass::usesRegister(MachineOperand &p, MachineBasicBlock::iterator I) {
244 MachineOperand &opnd = MI.getOperand(i);
304 static inline bool hasInefficientLEABaseReg(const MachineOperand &Base,
305 const MachineOperand &Index) {
310 static inline bool hasLEAOffset(const MachineOperand &Offset) {
327 const MachineOperand &Offset) {
357 const MachineOperand &Base = MI.getOperand(1 + X86::AddrBaseReg);
358 const MachineOperand &Scale = MI.getOperand(1 + X86::AddrScaleAmt);
359 const MachineOperand &Index = MI.getOperand(1 + X86::AddrIndexReg);
360 const MachineOperand &Disp = MI.getOperand(1 + X86::AddrDisp);
361 const MachineOperand &Segment = MI.getOperand(1 + X86::AddrSegmentReg);
450 MachineOperand &p = MI.getOperand(AddrOffset + X86::AddrBaseReg);
454 MachineOperand &q = MI.getOperand(AddrOffset + X86::AddrIndexReg);
461 void FixupLEAPass::seekLEAFixup(MachineOperand &p,
485 const MachineOperand &Dst = MI.getOperand(0);
486 const MachineOperand &Base = MI.getOperand(1 + X86::AddrBaseReg);
487 const MachineOperand &Scale = MI.getOperand(1 + X86::AddrScaleAmt);
488 const MachineOperand &Index = MI.getOperand(1 + X86::AddrIndexReg);
489 const MachineOperand &Offset = MI.getOperand(1 + X86::AddrDisp);
490 const MachineOperand &Segment = MI.getOperand(1 + X86::AddrSegmentReg);
508 const MachineOperand &Src = SrcR1 == DstR ? Index : Base;
517 const MachineOperand &SrcR = SrcR1 == DstR ? Base : Index;
535 const MachineOperand &Dest = MI.getOperand(0);
536 const MachineOperand &Base = MI.getOperand(1 + X86::AddrBaseReg);
537 const MachineOperand &Scale = MI.getOperand(1 + X86::AddrScaleAmt);
538 const MachineOperand &Index = MI.getOperand(1 + X86::AddrIndexReg);
539 const MachineOperand &Offset = MI.getOperand(1 + X86::AddrDisp);
540 const MachineOperand &Segment = MI.getOperand(1 + X86::AddrSegmentReg);
lib/Target/X86/X86FixupSetCC.cpp 80 for (auto &Op : MI->implicit_operands())
88 for (auto &Op : MI->implicit_operands())
lib/Target/X86/X86FlagsCopyLowering.cpp 121 void rewriteCopy(MachineInstr &MI, MachineOperand &FlagUse,
311 MachineOperand &OpV = MI.getOperand(OpIdx);
312 MachineOperand &OpMBB = MI.getOperand(OpIdx + 1);
328 MI.addOperand(MF, MachineOperand::CreateMBB(&NewMBB));
367 MachineOperand &VOp = CopyI->getOperand(1);
402 MachineOperand &DOp = CopyI->getOperand(0);
552 MachineOperand *FlagUse = MI.findRegisterUseOperand(X86::EFLAGS);
878 MachineOperand &FlagUse,
lib/Target/X86/X86FloatingPoint.cpp 314 static unsigned getFPReg(const MachineOperand &MO) {
449 const MachineOperand &MO = MI.getOperand(i);
977 for (const auto &MO : I->operands()) {
1018 MachineOperand &Op = MI.getOperand(i);
1105 MachineOperand::CreateReg(X86::ST0, /*isDef*/ true, /*isImp*/ true));
1151 MachineOperand::CreateReg(X86::ST0, /*isDef*/ false, /*isImp*/ true));
1454 const MachineOperand &MO1 = MI.getOperand(1);
1455 const MachineOperand &MO0 = MI.getOperand(0);
1532 const MachineOperand &MO = MI.getOperand(i + 1);
1603 MachineOperand &Op = MI.getOperand(i);
1632 MachineOperand &Op = MI.getOperand(i);
1695 SmallVector<MachineOperand *, 2> Uses;
1698 for (auto &MO : I->operands()) {
1715 for (auto *MO : Uses)
lib/Target/X86/X86FrameLowering.cpp 176 MachineOperand &MO = MBBI->getOperand(i);
216 for (const MachineOperand &MO : MI.operands()) {
2624 const MachineOperand &MO = MI.getOperand(0);
2744 auto RegMask = Prev->getOperand(1);
2762 for (const MachineOperand &MO : Prev->implicit_operands()) {
3121 for (const MachineOperand &MO : MI.operands()) {
lib/Target/X86/X86ISelLowering.cpp 4068 unsigned RegMaskSize = MachineOperand::getRegMaskSize(TRI->getNumRegs());
29270 MachineOperand &Base = MI.getOperand(1);
29271 MachineOperand &Scale = MI.getOperand(2);
29272 MachineOperand &Index = MI.getOperand(3);
29273 MachineOperand &Disp = MI.getOperand(4);
29274 MachineOperand &Segment = MI.getOperand(5);
30380 for (const auto &MO : MI.operands()) {
30716 const MachineOperand &MO = MI.getOperand(i);
30842 const MachineOperand &MO = MI.getOperand(i);
30854 const MachineOperand &MO = MI.getOperand(i);
31136 for (auto &MOp : II.operands())
lib/Target/X86/X86IndirectBranchTracking.cpp 87 static bool IsCallReturnTwice(llvm::MachineOperand &MOp) {
lib/Target/X86/X86InstrBuilder.h 65 void getFullAddress(SmallVectorImpl<MachineOperand> &MO) {
69 MO.push_back(MachineOperand::CreateReg(Base.Reg, false, false, false,
73 MO.push_back(MachineOperand::CreateFI(Base.FrameIndex));
76 MO.push_back(MachineOperand::CreateImm(Scale));
77 MO.push_back(MachineOperand::CreateReg(IndexReg, false, false, false, false,
81 MO.push_back(MachineOperand::CreateGA(GV, Disp, GVOpFlags));
83 MO.push_back(MachineOperand::CreateImm(Disp));
85 MO.push_back(MachineOperand::CreateReg(0, false, false, false, false, false,
95 const MachineOperand &Op0 = MI->getOperand(Operand);
104 const MachineOperand &Op1 = MI->getOperand(Operand + 1);
107 const MachineOperand &Op2 = MI->getOperand(Operand + 2);
110 const MachineOperand &Op3 = MI->getOperand(Operand + 3);
148 addOffset(const MachineInstrBuilder &MIB, const MachineOperand& Offset) {
lib/Target/X86/X86InstrInfo.cpp 674 MachineOperand &MO = MI.getOperand(i);
703 bool X86InstrInfo::classifyLEAReg(MachineInstr &MI, const MachineOperand &Src,
705 bool &isKill, MachineOperand &ImplicitOp,
902 const MachineOperand &Dest = MI.getOperand(0);
903 const MachineOperand &Src = MI.getOperand(1);
952 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
952 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
988 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
988 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
1011 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
1011 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
1046 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
1046 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
1051 const MachineOperand &Src2 = MI.getOperand(2);
1054 MachineOperand ImplicitOp2 = MachineOperand::CreateReg(0, false);
1054 MachineOperand ImplicitOp2 = MachineOperand::CreateReg(0, false);
1095 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
1095 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
1136 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
1136 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
1666 WorkingMI.addOperand(MachineOperand::CreateImm(Mask));
1677 WorkingMI.addOperand(MachineOperand::CreateImm(0x02));
2407 SmallVectorImpl<MachineOperand> &BranchCond,
2438 MachineBasicBlock &MBB, SmallVectorImpl<MachineOperand> &BranchCond,
2471 SmallVector<std::pair<MCPhysReg, const MachineOperand *>, 8> Clobbers;
2504 SmallVectorImpl<MachineOperand> &Cond,
2608 Cond.push_back(MachineOperand::CreateImm(BranchCode));
2671 SmallVectorImpl<MachineOperand> &Cond,
2682 SmallVector<MachineOperand, 4> Cond;
2736 MBP.RHS = MachineOperand::CreateImm(0);
2772 ArrayRef<MachineOperand> Cond,
2830 ArrayRef<MachineOperand> Cond,
3050 const MachineOperand *&Src,
3051 const MachineOperand *&Dest) const {
3196 const MachineInstr &MemOp, const MachineOperand *&BaseOp, int64_t &Offset,
3216 const MachineOperand &DispMO = MemOp.getOperand(MemRefBegin + X86::AddrDisp);
3815 MachineOperand *FlagDef = Sub->findRegisterDefOperand(X86::EFLAGS);
3847 MachineOperand &MO = MI.getOperand(i);
4347 const MachineOperand &MO = MI.getOperand(0);
4560 const MachineOperand &MO = MI.getOperand(OpNum);
4608 static void addOperands(MachineInstrBuilder &MIB, ArrayRef<MachineOperand> MOs,
4622 const MachineOperand &MO = MOs[i];
4639 MachineOperand &MO = NewMI.getOperand(Idx);
4659 ArrayRef<MachineOperand> MOs,
4673 MachineOperand &MO = MI.getOperand(i + 2);
4677 MachineOperand &MO = MI.getOperand(i);
4690 unsigned OpNo, ArrayRef<MachineOperand> MOs,
4700 MachineOperand &MO = MI.getOperand(i);
4718 ArrayRef<MachineOperand> MOs,
4729 ArrayRef<MachineOperand> MOs, MachineBasicBlock::iterator InsertPt,
4824 ArrayRef<MachineOperand> MOs, MachineBasicBlock::iterator InsertPt,
5017 MachineOperand &MO = MI.getOperand(Op);
5052 MachineOperand::CreateFI(FrameIndex), InsertPt,
5276 SmallVector<MachineOperand,X86::AddrNumOperands> MOs;
5343 MOs.push_back(MachineOperand::CreateReg(PICBase, false));
5344 MOs.push_back(MachineOperand::CreateImm(1));
5345 MOs.push_back(MachineOperand::CreateReg(0, false));
5346 MOs.push_back(MachineOperand::CreateCPI(CPI, 0));
5347 MOs.push_back(MachineOperand::CreateReg(0, false));
5480 SmallVector<MachineOperand, X86::AddrNumOperands> AddrOps;
5481 SmallVector<MachineOperand,2> BeforeOps;
5482 SmallVector<MachineOperand,2> AfterOps;
5483 SmallVector<MachineOperand,4> ImpOps;
5485 MachineOperand &Op = MI.getOperand(i);
5519 MachineOperand &MO = NewMIs[0]->getOperand(i);
5532 for (MachineOperand &BeforeOp : BeforeOps)
5536 for (MachineOperand &AfterOp : AfterOps)
5538 for (MachineOperand &ImpOp : ImpOps) {
5556 MachineOperand &MO0 = DataMI->getOperand(0);
5557 MachineOperand &MO1 = DataMI->getOperand(1);
5993 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
7563 const MachineOperand *Op = nullptr;
7575 const MachineOperand &Op1 = MI.getOperand(1);
7576 const MachineOperand &Op2 = MI.getOperand(3);
7647 return ParamLoadedValue(MachineOperand::CreateImm(0), Expr);
7670 MachineOperand &OldOp1 = OldMI1.getOperand(3);
7671 MachineOperand &OldOp2 = OldMI2.getOperand(3);
7672 MachineOperand &NewOp1 = NewMI1.getOperand(3);
7673 MachineOperand &NewOp2 = NewMI2.getOperand(3);
8096 for (const MachineOperand &MOP : MI.operands())
lib/Target/X86/X86InstrInfo.h 107 inline static bool isScale(const MachineOperand &MO) {
140 SmallVectorImpl<MachineOperand> &Cond,
223 bool classifyLEAReg(MachineInstr &MI, const MachineOperand &Src,
225 bool &isKill, MachineOperand &ImplicitOp,
283 bool canMakeTailCallConditional(SmallVectorImpl<MachineOperand> &Cond,
286 SmallVectorImpl<MachineOperand> &Cond,
291 SmallVectorImpl<MachineOperand> &Cond,
295 const MachineOperand *&BaseOp,
305 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
308 bool canInsertSelect(const MachineBasicBlock &, ArrayRef<MachineOperand> Cond,
399 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
444 ArrayRef<MachineOperand> MOs,
547 bool isCopyInstrImpl(const MachineInstr &MI, const MachineOperand *&Source,
548 const MachineOperand *&Destination) const override;
564 ArrayRef<MachineOperand> MOs,
lib/Target/X86/X86InstructionSelector.cpp 577 MachineOperand &InxOp = I.getOperand(2);
lib/Target/X86/X86MCInstLower.cpp 63 const MachineOperand &MO) const;
66 MCSymbol *GetSymbolFromOperand(const MachineOperand &MO) const;
67 MCOperand LowerSymbolOperand(const MachineOperand &MO, MCSymbol *Sym) const;
118 MCSymbol *X86MCInstLower::GetSymbolFromOperand(const MachineOperand &MO) const {
191 MCOperand X86MCInstLower::LowerSymbolOperand(const MachineOperand &MO,
399 const MachineOperand &MO) const {
404 case MachineOperand::MO_Register:
409 case MachineOperand::MO_Immediate:
411 case MachineOperand::MO_MachineBasicBlock:
412 case MachineOperand::MO_GlobalAddress:
413 case MachineOperand::MO_ExternalSymbol:
415 case MachineOperand::MO_MCSymbol:
417 case MachineOperand::MO_JumpTableIndex:
419 case MachineOperand::MO_ConstantPoolIndex:
421 case MachineOperand::MO_BlockAddress:
424 case MachineOperand::MO_RegisterMask:
468 for (const MachineOperand &MO : MI->operands())
1107 const MachineOperand &CallTarget = SOpers.getCallTarget();
1111 case MachineOperand::MO_GlobalAddress:
1112 case MachineOperand::MO_ExternalSymbol:
1121 case MachineOperand::MO_Immediate:
1129 case MachineOperand::MO_Register:
1257 const MachineOperand &CalleeMO = opers.getCallTarget();
1267 case MachineOperand::MO_Immediate:
1271 case MachineOperand::MO_ExternalSymbol:
1272 case MachineOperand::MO_GlobalAddress:
1375 MachineOperand TOp = MachineOperand::CreateMCSymbol(TSym);
1375 MachineOperand TOp = MachineOperand::CreateMCSymbol(TSym);
1476 MachineOperand TOp = MachineOperand::CreateMCSymbol(TSym);
1476 MachineOperand TOp = MachineOperand::CreateMCSymbol(TSym);
1605 const MachineOperand &Op) {
1637 const MachineOperand &DstOp = MI->getOperand(0);
1638 const MachineOperand &SrcOp1 = MI->getOperand(SrcOp1Idx);
1639 const MachineOperand &SrcOp2 = MI->getOperand(SrcOp2Idx);
1663 const MachineOperand &WriteMaskOp = MI->getOperand(SrcOp1Idx - 1);
2145 const MachineOperand &MaskOp = MI->getOperand(MaskIdx);
2217 const MachineOperand &MaskOp = MI->getOperand(MaskIdx);
2237 const MachineOperand &CtrlOp = MI->getOperand(MI->getNumOperands() - 1);
2248 const MachineOperand &MaskOp = MI->getOperand(6);
2265 const MachineOperand &MaskOp = MI->getOperand(6);
2284 const MachineOperand &DstOp = MI->getOperand(0);
2365 const MachineOperand &DstOp = MI->getOperand(0);
2475 const MachineOperand &DstOp = MI->getOperand(0);
lib/Target/X86/X86OptimizeLEAs.cpp 64 static inline bool isIdenticalOp(const MachineOperand &MO1,
65 const MachineOperand &MO2);
69 static bool isSimilarDispOp(const MachineOperand &MO1,
70 const MachineOperand &MO2);
80 MemOpKey(const MachineOperand *Base, const MachineOperand *Scale,
80 MemOpKey(const MachineOperand *Base, const MachineOperand *Scale,
81 const MachineOperand *Index, const MachineOperand *Segment,
81 const MachineOperand *Index, const MachineOperand *Segment,
82 const MachineOperand *Disp)
104 const MachineOperand *Operands[4];
107 const MachineOperand *Disp;
116 using PtrInfo = DenseMapInfo<const MachineOperand *>;
145 case MachineOperand::MO_Immediate:
147 case MachineOperand::MO_ConstantPoolIndex:
148 case MachineOperand::MO_JumpTableIndex:
151 case MachineOperand::MO_ExternalSymbol:
154 case MachineOperand::MO_GlobalAddress:
157 case MachineOperand::MO_BlockAddress:
160 case MachineOperand::MO_MCSymbol:
163 case MachineOperand::MO_MachineBasicBlock:
198 static inline bool isIdenticalOp(const MachineOperand &MO1,
199 const MachineOperand &MO2) {
205 static bool isValidDispOp(const MachineOperand &MO) {
211 static bool isSimilarDispOp(const MachineOperand &MO1,
212 const MachineOperand &MO2) {
394 const MachineOperand &Op1 = MI1.getOperand(N1 + X86::AddrDisp);
395 const MachineOperand &Op2 = MI2.getOperand(N2 + X86::AddrDisp);
435 for (auto &MO : MRI->use_nodbg_operands(Last.getOperand(0).getReg())) {
622 MachineOperand &MO = *UI++;
643 MachineOperand &Op = MI.getOperand(MemOpNo + X86::AddrDisp);
lib/Target/X86/X86RegisterInfo.cpp 550 if (MachineOperand::clobbersPhysReg(RegMask, getBaseRegister()))
748 MachineOperand &FI = MI.getOperand(FIOperandNum);
lib/Target/X86/X86SpeculativeLoadHardening.cpp 196 hardenLoadAddr(MachineInstr &MI, MachineOperand &BaseMO,
197 MachineOperand &IndexMO,
262 SmallVector<MachineOperand, 4> Cond;
291 MachineOperand &OpV = MI.getOperand(OpIdx);
292 MachineOperand &OpMBB = MI.getOperand(OpIdx + 1);
305 MI.addOperand(MF, MachineOperand::CreateMBB(&NewMBB));
484 MachineOperand *ZeroEFLAGSDefOp =
547 for (MachineOperand &Op : CMovI->operands()) {
1593 if (MachineOperand *DefOp = MI.findRegisterDefOperand(X86::EFLAGS)) {
1678 for (MachineOperand &Def : MI.defs())
1712 MachineOperand &BaseMO =
1714 MachineOperand &IndexMO =
1761 for (MachineOperand &Def : MI.defs())
1785 MachineOperand &BaseMO =
1787 MachineOperand &IndexMO =
1947 MachineInstr &MI, MachineOperand &BaseMO, MachineOperand &IndexMO,
1947 MachineInstr &MI, MachineOperand &BaseMO, MachineOperand &IndexMO,
1956 SmallVector<MachineOperand *, 2> HardenOpRegs;
2033 for (MachineOperand *Op : HardenOpRegs) {
2183 MachineOperand &BaseMO =
2185 MachineOperand &IndexMO =
2334 auto &DefOp = MI.getOperand(0);
2616 auto &TargetOp = MI.getOperand(0);
lib/Target/X86/X86VZeroUpper.cpp 141 static bool clobbersAllYmmAndZmmRegs(const MachineOperand &MO) {
154 for (const MachineOperand &MO : MI.operands()) {
170 for (const MachineOperand &MO : MI.operands()) {
lib/Target/XCore/XCoreAsmPrinter.cpp 205 const MachineOperand &MO = MI->getOperand(opNum);
207 case MachineOperand::MO_Register:
210 case MachineOperand::MO_Immediate:
213 case MachineOperand::MO_MachineBasicBlock:
216 case MachineOperand::MO_GlobalAddress:
219 case MachineOperand::MO_ConstantPoolIndex:
223 case MachineOperand::MO_BlockAddress:
lib/Target/XCore/XCoreInstrInfo.cpp 53 static bool isZeroImm(const MachineOperand &op) {
192 SmallVectorImpl<MachineOperand> &Cond,
220 Cond.push_back(MachineOperand::CreateImm(BranchCode));
241 Cond.push_back(MachineOperand::CreateImm(BranchCode));
274 ArrayRef<MachineOperand> Cond,
403 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
lib/Target/XCore/XCoreInstrInfo.h 54 SmallVectorImpl<MachineOperand> &Cond,
58 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
82 SmallVectorImpl<MachineOperand> &Cond) const override;
lib/Target/XCore/XCoreMCInstLower.cpp 31 MCOperand XCoreMCInstLower::LowerSymbolOperand(const MachineOperand &MO,
38 case MachineOperand::MO_MachineBasicBlock:
41 case MachineOperand::MO_GlobalAddress:
45 case MachineOperand::MO_BlockAddress:
49 case MachineOperand::MO_ExternalSymbol:
53 case MachineOperand::MO_JumpTableIndex:
56 case MachineOperand::MO_ConstantPoolIndex:
77 MCOperand XCoreMCInstLower::LowerOperand(const MachineOperand &MO,
83 case MachineOperand::MO_Register:
87 case MachineOperand::MO_Immediate:
89 case MachineOperand::MO_MachineBasicBlock:
90 case MachineOperand::MO_GlobalAddress:
91 case MachineOperand::MO_ExternalSymbol:
92 case MachineOperand::MO_JumpTableIndex:
93 case MachineOperand::MO_ConstantPoolIndex:
94 case MachineOperand::MO_BlockAddress:
96 case MachineOperand::MO_RegisterMask:
107 const MachineOperand &MO = MI->getOperand(i);
lib/Target/XCore/XCoreMCInstLower.h 25 typedef MachineOperand::MachineOperandType MachineOperandType;
32 MCOperand LowerOperand(const MachineOperand& MO, unsigned offset = 0) const;
35 MCOperand LowerSymbolOperand(const MachineOperand &MO,
lib/Target/XCore/XCoreRegisterInfo.cpp 264 MachineOperand &FrameOp = MI.getOperand(FIOperandNum);
unittests/CodeGen/MachineInstrTest.cpp 187 MI1->addOperand(*MF, MachineOperand::CreateReg(VirtualDef1, /*isDef*/ true));
188 MI1->addOperand(*MF, MachineOperand::CreateReg(VirtualUse, /*isDef*/ false));
191 MI2->addOperand(*MF, MachineOperand::CreateReg(VirtualDef2, /*isDef*/ true));
192 MI2->addOperand(*MF, MachineOperand::CreateReg(VirtualUse, /*isDef*/ false));
207 MI3->addOperand(*MF, MachineOperand::CreateReg(VirtualDef1, /*isDef*/ true));
208 MI3->addOperand(*MF, MachineOperand::CreateReg(SentinelReg, /*isDef*/ true));
211 MI4->addOperand(*MF, MachineOperand::CreateReg(VirtualDef2, /*isDef*/ true));
212 MI4->addOperand(*MF, MachineOperand::CreateReg(SentinelReg, /*isDef*/ false));
261 MachineOperand::CreateReg(VirtualDef1, /*isDef*/ true));
263 MachineOperand::CreateReg(VirtualReg, /*isDef*/ false));
267 MachineOperand::CreateReg(VirtualDef2, /*isDef*/ true));
269 MachineOperand::CreateReg(VirtualReg, /*isDef*/ false));
273 MachineOperand::CreateReg(VirtualDef1, /*isDef*/ true));
275 MachineOperand::CreateReg(SentinelReg, /*isDef*/ false));
279 MachineOperand::CreateReg(VirtualDef1, /*isDef*/ true));
281 MachineOperand::CreateReg(SentinelReg, /*isDef*/ true));
285 MachineOperand::CreateReg(VirtualDef2, /*isDef*/ true));
287 MachineOperand::CreateReg(PhysicalReg, /*isDef*/ false));
291 MachineOperand::CreateReg(VirtualDef2, /*isDef*/ true));
293 MachineOperand::CreateReg(PhysicalReg, /*isDef*/ true));
331 MI->addOperand(*MF, MachineOperand::CreateReg(0, /*isDef*/ true));
unittests/CodeGen/MachineOperandTest.cpp 27 MachineOperand MO = MachineOperand::CreateImm(50);
27 MachineOperand MO = MachineOperand::CreateImm(50);
49 MachineOperand MO = MachineOperand::CreateRegMask(&Dummy);
49 MachineOperand MO = MachineOperand::CreateRegMask(&Dummy);
66 MachineOperand MO = MachineOperand::CreateReg(
66 MachineOperand MO = MachineOperand::CreateReg(
91 MachineOperand MO = MachineOperand::CreateCImm(CImm);
91 MachineOperand MO = MachineOperand::CreateCImm(CImm);
109 MachineOperand MO = MachineOperand::CreateImm(3);
109 MachineOperand MO = MachineOperand::CreateImm(3);
120 MachineOperand::printSubRegIdx(OS, MO.getImm(), nullptr);
126 MachineOperand MO = MachineOperand::CreateCPI(0, 8);
126 MachineOperand MO = MachineOperand::CreateCPI(0, 8);
158 MachineOperand MO = MachineOperand::CreateTargetIndex(0, 8);
158 MachineOperand MO = MachineOperand::CreateTargetIndex(0, 8);
188 MachineOperand MO = MachineOperand::CreateJTI(3);
188 MachineOperand MO = MachineOperand::CreateJTI(3);
204 MachineOperand MO = MachineOperand::CreateES("foo");
204 MachineOperand MO = MachineOperand::CreateES("foo");
249 MachineOperand MO = MachineOperand::CreateGA(GV, 12);
249 MachineOperand MO = MachineOperand::CreateGA(GV, 12);
279 MachineOperand MO = MachineOperand::CreateRegLiveOut(&Mask);
279 MachineOperand MO = MachineOperand::CreateRegLiveOut(&Mask);
303 MachineOperand MO = MachineOperand::CreateMetadata(Node);
303 MachineOperand MO = MachineOperand::CreateMetadata(Node);
325 MachineOperand MO = MachineOperand::CreateMCSymbol(Sym);
325 MachineOperand MO = MachineOperand::CreateMCSymbol(Sym);
341 MachineOperand MO = MachineOperand::CreateCFIIndex(8);
341 MachineOperand MO = MachineOperand::CreateCFIIndex(8);
358 MachineOperand MO = MachineOperand::CreateIntrinsicID(Intrinsic::bswap);
358 MachineOperand MO = MachineOperand::CreateIntrinsicID(Intrinsic::bswap);
375 MO = MachineOperand::CreateIntrinsicID((Intrinsic::ID)-1);
387 MachineOperand MO = MachineOperand::CreatePredicate(CmpInst::ICMP_EQ);
387 MachineOperand MO = MachineOperand::CreatePredicate(CmpInst::ICMP_EQ);
404 MachineOperand MO1 = MachineOperand::CreateES(SymName1);
404 MachineOperand MO1 = MachineOperand::CreateES(SymName1);
405 MachineOperand MO2 = MachineOperand::CreateES(SymName2);
405 MachineOperand MO2 = MachineOperand::CreateES(SymName2);
usr/include/c++/7.4.0/array 50 typedef _Tp _Type[_Nm];
51 typedef __is_swappable<_Tp> _Is_swappable;
52 typedef __is_nothrow_swappable<_Tp> _Is_nothrow_swappable;
54 static constexpr _Tp&
58 static constexpr _Tp*
96 typedef _Tp value_type;
109 typedef _GLIBCXX_STD_C::__array_traits<_Tp, _Nm> _AT_Type;
usr/include/c++/7.4.0/bits/alloc_traits.h 387 using allocator_type = allocator<_Tp>;
389 using value_type = _Tp;
392 using pointer = _Tp*;
395 using const_pointer = const _Tp*;
474 construct(allocator_type& __a, _Up* __p, _Args&&... __args)
474 construct(allocator_type& __a, _Up* __p, _Args&&... __args)
486 destroy(allocator_type& __a, _Up* __p)
usr/include/c++/7.4.0/bits/allocator.h 108 class allocator: public __allocator_base<_Tp>
113 typedef _Tp* pointer;
114 typedef const _Tp* const_pointer;
115 typedef _Tp& reference;
116 typedef const _Tp& const_reference;
117 typedef _Tp value_type;
137 allocator(const allocator<_Tp1>&) throw() { }
usr/include/c++/7.4.0/bits/move.h 46 inline _GLIBCXX_CONSTEXPR _Tp*
47 __addressof(_Tp& __r) _GLIBCXX_NOEXCEPT
72 constexpr _Tp&&
73 forward(typename std::remove_reference<_Tp>::type& __t) noexcept
83 constexpr _Tp&&
84 forward(typename std::remove_reference<_Tp>::type&& __t) noexcept
98 move(_Tp&& __t) noexcept
104 : public __and_<__not_<is_nothrow_move_constructible<_Tp>>,
105 is_copy_constructible<_Tp>>::type { };
136 inline _GLIBCXX17_CONSTEXPR _Tp*
137 addressof(_Tp& __r) noexcept
143 const _Tp* addressof(const _Tp&&) = delete;
143 const _Tp* addressof(const _Tp&&) = delete;
184 typename enable_if<__and_<__not_<__is_tuple_like<_Tp>>,
185 is_move_constructible<_Tp>,
186 is_move_assignable<_Tp>>::value>::type
187 swap(_Tp& __a, _Tp& __b)
187 swap(_Tp& __a, _Tp& __b)
198 _Tp __tmp = _GLIBCXX_MOVE(__a);
usr/include/c++/7.4.0/bits/stl_construct.h 74 _Construct(_T1* __p, _Args&&... __args)
74 _Construct(_T1* __p, _Args&&... __args)
75 { ::new(static_cast<void*>(__p)) _T1(std::forward<_Args>(__args)...); }
75 { ::new(static_cast<void*>(__p)) _T1(std::forward<_Args>(__args)...); }
204 allocator<_Tp>&)
usr/include/c++/7.4.0/bits/stl_iterator.h 1224 __make_move_if_noexcept_iterator(_Tp* __i)
usr/include/c++/7.4.0/bits/stl_iterator_base_types.h 123 typedef _Tp value_type;
181 typedef _Tp value_type;
183 typedef _Tp* pointer;
184 typedef _Tp& reference;
192 typedef _Tp value_type;
194 typedef const _Tp* pointer;
195 typedef const _Tp& reference;
usr/include/c++/7.4.0/bits/stl_pair.h 100 return __and_<is_constructible<_T1, const _U1&>,
100 return __and_<is_constructible<_T1, const _U1&>,
107 return __and_<is_convertible<const _U1&, _T1>,
107 return __and_<is_convertible<const _U1&, _T1>,
114 return __and_<is_constructible<_T1, _U1&&>,
114 return __and_<is_constructible<_T1, _U1&&>,
121 return __and_<is_convertible<_U1&&, _T1>,
121 return __and_<is_convertible<_U1&&, _T1>,
128 using __do_converts = __and_<is_convertible<const _U1&, _T1>,
128 using __do_converts = __and_<is_convertible<const _U1&, _T1>,
133 return __and_<is_constructible<_T1, const _U1&>,
133 return __and_<is_constructible<_T1, const _U1&>,
142 using __do_converts = __and_<is_convertible<_U1&&, _T1>,
142 using __do_converts = __and_<is_convertible<_U1&&, _T1>,
147 return __and_<is_constructible<_T1, _U1&&>,
147 return __and_<is_constructible<_T1, _U1&&>,
209 : private __pair_base<_T1, _T2>
211 typedef _T1 first_type; /// @c first_type is the first bound type
214 _T1 first; /// @c first is a copy of the first object
252 using _PCCP = _PCC<true, _T1, _T2>;
260 constexpr pair(const _T1& __a, const _T2& __b)
269 explicit constexpr pair(const _T1& __a, const _T2& __b)
283 _T1, _T2>;
291 constexpr pair(const pair<_U1, _U2>& __p)
311 constexpr pair(_U1&& __x, const _T2& __y)
325 constexpr pair(const _T1& __x, _U2&& __y)
332 explicit pair(const _T1& __x, _U2&& __y)
341 constexpr pair(_U1&& __x, _U2&& __y)
342 : first(std::forward<_U1>(__x)), second(std::forward<_U2>(__y)) { }
360 constexpr pair(pair<_U1, _U2>&& __p)
361 : first(std::forward<_U1>(__p.first)),
379 __and_<is_copy_assignable<_T1>,
390 __and_<is_move_assignable<_T1>,
402 typename enable_if<__and_<is_assignable<_T1&, const _U1&>,
402 typename enable_if<__and_<is_assignable<_T1&, const _U1&>,
405 operator=(const pair<_U1, _U2>& __p)
413 typename enable_if<__and_<is_assignable<_T1&, _U1&&>,
413 typename enable_if<__and_<is_assignable<_T1&, _U1&&>,
416 operator=(pair<_U1, _U2>&& __p)
524 make_pair(_T1&& __x, _T2&& __y)
usr/include/c++/7.4.0/bits/stl_uninitialized.h 288 _ForwardIterator __result, allocator<_Tp>&)
usr/include/c++/7.4.0/bits/stl_vector.h 77 rebind<_Tp>::other _Tp_alloc_type;
216 class vector : protected _Vector_base<_Tp, _Alloc>
227 typedef _Vector_base<_Tp, _Alloc> _Base;
232 typedef _Tp value_type;
919 _Tp*
923 const _Tp*
1483 _M_realloc_insert(iterator __position, _Args&&... __args);
usr/include/c++/7.4.0/ext/alloc_traits.h 117 { typedef typename _Base_type::template rebind_alloc<_Tp> other; };
usr/include/c++/7.4.0/ext/new_allocator.h 63 typedef _Tp* pointer;
64 typedef const _Tp* const_pointer;
65 typedef _Tp& reference;
66 typedef const _Tp& const_reference;
67 typedef _Tp value_type;
111 return static_cast<_Tp*>(::operator new(__n * sizeof(_Tp)));
130 { return size_t(-1) / sizeof(_Tp); }
135 construct(_Up* __p, _Args&&... __args)
135 construct(_Up* __p, _Args&&... __args)
136 { ::new((void *)__p) _Up(std::forward<_Args>(__args)...); }
140 destroy(_Up* __p) { __p->~_Up(); }
usr/include/c++/7.4.0/initializer_list 50 typedef _E value_type;
51 typedef const _E& reference;
52 typedef const _E& const_reference;
54 typedef const _E* iterator;
55 typedef const _E* const_iterator;
usr/include/c++/7.4.0/type_traits 215 : public __is_void_helper<typename remove_cv<_Tp>::type>::type
326 : public __is_integral_helper<typename remove_cv<_Tp>::type>::type
354 : public __is_floating_point_helper<typename remove_cv<_Tp>::type>::type
381 : public __is_pointer_helper<typename remove_cv<_Tp>::type>::type
567 : public __is_null_pointer_helper<typename remove_cv<_Tp>::type>::type
581 : public __or_<is_lvalue_reference<_Tp>,
582 is_rvalue_reference<_Tp>>::type
588 : public __or_<is_integral<_Tp>, is_floating_point<_Tp>>::type
588 : public __or_<is_integral<_Tp>, is_floating_point<_Tp>>::type
601 : public __not_<__or_<is_function<_Tp>, is_reference<_Tp>,
601 : public __not_<__or_<is_function<_Tp>, is_reference<_Tp>,
602 is_void<_Tp>>>::type
611 : public __or_<is_arithmetic<_Tp>, is_enum<_Tp>, is_pointer<_Tp>,
611 : public __or_<is_arithmetic<_Tp>, is_enum<_Tp>, is_pointer<_Tp>,
611 : public __or_<is_arithmetic<_Tp>, is_enum<_Tp>, is_pointer<_Tp>,
612 is_member_pointer<_Tp>, is_null_pointer<_Tp>>::type
612 is_member_pointer<_Tp>, is_null_pointer<_Tp>>::type
631 : public __is_member_pointer_helper<typename remove_cv<_Tp>::type>::type
638 : public __or_<is_object<_Tp>, is_reference<_Tp>>::type
638 : public __or_<is_object<_Tp>, is_reference<_Tp>>::type
762 typename add_rvalue_reference<_Tp>::type declval() noexcept;
777 : public __and_<is_array<_Tp>, __not_<extent<_Tp>>>
777 : public __and_<is_array<_Tp>, __not_<extent<_Tp>>>
798 typedef decltype(__test<_Tp>(0)) type;
811 remove_all_extents<_Tp>::type>::type
825 : public __is_destructible_safe<_Tp>::type
889 typedef decltype(__test<_Tp>(0)) type;
894 : public __and_<__not_<is_void<_Tp>>,
895 __is_default_constructible_impl<_Tp>>
915 : public __is_default_constructible_atom<_Tp>::type
921 : public __is_default_constructible_safe<_Tp>::type
984 typedef decltype(__test<_Tp, _Arg>(0)) type;
989 : public __and_<is_destructible<_Tp>,
990 __is_direct_constructible_impl<_Tp, _Arg>>
1072 __is_direct_constructible_ref_cast<_Tp, _Arg>,
1073 __is_direct_constructible_new_safe<_Tp, _Arg>
1079 : public __is_direct_constructible_new<_Tp, _Arg>::type
1119 : public __is_direct_constructible<_Tp, _Arg>
1130 : public __is_constructible_impl<_Tp, _Args...>::type
1142 : public is_constructible<_Tp, const _Tp&>
1142 : public is_constructible<_Tp, const _Tp&>
1148 : public __is_copy_constructible_impl<_Tp>
1160 : public is_constructible<_Tp, _Tp&&>
1160 : public is_constructible<_Tp, _Tp&&>
1166 : public __is_move_constructible_impl<_Tp>
1215 : public __and_<is_constructible<_Tp, _Args...>,
1216 __is_nt_constructible_impl<_Tp, _Args...>>
1246 : public is_nothrow_constructible<_Tp, _Tp&&>
1246 : public is_nothrow_constructible<_Tp, _Tp&&>
1252 : public __is_nothrow_move_constructible_impl<_Tp>
1286 : public is_assignable<_Tp&, const _Tp&>
1286 : public is_assignable<_Tp&, const _Tp&>
1292 : public __is_copy_assignable_impl<_Tp>
1304 : public is_assignable<_Tp&, _Tp&&>
1304 : public is_assignable<_Tp&, _Tp&&>
1310 : public __is_move_assignable_impl<_Tp>
1352 : public is_nothrow_assignable<_Tp&, _Tp&&>
1352 : public is_nothrow_assignable<_Tp&, _Tp&&>
1358 : public __is_nt_move_assignable_impl<_Tp>
1400 : public __and_<is_default_constructible<_Tp>,
1401 __is_implicitly_default_constructible_safe<_Tp>>
1526 static void __test_aux(_To1);
1538 typedef decltype(__test<_From, _To>(0)) type;
1538 typedef decltype(__test<_From, _To>(0)) type;
1545 : public __is_convertible_helper<_From, _To>::type
1545 : public __is_convertible_helper<_From, _To>::type
1554 { typedef _Tp type; };
1558 { typedef _Tp type; };
1563 { typedef _Tp type; };
1574 remove_const<typename remove_volatile<_Tp>::type>::type type;
1629 { typedef _Tp type; };
1633 { typedef _Tp type; };
1659 { typedef _Tp&& type; };
1664 : public __add_rvalue_reference_helper<_Tp>
1955 { typedef _Tp type; };
1983 { typedef _Up type; };
2104 { typedef typename remove_cv<_Up>::type __type; };
2131 typedef _Tp __type;
2574 typename remove_reference<_Tp>::type>::type>::type