|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/AArch64/AArch64GenInstrInfo.inc18210 MI.getOperand(1).isReg()
18285 MI.getOperand(0).isReg()
18286 && MI.getOperand(1).isReg()
18298 MI.getOperand(1).isReg()
18299 && MI.getOperand(2).isReg()
18336 MI.getOperand(1).isReg()
gen/lib/Target/AArch64/AArch64GenSubtargetInfo.inc18057 MI->getOperand(0).isReg()
18094 MI->getOperand(0).isReg()
18203 MI->getOperand(0).isReg()
18240 MI->getOperand(0).isReg()
18283 MI->getOperand(0).isReg()
18320 MI->getOperand(0).isReg()
18363 MI->getOperand(0).isReg()
18400 MI->getOperand(0).isReg()
18573 MI->getOperand(0).isReg()
20274 MI->getOperand(0).isReg()
20311 MI->getOperand(0).isReg()
20355 MI->getOperand(0).isReg()
20855 MI->getOperand(0).isReg()
20892 MI->getOperand(0).isReg()
21398 MI->getOperand(0).isReg()
21435 MI->getOperand(0).isReg()
21480 MI->getOperand(0).isReg()
21517 MI->getOperand(0).isReg()
22064 MI->getOperand(0).isReg()
22101 MI->getOperand(0).isReg()
22146 MI->getOperand(0).isReg()
22183 MI->getOperand(0).isReg()
22228 MI->getOperand(0).isReg()
22265 MI->getOperand(0).isReg()
gen/lib/Target/X86/X86GenInstrInfo.inc49350 MI.getOperand(1).isReg()
49352 && MI.getOperand(3).isReg()
include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h 94 if (!MO.isReg()) {
198 if (!MO.isReg())
203 if (!MO.isReg()) {
485 if (!MO.isReg()) {
527 if (!MO.isReg() ||
556 if (MO.isReg()) {
575 if (!MO.isReg() ||
618 if (MO.isReg()) {
include/llvm/CodeGen/GlobalISel/MIPatternMatch.h 65 return MO->isReg();
include/llvm/CodeGen/LiveRegUnits.h 54 if (!O->isReg())
include/llvm/CodeGen/LiveVariables.h 217 if (MO.isReg() && MO.isKill() && MO.getReg() == reg) {
253 if (MO.isReg() && MO.isDef() && MO.getReg() == reg) {
include/llvm/CodeGen/MachineInstr.h 1065 && getOperand(0).isReg()
1076 return isDebugValue() && getOperand(0).isReg() && !getOperand(0).getReg().isValid();
1369 if (!MO.isReg() || !MO.isDef() || !MO.isTied())
1382 if (!MO.isReg() || !MO.isUse() || !MO.isTied())
1645 if (MO.isReg() && MO.isTied()) {
include/llvm/CodeGen/MachineInstrBuilder.h 497 assert(RegOp.isReg() && "Not a register operand");
include/llvm/CodeGen/MachineOperand.h 219 return isReg() ? 0 : SubReg_TargetFlags;
222 assert(!isReg() && "Register operands can't have target flags");
227 assert(!isReg() && "Register operands can't have target flags");
354 assert(isReg() && "This is not a register operand!");
359 assert(isReg() && "Wrong MachineOperand accessor");
364 assert(isReg() && "Wrong MachineOperand accessor");
369 assert(isReg() && "Wrong MachineOperand accessor");
374 assert(isReg() && "Wrong MachineOperand accessor");
379 assert(isReg() && "Wrong MachineOperand accessor");
384 assert(isReg() && "Wrong MachineOperand accessor");
389 assert(isReg() && "Wrong MachineOperand accessor");
425 assert(isReg() && "Wrong MachineOperand accessor");
430 assert(isReg() && "Wrong MachineOperand accessor");
435 assert(isReg() && "Wrong MachineOperand accessor");
440 assert(isReg() && "Wrong MachineOperand accessor");
452 assert(isReg() && "Wrong MachineOperand accessor");
465 assert(isReg() && "Wrong MachineOperand mutator");
489 assert(isReg() && "Wrong MachineOperand mutator");
494 assert(isReg() && !IsDef && "Wrong MachineOperand mutator");
500 assert(isReg() && IsDef && "Wrong MachineOperand mutator");
505 assert(isReg() && "Wrong MachineOperand mutator");
512 assert(isReg() && "Wrong MachineOperand mutator");
517 assert(isReg() && IsDef && "Wrong MachineOperand mutator");
522 assert(isReg() && !IsDef && "Wrong MachineOperand mutator");
944 assert(isReg() && "Can only add reg operand to use lists");
include/llvm/CodeGen/MachineRegisterInfo.h 124 assert(MO && MO->isReg() && "This is not a register operand!");
827 assert(MI->getOperand(0).isReg());
lib/CodeGen/AggressiveAntiDepBreaker.cpp 232 if (!MO.isReg() || !MO.isImplicit())
252 if (!MO.isReg()) continue;
367 if (!MO.isReg() || !MO.isDef()) continue;
377 if (!MO.isReg() || !MO.isDef()) continue;
420 if (!MO.isReg() || !MO.isDef()) continue;
473 if (!MO.isReg() || !MO.isUse()) continue;
508 if (!MO.isReg()) continue;
lib/CodeGen/AntiDepBreaker.h 61 if (MI.getOperand(0).isReg() && MI.getOperand(0).getReg() == OldReg)
lib/CodeGen/AsmPrinter/AsmPrinter.cpp 810 assert(Op.isReg() && "KILL instruction must have only register operands");
840 bool MemLoc = MI->getOperand(0).isReg() && MI->getOperand(1).isImm();
879 if (MI->getOperand(0).isReg()) {
lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp 473 for (; MI->getOperand(NumDefs).isReg() && MI->getOperand(NumDefs).isDef();
625 if (MO.isReg()) {
lib/CodeGen/AsmPrinter/DbgEntityHistoryCalculator.cpp 50 return MI.getOperand(0).isReg() ? MI.getOperand(0).getReg() : Register();
271 if (MO.isReg() && MO.isDef() && MO.getReg()) {
lib/CodeGen/AsmPrinter/DebugHandlerBase.cpp 35 if (!Instruction.getOperand(0).isReg())
218 return MI->getOperand(0).isReg() && MI->getOperand(0).getReg();
lib/CodeGen/AsmPrinter/DwarfDebug.cpp 235 if (MI->getOperand(0).isReg()) {
590 if (MO.isReg() && MO.isDef() &&
652 } else if (ParamValue->first.isReg()) {
723 if (!CalleeOp.isGlobal() && !CalleeOp.isReg())
729 if (CalleeOp.isReg()) {
lib/CodeGen/BranchFolding.cpp 877 if (MO.isReg() && MO.isUndef()) {
1880 if (!MO.isReg())
1918 if (!MO.isReg() || MO.isUse())
1946 if (!MO.isReg())
2019 if (!MO.isReg())
2069 if (!MO.isReg() || !MO.isUse() || !MO.isKill())
2087 if (!MO.isReg() || !MO.isDef() || MO.isDead())
lib/CodeGen/BreakFalseDeps.cpp 131 if (!CurrMO.isReg() || CurrMO.isDef() || CurrMO.isUndef() ||
203 if (!MO.isReg() || !MO.getReg())
lib/CodeGen/CriticalAntiDepBreaker.cpp 189 if (!MO.isReg()) continue;
274 if (!MO.isReg()) continue;
305 if (!MO.isReg()) continue;
367 if (!CheckOper.isReg() || !CheckOper.isDef() ||
615 if (!MO.isReg()) continue;
lib/CodeGen/DeadMachineInstructionElim.cpp 77 if (MO.isReg() && MO.isDef()) {
142 if (MO.isReg() && MO.isDef()) {
161 if (MO.isReg() && MO.isUse()) {
lib/CodeGen/DetectDeadLanes.cpp 222 if (!MO.isReg() || !Register::isVirtualRegister(MO.getReg()))
378 if (!MO.isReg() || !MO.readsReg())
537 if (!MO.isReg())
lib/CodeGen/EarlyIfConversion.cpp 260 if (!MO.isReg())
380 if (!MO.isReg())
lib/CodeGen/ExecutionDomainFix.cpp 242 if (!MO.isReg())
263 if (!mo.isReg())
273 if (!mo.isReg())
294 if (!mo.isReg())
384 if (!mo.isReg())
lib/CodeGen/ExpandPostRAPseudos.cpp 71 if (MO.isReg())
77 assert((MI->getOperand(0).isReg() && MI->getOperand(0).isDef()) &&
79 (MI->getOperand(2).isReg() && MI->getOperand(2).isUse()) &&
lib/CodeGen/GlobalISel/CSEInfo.cpp 335 if (MO.isReg()) {
lib/CodeGen/GlobalISel/CombinerHelper.cpp 372 assert(LoadValue.isReg() && "Result wasn't a register?");
lib/CodeGen/GlobalISel/InstructionSelector.cpp 51 if (MO.isReg() && MO.getReg())
59 if (!Root.isReg())
lib/CodeGen/GlobalISel/RegBankSelect.cpp 239 assert(MO.isReg() && "We should only repair register operand");
469 if (!MO.isReg())
729 assert(MO.isReg() && "Trying to repair a non-reg operand");
lib/CodeGen/GlobalISel/RegisterBankInfo.cpp 180 if (!MO.isReg())
229 if (!MO.isReg())
442 if (!MO.isReg()) {
605 if (!MO.isReg()) {
lib/CodeGen/GlobalISel/Utils.cpp 125 if (!MO.isReg())
129 assert(MO.isReg() && "Unsupported non-reg operand");
168 if (!MO.isReg() || !MO.isDef())
lib/CodeGen/IfConversion.cpp 1946 if (!MO.isReg())
2114 if (!MO.isReg())
lib/CodeGen/ImplicitNullChecks.cpp 278 if (!(MOA.isReg() && MOA.getReg()))
283 if (!(MOB.isReg() && MOB.getReg()))
369 !BaseOp->isReg() || BaseOp->getReg() != PointerReg)
416 if (!(DependenceMO.isReg() && DependenceMO.getReg()))
477 if (!(MBP.LHS.isReg() && MBP.RHS.isImm() && MBP.RHS.getImm() == 0 &&
601 return MO.isReg() && MO.getReg() && MO.isDef() &&
643 if (MO.isReg()) {
690 if (!MO.isReg() || !MO.isDef())
700 if (!MO.isReg() || !MO.getReg() || !MO.isDef())
lib/CodeGen/InlineSpiller.cpp 559 if (MO.isReg() && MO.isUse() && MO.getReg() == VirtReg.reg)
624 if (MO.isReg() && MO.isUse() && MO.getReg() == VirtReg.reg) {
845 if (!MO->isReg())
884 if (!MO.isReg() || !MO.isImplicit())
1523 if (MO.isReg() && MO.isImplicit() && MO.isDef() && !MO.isDead())
lib/CodeGen/LiveDebugValues.cpp 89 return MI.getOperand(0).isReg() ? MI.getOperand(0).getReg() : Register();
697 assert(MI.getOperand(0).isReg() && MI.getOperand(0).getReg() == 0 &&
815 if (MO.isReg() && MO.isDef() && MO.getReg() &&
864 if (!MO.isReg() || !MO.isUse()) {
1301 return Op.isReg() && Op.getReg() != SP && Op.getReg() != FP;
lib/CodeGen/LiveDebugVariables.cpp 228 if (LocMO.isReg()) {
233 if (locations[i].isReg() &&
245 if (locations.back().isReg()) {
568 if (locations[i].isReg() &&
602 !(MI.getOperand(1).isReg() || MI.getOperand(1).isImm()) ||
616 if (MI.getOperand(0).isReg() &&
849 if (!LocMO.isReg()) {
1123 if (!Loc->isReg() || Loc->getReg() != OldReg)
1171 if (Loc.isReg() && Loc.getReg() &&
1267 if (!LocMO.isReg())
lib/CodeGen/LiveInterval.cpp 904 if (!MOI->isReg() || !MOI->isDef())
lib/CodeGen/LiveIntervals.cpp 779 if (!MO.isReg() || MO.getReg() != Reg)
979 if (!MO.isReg())
1065 if (MO->isReg() && MO->isUse())
1366 if (MO->isReg() && !MO->isUse())
1446 if (MO->isReg() && !MO->isUndef() &&
1514 if (!MO.isReg() || MO.getReg() != Reg)
1603 if (MOI->isReg() && Register::isVirtualRegister(MOI->getReg()) &&
lib/CodeGen/LivePhysRegs.cpp 46 if (O->isReg()) {
61 if (!O->isReg() || !O->readsReg() || O->isDebug())
88 if (O->isReg() && !O->isDebug()) {
110 if (Reg.second->isReg() && Reg.second->isDead())
292 if (!MO->isReg() || !MO->isDef() || MO->isDebug())
309 if (!MO->isReg() || !MO->readsReg() || MO->isDebug())
lib/CodeGen/LiveRangeEdit.cpp 113 if (!MO.isReg() || !MO.getReg() || !MO.readsReg())
292 if (VRM && MI->getOperand(0).isReg() && MI->getOperand(0).isDef() &&
309 if (!MOI->isReg())
352 if (MO.isReg() && Register::isPhysicalRegister(MO.getReg()))
lib/CodeGen/LiveRangeShrink.cpp 141 if (!MO.isReg() || MO.isDebug())
173 if (!MO.isReg() || MO.isDead() || MO.isDebug())
234 if (MI.getOperand(0).isReg())
236 EndIter->getOperand(0).isReg() &&
lib/CodeGen/LiveRegUnits.cpp 47 if (O->isReg()) {
60 if (!O->isReg() || !O->readsReg() || O->isDebug())
72 if (O->isReg()) {
lib/CodeGen/LiveVariables.cpp 216 if (!MO.isReg() || !MO.isDef() || MO.getReg() == 0)
521 if (!MO.isReg() || MO.getReg() == 0)
692 if (MO.isReg() && MO.isKill()) {
785 if (I->isReg() && Register::isVirtualRegister(I->getReg())) {
lib/CodeGen/MIRCanonicalizerPass.cpp 170 if (!MO.isReg())
190 if (!MO.isReg() || !Register::isVirtualRegister(MO.getReg()))
202 if (II->getOperand(i).isReg()) {
318 if (!MI->getOperand(0).isReg())
320 if (!MI->getOperand(1).isReg())
358 if (!MO.isReg())
lib/CodeGen/MIRParser/MIParser.cpp 360 assert(Operand.isReg() && Operand.isUse() &&
915 if (OpCode == TargetOpcode::DBG_VALUE && MO.isReg())
1371 if (!DefOperand.isReg() || !DefOperand.isDef())
2538 if (Dest.isReg())
lib/CodeGen/MIRPrinter.cpp 719 for (; I < E && MI.getOperand(I).isReg() && MI.getOperand(I).isDef() &&
849 if (ShouldPrintRegisterTies && Op.isReg() && Op.isTied() && !Op.isDef())
lib/CodeGen/MIRVRegNamerUtils.cpp 60 if (MI->getNumOperands() > 0 && MI->getOperand(0).isReg()) {
148 if (!MO.isReg())
279 if (!(MO.isReg() && Register::isVirtualRegister(MO.getReg())))
296 if (!MO.isReg() && !MO.isFI())
301 RegQueue.push(MO.isReg() ? TypedVReg(MO.getReg())
lib/CodeGen/MachineBasicBlock.cpp 908 if (!OI->isReg() || OI->getReg() == 0 ||
929 if (!OI->isReg() || OI->getReg() == 0)
lib/CodeGen/MachineCSE.cpp 168 if (!MO.isReg() || !MO.isUse())
237 if (!MO.isReg() || !MO.getReg())
283 if (!MO.isReg() || MO.isDef())
302 if (!MO.isReg() || !MO.isDef())
379 if (!MO.isReg() || !MO.isDef())
466 if (MO.isReg() && MO.isUse() && Register::isVirtualRegister(MO.getReg())) {
596 if (!MO.isReg() || !MO.isDef())
785 if (use.isReg() && !Register::isVirtualRegister(use.getReg()))
lib/CodeGen/MachineCombiner.cpp 140 if (MO.isReg() && Register::isVirtualRegister(MO.getReg()))
171 if (!(MO.isReg() && Register::isVirtualRegister(MO.getReg())))
226 if (!(MO.isReg() && Register::isVirtualRegister(MO.getReg())))
lib/CodeGen/MachineCopyPropagation.cpp 372 if (&MIUse != &Use && MIUse.isReg() && MIUse.isImplicit() &&
396 if (!MOUse.isReg() || MOUse.isTied() || MOUse.isUndef() || MOUse.isDef() ||
505 if (!MO.isReg() || !MO.readsReg())
528 if (!MO.isReg() || !MO.isDef())
543 if (MO.isReg() && MO.isEarlyClobber()) {
561 if (!MO.isReg())
lib/CodeGen/MachineInstr.cpp 163 if (MO.isReg())
172 if (MO.isReg())
219 bool isImpReg = Op.isReg() && Op.isImplicit();
221 while (OpNo && Operands[OpNo-1].isReg() && Operands[OpNo-1].isImplicit()) {
267 if (NewMO->isReg()) {
302 if (Operands[i].isReg())
307 if (MRI && Operands[OpNo].isReg())
617 if (!MO.isReg()) {
684 if (!MO.isReg() || !MO.isDef())
711 if (MO.isReg() && MO.isImplicit())
725 if (!MO.isReg() || !MO.isDef() || MO.isImplicit())
842 if (!getOperand(OpIdx).isReg())
893 if (!MO.isReg() || MO.getReg() != Reg)
904 assert(MO.isReg() &&
934 if (MO.isReg() && MO.isUse() && MO.isImplicit() && MO.getReg() == Reg)
947 if (!MO.isReg() || !MO.isUse())
971 if (!MO.isReg() || MO.getReg() != Reg)
1001 if (!MO.isReg() || !MO.isDef())
1091 if (UseMO.isReg() && UseMO.isUse() && UseMO.TiedTo == OpIdx + 1)
1134 if (MO.isReg() && MO.isUse())
1146 if (!MO.isReg() || MO.getReg() != FromReg)
1152 if (!MO.isReg() || MO.getReg() != FromReg)
1388 if (!MO.isReg() || MO.isUse())
1403 if ((MO.isReg() && MO.isImplicit()) || MO.isRegMask())
1412 if (!Operand.isReg() || Operand.isDef())
1426 if (!Op.isReg())
1491 if (MO.isReg() && MO.isTied() && !MO.isDef())
1501 if (!MO.isReg() || !MO.isDef() || MO.isImplicit())
1794 if (!MO.isReg() || !MO.isUse() || MO.isUndef())
1855 if (!MO.isReg() || !MO.isUse() || !MO.isKill())
1873 if (!MO.isReg() || !MO.isDef())
1918 if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg)
1926 if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg || MO.getSubReg() == 0)
1940 if (MO.isReg() && MO.getReg() == Reg && MO.isDef() &&
1958 if (!MO.isReg() || !MO.isDef()) continue;
1983 if (MO.isReg() && MO.isDef() && Register::isVirtualRegister(MO.getReg()))
2037 if (MO.isReg())
2073 assert(MI.getOperand(0).isReg() && "can't spill non-register");
2107 if (!MI.getOperand(0).isReg())
2115 if (DI->getOperand(0).isReg() &&
2125 if (!getOperand(0).isReg())
2134 if (DI->getOperand(0).isReg() &&
lib/CodeGen/MachineInstrBundle.cpp 63 if (MO.isReg() && MO.isInternalRead())
150 if (!MO.isReg())
290 if (!MO.isReg() || MO.getReg() != Reg)
329 if (!MO.isReg())
lib/CodeGen/MachineLICM.cpp 424 if (!MO.isReg())
526 if (!MO.isReg())
554 if (!MO.isReg() || MO.isDef() || !MO.getReg())
579 if (!MO.isReg() || !MO.getReg() || MO.isDef()) continue;
769 if (!MO.isDef() || !MO.isReg() || !MO.getReg())
852 if (!MO.isReg() || MO.isImplicit())
923 if (MO.isReg()) {
1009 if (!MO.isReg())
1061 if (!MO.isReg() || !MO.isDef())
1104 if (!MO.isReg() || !MO.isUse())
1131 if (!DefMO.isReg() || !DefMO.isDef())
1225 if (!MO.isReg() || MO.isImplicit())
1379 assert((!MO.isReg() || MO.getReg() == 0 ||
1384 if (MO.isReg() && MO.isDef() &&
1486 if (MO.isReg() && MO.isDef() && !MO.isDead())
lib/CodeGen/MachineLoopUtils.cpp 76 if (MO.isReg() && Remaps.count(MO.getReg()))
lib/CodeGen/MachineOperand.cpp 99 assert(isReg() && "Wrong MachineOperand accessor");
116 assert(isReg() && "Wrong MachineOperand accessor");
134 assert(isReg() && "Wrong MachineOperand accessor");
143 if (!isReg() || !isOnRegUseList())
154 assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm");
163 assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm");
173 assert((!isReg() || !isTied()) &&
186 assert((!isReg() || !isTied()) &&
198 assert((!isReg() || !isTied()) &&
208 assert((!isReg() || !isTied()) &&
219 assert((!isReg() || !isTied()) &&
241 bool WasReg = isReg();
lib/CodeGen/MachineOutliner.cpp 1249 if (!MOP.isReg())
lib/CodeGen/MachinePipeliner.cpp 770 if (!MOI->isReg())
1555 if (MO.isReg() && MO.isUse()) {
1566 if (MO.isReg() && MO.isDef() && !MO.isDead()) {
2063 if (!BaseOp->isReg())
2474 if (!MO.isReg() || !Register::isVirtualRegister(MO.getReg()))
2618 if (!MO.isReg())
2630 if (!DMO.isReg() || !DMO.isDef())
2769 if (MO.isReg() && MO.isUse() && MO.getReg() == OverlapReg) {
lib/CodeGen/MachineRegisterInfo.cpp 238 if (!MO->isReg()) {
351 if (Src->isReg()) {
lib/CodeGen/MachineScheduler.cpp 931 if (!MO.isReg())
946 if (MO2.isReg() && MO2.isDef() && MO2.getReg() == Reg && !MO2.isDead()) {
1481 if (BaseOp->isReg())
2934 if (Op.isReg() && !Register::isPhysicalRegister(Op.getReg())) {
lib/CodeGen/MachineSink.cpp 411 if (!MO.isReg() || !MO.getReg().isVirtual())
440 if (!MO.isReg() || !MO.isUse())
639 if (!MO.isReg()) continue; // Ignore non-register operands.
745 if (!BaseOp->isReg())
755 return MBP.LHS.isReg() && MBP.RHS.isImm() && MBP.RHS.getImm() == 0 &&
880 if (!MO.isReg()) continue;
953 if (!MO.isReg() || !MO.isDef() || !MO.getReg().isVirtual())
976 if (MO.isReg() && MO.isUse())
986 assert(MI.getOperand(1).isReg());
994 if (!MO.isReg() || !MO.isDef() || !MO.getReg().isVirtual())
1004 assert(User.getOperand(0).isReg() &&
1186 if (!MO.isReg())
1257 if (MO.isReg() && Register::isPhysicalRegister(MO.getReg())) {
1312 if (!MO.isReg() || !MO.isDef())
lib/CodeGen/MachineTraceMetrics.cpp 661 if (!MO.isReg())
709 if (!MO.isReg())
903 if (!MO.isReg())
lib/CodeGen/MachineVerifier.cpp 889 if (!MO.isReg() || !MO.isImplicit())
936 if (!MO->isReg()) {
960 if (MO->isReg() && Register::isPhysicalRegister(MO->getReg()))
1043 if (!MO.isReg())
1281 if (!SrcOp.isReg()) {
1303 if (!SrcOp.isReg()) {
1341 if (!IdxOp.isReg() || MRI->getType(IdxOp.getReg()).isPointer())
1459 if (!DstOp.isReg() || !MRI->getType(DstOp.getReg()).isPointer()) {
1464 if (!AllocOp.isReg() || !MRI->getType(AllocOp.getReg()).isScalar()) {
1598 NumDefs = (MONum == 0 && MO->isReg()) ? NumDefs : 0;
1603 if (!MO->isReg())
1613 if (MO->isReg() &&
1623 if (!MO->isReg())
1631 if (!MOTied.isReg())
1637 } else if (MO->isReg() && MO->isTied())
1641 if (MO->isReg() && !MO->isImplicit() && !MI->isVariadic() && MO->getReg())
1657 if (!OtherMO.isReg())
2022 if (!MOP.isReg() || !MOP.isImplicit())
2215 if (!MODef.isReg() || !MODef.isDef()) {
2228 if (!MO0.isReg()) {
2416 if (!MOI->isReg() || !MOI->isDef())
2556 if (!MOI->isReg() || MOI->getReg() != Reg)
lib/CodeGen/ModuloSchedule.cpp 78 if (!Op.isReg() || !Op.isDef())
625 if (!MO.isReg() || !MO.isDef() ||
727 if (!MOI->isReg() || !MOI->isDef())
918 if (!BaseOp->isReg())
986 if (MO.isReg() && MO.isUse())
1027 if (!MO.isReg() || !Register::isVirtualRegister(MO.getReg()))
1320 if (!MO.isReg() || MO.getReg().isPhysical() || MO.isImplicit())
1562 return MO->isReg() && MO->getReg().isVirtual() &&
lib/CodeGen/PeepholeOptimizer.cpp 1356 if (!MO.isReg() || MO.isDef())
1488 if (!MO.isReg())
1662 if (MO.isReg()) {
1759 if (!MOp.isReg())
1848 if (!MO.isReg() || !MO.getReg())
2037 assert(MO.isReg() && "Invalid PHI instruction");
lib/CodeGen/ProcessImplicitDefs.cpp 69 if (MO.isReg() && MO.isUse() && MO.readsReg())
101 if (!MO.isReg())
lib/CodeGen/ReachingDefAnalysis.cpp 106 if (!MO.isReg() || !MO.getReg())
lib/CodeGen/RegAllocFast.cpp 891 if (!MO.isReg()) continue;
906 if (!MO.isReg() || !MO.isDef()) continue;
921 if (!MO.isReg()) continue;
947 if (!MO.isReg()) continue;
962 if (!MO.isReg() || (MO.isDef() && !MO.isEarlyClobber())) continue;
1045 if (!MO.isReg()) continue;
1096 if (!MO.isReg()) continue;
1124 if (!MO.isReg() || !MO.isUse())
1140 if (!MO.isReg()) continue;
1167 if (!MO.isReg() || !MO.isDef() || !MO.getReg() || MO.isEarlyClobber())
1180 if (!MO.isReg() || !MO.isDef() || !MO.getReg() || MO.isEarlyClobber())
1215 if (!MO.isReg())
lib/CodeGen/RegisterCoalescer.cpp 1194 if (!Op.isReg() || !Op.isDef() || Op.getReg() != Reg)
1317 if (MO.isReg()) {
1337 if (MO.isReg() && MO.isDef()) {
1555 if (MO.isReg() && MO.isUse())
1618 if (MO.isReg() && MO.isDef() && MO.getReg() == DstReg)
2394 if (!MO.isReg() || MO.getReg() != Reg || !MO.isDef())
2828 if (!MO.isReg() || MO.isDef() || MO.getReg() != Reg)
2944 if (MO.isReg() && MO.isDef() && MO.getReg() == Reg) {
lib/CodeGen/RegisterPressure.cpp 500 if (!MO.isReg() || !MO.getReg())
531 if (!MO.isReg() || !MO.getReg())
lib/CodeGen/RegisterScavenging.cpp 134 if (!MO.isReg())
205 if (!MO.isReg())
330 if (!MO.isReg() || MO.isUndef() || !MO.getReg())
433 if (MO.isReg() && Register::isVirtualRegister(MO.getReg())) {
544 if (MO.isReg() && MO.getReg() != 0 && !(MO.isUse() && MO.isUndef()) &&
695 if (!MO.isReg())
717 if (!MO.isReg())
740 if (!MO.isReg() || !Register::isVirtualRegister(MO.getReg()))
lib/CodeGen/ScheduleDAGInstrs.cpp 206 if (!MO.isReg() || MO.isDef()) continue;
409 if (OtherMO.isReg() && OtherMO.isDef() && OtherMO.getReg() == Reg)
839 if (!MO.isReg() || !MO.isDef())
856 if (!MO.isReg() || !MO.isUse())
1089 if (!MO.isReg() || !MO.readsReg())
1119 if (MO.isReg()) {
lib/CodeGen/SelectionDAG/FastISel.cpp 171 if (!MO.isReg())
lib/CodeGen/SelectionDAG/InstrEmitter.cpp 347 MIB->getOperand(Idx-1).isReg() &&
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp 5576 IsIndirect = (Op->isReg()) ? IsIndirect : true;
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp 1639 if (!OPI->isReg() || !OPI->isDef())
1654 if (!OPI2->isReg() || (!Register::isPhysicalRegister(OPI->getReg()) &&
lib/CodeGen/ShrinkWrap.cpp 277 if (MO.isReg()) {
lib/CodeGen/StackMaps.cpp 55 : MI(MI), HasDef(MI->getOperand(0).isReg() && MI->getOperand(0).isDef() &&
59 while (CheckStartIdx < e && MI->getOperand(CheckStartIdx).isReg() &&
76 !(MI->getOperand(ScratchIdx).isReg() &&
146 if (MOI->isReg()) {
lib/CodeGen/TailDuplicator.cpp 385 if (!MO.isReg())
lib/CodeGen/TargetInstrInfo.cpp 161 if (HasDef && !MI.getOperand(0).isReg())
170 assert(MI.getOperand(Idx1).isReg() && MI.getOperand(Idx2).isReg() &&
170 assert(MI.getOperand(Idx1).isReg() && MI.getOperand(Idx2).isReg() &&
303 if (!MI.getOperand(SrcOpIdx1).isReg() || !MI.getOperand(SrcOpIdx2).isReg())
303 if (!MI.getOperand(SrcOpIdx1).isReg() || !MI.getOperand(SrcOpIdx2).isReg())
334 if (MO.isReg()) {
677 if (Op1.isReg() && Register::isVirtualRegister(Op1.getReg()))
679 if (Op2.isReg() && Register::isVirtualRegister(Op2.getReg()))
888 if (!MI.getNumOperands() || !MI.getOperand(0).isReg())
926 if (!MO.isReg()) continue;
lib/CodeGen/TargetSchedule.cpp 161 if (MO.isReg() && MO.isDef())
177 if (MO.isReg() && MO.readsReg() && !MO.isDef())
lib/CodeGen/TwoAddressInstructionPass.cpp 231 if (!MO.isReg())
300 if (!MO.isReg())
505 if (!MO.isReg() || !MO.isUse() || MO.getReg() != Reg)
911 if (!MO.isReg())
955 if (!MO.isReg())
1093 if (!MO.isReg())
1130 if (!MO.isReg())
1218 if (OtherOpIdx == BaseOpIdx || !MI->getOperand(OtherOpIdx).isReg() ||
1400 if (MO.isReg() && Register::isVirtualRegister(MO.getReg())) {
1428 if (MO.isReg())
1547 !MI->getOperand(i).isReg() ||
1592 assert(MO.isReg() && MO.getReg() == RegB && MO.isUse() &&
1617 if (MO.isReg() && MO.getReg() == RegB && MO.isUse()) {
1657 if (MO.isReg() && MO.getReg() == RegB && MO.isUse()) {
lib/CodeGen/VirtRegMap.cpp 515 if (!MO.isReg() || !MO.getReg().isVirtual())
lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp 554 if (U.isReg() && U.isUse() && Substs.find(U.getReg()) != Substs.end()) {
687 if (MO.isReg()) {
lib/Target/AArch64/AArch64AsmPrinter.cpp 551 assert(MO.isReg() && "Should only get here with a register!");
578 if (MO.isReg())
593 if (MO.isReg()) {
626 if (MO.isReg()) {
661 assert(MO.isReg() && "unexpected inline asm memory operand");
676 assert(MI->getOperand(0).isReg() && MI->getOperand(1).isImm());
lib/Target/AArch64/AArch64CallLowering.cpp 808 unsigned Opc = getCallOpcode(F, Info.Callee.isReg(), true);
881 if (!Use.isReg())
910 if (Info.Callee.isReg())
968 unsigned Opc = getCallOpcode(F, Info.Callee.isReg(), false);
996 if (Info.Callee.isReg())
lib/Target/AArch64/AArch64CollectLOH.cpp 474 if (!MO.isReg() || !MO.isDef())
485 if (!MO.isReg() || !MO.readsReg())
534 assert(Def.isReg() && Def.isDef() && "Expected reg def");
535 assert(Op.isReg() && Op.isUse() && "Expected reg use");
lib/Target/AArch64/AArch64CondBrTuning.cpp 94 if (MO.isReg() && MO.isDead() && MO.getReg() == AArch64::NZCV)
lib/Target/AArch64/AArch64ConditionalCompares.cpp 692 if (CmpMI->getOperand(FirstOp + 1).isReg())
lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp 144 if (!MO.isReg() || !MO.isDef())
lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp 98 assert(MO.isReg() && MO.getReg());
lib/Target/AArch64/AArch64FalkorHWPFFix.cpp 668 else if (LI.OffsetOpnd->isReg())
746 if (MO.isReg() && MO.readsReg())
lib/Target/AArch64/AArch64FastISel.cpp 2070 if (Opnd.isReg()) {
lib/Target/AArch64/AArch64InstrInfo.cpp 992 if (!MI.getOperand(1).isReg())
1070 assert(MO.isReg() &&
1642 assert(MI.getDesc().getNumOperands() == 3 && MI.getOperand(0).isReg() &&
1933 assert((MI.getOperand(1).isReg() || MI.getOperand(1).isFI()) &&
1941 if (MI.getOperand(1).isReg()) {
1995 if ((!LdSt.getOperand(1).isReg() && !LdSt.getOperand(1).isFI()) ||
2000 if (!LdSt.getOperand(1).isReg() ||
2001 (!LdSt.getOperand(2).isReg() && !LdSt.getOperand(2).isFI()) ||
2028 assert((BaseOp->isReg() || BaseOp->isFI()) &&
2334 assert((BaseOp1.isReg() || BaseOp1.isFI()) &&
2338 if (BaseOp1.isReg() && BaseOp1.getReg() != BaseOp2.getReg())
3600 if (MO.isReg() && Register::isVirtualRegister(MO.getReg()))
3610 assert(MI->getNumOperands() >= 4 && MI->getOperand(0).isReg() &&
3611 MI->getOperand(1).isReg() && MI->getOperand(2).isReg() &&
3611 MI->getOperand(1).isReg() && MI->getOperand(2).isReg() &&
3612 MI->getOperand(3).isReg() && "MAdd/MSub must have a least 4 regs");
3699 assert(Root.getOperand(1).isReg() && Root.getOperand(2).isReg() &&
3699 assert(Root.getOperand(1).isReg() && Root.getOperand(2).isReg() &&
3759 assert(Root.getOperand(1).isReg() && Root.getOperand(2).isReg() &&
3759 assert(Root.getOperand(1).isReg() && Root.getOperand(2).isReg() &&
3766 assert(Root.getOperand(1).isReg() && Root.getOperand(2).isReg() &&
3766 assert(Root.getOperand(1).isReg() && Root.getOperand(2).isReg() &&
5139 if (!getMemOperandWithOffset(MI, Base, Offset, &TRI) || !Base->isReg() ||
5410 if (MOP.isReg() && !MOP.isImplicit() &&
5511 (Base->isReg() && Base->getReg() != AArch64::SP))
lib/Target/AArch64/AArch64InstructionSelector.cpp 415 if (!MO.isReg()) {
1389 I.getOperand(0).isReg() ? MRI.getType(I.getOperand(0).getReg()) : LLT{};
2879 assert(LaneIdxOp.isReg() && "Lane index operand was not a register?");
3148 assert(LHS.isReg() && RHS.isReg() && "Expected LHS and RHS to be registers!");
3148 assert(LHS.isReg() && RHS.isReg() && "Expected LHS and RHS to be registers!");
3172 assert(LHS.isReg() && RHS.isReg() && "Expected LHS and RHS to be registers!");
3172 assert(LHS.isReg() && RHS.isReg() && "Expected LHS and RHS to be registers!");
3226 assert(LHS.isReg() && RHS.isReg() && "Expected LHS and RHS to be registers!");
3226 assert(LHS.isReg() && RHS.isReg() && "Expected LHS and RHS to be registers!");
3478 assert(LHS.isReg() && RHS.isReg() && Predicate.isPredicate() &&
3478 assert(LHS.isReg() && RHS.isReg() && Predicate.isPredicate() &&
4024 else if (Root.isReg()) {
4117 if (!Root.isReg())
4179 if (!Root.isReg())
4344 if (!Root.isReg())
4355 if (!OffImm.isReg())
4388 if (!Root.isReg())
4458 if (!Root.isReg())
4572 if (!Root.isReg())
lib/Target/AArch64/AArch64RedundantCopyElimination.cpp 184 if (!PredI.getOperand(1).isReg())
407 return !O.isDead() && O.isReg() && O.isDef() &&
lib/Target/AArch64/AArch64RegisterBankInfo.cpp 619 if (!MO.isReg() || !MO.getReg())
840 if (MI.getOperand(Idx).isReg() && MI.getOperand(Idx).getReg()) {
lib/Target/AArch64/AArch64SpeculationHardening.cpp 485 return Op.isReg() && (AArch64::GPR32allRegClass.contains(Op.getReg()) ||
523 if (!Use.isReg())
632 if (Op.isReg() && RegsNeedingCSDBBeforeUse[Op.getReg()]) {
lib/Target/AArch64/AArch64StackTaggingPreRA.cpp 154 if (UseI->getOperand(OpIdx).isReg() &&
lib/Target/AArch64/AArch64StorePairSuppress.cpp 153 BaseOp->isReg()) {
lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp 704 if (!MO.isReg())
1296 if (MO.isReg()) {
lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp 223 if (MO.isReg()) {
lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp 1025 if (RI.isReg()) {
1892 if (!Cond[0].isReg())
2866 assert(Instr.getOperand(i * 2 + 1).isReg() &&
lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp 59 if (!Op.isReg())
766 if (!Op.isReg() || Op.isDef())
1125 if (!MI.getOperand(I).isReg())
1907 if (!MI.getOperand(i).isReg())
1960 if (!MO.isReg())
1980 if (!Op.isReg())
2005 if (!MI.getOperand(I).isReg())
2467 assert(MI.getOperand(0).isReg());
lib/Target/AMDGPU/GCNDPPCombine.cpp 321 if (!Src1 || !Src1->isReg()) {
355 assert(DstOpnd && DstOpnd->isReg());
380 assert(OldOpnd && OldOpnd->isReg());
381 assert(SrcOpnd && SrcOpnd->isReg());
lib/Target/AMDGPU/GCNHazardRecognizer.cpp 478 if (Op.isReg())
555 if (!Use.isReg())
592 if (!Use.isReg() || TRI.isVGPR(MF.getRegInfo(), Use.getReg()))
614 if (!Use.isReg() || !TRI->isVGPR(MF.getRegInfo(), Use.getReg()))
694 (!SOffset || !SOffset->isReg()))
776 if (Op.isReg() && Op.isDef()) {
792 if (!LaneSelectOp->isReg() || !TRI->isSGPRReg(MRI, LaneSelectOp->getReg()))
835 if (!Use.isReg() || TRI->isVGPR(MF.getRegInfo(), Use.getReg()))
1220 if (!Use.isReg() || !TRI.isVGPR(MF.getRegInfo(), Use.getReg()))
1240 if (!Op.isReg() || !TRI.isAGPR(MF.getRegInfo(), Op.getReg()))
1377 if (!Op.isReg() || !TRI.isVGPR(MF.getRegInfo(), Op.getReg()))
lib/Target/AMDGPU/GCNIterativeScheduler.cpp 392 if (Op.isReg() && Op.isDef())
lib/Target/AMDGPU/GCNRegBankReassign.cpp 364 if (!Op.isReg() || Op.isUndef())
lib/Target/AMDGPU/GCNRegPressure.cpp 200 assert(MO.isDef() && MO.isReg() && Register::isVirtualRegister(MO.getReg()));
213 assert(MO.isUse() && MO.isReg() && Register::isVirtualRegister(MO.getReg()));
234 if (!MO.isReg() || !Register::isVirtualRegister(MO.getReg()))
331 if (!MO.isReg() || !Register::isVirtualRegister(MO.getReg()) || MO.isDead())
407 if (!MO.isReg())
lib/Target/AMDGPU/GCNSchedStrategy.cpp 410 if (Op.isReg() && Op.isDef())
lib/Target/AMDGPU/R600AsmPrinter.cpp 58 if (!MO.isReg())
lib/Target/AMDGPU/R600ControlFlowFinalizer.cpp 303 if (!MO.isReg())
429 if (MO.isReg() && MO.isInternalRead())
lib/Target/AMDGPU/R600EmitClauseMarkers.cpp 79 if (MO.isReg() && MO.getReg() == R600::ALU_LITERAL_X)
203 if (!MOI->isReg() || !MOI->isDef() ||
lib/Target/AMDGPU/R600InstrInfo.cpp 100 if (I->isReg() && !Register::isVirtualRegister(I->getReg()) && I->isUse() &&
245 if (!I->isReg() || !I->isUse() || Register::isVirtualRegister(I->getReg()))
lib/Target/AMDGPU/R600MachineScheduler.cpp 164 if (MO.isReg() && MO.getReg() == R600::ALU_LITERAL_X)
366 if (MO.isReg() && !MO.isDef() &&
lib/Target/AMDGPU/R600OptimizeVectorRegisters.cpp 296 if (!MOp->isReg())
lib/Target/AMDGPU/SIFixSGPRCopies.cpp 156 if (!MI.getOperand(i).isReg() ||
439 if ((MO.isReg() && ((MO.isDef() && MO.getReg() != Reg) || !MO.isDef())) ||
440 (!MO.isImm() && !MO.isReg()) || (MO.isImm() && Imm)) {
707 if ((Src0.isReg() && TRI->isSGPRReg(*MRI, Src0.getReg()) &&
709 (Src1.isReg() && TRI->isSGPRReg(*MRI, Src1.getReg()) &&
722 if (Def.isReg() &&
lib/Target/AMDGPU/SIFixupVectorISel.cpp 94 if (!WOp->isReg() || !Register::isVirtualRegister(WOp->getReg()))
lib/Target/AMDGPU/SIFoldOperands.cpp 54 assert(FoldOp->isReg() || FoldOp->isGlobal());
191 assert(Old.isReg());
391 if (CanCommute && (!MI->getOperand(CommuteIdx0).isReg() ||
392 !MI->getOperand(CommuteIdx1).isReg()))
410 if (!OtherOp.isReg() ||
458 assert (Sub->isReg());
461 SubDef && Sub->isReg() && !Sub->getSubReg() &&
470 if (!Op->isReg())
502 if (!OpToFold.isReg())
553 if (UseOp.isReg() && OpToFold.isReg()) {
553 if (UseOp.isReg() && OpToFold.isReg()) {
594 if (!SOff->isReg() || (SOff->getReg() != MFI->getScratchWaveOffsetReg() &&
669 if (UseMI->isCopy() && OpToFold.isReg() &&
711 } else if (Def->isReg() && TRI->isAGPR(*MRI, Def->getReg())) {
724 assert(Def->isReg());
800 if (OpToFold.isReg() && TRI->isSGPRReg(*MRI, OpToFold.getReg())) {
945 if (Op.isReg()) {
992 bool UseCopy = TII->getNamedOperand(*MI, AMDGPU::OpName::src2)->isReg();
1095 TII->get(Src0->isReg() ? (unsigned)AMDGPU::COPY : getMovOpc(false));
1221 assert(Fold.OpToFold && Fold.OpToFold->isReg());
1253 if (!Src0->isReg() || !Src1->isReg() ||
1253 if (!Src0->isReg() || !Src1->isReg() ||
1399 if (Src0->isReg() && Src1->isReg() && Src0->getReg() == Src1->getReg() &&
1399 if (Src0->isReg() && Src1->isReg() && Src0->getReg() == Src1->getReg() &&
1419 if (OMod == SIOutMods::NONE || !RegOp->isReg() ||
1493 CurrentKnownM0Val = (NewM0Val.isReg() && NewM0Val.getReg().isPhysical()) ?
1503 if (!FoldingImm && !OpToFold.isReg())
1506 if (OpToFold.isReg() && !Register::isVirtualRegister(OpToFold.getReg()))
1516 if (Dst.isReg() && !Register::isVirtualRegister(Dst.getReg()))
lib/Target/AMDGPU/SIFormMemoryClauses.cpp 125 if (!MO.isReg() || MO.isDef())
216 if (!MO.isReg())
266 if (!MO.isReg())
lib/Target/AMDGPU/SIISelLowering.cpp 3546 if (Val->isReg())
lib/Target/AMDGPU/SIInsertSkips.cpp 251 assert(MI.getOperand(0).isReg());
373 if (Op1.getReg() != ExecReg && Op2.isReg() && Op2.getReg() == ExecReg) {
383 if (Op2.isReg()) {
lib/Target/AMDGPU/SIInsertWaitcnts.cpp 465 if (!Op.isReg() || !TRI->isInAllocatableClass(Op.getReg()) ||
573 if (Op.isReg() && !Op.isDef() && TRI->isVGPR(MRIA, Op.getReg())) {
620 if (DefMO.isReg() && DefMO.isDef() &&
629 if (MO.isReg() && !MO.isDef() && TRI->isVGPR(MRIA, MO.getReg())) {
1382 Inst.getOperand(0).isReg() &&
lib/Target/AMDGPU/SIInstrInfo.cpp 277 assert(BaseOp->isReg() && "getMemOperandWithOffset only supports base "
311 assert(BaseOp->isReg() && "getMemOperandWithOffset only supports base "
321 if (SOffset && SOffset->isReg()) {
353 assert(BaseOp->isReg() && "getMemOperandWithOffset only supports base "
367 assert(BaseOp->isReg() && "getMemOperandWithOffset only supports base "
386 assert(BaseOp->isReg() && "getMemOperandWithOffset only supports base "
400 if (!BaseOp1.isReg() || !BaseOp2.isReg())
400 if (!BaseOp1.isReg() || !BaseOp2.isReg())
623 assert(DefOp.isReg() || DefOp.isImm());
625 if (DefOp.isReg()) {
1435 assert(SrcOp.isReg());
1552 if (MO.isReg())
1594 assert(SrcOp.isReg());
1685 if (Src0.isReg() && Src1.isReg()) {
1685 if (Src0.isReg() && Src1.isReg()) {
1692 } else if (Src0.isReg() && !Src1.isReg()) {
1692 } else if (Src0.isReg() && !Src1.isReg()) {
1696 } else if (!Src0.isReg() && Src1.isReg()) {
1696 } else if (!Src0.isReg() && Src1.isReg()) {
2059 if(Cond.size() == 1 && Cond[0].isReg()) {
2373 if (Src0->isReg() && Src0->getReg() == Reg) {
2374 if (!Src1->isReg() || RI.isSGPRClass(MRI->getRegClass(Src1->getReg())))
2377 if (!Src2->isReg() || RI.isSGPRClass(MRI->getRegClass(Src2->getReg())))
2425 if (Src2->isReg() && Src2->getReg() == Reg) {
2429 if (Src0->isReg()) {
2449 if (Src1->isReg() && !Src0Inlined ) {
2594 if (!MO->isReg())
2632 if (!Src0->isReg() && !Src0->isImm())
2656 !Src0->isReg() ||
3006 if (!Src1->isReg() || !RI.isVGPR(MRI, Src1->getReg()))
3015 if (!Src2->isReg() || !RI.isVGPR(MRI, Src2->getReg()) ||
3026 if (Src1 && (!Src1->isReg() || !RI.isVGPR(MRI, Src1->getReg()) ||
3108 if (!MO.isReg())
3220 if (!Op.isReg())
3264 if (!MO.isReg() && (!MO.isImm() || !isInlineConstant(MI, i))) {
3284 if (!MI.getOperand(i).isReg())
3318 if (!MO.isReg() || !RI.hasVGPRs(RI.getRegClassForReg(MRI, MO.getReg()))) {
3324 if (!MO.isReg()) {
3346 if (!Dst.isReg() || Dst.getReg() != AMDGPU::VCC) {
3371 if (!Dst.isReg() || !Dst.isTied()) {
3378 if (!TiedMO.isReg() || !TiedMO.isImplicit() || !TiedMO.isUse()) {
3414 if (Dst.isReg()) {
3452 if (MO.isReg()) {
3500 if (MO.isReg() && MO.getReg() != AMDGPU::M0) {
3519 if (Src0.isReg() && Src1.isReg() && Src2.isReg()) {
3519 if (Src0.isReg() && Src1.isReg() && Src2.isReg()) {
3519 if (Src0.isReg() && Src1.isReg() && Src2.isReg()) {
3533 if (!Src0.isReg() &&
3536 if (!Src1.isReg() &&
3606 if (!ImpUse.isReg() || !ImpUse.isUse() ||
3739 return MI.getOperand(1).isReg() ||
3835 if (MO.isReg())
3916 if (!MO.isReg())
3941 if (MO.isReg())
3968 if (MO->isReg())
3975 if (Op.isReg()) {
3996 if (MO->isReg()) {
4027 Src0.isReg() && (RI.isSGPRReg(MRI, Src0.getReg()) ||
4036 if (Src0.isReg() && RI.isVGPR(MRI, Src0.getReg())) {
4042 if (Src1.isReg() && RI.isVGPR(MRI, Src1.getReg())) {
4053 if (Src0.isReg() && RI.isAGPR(MRI, Src0.getReg()))
4056 if (Src1.isReg() && RI.isAGPR(MRI, Src1.getReg()))
4067 if (Opc == AMDGPU::V_READLANE_B32 && Src1.isReg() &&
4091 if ((!Src1.isImm() && !Src1.isReg()) ||
4111 else if (Src1.isReg()) {
4140 if (Src1.isReg() && !RI.isSGPRClass(MRI.getRegClass(Src1.getReg()))) {
4146 if (Src2.isReg() && !RI.isSGPRClass(MRI.getRegClass(Src2.getReg()))) {
4170 if (!MO.isReg()) {
4423 if (MO.isReg() && MO.isUse()) {
4542 if (!MI.getOperand(i).isReg() ||
4579 if (!Op.isReg() || !Register::isVirtualRegister(Op.getReg()))
4604 if (!Op.isReg() || !Register::isVirtualRegister(Op.getReg()))
4638 if (Src.isReg() && RI.hasVectorRegisters(MRI.getRegClass(Src.getReg())))
5014 if (Op.isReg() && Op.getReg() == AMDGPU::SCC) {
5053 bool HasDst = Inst.getOperand(0).isReg() && Inst.getOperand(0).isDef();
5190 bool Src0IsSGPR = Src0.isReg() &&
5192 bool Src1IsSGPR = Src1.isReg() &&
5299 const TargetRegisterClass *Src0RC = Src0.isReg() ?
5426 const TargetRegisterClass *Src0RC = Src0.isReg() ?
5431 const TargetRegisterClass *Src1RC = Src1.isReg() ?
5496 if (Src0.isReg() && RI.isSGPRReg(MRI, Src0.getReg())) {
5530 const TargetRegisterClass *SrcRC = Src.isReg() ?
5718 assert(Op.isReg() && Op.getReg() == AMDGPU::SCC && Op.isDef() &&
5809 if (!MO.isReg())
6251 if (Op.isReg() && Op.getReg() == AMDGPU::VCC)
6373 assert(RegOpnd.isReg());
6430 if (Op1.isReg() && Register::isVirtualRegister(Op1.getReg())) {
lib/Target/AMDGPU/SIInstrInfo.h 683 return MO.isReg() && RI.isVGPR(MRI, MO.getReg());});
819 if (MO.isReg()) {
1046 assert(O.isReg());
lib/Target/AMDGPU/SILoadStoreOptimizer.cpp 169 if (!AddrOp->isReg())
563 if (Op.isReg()) {
595 if (Use.isReg() &&
1441 if (!Op.isReg())
1464 if (!Base.isReg())
1474 if (!BaseLo.isReg() || !BaseHi.isReg())
1474 if (!BaseLo.isReg() || !BaseHi.isReg())
lib/Target/AMDGPU/SILowerControlFlow.cpp 191 J->getOperand(1).isReg() && J->getOperand(1).getReg() == SaveExecReg) {
364 if (MI.getOperand(1).isReg()) {
444 if (!Op.isReg() || !Register::isVirtualRegister(Op.getReg())) {
463 if (SrcOp.isReg() && SrcOp.isUse() &&
lib/Target/AMDGPU/SILowerI1Copies.cpp 775 if (MO.isReg() && MO.getReg() == AMDGPU::SCC) {
lib/Target/AMDGPU/SIOptimizeExecMasking.cpp 67 if (Src.isReg() &&
83 if (Dst.isReg() &&
85 MI.getOperand(1).isReg())
110 if (Src1.isReg() && Src1.getReg() == AMDGPU::EXEC)
113 if (Src2.isReg() && Src2.getReg() == AMDGPU::EXEC)
126 if (Src1.isReg() && Src1.getReg() == AMDGPU::EXEC_LO)
129 if (Src2.isReg() && Src2.getReg() == AMDGPU::EXEC_LO)
393 if (Src0.isReg() && Src0.getReg() == CopyFromExec) {
395 } else if (Src1.isReg() && Src1.getReg() == CopyFromExec) {
lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp 112 if (Op->isReg() && Op->getReg() != Exec)
115 if (Op->isReg() && Op->getReg() != Exec)
210 !And->getOperand(1).isReg() || !And->getOperand(2).isReg())
210 !And->getOperand(1).isReg() || !And->getOperand(2).isReg())
232 if (Op1->isImm() && Op2->isReg())
234 if (!Op1->isReg() || !Op2->isImm() || Op2->getImm() != 1)
249 if (!Op1->isImm() || !Op2->isImm() || !CC->isReg() ||
357 if (Op.isReg())
398 if (Op.isReg())
lib/Target/AMDGPU/SIPeepholeSDWA.cpp 114 assert(Target->isReg());
115 assert(Replaced->isReg());
276 assert(To.isReg() && From.isReg());
276 assert(To.isReg() && From.isReg());
288 return LHS.isReg() &&
289 RHS.isReg() &&
296 if (!Reg->isReg() || !Reg->isDef())
318 if (!Reg->isReg())
326 if (DefMO.isReg() && DefMO.getReg() == Reg->getReg())
377 assert(Src && (Src->isReg() || Src->isImm()));
419 assert(Src && Src->isReg());
476 Operand->isReg() &&
498 if (!MO.isReg())
529 if (Op.isReg()) {
731 if (!Op1 || !Op1->isReg() || !Op2 || !Op2->isReg())
731 if (!Op1 || !Op1->isReg() || !Op2 || !Op2->isReg())
841 assert(OrDst && OrDst->isReg());
1178 if (!Op.isImm() && !(Op.isReg() && !TRI->isVGPR(*MRI, Op.getReg())))
1186 if (ST.hasSDWAScalar() && ConstantBusCount == 0 && Op.isReg() &&
1197 else if (Op.isReg())
lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp 90 if (!MO.isReg())
124 if (!MO.isReg())
lib/Target/AMDGPU/SIShrinkInstructions.cpp 79 if (Src0.isReg()) {
177 if ((MO.isReg() && MO.isImplicit()) || MO.isRegMask())
185 if (!MI.getOperand(0).isReg())
280 if (MI.getOperand(i).isReg() && MI.getOperand(i).isTied() &&
363 if (Register::isVirtualRegister(Dest->getReg()) && SrcReg->isReg()) {
369 if (SrcReg->isReg() && SrcReg->getReg() == Dest->getReg()) {
393 if (!MO.isReg())
464 if (!Xop.isReg())
636 if (!Src0->isReg() && Src1->isReg()) {
636 if (!Src0->isReg() && Src1->isReg()) {
644 if (Register::isVirtualRegister(Dest->getReg()) && Src0->isReg()) {
650 if (Src0->isReg() && Src0->getReg() == Dest->getReg()) {
742 if (!Src2->isReg())
lib/Target/AMDGPU/SIWholeQuadMode.cpp 273 if (!Use.isReg() || !Use.isUse())
360 if (Inactive.isReg()) {
390 if (!MO.isReg())
544 if (Op.isReg()) {
lib/Target/ARC/ARCInstrInfo.cpp 438 if (!MI.getOperand(BasePos).isReg() || !MI.getOperand(OffsetPos).isImm())
lib/Target/ARC/ARCOptAddrMode.cpp 201 assert(Base.isReg() && "Base operand must be register");
294 if (Ldst->mayStore() && Ldst->getOperand(0).isReg()) {
406 if (!O.isReg() || !O.isUse())
lib/Target/ARM/A15SDOptimizer.cpp 134 if (!MO.isReg())
161 assert(MO->isReg() && "Non-register operand found!");
192 if ((!MO.isReg()) || (!MO.isUse()))
214 if ((!MODef.isReg()) || (!MODef.isDef()))
296 if (!MI->getOperand(I).isReg())
404 if (!MO.isReg() || !MO.isUse())
lib/Target/ARM/ARMAsmPrinter.cpp 277 if (MI->getOperand(OpNum).isReg()) {
302 if (!MI->getOperand(OpNum).isReg())
323 while (MI->getOperand(RegOps).isReg()) {
378 if (!MO.isReg())
392 if (!MO.isReg())
401 if (!MI->getOperand(OpNum).isReg())
418 if (!MO.isReg())
447 if (!MI->getOperand(OpNum).isReg())
455 assert(MO.isReg() && "unexpected inline asm memory operand");
1468 if (MI->getOperand(1).isReg()) {
lib/Target/ARM/ARMBaseInstrInfo.cpp 279 if (MO.isReg() && Register::isVirtualRegister(MO.getReg())) {
551 (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)) {
562 if (MO.isReg() && MO.getReg() == ARM::CPSR && MO.isDef() && !MO.isDead())
580 assert(Offset.isReg());
685 if (!MO.isReg() || MO.isUndef() || MO.isUse())
1211 if (MI.getOperand(1).isFI() && MI.getOperand(2).isReg() &&
1448 if (MI.getOperand(1).isFI() && MI.getOperand(2).isReg() &&
2196 if (!MO.isReg())
2459 if (MO.isReg() && !MO.isImplicit() &&
2809 OI->getOperand(0).isReg() && OI->getOperand(1).isReg() &&
2809 OI->getOperand(0).isReg() && OI->getOperand(1).isReg() &&
3063 if (!MO.isReg() || MO.getReg() != ARM::CPSR)
3792 if (Op.isReg() && Op.getReg() == BaseReg)
4750 !MI.getOperand(i).isReg())
lib/Target/ARM/ARMCallLowering.cpp 521 bool IsDirect = !Info.Callee.isReg();
lib/Target/ARM/ARMConstantIslandPass.cpp 2062 if (!MO.isReg() || !MO.getReg())
2081 if (!MO.isReg() || !MO.getReg())
2142 if (!MO.isReg() || !MO.getReg())
lib/Target/ARM/ARMExpandPseudoInsts.cpp 98 assert(MO.isReg() && MO.getReg());
lib/Target/ARM/ARMFastISel.cpp 256 if (!MO.isReg() || !MO.isDef()) continue;
lib/Target/ARM/ARMISelLowering.cpp 9843 if (!OI->isReg()) continue;
10757 if (op.isReg() && op.isUse()) {
10785 if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR) {
lib/Target/ARM/ARMLoadStoreOptimizer.cpp 205 if (!MO.isReg())
874 if (!MO.isReg() || !MO.isDef() || MO.isDead())
939 if (!MO.isReg() || MO.getReg() != ImpDefReg)
957 if (!MO.isReg() || !MO.isKill())
1586 if (!MI.getOperand(1).isReg())
1610 if (MI.getOperand(0).isReg() && MI.getOperand(0).isUndef())
2122 if (!MO.isReg())
lib/Target/ARM/ARMLowOverheadLoops.cpp 123 if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg)
136 if (!MO.isReg() || !MO.isUse() || MO.getReg() != Reg)
294 if (MI.getOpcode() != ARM::t2LoopDec && MO.isReg() &&
lib/Target/ARM/ARMRegisterBankInfo.cpp 456 if (MaybeReg.isReg() && MaybeReg.getReg()) {
lib/Target/ARM/Thumb1FrameLowering.cpp 642 if (MO.isReg() && (MO.isImplicit() || MO.isDef()))
757 if (MO.isReg() && (MO.isImplicit() || MO.isDef()) &&
979 if (Op.isReg())
lib/Target/ARM/Thumb2ITBlockPass.cpp 88 if (!MO.isReg())
115 if (!MO.isReg() || MO.isDef() || !MO.isKill())
lib/Target/ARM/Thumb2SizeReduction.cpp 301 if (!MO.isReg() || MO.isUndef() || MO.isUse())
310 if (!MO.isReg() || MO.isUndef() || MO.isDef())
381 if (!MO.isReg() || MO.isImplicit())
870 if (MO.isReg()) {
952 if (MO.isReg() && MO.isImplicit() && MO.getReg() == ARM::CPSR)
975 if (!MO.isReg() || MO.isUndef() || MO.isUse())
990 if (!MO.isReg() || MO.isUndef() || MO.isDef())
lib/Target/AVR/AVRAsmPrinter.cpp 98 assert(RegOp.isReg() && "Operand must be a register when you're"
145 assert(MO.isReg() && "Unexpected inline asm memory operand");
lib/Target/AVR/AVRExpandPseudoInsts.cpp 876 if (MO.isReg() && MO.getReg() != 0 && !MO.isDef() &&
lib/Target/BPF/BPFAsmPrinter.cpp 125 assert(BaseMO.isReg() && "Unexpected base pointer for inline asm memory operand.");
lib/Target/BPF/BPFMIChecking.cpp 115 if (!MO.isReg() || MO.isUse())
lib/Target/BPF/BPFMIPeephole.cpp 92 if (!opnd.isReg())
105 if (!opnd.isReg())
418 if (!opnd.isReg()) {
lib/Target/BPF/BPFMISimplifyPatchable.cpp 94 if (!MI.getOperand(0).isReg() || !MI.getOperand(1).isReg())
94 if (!MI.getOperand(0).isReg() || !MI.getOperand(1).isReg())
lib/Target/BPF/BTFDebug.cpp 1013 for (; MI->getOperand(NumDefs).isReg() && MI->getOperand(NumDefs).isDef();
lib/Target/Hexagon/BitTracker.cpp 856 if (!MO.isReg() || !MO.isUse())
874 if (!MO.isReg() || !MO.isDef())
lib/Target/Hexagon/HexagonAsmPrinter.cpp 131 if (!MO.isReg())
165 if (Base.isReg())
lib/Target/Hexagon/HexagonBitSimplify.cpp 291 if (!Op.isReg() || !Op.isDef())
303 if (!Op.isReg() || !Op.isUse())
1016 if (!Op.isReg() || !Op.isDef())
1258 assert(MI.getOperand(OpN).isReg());
1326 if (!Op.isReg())
1953 if (!MI->getOperand(0).isReg())
2140 if (!Op.isReg())
2723 if (!Op0.isReg() || !Op0.isDef())
3012 if (!Op.isReg())
3089 if (!Op.isReg()) {
lib/Target/Hexagon/HexagonBitTracker.cpp 169 if (MO.isReg())
196 if (!MO.isReg() || !MO.isDef())
271 if (!Op.isReg())
1043 if (!Op.isReg() || !Op.isDef())
1190 assert(MD.isReg() && MD.isDef());
lib/Target/Hexagon/HexagonBlockRanges.cpp 321 if (!Op.isReg() || !Op.isUse() || Op.isUndef())
337 if (!Op.isReg() || !Op.isDef() || Op.isUndef())
lib/Target/Hexagon/HexagonConstExtenders.cpp 235 if (Op.isReg()) {
1925 if (!Op.isReg() || !Op.isUse() ||
lib/Target/Hexagon/HexagonConstPropagation.cpp 693 if (!MO.isReg() || !MO.isDef())
1920 if (MI.getNumOperands() == 0 || !MI.getOperand(0).isReg())
2593 bool Reg1 = Src1.isReg(), Reg2 = Src2.isReg();
2593 bool Reg1 = Src1.isReg(), Reg2 = Src2.isReg();
2696 if (ValOp.isReg()) {
2793 if (!MO.isReg() || !MO.isUse() || MO.isImplicit())
2814 if (!MO.isReg() || !MO.isUse() || MO.isImplicit())
2832 if (!MO.isReg() || !MO.isDef())
3095 if (MO.isReg() && MO.isUse())
lib/Target/Hexagon/HexagonCopyToCombine.cpp 134 assert(Op0.isReg() && Op1.isReg());
134 assert(Op0.isReg() && Op1.isReg());
147 assert(Op0.isReg());
240 if (!Op.isReg() || Op.getReg() != RegNotKilled || !Op.isKill())
258 return MO.isReg() ? MO.getReg() : Register();
409 if (!Op.isReg() || !Op.isUse() || !Op.getReg())
442 if (Op.isReg()) {
608 bool IsHiReg = HiOperand.isReg();
609 bool IsLoReg = LoOperand.isReg();
lib/Target/Hexagon/HexagonEarlyIfConv.cpp 385 if (!MO.isReg() || !MO.isDef())
402 if (!MO.isReg() || !MO.isUse())
473 assert(RA.isReg() && RB.isReg());
473 assert(RA.isReg() && RB.isReg());
492 if (!MO.isReg() || !MO.isDef())
lib/Target/Hexagon/HexagonExpandCondsets.cpp 320 if (!Op.isReg() || !Op.isUse() || Op.getReg() != Reg ||
373 if (!Op.isReg() || !Op.isDef())
498 if (!Op.isReg() || !DefRegs.count(Op))
581 if (SO.isReg()) {
641 if (SrcOp.isReg()) {
680 if (Op.isReg())
689 if (ST.isReg() && SF.isReg()) {
689 if (ST.isReg() && SF.isReg()) {
729 if (!Op.isReg() || !Op.isDef())
765 if (!Op.isReg() || !Op.isDef())
799 if (!Op.isReg())
878 if (!MO.isReg() || !MO.isDef())
889 if (!MO.isReg() || !MO.isImplicit())
900 if (Op.isReg())
921 if (!Op.isReg() || RO != RegisterRef(Op))
992 if (!Op.isReg())
1082 if (Op.isReg())
1194 if (!S1.isReg() && !S2.isReg())
1194 if (!S1.isReg() && !S2.isReg())
1223 if (S1.isReg()) {
1234 if (!Done && S2.isReg()) {
1284 if (Op.isReg() && Op.isUse())
lib/Target/Hexagon/HexagonFrameLowering.cpp 305 if (MO.isReg()) {
lib/Target/Hexagon/HexagonGenInsert.cpp 608 if (MO.isReg() && MO.isDef()) {
725 if (!MO.isReg() || !MO.isDef())
738 if (!MO.isReg() || !MO.isUse())
1478 if (!MO.isReg() || !MO.isDef())
lib/Target/Hexagon/HexagonGenMux.cpp 172 if (!MO.isReg() || MO.isImplicit())
210 bool IsReg1 = Src1.isReg(), IsReg2 = Src2.isReg();
210 bool IsReg1 = Src1.isReg(), IsReg2 = Src2.isReg();
306 Register SR1 = Src1->isReg() ? Src1->getReg() : Register();
307 Register SR2 = Src2->isReg() ? Src2->getReg() : Register();
365 if (!Op.isReg() || !Op.isUse())
lib/Target/Hexagon/HexagonGenPredicate.cpp 354 if (MO.isReg() && MO.isUse())
375 if (!MO.isReg() || !MO.isUse())
lib/Target/Hexagon/HexagonHardwareLoops.cpp 676 if (Op1.isReg()) {
696 if (InitialValue->isReg()) {
706 if (EndValue->isReg()) {
736 if (Start->isReg()) {
742 if (End->isReg()) {
749 if (!Start->isReg() && !Start->isImm())
751 if (!End->isReg() && !End->isImm())
849 bool RegToImm = Start->isReg() && End->isImm(); // for (reg..imm)
850 bool RegToReg = Start->isReg() && End->isReg(); // for (reg..reg)
850 bool RegToReg = Start->isReg() && End->isReg(); // for (reg..reg)
887 if (Start->isReg()) {
1038 if (!MO.isReg() || !MO.isDef())
1058 if (!OPO.isReg() || !OPO.isDef())
1093 if (!MO.isReg() || !MO.isDef())
1343 if (MO.isReg() && MO.isUse()) {
1419 if (!InitVal->isReg())
1503 if (!MO.isReg())
1584 assert(MO.isReg());
1702 if (!Cond[CSz-1].isReg())
1720 if (MO.isReg()) {
1769 if (MO.isReg() && MO.getReg() == RB.first) {
1777 } else if (MO.isReg()) {
1836 if (MO.isReg() && MO.getReg() == RB.first) {
lib/Target/Hexagon/HexagonHazardRecognizer.cpp 51 if (!MO.isReg() || RegDefs.count(MO.getReg()) == 0)
116 if (MO.isReg() && MO.isDef() && !MO.isImplicit())
lib/Target/Hexagon/HexagonInstrInfo.cpp 193 if (!MO.isReg())
633 if (Cond[2].isReg()) {
1583 if (!Op.isReg() || !Op.isDef() || Op.isImplicit())
1623 if (MO.isReg()) {
2620 if (MI2.getOperand(I).isReg() && DstReg == MI2.getOperand(I).getReg())
2625 if (MI1.getOperand(0).isReg() && MI2.getOperand(3).isReg() &&
2625 if (MI1.getOperand(0).isReg() && MI2.getOperand(3).isReg() &&
2944 assert((!BaseOp || BaseOp->isReg()) &&
2955 if (Op.isReg() && Op.isUse() && Op.getReg() == Hexagon::R29)
2965 if (!Stored.isReg())
2969 if (Op.isReg() && Op.isDef() && Op.getReg() == Stored.getReg())
3101 if (MO.isReg() && MO.isDef() && MO.isImplicit() && (MO.getReg() == PredReg))
3216 if (!MI.getOperand(BasePos).isReg() || !MI.getOperand(OffsetPos).isImm())
4103 if (DefMO.isReg() && Register::isPhysicalRegister(DefMO.getReg())) {
4312 for (; MI.getOperand(NumDefs).isReg() && MI.getOperand(NumDefs).isDef();
lib/Target/Hexagon/HexagonNewValueJump.cpp 151 if (!Op.isReg() || !Op.isDef())
176 if (II->getOperand(i).isReg() &&
565 if (foundJump && !foundCompare && MI.getOperand(0).isReg() &&
572 isSecondOpReg = MI.getOperand(2).isReg();
601 if (MI.getOperand(0).isReg() && MI.getOperand(0).isDef() &&
652 if (!MO.isReg() || !MO.isUse())
659 if (!Op.isReg() || !Op.isUse() || !Op.isKill())
705 if (cmpInstr->getOperand(0).isReg() &&
708 if (cmpInstr->getOperand(1).isReg() &&
lib/Target/Hexagon/HexagonOptAddrMode.cpp 133 if (StOp.isReg() && StOp.getReg() == TfrDefR)
200 if (UseMID.mayStore() && UseMI.getOperand(2).isReg() &&
365 if (!BaseOp.isReg() || BaseOp.getReg() != AddDefR)
756 if (op.isReg() && op.isUse() && DefR == op.getReg())
lib/Target/Hexagon/HexagonSplitDouble.cpp 179 if (MI->getOperand(1).isReg())
184 if (MI->getOperand(0).isReg())
211 if (!Op.isReg())
259 if (&MO == &Op || !MO.isReg() || MO.getSubReg())
443 if (Op.isReg() && Part.count(Op.getReg()))
500 assert(Cond[1].isReg() && "Unexpected Cond vector from analyzeBranch");
601 if (!Op.isReg()) {
704 assert(Op0.isReg() && Op1.isImm());
732 assert(Op0.isReg());
740 if (!Op1.isReg()) {
748 if (!Op2.isReg()) {
761 assert(Op0.isReg() && Op1.isReg());
761 assert(Op0.isReg() && Op1.isReg());
784 assert(Op0.isReg() && Op1.isReg() && Op2.isImm());
784 assert(Op0.isReg() && Op1.isReg() && Op2.isImm());
909 assert(Op0.isReg() && Op1.isReg() && Op2.isReg() && Op3.isImm());
909 assert(Op0.isReg() && Op1.isReg() && Op2.isReg() && Op3.isImm());
909 assert(Op0.isReg() && Op1.isReg() && Op2.isReg() && Op3.isImm());
1080 if (!Op.isReg() || !Op.isUse() || !Op.getSubReg())
1105 if (!Op.isReg() || !Op.isUse())
lib/Target/Hexagon/HexagonStoreWidening.cpp 123 assert(MO.isReg() && "Expecting register operand");
161 return MI->getOperand(0).isReg();
lib/Target/Hexagon/HexagonSubtarget.cpp 240 if (!MO.isReg())
281 if (BaseOp0 == nullptr || !BaseOp0->isReg() || Size0 >= 32)
293 if (BaseOp1 == nullptr || !BaseOp1->isReg() || Size1 >= 32 ||
352 if (MO.isReg() && MO.getReg() && MO.isUse() && MO.getReg() == DReg) {
427 if (MO.isReg() && MO.isDef() && MO.getReg() == DepR)
435 if (MO.isReg() && MO.isUse() && MO.getReg() == DepR) {
lib/Target/Hexagon/HexagonVLIWPacketizer.cpp 150 if (!MO.isReg() || !MO.isDef())
312 if (MO.isReg() && MO.getReg() == DepReg && !MO.isImplicit())
387 if (MO.isReg() && MO.getReg() == MI->getOperand(0).getReg())
429 if (MO.isReg() && MO.getReg() == DestReg)
577 if (MO.isReg() && MO.isDef())
581 if (MO.isReg() && MO.isUse() && DefRegsSet.count(MO.getReg()))
651 if (Val.isReg() && Val.getReg() != DepReg)
704 if (!MO.isReg())
716 if (!MO.isReg())
765 if (MO.isReg() && TempSU->getInstr()->modifiesRegister(MO.getReg(), HRI))
778 if (MO.isReg() && MO.getReg() == DepReg)
790 if (!MO.isReg() || !MO.isDef() || !MO.isImplicit())
803 if (MO.isReg() && MO.isUse() && MO.isImplicit() && MO.getReg() == DepReg)
833 if (!MO.isReg() || MO.getReg() != DepReg || !MO.isImplicit())
947 if (Op.isReg() && Op.getReg() && Op.isUse() &&
1204 if (!MO.isReg() || !MO.isDef() || !MO.isDead())
1210 if (!MO.isReg() || !MO.isDef() || !MO.isDead())
1273 if (OpI.isReg()) {
1356 if (NOp1.isReg() && I.getOperand(0).getReg() == NOp1.getReg())
1380 if (OpR.isReg() && PI->modifiesRegister(OpR.getReg(), HRI)) {
1588 if (Op.isReg() && Op.isDef()) {
lib/Target/Hexagon/HexagonVectorPrint.cpp 110 if (MI.getOperand(0).isReg() && MI.getOperand(0).isDef()) {
116 if (MI.mayStore() && MI.getNumOperands() >= 3 && MI.getOperand(2).isReg()) {
122 if (MI.mayStore() && MI.getNumOperands() >= 4 && MI.getOperand(3).isReg()) {
lib/Target/Hexagon/RDFDeadCode.cpp 67 if (Op.isReg() && MRI.isReserved(Op.getReg()))
lib/Target/Hexagon/RDFGraph.cpp 609 assert(Op.isReg());
974 assert(Op.isReg() || Op.isRegMask());
975 if (Op.isReg())
1272 if (!Op.isReg() || Op.getReg() == 0 || !Op.isUse() || Op.isUndef())
1292 if (!Op.isReg() || !Op.isDef() || Op.isImplicit())
1337 if (!Op.isReg() || !Op.isDef() || !Op.isImplicit())
1366 if (!Op.isReg() || !Op.isUse())
lib/Target/Hexagon/RDFLiveness.cpp 890 if (!Op.isReg() || !Op.isDef() || Op.isImplicit())
899 if (!Op.isReg() || !Op.isUse() || Op.isUndef())
lib/Target/Lanai/LanaiAsmPrinter.cpp 134 if (!MO.isReg())
lib/Target/Lanai/LanaiDelaySlotFiller.cpp 108 assert(RI->getOpcode() == Lanai::LDW_RI && RI->getOperand(0).isReg() &&
110 RI->getOperand(1).isReg() &&
115 RI->getOperand(0).isReg() &&
117 RI->getOperand(1).isReg() &&
207 if (!MO.isReg() || !(Reg = MO.getReg()))
236 if (!MO.isReg() || !(Reg = MO.getReg()))
lib/Target/Lanai/LanaiInstrInfo.cpp 364 if (!MO.isReg() || MO.getReg() != Lanai::SR)
476 if (!MO.isReg())
764 if (!LdSt.getOperand(1).isReg() || !LdSt.getOperand(2).isImm() ||
791 assert(BaseOp->isReg() && "getMemOperandWithOffset only supports base "
lib/Target/Lanai/LanaiMemAluCombiner.cpp 185 return ((Op.isReg() && Op.getReg() == Lanai::R0) ||
247 assert((AluOffset.isReg() || AluOffset.isImm()) &&
264 if (AluOffset.isReg())
307 if (Offset.isReg() && Offset.getReg() == Lanai::R0)
318 } else if (Op2.isReg()) {
320 if (Offset.isReg() && Op2.getReg() == Offset.getReg())
356 if (Offset->isReg() && InstrUsesReg(First, Offset))
lib/Target/Mips/MicroMipsSizeReduction.cpp 287 if (MO.isReg() && ((MO.getReg() == Mips::SP)))
294 if (MO.isReg() && Mips::GPRMM16RegClass.contains(MO.getReg()))
301 if (MO.isReg() && Mips::GPRMM16ZeroRegClass.contains(MO.getReg()))
lib/Target/Mips/Mips16InstrInfo.cpp 360 if (MO.isReg() && MO.getReg() != 0 && !MO.isDef() &&
376 if (MO.isReg() && MO.isDef()) {
lib/Target/Mips/Mips16RegisterInfo.cpp 109 if ((MI.getNumOperands()> OpNo+2) && MI.getOperand(OpNo+2).isReg())
lib/Target/Mips/MipsAsmPrinter.cpp 574 if (Subtarget->isGP64bit() && NumVals == 1 && MO.isReg()) {
599 if (!MO.isReg())
626 assert(BaseMO.isReg() && "Unexpected base pointer for inline asm memory operand.");
lib/Target/Mips/MipsBranchExpansion.cpp 345 if (!MO.isReg()) {
lib/Target/Mips/MipsCallLowering.cpp 570 Info.Callee.isReg() || IsCalleeGlobalPIC ? Mips::JALRPseudo : Mips::JAL);
lib/Target/Mips/MipsDelaySlotFiller.cpp 331 if (!MO.isReg() || !MO.isDef() || !(R = MO.getReg()))
420 if (MO.isReg() && MO.getReg())
lib/Target/Mips/MipsInstrInfo.cpp 113 assert((Cond[i].isImm() || Cond[i].isReg()) &&
466 (I->getOperand(0).isReg() &&
469 (I->getOperand(1).isReg() &&
701 if (!MI.getOperand(SrcOpIdx1).isReg() || !MI.getOperand(SrcOpIdx2).isReg())
701 if (!MI.getOperand(SrcOpIdx1).isReg() || !MI.getOperand(SrcOpIdx2).isReg())
lib/Target/Mips/MipsOptimizePICCall.cpp 130 if (!MO.isReg() || !MO.isUse() || !Register::isVirtualRegister(MO.getReg()))
172 if (MO.isReg() && MO.getReg() == Reg) {
lib/Target/Mips/MipsRegisterBankInfo.cpp 422 if (Op.isReg()) {
lib/Target/Mips/MipsSEFrameLowering.cpp 171 assert(I->getOperand(0).isReg() && I->getOperand(1).isFI());
186 assert(I->getOperand(0).isReg() && I->getOperand(1).isFI());
204 assert(I->getOperand(0).isReg() && I->getOperand(1).isFI());
229 assert(I->getOperand(0).isReg() && I->getOperand(1).isFI());
305 if (I->getNumOperands() == 4 && I->getOperand(3).isReg()
348 if ((Op1.isReg() && Op1.isUndef()) || (Op2.isReg() && Op2.isUndef())) {
348 if ((Op1.isReg() && Op1.isUndef()) || (Op2.isReg() && Op2.isUndef())) {
370 if (I->getNumOperands() == 4 && I->getOperand(3).isReg()
lib/Target/Mips/MipsSEISelLowering.cpp 3523 MI.getOperand(1).isReg() ? RegInfo.getRegClass(MI.getOperand(1).getReg())
3575 MI.getOperand(1).isReg() ? RegInfo.getRegClass(MI.getOperand(1).getReg())
lib/Target/NVPTX/NVPTXPeephole.cpp 84 if (Op.isReg() && Register::isVirtualRegister(Op.getReg())) {
97 if (BaseAddrOp.isReg() && BaseAddrOp.getReg() == NVPTX::VRFrame) {
lib/Target/NVPTX/NVPTXProxyRegErasure.cpp 99 assert(InOp.isReg() && "ProxyReg input operand should be a register.");
100 assert(OutOp.isReg() && "ProxyReg output operand should be a register.");
113 if (Op.isReg() && Op.getReg() == From.getReg()) {
lib/Target/NVPTX/NVPTXReplaceImageHandles.cpp 137 assert(Op.isReg() && "Handle is not in a reg?");
lib/Target/PowerPC/PPCAsmPrinter.cpp 261 if (!MI->getOperand(OpNo).isReg() ||
263 !MI->getOperand(OpNo+1).isReg())
274 if(!MI->getOperand(OpNo).isReg())
325 assert(MI->getOperand(OpNo).isReg());
331 assert(MI->getOperand(OpNo).isReg());
484 assert(MI->getOperand(0).isReg() &&
488 assert(MI->getOperand(1).isReg() &&
548 if (MO.isReg()) {
lib/Target/PowerPC/PPCBranchCoalescing.cpp 343 if (Op1.isReg() &&
358 if (Op1.isReg() && Op2.isReg() &&
358 if (Op1.isReg() && Op2.isReg() &&
460 if (Use.isReg() && Register::isVirtualRegister(Use.getReg())) {
lib/Target/PowerPC/PPCCTRLoops.cpp 116 if (MO.isReg()) {
lib/Target/PowerPC/PPCFrameLowering.cpp 367 if (!MO.isReg() || !PPC::VRRCRegClass.contains(MO.getReg()))
574 if (!MO.isReg())
1742 assert(MBBI->getOperand(0).isReg() && "Expecting register operand.");
1755 assert(MBBI->getOperand(0).isReg() && "Expecting register operand.");
lib/Target/PowerPC/PPCInstrInfo.cpp 162 if (!MO.isReg() || !MO.isDef() || MO.isImplicit())
1348 if (UseMI.getOperand(UseIdx).isReg() &&
1571 if (MO.isReg()) {
2154 assert(MI.getOperand(2).isReg() &&
2166 assert(MI.getOperand(2).isReg() && MI.getOperand(1).isReg() &&
2166 assert(MI.getOperand(2).isReg() && MI.getOperand(1).isReg() &&
2174 assert(MI.getOperand(2).isReg() && MI.getOperand(1).isReg() &&
2174 assert(MI.getOperand(2).isReg() && MI.getOperand(1).isReg() &&
2272 assert(MI.getOperand(OpNo).isReg() && "Operand must be a REG");
2352 if (!MI.getOperand(i).isReg())
2382 bool IsVFReg = (MI.getNumOperands() && MI.getOperand(0).isReg())
2395 if (MO.isReg() && MO.isUse() && !MO.isImplicit()) {
2468 if (MO.isReg() && MO.isUse() && MO.isKill() &&
2695 assert(RegOperand.isReg() && "Instruction format is not right");
2772 bool IsVFReg = MI.getOperand(0).isReg()
3978 if (!MI.getOperand(1).isImm() || !MI.getOperand(2).isReg())
4104 if (MI.getOperand(I).isReg()) {
4126 assert(MI.getOperand(1).isReg() && MI.getOperand(2).isReg());
4126 assert(MI.getOperand(1).isReg() && MI.getOperand(2).isReg());
4274 if (!LdSt.getOperand(1).isImm() || !LdSt.getOperand(2).isReg())
lib/Target/PowerPC/PPCMIPeephole.cpp 148 if (!Op->isReg())
539 if (Use.getOperand(i).isReg() &&
687 SrcMI->getOperand(0).isReg() && SrcMI->getOperand(1).isReg()))
687 SrcMI->getOperand(0).isReg() && SrcMI->getOperand(1).isReg()))
949 (*BII).getOperand(1).isReg()) {
962 if (MO.isReg() && !Register::isVirtualRegister(MO.getReg()))
1015 if (CMPI->getOperand(I).isReg()) {
1155 if (CMPI1->getOperand(2).isReg() && CMPI2->getOperand(2).isReg()) {
1155 if (CMPI1->getOperand(2).isReg() && CMPI2->getOperand(2).isReg()) {
1281 if (CMPI2->getOperand(I).isReg()) {
1430 assert(SrcMI->getOperand(1).isReg() &&
lib/Target/PowerPC/PPCPreEmitPeephole.cpp 91 assert(BBI->getOperand(0).isReg() &&
126 assert(AfterBBI->getOperand(0).isReg() &&
lib/Target/PowerPC/PPCReduceCRLogicals.cpp 66 if (MI.getOperand(i - 1).isReg()) {
232 assert(FirstTerminator->getOperand(0).isReg() &&
lib/Target/PowerPC/PPCVSXSwapRemoval.cpp 254 if (!MO.isReg())
601 if (!MO.isReg())
lib/Target/RISCV/RISCVAsmPrinter.cpp 105 if (!MO.isReg())
133 if (!MO.isReg())
lib/Target/RISCV/RISCVFrameLowering.cpp 280 if (I->mayLoad() && I->getOperand(0).isReg()) {
lib/Target/RISCV/RISCVISelLowering.cpp 1281 return MO.isReg() && MO.isUse() && SelectDests.count(MO.getReg());
lib/Target/RISCV/RISCVInstrInfo.cpp 486 return (MI.getOperand(1).isReg() && MI.getOperand(1).getReg() == RISCV::X0);
lib/Target/Sparc/DelaySlotFiller.cpp 253 if (!MO.isReg())
303 assert(Reg.isReg() && "CALL first operand is not a register.");
310 assert(Operand1.isReg() && "CALLrr second operand is not a register.");
324 if (!MO.isReg())
lib/Target/Sparc/SparcAsmPrinter.cpp 393 if (MI->getOperand(opNum+1).isReg() &&
lib/Target/SystemZ/SystemZElimCompare.cpp 139 if (MI.getNumOperands() > 0 && MI.getOperand(0).isReg() &&
154 if (MO.isReg()) {
527 Compare.getOperand(1).isReg() ? Compare.getOperand(1).getReg() : Register();
lib/Target/SystemZ/SystemZISelLowering.cpp 70 if (Op.isReg())
6504 if (Base.isReg())
lib/Target/SystemZ/SystemZInstrInfo.cpp 101 if (EarlierMI->getOperand(0).isReg() && EarlierMI->getOperand(0).isUse())
521 if (MI.getNumExplicitOperands() == 2 && MI.getOperand(0).isReg() &&
986 if (Op.isReg() && Op.isKill())
lib/Target/SystemZ/SystemZInstrInfo.h 128 bool isIndirect() { return Target != nullptr && Target->isReg(); }
lib/Target/SystemZ/SystemZMCInstLower.cpp 99 if (!MO.isReg() || !MO.isImplicit())
lib/Target/SystemZ/SystemZRegisterInfo.cpp 389 if (MO.isReg() && Register::isPhysicalRegister(MO.getReg())) {
lib/Target/WebAssembly/WebAssemblyCFGStackify.cpp 716 if (!MO.isReg() || Register::isPhysicalRegister(MO.getReg()))
lib/Target/WebAssembly/WebAssemblyExplicitLocals.cpp 177 if (!DefMO.isReg())
310 if (!MO.isReg())
390 (!MO.isReg() || MRI.use_empty(MO.getReg()) ||
lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp 196 bool IsBrOnExn = Cond[1].isReg() && MRI.getRegClass(Cond[1].getReg()) ==
226 if (Cond[1].isReg() &&
lib/Target/WebAssembly/WebAssemblyMCInstLower.cpp 244 if (MO.isReg())
lib/Target/WebAssembly/WebAssemblyPeephole.cpp 163 if (!Op2.isReg())
lib/Target/WebAssembly/WebAssemblyRegStackify.cpp 335 if (!MO.isReg() || MO.isUndef())
392 if (MO.isReg() && MO.isDef() && MO.getReg() == Reg)
437 if (!MO.isReg())
712 if (MO.isReg() && MO.getReg() == Reg)
807 if (!Op.isReg())
916 if (!MO.isReg())
lib/Target/WebAssembly/WebAssemblyRegisterInfo.cpp 93 if (OtherMO.isReg()) {
lib/Target/WebAssembly/WebAssemblyUtilities.cpp 33 if (!MO.isReg() || MO.isImplicit() || !MO.isDef())
lib/Target/X86/X86AsmPrinter.cpp 487 if (MO.isReg()) {
500 if (MO.isReg())
lib/Target/X86/X86AvoidStoreForwardingBlocks.cpp 318 if (!((Base.isReg() && Base.getReg() != X86::NoRegister) || Base.isFI()))
324 if (!(Index.isReg() && Index.getReg() == X86::NoRegister))
326 if (!(Segment.isReg() && Segment.getReg() == X86::NoRegister))
406 if (LoadBase.isReg())
427 if (StoreBase.isReg())
430 assert(StoreSrcVReg.isReg() && "Expected virtual register");
503 if (LoadBase.isReg()) {
513 if (StoreBase.isReg()) {
620 if (LoadBase.isReg() != StoreBase.isReg())
620 if (LoadBase.isReg() != StoreBase.isReg())
622 if (LoadBase.isReg())
lib/Target/X86/X86CallFrameOptimization.cpp 336 if (!MO.isReg())
394 if (J->isCopy() && J->getOperand(0).isReg() && J->getOperand(1).isReg() &&
394 if (J->isCopy() && J->getOperand(0).isReg() && J->getOperand(1).isReg() &&
427 if (!I->getOperand(X86::AddrBaseReg).isReg() ||
454 if (!MO.isReg())
lib/Target/X86/X86CallLowering.cpp 399 unsigned CallOpc = Info.Callee.isReg()
450 if (Info.Callee.isReg())
lib/Target/X86/X86CmovConversion.cpp 437 if (!MO.isReg() || !MO.isUse())
457 if (!MO.isReg() || !MO.isDef())
782 if (!MOp.isReg())
lib/Target/X86/X86DomainReassignment.cpp 145 if (MO.isReg() && MO.isDef() && !MO.isDead() &&
513 if (MO.isReg())
541 if (Op.isReg() && Op.getReg() == Reg)
577 if (!Op.isReg() || !Op.isUse())
593 if (!DefOp.isReg())
lib/Target/X86/X86EvexToVex.cpp 131 if (!MO.isReg())
lib/Target/X86/X86ExpandPseudo.cpp 90 if (Selector.isReg())
288 assert(DestAddr.isReg() && "Offset should be in register!");
lib/Target/X86/X86FastISel.cpp 3957 if (!MO.isReg() || MO.isDef() || MO.getReg() != AM.IndexReg)
lib/Target/X86/X86FixupBWInsts.cpp 250 if (!MO.isReg())
lib/Target/X86/X86FixupLEAs.cpp 245 if (opnd.isReg() && opnd.getReg() == p.getReg()) {
306 return Base.isReg() && isInefficientLEAReg(Base.getReg()) && Index.isReg() &&
306 return Base.isReg() && isInefficientLEAReg(Base.getReg()) && Index.isReg() &&
451 if (p.isReg() && p.getReg() != X86::ESP) {
455 if (q.isReg() && q.getReg() != X86::ESP) {
lib/Target/X86/X86FixupSetCC.cpp 81 if (Op.isReg() && (Op.getReg() == X86::EFLAGS) && Op.isDef())
89 if (Op.isReg() && (Op.getReg() == X86::EFLAGS) && Op.isUse())
lib/Target/X86/X86FlagsCopyLowering.cpp 368 assert(VOp.isReg() &&
725 MI.getOperand(0).isReg() &&
897 assert(SetBI.getOperand(0).isReg() &&
1027 assert(SetCCI.getOperand(0).isReg() &&
lib/Target/X86/X86FloatingPoint.cpp 315 assert(MO.isReg() && "Expected an FP register!");
450 if (MO.isReg() && MO.isDead())
978 if (!MO.isReg())
1019 if (!Op.isReg() || Op.getReg() < X86::FP0 || Op.getReg() > X86::FP6)
1533 if (!MO.isReg())
1604 if (!Op.isReg() || Op.getReg() < X86::FP0 || Op.getReg() > X86::FP6)
1633 if (!Op.isReg() || Op.getReg() < X86::FP0 || Op.getReg() > X86::FP6)
1699 if (!MO.isReg())
lib/Target/X86/X86FrameLowering.cpp 177 if (!MO.isReg() || MO.isDef())
217 if (!MO.isReg())
2763 if (MO.isReg() && MO.isDef() &&
lib/Target/X86/X86ISelLowering.cpp29561 !MI.getOperand(MI.getNumOperands() - 1).isReg() ||
30381 if (MO.isReg() && MO.isUse())
30719 else if (MO.isReg()) // Don't add the whole operand, we don't want to
30843 if (MO.isReg()) // Don't add the whole operand, we don't want to
30857 else if (MO.isReg()) // Don't add the whole operand, we don't want to
31137 if (MOp.isReg())
lib/Target/X86/X86InstrBuilder.h 96 if (Op0.isReg()) {
lib/Target/X86/X86InstrInfo.cpp 197 MI.getOperand(Op + X86::AddrIndexReg).isReg() &&
600 if (MI.getOperand(1 + X86::AddrBaseReg).isReg() &&
602 MI.getOperand(1 + X86::AddrIndexReg).isReg() &&
621 MI.getOperand(1 + X86::AddrIndexReg).isReg() &&
623 !MI.getOperand(1 + X86::AddrDisp).isReg()) {
625 if (!MI.getOperand(1 + X86::AddrBaseReg).isReg())
675 if (MO.isReg() && MO.isDef() &&
912 if (MI.getOperand(2).isReg() && MI.getOperand(2).isUndef())
2131 if (!MI.getOperand(SrcOpIdx1).isReg() ||
2132 !MI.getOperand(SrcOpIdx2).isReg())
2172 if (!MI.getOperand(SrcOpIdx1).isReg() ||
2173 !MI.getOperand(SrcOpIdx2).isReg())
3206 if (!BaseOp->isReg()) // Can be an MO_FrameIndex
3224 assert(BaseOp->isReg() && "getMemOperandWithOffset only supports base "
3630 if (NewCC != X86::COND_INVALID && J->getOperand(1).isReg() &&
3848 if (!MO.isReg())
4641 if (!MO.isReg())
4702 assert(MO.isReg() && "Expected to fold into reg operand!");
4805 !MI.getOperand(1).isReg())
4874 if (isTwoAddr && NumOps >= 2 && OpNum < 2 && MI.getOperand(0).isReg() &&
4875 MI.getOperand(1).isReg() &&
5488 else if (Op.isReg() && Op.isImplicit())
5520 if (MO.isReg())
7246 assert(Inst.getOperand(3).isReg() &&
7578 assert(Op2.isReg() && (Op2.getReg() == X86::NoRegister ||
7583 if ((Op1.isReg() && Op1.getReg() == MI.getOperand(0).getReg()) ||
7586 else if ((Op1.isReg() && Op1.getReg() != X86::NoRegister &&
7596 if ((Op1.isReg() && Op1.getReg() != X86::NoRegister)) {
7601 if (Op && Op->isReg() && Op->getReg() == Op2.getReg() && Coef > 0) {
7630 if (((Op1.isReg() && Op1.getReg() != X86::NoRegister) || Op1.isFI()) &&
7675 assert(OldOp1.isReg() && OldOp1.getReg() == X86::EFLAGS && OldOp1.isDead() &&
7677 assert(OldOp2.isReg() && OldOp2.getReg() == X86::EFLAGS && OldOp2.isDead() &&
7683 assert(NewOp1.isReg() && NewOp1.getReg() == X86::EFLAGS &&
7685 assert(NewOp2.isReg() && NewOp2.getReg() == X86::EFLAGS &&
lib/Target/X86/X86InstrInfo.h 116 MI.getOperand(Op + X86::AddrBaseReg).isReg() &&
118 MI.getOperand(Op + X86::AddrIndexReg).isReg() &&
129 MI.getOperand(Op + X86::AddrSegmentReg).isReg() && isLeaMem(MI, Op);
lib/Target/X86/X86InstructionSelector.cpp 475 assert(I.getOperand(0).isReg() && "unsupported opperand.");
lib/Target/X86/X86MCInstLower.cpp 1641 StringRef DstName = DstOp.isReg() ? GetRegisterName(DstOp.getReg()) : "mem";
1643 SrcOp1.isReg() ? GetRegisterName(SrcOp1.getReg()) : "mem";
1645 SrcOp2.isReg() ? GetRegisterName(SrcOp2.getReg()) : "mem";
1664 if (WriteMaskOp.isReg()) {
lib/Target/X86/X86OptimizeLEAs.cpp 201 (!MO1.isReg() || !Register::isPhysicalRegister(MO1.getReg()));
lib/Target/X86/X86RegisterBankInfo.cpp 117 if (!MO.isReg())
131 if (!MI.getOperand(Idx).isReg())
lib/Target/X86/X86SpeculativeLoadHardening.cpp 548 if (!Op.isReg() || Op.getReg() != PS->InitialReg)
1676 return Op.isReg() && LoadDepRegs.test(Op.getReg());
1679 if (Def.isReg())
1744 MI.getDesc().getNumDefs() == 1 && MI.getOperand(0).isReg() &&
1762 if (Def.isReg())
1987 assert(BaseMO.isReg() &&
2187 if ((BaseMO.isReg() && BaseMO.getReg() == DefReg) ||
2188 (IndexMO.isReg() && IndexMO.getReg() == DefReg))
2611 if (!MI.getOperand(0).isReg())
lib/Target/X86/X86VZeroUpper.cpp 157 if (!MO.isReg())
lib/Target/X86/X86WinAllocaExpander.cpp 82 assert(MI->getOperand(0).isReg());
unittests/CodeGen/MachineOperandTest.cpp 73 ASSERT_TRUE(MO.isReg());