|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h 93 MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx);
191 MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx);
252 if (State.MIs[InsnID]->getOperand(1).isCImm())
253 Value = State.MIs[InsnID]->getOperand(1).getCImm()->getSExtValue();
254 else if (State.MIs[InsnID]->getOperand(1).isImm())
255 Value = State.MIs[InsnID]->getOperand(1).getImm();
276 if (State.MIs[InsnID]->getOperand(1).isCImm())
277 Value = State.MIs[InsnID]->getOperand(1).getCImm()->getValue();
296 assert(State.MIs[InsnID]->getOperand(1).isFPImm() && "Expected FPImm operand");
298 APFloat Value = State.MIs[InsnID]->getOperand(1).getFPImm()->getValueAPF();
484 MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx);
526 MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx);
544 MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx);
574 MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx);
599 State.MIs[InsnID]->getOperand(OpIdx));
617 MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx);
642 MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx);
659 MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx);
674 MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx);
687 if (!State.MIs[InsnID]->getOperand(OpIdx).isMBB()) {
700 if (!State.MIs[InsnID]->getOperand(OpIdx).isImm()) {
729 if (!State.MIs[InsnID]->getOperand(OpIdx).isIdenticalTo(
730 State.MIs[OtherInsnID]->getOperand(OtherOpIdx))) {
779 OutMIs[NewInsnID].add(State.MIs[OldInsnID]->getOperand(OpIdx));
793 MachineOperand &MO = State.MIs[OldInsnID]->getOperand(OpIdx);
811 OutMIs[NewInsnID].addReg(State.MIs[OldInsnID]->getOperand(OpIdx).getReg(),
909 if (State.MIs[OldInsnID]->getOperand(1).isCImm()) {
911 State.MIs[OldInsnID]->getOperand(1).getCImm()->getSExtValue());
912 } else if (State.MIs[OldInsnID]->getOperand(1).isImm())
913 OutMIs[NewInsnID].add(State.MIs[OldInsnID]->getOperand(1));
928 if (State.MIs[OldInsnID]->getOperand(1).isFPImm())
930 State.MIs[OldInsnID]->getOperand(1).getFPImm());
include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h 53 Register DstReg = MI.getOperand(0).getReg();
54 Register SrcReg = lookThroughCopyInstrs(MI.getOperand(1).getReg());
83 auto &CstVal = SrcMI->getOperand(1);
98 Register DstReg = MI.getOperand(0).getReg();
99 Register SrcReg = lookThroughCopyInstrs(MI.getOperand(1).getReg());
124 auto &CstVal = SrcMI->getOperand(1);
139 Register DstReg = MI.getOperand(0).getReg();
140 Register SrcReg = lookThroughCopyInstrs(MI.getOperand(1).getReg());
165 Register DstReg = MI.getOperand(0).getReg();
166 Register SrcReg = lookThroughCopyInstrs(MI.getOperand(1).getReg());
174 auto &CstVal = SrcMI->getOperand(1);
194 MI.getOperand(1).getReg(), MRI)) {
196 Register DstReg = MI.getOperand(0).getReg();
255 getDefIgnoringCopies(MI.getOperand(NumDefs).getReg(), MRI);
259 LLT OpTy = MRI.getType(MI.getOperand(NumDefs).getReg());
260 LLT DestTy = MRI.getType(MI.getOperand(0).getReg());
268 MergeI = getDefIgnoringCopies(SrcDef->getOperand(1).getReg(), MRI);
294 DstRegs.push_back(MI.getOperand(DefIdx).getReg());
301 = MRI.getType(MergeI->getOperand(0).getReg()).getElementType();
305 Builder.buildUnmerge(TmpRegs, MergeI->getOperand(Idx + 1).getReg());
310 Builder.buildUnmerge(DstRegs, MergeI->getOperand(Idx + 1).getReg());
331 Regs.push_back(MergeI->getOperand(Idx).getReg());
333 Builder.buildMerge(MI.getOperand(DefIdx).getReg(), Regs);
337 LLT MergeSrcTy = MRI.getType(MergeI->getOperand(1).getReg());
342 Register MergeSrc = MergeI->getOperand(Idx + 1).getReg();
343 Builder.buildInstr(ConvertOp, {MI.getOperand(Idx).getReg()},
356 MRI.replaceRegWith(MI.getOperand(Idx).getReg(),
357 MergeI->getOperand(Idx + 1).getReg());
391 unsigned Src = lookThroughCopyInstrs(MI.getOperand(1).getReg());
396 LLT DstTy = MRI.getType(MI.getOperand(0).getReg());
401 unsigned Offset = MI.getOperand(2).getImm();
416 MI.getOperand(0).getReg(),
417 MergeI->getOperand(MergeSrcIdx + 1).getReg(),
453 for (auto &Use : MRI.use_instructions(MI.getOperand(0).getReg()))
513 if (PrevMI == &DefMI && MRI.hasOneUse(DefMI.getOperand(0).getReg()))
include/llvm/CodeGen/GlobalISel/MIPatternMatch.h 183 return (L.match(MRI, TmpMI->getOperand(1).getReg()) &&
184 R.match(MRI, TmpMI->getOperand(2).getReg())) ||
185 (Commutable && (R.match(MRI, TmpMI->getOperand(1).getReg()) &&
186 L.match(MRI, TmpMI->getOperand(2).getReg())));
251 return L.match(MRI, TmpMI->getOperand(1).getReg());
include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h 151 MIB.addUse(SrcMIB->getOperand(0).getReg());
167 return MRI.getType(SrcMIB->getOperand(0).getReg());
180 return SrcMIB->getOperand(0).getReg();
include/llvm/CodeGen/LiveVariables.h 216 MachineOperand &MO = MI.getOperand(i);
252 MachineOperand &MO = MI.getOperand(i);
include/llvm/CodeGen/MachineInstr.h 1253 return (Idx == -1) ? nullptr : &getOperand(Idx);
1280 return (Idx == -1) ? nullptr : &getOperand(Idx);
1644 MachineOperand &MO = getOperand(OpIdx);
1646 getOperand(findTiedOperandIdx(OpIdx)).TiedTo = 0;
include/llvm/CodeGen/MachineInstrBuilder.h 85 Register getReg(unsigned Idx) const { return MI->getOperand(Idx).getReg(); }
include/llvm/CodeGen/MachineRegisterInfo.h 827 assert(MI->getOperand(0).isReg());
828 MI->getOperand(0).setReg(Reg);
1053 return Op - &Op->getParent()->getOperand(0);
lib/CodeGen/AggressiveAntiDepBreaker.cpp 251 MachineOperand &MO = MI.getOperand(i);
366 MachineOperand &MO = MI.getOperand(i);
376 MachineOperand &MO = MI.getOperand(i);
419 MachineOperand &MO = MI.getOperand(i);
472 MachineOperand &MO = MI.getOperand(i);
507 MachineOperand &MO = MI.getOperand(i);
710 if (UseMI->getOperand(Idx).isEarlyClobber()) {
lib/CodeGen/AntiDepBreaker.h 61 if (MI.getOperand(0).isReg() && MI.getOperand(0).getReg() == OldReg)
61 if (MI.getOperand(0).isReg() && MI.getOperand(0).getReg() == OldReg)
62 MI.getOperand(0).setReg(NewReg);
lib/CodeGen/AsmPrinter/AsmPrinter.cpp 1089 OutStreamer->EmitLabel(MI.getOperand(0).getMCSymbol());
lib/CodeGen/BranchFolding.cpp 876 MachineOperand &MO = MBBICommon->getOperand(I);
878 const MachineOperand &OtherMO = MBBI->getOperand(I);
lib/CodeGen/BreakFalseDeps.cpp 109 MachineOperand &MO = MI->getOperand(OpIdx);
165 Register reg = MI->getOperand(OpIdx).getReg();
202 MachineOperand &MO = MI->getOperand(i);
237 if (!LiveRegSet.contains(UndefMI->getOperand(OpIdx).getReg()))
lib/CodeGen/CFIInstrInserter.cpp 168 unsigned CFIIndex = MI.getOperand(0).getCFIIndex();
lib/CodeGen/CalcSpillWeights.cpp 108 if (MI->getOperand(0).getReg() != Reg)
112 Reg = MI->getOperand(1).getReg();
lib/CodeGen/CriticalAntiDepBreaker.cpp 188 MachineOperand &MO = MI.getOperand(i);
262 MachineOperand &MO = MI.getOperand(i);
304 MachineOperand &MO = MI.getOperand(i);
362 const MachineOperand &CheckOper = MI->getOperand(i);
614 MachineOperand &MO = MI.getOperand(i);
lib/CodeGen/DeadMachineInstructionElim.cpp 141 const MachineOperand &MO = MI->getOperand(i);
160 const MachineOperand &MO = MI->getOperand(i);
lib/CodeGen/EarlyIfConversion.cpp 513 if (PI.PHI->getOperand(i+1).getMBB() == TPred)
514 PI.TReg = PI.PHI->getOperand(i).getReg();
515 if (PI.PHI->getOperand(i+1).getMBB() == FPred)
516 PI.FReg = PI.PHI->getOperand(i).getReg();
569 Register DstReg = PI.PHI->getOperand(0).getReg();
596 Register PHIDst = PI.PHI->getOperand(0).getReg();
605 MachineBasicBlock *MBB = PI.PHI->getOperand(i-1).getMBB();
607 PI.PHI->getOperand(i-1).setMBB(Head);
608 PI.PHI->getOperand(i-2).setReg(DstReg);
lib/CodeGen/ExecutionDomainFix.cpp 241 MachineOperand &MO = MI->getOperand(i);
262 MachineOperand &mo = mi->getOperand(i);
272 MachineOperand &mo = mi->getOperand(i);
293 MachineOperand &mo = mi->getOperand(i);
lib/CodeGen/ExpandPostRAPseudos.cpp 77 assert((MI->getOperand(0).isReg() && MI->getOperand(0).isDef()) &&
77 assert((MI->getOperand(0).isReg() && MI->getOperand(0).isDef()) &&
78 MI->getOperand(1).isImm() &&
79 (MI->getOperand(2).isReg() && MI->getOperand(2).isUse()) &&
79 (MI->getOperand(2).isReg() && MI->getOperand(2).isUse()) &&
80 MI->getOperand(3).isImm() && "Invalid subreg_to_reg");
82 Register DstReg = MI->getOperand(0).getReg();
83 Register InsReg = MI->getOperand(2).getReg();
84 assert(!MI->getOperand(2).getSubReg() && "SubIdx on physreg?");
85 unsigned SubIdx = MI->getOperand(3).getImm();
120 MI->getOperand(2).isKill());
143 MachineOperand &DstMO = MI->getOperand(0);
144 MachineOperand &SrcMO = MI->getOperand(1);
lib/CodeGen/GlobalISel/CSEMIRBuilder.cpp 132 return buildCopy(Op.getReg(), MIB->getOperand(0).getReg());
lib/CodeGen/GlobalISel/CallLowering.cpp 468 return MIB->getOperand(0).getReg();
lib/CodeGen/GlobalISel/CombinerHelper.cpp 75 Register DstReg = MI.getOperand(0).getReg();
76 Register SrcReg = MI.getOperand(1).getReg();
86 Register DstReg = MI.getOperand(0).getReg();
87 Register SrcReg = MI.getOperand(1).getReg();
138 assert(MRI.getType(Undef->getOperand(0).getReg()) ==
145 Ops.push_back(Undef->getOperand(0).getReg());
158 Register DstReg = MI.getOperand(0).getReg();
189 LLT DstType = MRI.getType(MI.getOperand(0).getReg());
190 Register Src1 = MI.getOperand(1).getReg();
216 ShuffleVectorInst::getShuffleMask(MI.getOperand(3).getShuffleMask(), Mask);
235 Register Src2 = MI.getOperand(2).getReg();
253 Register DstReg = MI.getOperand(0).getReg();
371 auto &LoadValue = MI.getOperand(0);
407 MRI.getType(UseMI.getOperand(0).getReg()),
426 Register ChosenDstReg = Preferred.MI->getOperand(0).getReg();
437 UseMO.setReg(PreviouslyEmitted->getOperand(0).getReg());
443 Register NewDstReg = MRI.cloneVirtualRegister(MI.getOperand(0).getReg());
458 auto &LoadValue = MI.getOperand(0);
470 Register UseDstReg = UseMI->getOperand(0).getReg();
471 MachineOperand &UseSrcMO = UseMI->getOperand(1);
529 MI.getOperand(0).setReg(ChosenDstReg);
566 Base = MI.getOperand(1).getReg();
577 Offset = Use.getOperand(2).getReg();
600 for (auto &GEPUse : MRI.use_instructions(Use.getOperand(0).getReg())) {
615 Addr = Use.getOperand(0).getReg();
633 Addr = MI.getOperand(1).getReg();
638 Base = AddrDef->getOperand(1).getReg();
639 Offset = AddrDef->getOperand(2).getReg();
657 if (Base == MI.getOperand(0).getReg()) {
664 if (MI.getOperand(0).getReg() == Addr) {
719 MIB.addUse(MI.getOperand(0).getReg());
721 MIB.addDef(MI.getOperand(0).getReg());
765 if (!MBB->isLayoutSuccessor(BrCond->getOperand(1).getMBB()))
768 MachineInstr *CmpMI = MRI.getVRegDef(BrCond->getOperand(0).getReg());
770 !MRI.hasOneUse(CmpMI->getOperand(0).getReg()))
783 MachineBasicBlock *BrTarget = MI.getOperand(0).getMBB();
786 MachineInstr *CmpMI = MRI.getVRegDef(BrCond->getOperand(0).getReg());
789 (CmpInst::Predicate)CmpMI->getOperand(1).getPredicate());
793 CmpMI->getOperand(1).setPredicate(InversePred);
798 BrCond->getOperand(1).setMBB(BrTarget);
934 if (FIDef && !MFI.isFixedObjectIndex(FIDef->getOperand(1).getIndex()))
960 unsigned FI = FIDef->getOperand(1).getIndex();
1049 if (FIDef && !MFI.isFixedObjectIndex(FIDef->getOperand(1).getIndex()))
1088 unsigned FI = FIDef->getOperand(1).getIndex();
1157 if (FIDef && !MFI.isFixedObjectIndex(FIDef->getOperand(1).getIndex()))
1195 unsigned FI = FIDef->getOperand(1).getIndex();
1265 Register Dst = MI.getOperand(1).getReg();
1266 Register Src = MI.getOperand(2).getReg();
1267 Register Len = MI.getOperand(3).getReg();
lib/CodeGen/GlobalISel/GISelKnownBits.cpp 66 return getKnownBits(MI.getOperand(0).getReg());
126 MachineOperand Dst = MI.getOperand(0);
127 MachineOperand Src = MI.getOperand(1);
158 computeKnownBitsImpl(MI.getOperand(1).getReg(), Known2, DemandedElts,
163 computeKnownBitsImpl(MI.getOperand(2).getReg(), Known2, DemandedElts,
170 computeKnownBitsImpl(MI.getOperand(2).getReg(), Known, DemandedElts,
172 computeKnownBitsImpl(MI.getOperand(1).getReg(), Known2, DemandedElts,
184 LLT Ty = MRI.getType(MI.getOperand(1).getReg());
197 computeKnownBitsImpl(MI.getOperand(1).getReg(), Known2, DemandedElts,
201 computeKnownBitsImpl(MI.getOperand(2).getReg(), Known2, DemandedElts,
212 computeKnownBitsImpl(MI.getOperand(2).getReg(), Known, DemandedElts,
214 computeKnownBitsImpl(MI.getOperand(1).getReg(), Known2, DemandedElts,
225 computeKnownBitsImpl(MI.getOperand(2).getReg(), Known, DemandedElts,
227 computeKnownBitsImpl(MI.getOperand(1).getReg(), Known2, DemandedElts,
237 computeKnownBitsImpl(MI.getOperand(2).getReg(), Known, DemandedElts,
239 computeKnownBitsImpl(MI.getOperand(1).getReg(), Known2, DemandedElts,
258 computeKnownBitsImpl(MI.getOperand(3).getReg(), Known, DemandedElts,
263 computeKnownBitsImpl(MI.getOperand(2).getReg(), Known2, DemandedElts,
280 computeKnownBitsImpl(MI.getOperand(1).getReg(), Known, DemandedElts,
288 computeKnownBitsImpl(MI.getOperand(1).getReg(), Known, DemandedElts,
312 computeKnownBitsImpl(MI.getOperand(2).getReg(), RHSKnown, DemandedElts,
316 MachineInstr *RHSMI = MRI.getVRegDef(MI.getOperand(2).getReg());
323 computeKnownBitsImpl(MI.getOperand(1).getReg(), Known, DemandedElts,
350 Register SrcReg = MI.getOperand(1).getReg();
lib/CodeGen/GlobalISel/IRTranslator.cpp 1911 Idx = MIRBuilder.buildSExtOrTrunc(VecIdxTy, Idx)->getOperand(0).getReg();
lib/CodeGen/GlobalISel/InstructionSelect.cpp 170 Register SrcReg = MI.getOperand(1).getReg();
171 Register DstReg = MI.getOperand(0).getReg();
lib/CodeGen/GlobalISel/InstructionSelector.cpp 45 I.getOperand(OpIdx), OpIdx);
66 MachineOperand &RHS = RootI->getOperand(2);
lib/CodeGen/GlobalISel/LegalizerHelper.cpp 386 Args.push_back({MI.getOperand(i).getReg(), OpType});
387 return createLibcall(MIRBuilder, Libcall, {MI.getOperand(0).getReg(), OpType},
400 Register Reg = MI.getOperand(i).getReg();
414 Intrinsic::ID ID = MI.getOperand(0).getIntrinsicID();
437 Info.IsTailCall = MI.getOperand(MI.getNumOperands() - 1).getImm() == 1 &&
485 return createLibcall(MIRBuilder, Libcall, {MI.getOperand(0).getReg(), ToType},
486 {{MI.getOperand(1).getReg(), FromType}});
491 LLT LLTy = MRI.getType(MI.getOperand(0).getReg());
539 unsigned FromSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
540 unsigned ToSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
551 unsigned FromSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
552 unsigned ToSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
564 unsigned FromSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
565 unsigned ToSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
579 unsigned FromSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
580 unsigned ToSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
602 uint64_t SizeOp0 = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
618 MIRBuilder.buildUndef(NarrowTy)->getOperand(0).getReg());
620 Register DstReg = MI.getOperand(0).getReg();
629 LLT Ty = MRI.getType(MI.getOperand(0).getReg());
630 const APInt &Val = MI.getOperand(1).getCImm()->getValue();
654 insertParts(MI.getOperand(0).getReg(),
664 Register SrcReg = MI.getOperand(1).getReg();
679 MIRBuilder.buildMerge(MI.getOperand(0).getReg(), {SrcReg, Shift.getReg(0)});
687 LLT SrcTy = MRI.getType(MI.getOperand(1).getReg());
696 SmallVector<Register, 4> Srcs = {MI.getOperand(1).getReg()};
699 MIRBuilder.buildMerge(MI.getOperand(0).getReg(), Srcs);
707 uint64_t SizeOp1 = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
713 auto Unmerge = MIRBuilder.buildUnmerge(NarrowTy, MI.getOperand(1).getReg());
714 MIRBuilder.buildCopy(MI.getOperand(0).getReg(), Unmerge.getReg(0));
728 extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, Src1Regs);
729 extractParts(MI.getOperand(2).getReg(), NarrowTy, NumParts, Src2Regs);
746 Register DstReg = MI.getOperand(0).getReg();
763 extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, Src1Regs);
764 extractParts(MI.getOperand(2).getReg(), NarrowTy, NumParts, Src2Regs);
782 MIRBuilder.buildMerge(MI.getOperand(0).getReg(), DstRegs);
795 Register DstReg = MI.getOperand(0).getReg();
803 MIRBuilder.buildLoad(TmpReg, MI.getOperand(1).getReg(), MMO);
814 Register DstReg = MI.getOperand(0).getReg();
815 Register PtrReg = MI.getOperand(1).getReg();
841 Register SrcReg = MI.getOperand(0).getReg();
856 MIRBuilder.buildStore(TmpReg, MI.getOperand(1).getReg(), MMO);
919 MachineBasicBlock &OpMBB = *MI.getOperand(i + 1).getMBB();
921 extractParts(MI.getOperand(i).getReg(), NarrowTy, NumParts,
931 MIB.addUse(SrcRegs[j / 2][i]).add(MI.getOperand(j + 1));
934 MIRBuilder.buildMerge(MI.getOperand(0).getReg(), DstRegs);
951 uint64_t SrcSize = MRI.getType(MI.getOperand(2).getReg()).getSizeInBits();
958 MIRBuilder.buildUnmerge({LHSL, LHSH}, MI.getOperand(2).getReg());
962 MIRBuilder.buildUnmerge({RHSL, RHSH}, MI.getOperand(3).getReg());
965 static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate());
966 LLT ResTy = MRI.getType(MI.getOperand(0).getReg());
973 MIRBuilder.buildICmp(Pred, MI.getOperand(0).getReg(), Or, Zero);
980 MIRBuilder.buildSelect(MI.getOperand(0).getReg(), CmpHEQ, CmpLU, CmpH);
990 if (!MI.getOperand(2).isImm())
992 int64_t SizeInBits = MI.getOperand(2).getImm();
1000 MachineOperand &MO1 = MI.getOperand(1);
1002 MO1.setReg(TruncMIB->getOperand(0).getReg());
1004 MachineOperand &MO2 = MI.getOperand(0);
1034 MIRBuilder.buildUnmerge(SrcRegs, MI.getOperand(1).getReg());
1038 ->getOperand(0)
1057 ->getOperand(0)
1066 ->getOperand(0)
1073 Register DstReg = MI.getOperand(0).getReg();
1083 MachineOperand &MO = MI.getOperand(OpIdx);
1085 MO.setReg(ExtB->getOperand(0).getReg());
1090 MachineOperand &MO = MI.getOperand(OpIdx);
1093 MO.setReg(ExtB->getOperand(0).getReg());
1098 MachineOperand &MO = MI.getOperand(OpIdx);
1107 MachineOperand &MO = MI.getOperand(OpIdx);
1116 MachineOperand &MO = MI.getOperand(OpIdx);
1125 MachineOperand &MO = MI.getOperand(OpIdx);
1159 Register DstReg = MI.getOperand(0).getReg();
1164 Register Src1 = MI.getOperand(1).getReg();
1182 Register SrcReg = MI.getOperand(I).getReg();
1236 Register SrcReg = MI.getOperand(I).getReg();
1282 Register SrcReg = MI.getOperand(NumDst).getReg();
1287 Register Dst0Reg = MI.getOperand(0).getReg();
1306 MI.getOperand(NumDst).setReg(WideSrc->getOperand(0).getReg());
1306 MI.getOperand(NumDst).setReg(WideSrc->getOperand(0).getReg());
1318 Register DstReg = MI.getOperand(0).getReg();
1319 Register SrcReg = MI.getOperand(1).getReg();
1323 unsigned Offset = MI.getOperand(2).getImm();
1387 MI.getOperand(2).setImm((WideTy.getSizeInBits() / SrcTy.getSizeInBits()) *
1426 {MI.getOperand(2).getReg()});
1428 {MI.getOperand(3).getReg()});
1434 LLT OrigTy = MRI.getType(MI.getOperand(0).getReg());
1440 MIRBuilder.buildICmp(CmpInst::ICMP_NE, MI.getOperand(1).getReg(), NewOp,
1443 MIRBuilder.buildTrunc(MI.getOperand(0).getReg(), NewOp);
1459 Register SrcReg = MI.getOperand(1).getReg();
1486 MIRBuilder.buildZExtOrTrunc(MI.getOperand(0), MIBNewOp);
1492 Register DstReg = MI.getOperand(0).getReg();
1499 MI.getOperand(0).setReg(DstExt);
1518 Register DstReg = MI.getOperand(0).getReg();
1524 MI.getOperand(0).setReg(DstExt);
1616 bool IsVec = MRI.getType(MI.getOperand(1).getReg()).isVector();
1662 LLT Ty = MRI.getType(MI.getOperand(0).getReg());
1676 MachineOperand &SrcMO = MI.getOperand(1);
1687 MachineOperand &SrcMO = MI.getOperand(1);
1742 MI.getOperand(1).getPredicate()))
1763 MachineBasicBlock &OpMBB = *MI.getOperand(I + 1).getMBB();
1776 Register VecReg = MI.getOperand(1).getReg();
1801 Register VecReg = MI.getOperand(1).getReg();
1921 .addUse(MI.getOperand(1).getReg())
1922 .addUse(MI.getOperand(2).getReg());
1925 MIRBuilder.buildMul(ProdReg, QuotReg, MI.getOperand(2).getReg());
1926 MIRBuilder.buildSub(MI.getOperand(0).getReg(), MI.getOperand(1).getReg(),
1926 MIRBuilder.buildSub(MI.getOperand(0).getReg(), MI.getOperand(1).getReg(),
1938 Register Res = MI.getOperand(0).getReg();
1939 Register Overflow = MI.getOperand(1).getReg();
1940 Register LHS = MI.getOperand(2).getReg();
1941 Register RHS = MI.getOperand(3).getReg();
1980 Register Res = MI.getOperand(0).getReg();
2002 Register SubByReg = MI.getOperand(1).getReg();
2003 Register ZeroReg = Zero->getOperand(0).getReg();
2015 Register Res = MI.getOperand(0).getReg();
2016 Register LHS = MI.getOperand(1).getReg();
2017 Register RHS = MI.getOperand(2).getReg();
2027 Register OldValRes = MI.getOperand(0).getReg();
2028 Register SuccessRes = MI.getOperand(1).getReg();
2029 Register Addr = MI.getOperand(2).getReg();
2030 Register CmpVal = MI.getOperand(3).getReg();
2031 Register NewVal = MI.getOperand(4).getReg();
2042 Register DstReg = MI.getOperand(0).getReg();
2043 Register PtrReg = MI.getOperand(1).getReg();
2133 Register SrcReg = MI.getOperand(0).getReg();
2134 Register PtrReg = MI.getOperand(1).getReg();
2178 Register Res = MI.getOperand(0).getReg();
2179 Register CarryOut = MI.getOperand(1).getReg();
2180 Register LHS = MI.getOperand(2).getReg();
2181 Register RHS = MI.getOperand(3).getReg();
2190 Register Res = MI.getOperand(0).getReg();
2191 Register CarryOut = MI.getOperand(1).getReg();
2192 Register LHS = MI.getOperand(2).getReg();
2193 Register RHS = MI.getOperand(3).getReg();
2194 Register CarryIn = MI.getOperand(4).getReg();
2208 Register Res = MI.getOperand(0).getReg();
2209 Register BorrowOut = MI.getOperand(1).getReg();
2210 Register LHS = MI.getOperand(2).getReg();
2211 Register RHS = MI.getOperand(3).getReg();
2220 Register Res = MI.getOperand(0).getReg();
2221 Register BorrowOut = MI.getOperand(1).getReg();
2222 Register LHS = MI.getOperand(2).getReg();
2223 Register RHS = MI.getOperand(3).getReg();
2224 Register BorrowIn = MI.getOperand(4).getReg();
2260 assert(MI.getOperand(2).isImm() && "Expected immediate");
2261 int64_t SizeInBits = MI.getOperand(2).getImm();
2263 Register DstReg = MI.getOperand(0).getReg();
2264 Register SrcReg = MI.getOperand(1).getReg();
2269 MIRBuilder.buildInstr(TargetOpcode::G_SHL, {TmpRes}, {SrcReg, MIBSz->getOperand(0).getReg()});
2270 MIRBuilder.buildInstr(TargetOpcode::G_ASHR, {DstReg}, {TmpRes, MIBSz->getOperand(0).getReg()});
2290 Register DstReg = MI.getOperand(0).getReg();
2319 const Register DstReg = MI.getOperand(0).getReg();
2343 MIRBuilder.buildExtract(PartOpReg, MI.getOperand(I).getReg(), Offset);
2359 MIRBuilder.buildExtract(PartOpReg, MI.getOperand(I).getReg(),
2374 extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, Src0Regs);
2377 extractParts(MI.getOperand(2).getReg(), NarrowTy, NumParts, Src1Regs);
2380 extractParts(MI.getOperand(3).getReg(), NarrowTy, NumParts, Src2Regs);
2428 const Register DstReg = MI.getOperand(0).getReg();
2446 Register SrcReg = MI.getOperand(I).getReg();
2508 Register DstReg = MI.getOperand(0).getReg();
2509 Register SrcReg = MI.getOperand(1).getReg();
2554 Register DstReg = MI.getOperand(0).getReg();
2555 Register Src0Reg = MI.getOperand(2).getReg();
2590 = static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate());
2593 extractParts(MI.getOperand(2).getReg(), NarrowTy1, NumParts, Src1Regs);
2594 extractParts(MI.getOperand(3).getReg(), NarrowTy1, NumParts, Src2Regs);
2621 Register DstReg = MI.getOperand(0).getReg();
2622 Register CondReg = MI.getOperand(1).getReg();
2669 extractParts(MI.getOperand(1).getReg(), NarrowTy1, NumParts, Src0Regs);
2671 extractParts(MI.getOperand(2).getReg(), NarrowTy0, NumParts, Src1Regs);
2672 extractParts(MI.getOperand(3).getReg(), NarrowTy0, NumParts, Src2Regs);
2693 const Register DstReg = MI.getOperand(0).getReg();
2734 Register SrcReg = MI.getOperand(I).getReg();
2735 MachineBasicBlock &OpMBB = *MI.getOperand(I + 1).getMBB();
2765 const Register SrcReg = MI.getOperand(NumDst).getReg();
2768 LLT DstTy = MRI.getType(MI.getOperand(0).getReg());
2789 MIB.addDef(MI.getOperand(I * PartsPerUnmerge + J).getReg());
2802 Register DstReg = MI.getOperand(0).getReg();
2834 Register SrcReg = MI.getOperand(SrcIdx + 1).getReg();
2872 Register ValReg = MI.getOperand(0).getReg();
2873 Register AddrReg = MI.getOperand(1).getReg();
3047 MIRBuilder.buildUnmerge({InL, InH}, MI.getOperand(1).getReg());
3050 MIRBuilder.buildMerge(MI.getOperand(0).getReg(), {InL, InH});
3123 MIRBuilder.buildMerge(MI.getOperand(0).getReg(), {Lo.getReg(), Hi.getReg()});
3140 Register DstReg = MI.getOperand(0).getReg();
3145 Register Amt = MI.getOperand(2).getReg();
3171 MIRBuilder.buildUnmerge({InL, InH}, MI.getOperand(1).getReg());
3247 MachineBasicBlock &OpMBB = *MI.getOperand(I + 1).getMBB();
3313 if (MRI.getType(MI.getOperand(1).getReg()).isVector())
3326 LLT DstTy = MRI.getType(MI.getOperand(0).getReg());
3332 MIB.addDef(MI.getOperand(I).getReg());
3338 MIB.addUse(MI.getOperand(NumDst).getReg());
3414 Register DstReg = MI.getOperand(0).getReg();
3415 Register Src1 = MI.getOperand(1).getReg();
3416 Register Src2 = MI.getOperand(2).getReg();
3455 int64_t SizeOp1 = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
3464 extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, SrcRegs);
3466 Register OpReg = MI.getOperand(0).getReg();
3467 uint64_t OpStart = MI.getOperand(2).getImm();
3503 Register DstReg = MI.getOperand(0).getReg();
3519 uint64_t SizeOp0 = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
3531 extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, SrcRegs);
3533 Register OpReg = MI.getOperand(2).getReg();
3534 uint64_t OpStart = MI.getOperand(3).getImm();
3578 Register DstReg = MI.getOperand(0).getReg();
3590 Register DstReg = MI.getOperand(0).getReg();
3599 if (!extractParts(MI.getOperand(1).getReg(), DstTy, NarrowTy, LeftoverTy,
3604 if (!extractParts(MI.getOperand(2).getReg(), DstTy, NarrowTy, Unused,
3611 DstRegs.push_back(Inst->getOperand(0).getReg());
3618 DstLeftoverRegs.push_back(Inst->getOperand(0).getReg());
3634 Register CondReg = MI.getOperand(1).getReg();
3639 Register DstReg = MI.getOperand(0).getReg();
3646 if (!extractParts(MI.getOperand(2).getReg(), DstTy, NarrowTy, LeftoverTy,
3651 if (!extractParts(MI.getOperand(3).getReg(), DstTy, NarrowTy, Unused,
3658 DstRegs.push_back(Select->getOperand(0).getReg());
3664 DstLeftoverRegs.push_back(Select->getOperand(0).getReg());
3693 Register SrcReg = MI.getOperand(1).getReg();
3703 MIRBuilder.buildSelect(MI.getOperand(0).getReg(), MIBICmp, MIBLen,
3727 Op = MIBOp->getOperand(0).getReg();
3730 MIRBuilder.buildInstr(TargetOpcode::G_SUB, {MI.getOperand(0).getReg()},
3743 Register SrcReg = MI.getOperand(1).getReg();
3754 MIRBuilder.buildSelect(MI.getOperand(0).getReg(), MIBICmp, MIBLen,
3774 TargetOpcode::G_SUB, {MI.getOperand(0).getReg()},
3781 MI.getOperand(1).setReg(MIBTmp->getOperand(0).getReg());
3781 MI.getOperand(1).setReg(MIBTmp->getOperand(0).getReg());
3791 Register Dst = MI.getOperand(0).getReg();
3792 Register Src = MI.getOperand(1).getReg();
3847 Register Dst = MI.getOperand(0).getReg();
3848 Register Src = MI.getOperand(1).getReg();
3868 Register Dst = MI.getOperand(0).getReg();
3869 Register Src = MI.getOperand(1).getReg();
3906 Register Dst = MI.getOperand(0).getReg();
3907 Register Src = MI.getOperand(1).getReg();
3963 Register Dst = MI.getOperand(0).getReg();
3964 Register Src0 = MI.getOperand(1).getReg();
3965 Register Src1 = MI.getOperand(2).getReg();
3979 Register Dst = MI.getOperand(0).getReg();
3980 Register Src0 = MI.getOperand(1).getReg();
3981 Register Src1 = MI.getOperand(2).getReg();
4030 Register Dst = MI.getOperand(0).getReg();
4031 Register Src0 = MI.getOperand(1).getReg();
4032 Register Src1 = MI.getOperand(2).getReg();
4058 Register DstReg = MI.getOperand(0).getReg();
4062 auto Mul = MIRBuilder.buildFMul(Ty, MI.getOperand(1), MI.getOperand(2),
4062 auto Mul = MIRBuilder.buildFMul(Ty, MI.getOperand(1), MI.getOperand(2),
4064 MIRBuilder.buildFAdd(DstReg, Mul, MI.getOperand(3), Flags);
4072 const Register SrcReg = MI.getOperand(NumDst).getReg();
4075 Register Dst0Reg = MI.getOperand(0).getReg();
4092 MIRBuilder.buildTrunc(MI.getOperand(I), Shift);
4104 Register DstReg = MI.getOperand(0).getReg();
4105 Register Src0Reg = MI.getOperand(1).getReg();
4106 Register Src1Reg = MI.getOperand(2).getReg();
4111 const Constant *ShufMask = MI.getOperand(3).getShuffleMask();
4163 Register Dst = MI.getOperand(0).getReg();
4164 Register AllocSize = MI.getOperand(1).getReg();
4165 unsigned Align = MI.getOperand(2).getImm();
4198 Register Dst = MI.getOperand(0).getReg();
4199 Register Src = MI.getOperand(1).getReg();
4200 unsigned Offset = MI.getOperand(2).getImm();
4230 Register Dst = MI.getOperand(0).getReg();
4231 Register Src = MI.getOperand(1).getReg();
4232 Register InsertSrc = MI.getOperand(2).getReg();
4233 uint64_t Offset = MI.getOperand(3).getImm();
4270 Register Dst0 = MI.getOperand(0).getReg();
4271 Register Dst1 = MI.getOperand(1).getReg();
4272 Register LHS = MI.getOperand(2).getReg();
4273 Register RHS = MI.getOperand(3).getReg();
lib/CodeGen/GlobalISel/Localizer.cpp 103 InsertMBB = MIUse.getOperand(MIUse.getOperandNo(&MOUse) + 1).getMBB();
124 Register Reg = MI.getOperand(0).getReg();
156 LocalizedMI->getOperand(0).setReg(NewReg);
180 Register Reg = MI->getOperand(0).getReg();
lib/CodeGen/GlobalISel/RegBankSelect.cpp 468 const MachineOperand &MO = MI.getOperand(OpIdx);
594 MachineOperand &MO = MI.getOperand(OpIdx);
728 const MachineOperand &MO = MI.getOperand(OpIdx);
758 MachineBasicBlock &Pred = *MI.getOperand(OpIdx + 1).getMBB();
lib/CodeGen/GlobalISel/RegisterBankInfo.cpp 441 MachineOperand &MO = MI.getOperand(OpIdx);
790 OS << '(' << printReg(getMI().getOperand(Idx).getReg(), TRI) << ", [";
lib/CodeGen/GlobalISel/Utils.cpp 122 MachineOperand &MO = I.getOperand(OpI);
252 MRI.getType(MI->getOperand(0).getReg()).getSizeInBits()));
253 VReg = MI->getOperand(1).getReg();
256 VReg = MI->getOperand(1).getReg();
261 VReg = MI->getOperand(1).getReg();
300 return MI->getOperand(1).getFPImm();
306 auto DstTy = MRI.getType(DefMI->getOperand(0).getReg());
310 Register SrcReg = DefMI->getOperand(1).getReg();
lib/CodeGen/ImplicitNullChecks.cpp 626 DefReg = MI->getOperand(0).getReg();
lib/CodeGen/InlineSpiller.cpp 379 Register SrcReg = CopyMI.getOperand(1).getReg();
512 LiveInterval &SnipLI = LIS.getInterval(MI->getOperand(1).getReg());
558 MachineOperand &MO = MI.getOperand(i);
623 MachineOperand &MO = OpPair.first->getOperand(OpPair.second);
814 MachineOperand &MO = MI->getOperand(Idx);
883 MachineOperand &MO = FoldMI->getOperand(i - 1);
1017 MI->getOperand(0).setIsDead();
1043 MachineOperand &MO = OpPair.first->getOperand(OpPair.second);
1522 MachineOperand &MO = RMEnt->getOperand(i - 1);
lib/CodeGen/LiveDebugValues.cpp 1320 !MI.isIndirectDebugValue() && IsRegOtherThanSPAndFP(MI.getOperand(0)) &&
lib/CodeGen/LiveDebugVariables.cpp 602 !(MI.getOperand(1).isReg() || MI.getOperand(1).isImm()) ||
602 !(MI.getOperand(1).isReg() || MI.getOperand(1).isImm()) ||
603 !MI.getOperand(2).isMetadata()) {
616 if (MI.getOperand(0).isReg() &&
617 Register::isVirtualRegister(MI.getOperand(0).getReg())) {
618 const Register Reg = MI.getOperand(0).getReg();
642 assert(!MI.getOperand(1).isImm() && "DBG_VALUE with indirect flag before "
649 UV->addDef(Idx, MI.getOperand(0));
660 if (MI.getNumOperands() != 1 || !MI.getOperand(0).isMetadata()) {
778 Register DstReg = MI->getOperand(0).getReg();
824 unsigned LocNo = getLocationNo(CopyMI->getOperand(0));
lib/CodeGen/LiveRangeEdit.cpp 175 (*--MI).getOperand(0).setIsDead(false);
292 if (VRM && MI->getOperand(0).isReg() && MI->getOperand(0).isDef() &&
292 if (VRM && MI->getOperand(0).isReg() && MI->getOperand(0).isDef() &&
294 Dest = MI->getOperand(0).getReg();
351 const MachineOperand &MO = MI->getOperand(i-1);
371 MI->getOperand(0).setIsDead(true);
lib/CodeGen/LiveRangeShrink.cpp 234 if (MI.getOperand(0).isReg())
236 EndIter->getOperand(0).isReg() &&
237 EndIter->getOperand(0).getReg() == MI.getOperand(0).getReg();
237 EndIter->getOperand(0).getReg() == MI.getOperand(0).getReg();
lib/CodeGen/LiveVariables.cpp 215 MachineOperand &MO = LastDef->getOperand(i);
516 MachineOperand &MO = MI.getOperand(i);
551 HandleRegMask(MI.getOperand(RegMasks[i]));
691 MachineOperand &MO = MI.getOperand(i);
773 Defs.insert(BBI->getOperand(0).getReg());
777 if (BBI->getOperand(i+1).getMBB() == BB)
778 getVarInfo(BBI->getOperand(i).getReg()).AliveBlocks.set(NumNew);
lib/CodeGen/LocalStackSlotAllocation.cpp 321 if (MI.getOperand(i).isFI()) {
323 if (!MFI.isObjectPreAllocated(MI.getOperand(i).getIndex()))
325 int Idx = MI.getOperand(i).getIndex();
366 if (!MI.getOperand(idx).isFI())
369 if (FrameIdx == MI.getOperand(idx).getIndex())
lib/CodeGen/MIRCanonicalizerPass.cpp 169 MachineOperand &MO = II->getOperand(i);
189 MachineOperand &MO = II->getOperand(0);
198 if (II->getOperand(i).isImm()) {
202 if (II->getOperand(i).isReg()) {
203 if (!Register::isVirtualRegister(II->getOperand(i).getReg()))
204 if (llvm::find(PhysRegDefs, II->getOperand(i).getReg()) ==
318 if (!MI->getOperand(0).isReg())
320 if (!MI->getOperand(1).isReg())
323 const Register Dst = MI->getOperand(0).getReg();
324 const Register Src = MI->getOperand(1).getReg();
429 Register vRegToRename = MI.getOperand(0).getReg();
lib/CodeGen/MIRVRegNamerUtils.cpp 60 if (MI->getNumOperands() > 0 && MI->getOperand(0).isReg()) {
61 const Register Dst = MI->getOperand(0).getReg();
142 MachineOperand &MO = Def->getOperand(I);
278 MachineOperand &MO = candidate->getOperand(i);
293 MachineOperand &MO = candidate->getOperand(i);
lib/CodeGen/MachineBasicBlock.cpp 508 if (I->getOperand(1).getReg() == PhysReg) {
509 Register VirtReg = I->getOperand(0).getReg();
1030 if (I->getOperand(ni+1).getMBB() == NMBB) {
1031 MachineOperand &MO = I->getOperand(ni);
1207 if (I->getOperand(i).isMBB() &&
1208 I->getOperand(i).getMBB() == Old)
1209 I->getOperand(i).setMBB(New);
1220 MachineOperand &MO = MI.getOperand(i);
lib/CodeGen/MachineCSE.cpp 177 Register SrcReg = DefMI->getOperand(1).getReg();
180 if (DefMI->getOperand(0).getSubReg())
194 if (DefMI->getOperand(1).getSubReg())
595 MachineOperand &MO = MI->getOperand(i);
599 Register NewReg = CSMI->getOperand(i).getReg();
603 if (MO.isImplicit() && !MO.isDead() && CSMI->getOperand(i).isDead())
657 CSMI->getOperand(ImplicitDefToUpdate).setIsDead(false);
659 if (!MI->getOperand(PhysDef.first).isDead())
660 CSMI->getOperand(PhysDef.first).setIsDead(false);
825 assert(MI->getOperand(0).isDef() &&
827 Register VReg = MI->getOperand(0).getReg();
833 NewMI.getOperand(0).setReg(NewReg);
lib/CodeGen/MachineCopyPropagation.cpp 111 markRegsUnavailable({MI->getOperand(0).getReg()}, TRI);
122 Register Def = MI->getOperand(0).getReg();
123 Register Src = MI->getOperand(1).getReg();
161 !TRI.isSubRegisterEq(AvailCopy->getOperand(0).getReg(), Reg))
166 Register AvailSrc = AvailCopy->getOperand(1).getReg();
167 Register AvailDef = AvailCopy->getOperand(0).getReg();
293 if (PrevCopy->getOperand(0).isDead())
303 Register CopyDef = Copy.getOperand(0).getReg();
390 MachineOperand &MOUse = MI.getOperand(OpIdx);
413 Register CopyDstReg = Copy->getOperand(0).getReg();
414 const MachineOperand &CopySrc = Copy->getOperand(1);
469 if (MI->isCopy() && !TRI->regsOverlap(MI->getOperand(0).getReg(),
470 MI->getOperand(1).getReg())) {
471 Register Def = MI->getOperand(0).getReg();
472 Register Src = MI->getOperand(1).getReg();
499 Src = MI->getOperand(1).getReg();
586 Register Reg = MaybeDead->getOperand(0).getReg();
622 assert(!MRI->isReserved(MaybeDead->getOperand(0).getReg()));
626 unsigned SrcReg = MaybeDead->getOperand(1).getReg();
lib/CodeGen/MachineInstr.cpp 1051 MachineOperand &DefMO = getOperand(DefIdx);
1052 MachineOperand &UseMO = getOperand(UseIdx);
1793 MachineOperand &MO = getOperand(i);
1830 if (getOperand(OpIdx).isImplicit() &&
1834 getOperand(OpIdx).setIsKill(false);
1872 MachineOperand &MO = getOperand(i);
1895 if (getOperand(OpIdx).isImplicit() &&
1899 getOperand(OpIdx).setIsDead(false);
2099 Orig.getOperand(0).ChangeToFrameIndex(FrameIndex);
2100 Orig.getOperand(1).ChangeToImmediate(0U);
2101 Orig.getOperand(3).setMetadata(Expr);
2107 if (!MI.getOperand(0).isReg())
2115 if (DI->getOperand(0).isReg() &&
2116 DI->getOperand(0).getReg() == MI.getOperand(0).getReg())
2116 DI->getOperand(0).getReg() == MI.getOperand(0).getReg())
2125 if (!getOperand(0).isReg())
2128 unsigned DefReg = getOperand(0).getReg();
2134 if (DI->getOperand(0).isReg() &&
2135 DI->getOperand(0).getReg() == DefReg){
2142 DBI->getOperand(0).setReg(Reg);
lib/CodeGen/MachineInstrBundle.cpp 62 MachineOperand &MO = MII->getOperand(i);
149 MachineOperand &MO = MII->getOperand(i);
lib/CodeGen/MachineLICM.cpp 768 const MachineOperand &MO = I->getOperand(0);
1103 const MachineOperand &MO = UseMI.getOperand(i);
1130 MachineOperand &DefMO = MI.getOperand(i);
1224 const MachineOperand &MO = MI.getOperand(i);
1376 const MachineOperand &MO = MI->getOperand(i);
1392 Register Reg = MI->getOperand(Idx).getReg();
1405 Register Reg = MI->getOperand(Idx).getReg();
lib/CodeGen/MachineLoopUtils.cpp 82 if (MI.getOperand(2).getMBB() != Preheader)
89 Register R = MI.getOperand(LoopRegIdx).getReg();
92 OrigPhi.getOperand(InitRegIdx).setReg(R);
98 Register LoopReg = OrigPhi.getOperand(LoopRegIdx).getReg();
99 MI.getOperand(LoopRegIdx).setReg(LoopReg);
lib/CodeGen/MachinePipeliner.cpp 353 MachineOperand &DefOp = PI.getOperand(0);
358 MachineOperand &RegOp = PI.getOperand(i);
365 MachineBasicBlock &PredB = *PI.getOperand(i+1).getMBB();
588 if (Phi.getOperand(i + 1).getMBB() != Loop)
589 InitVal = Phi.getOperand(i).getReg();
591 LoopVal = Phi.getOperand(i).getReg();
599 if (Phi.getOperand(i + 1).getMBB() == LoopBB)
600 return Phi.getOperand(i).getReg();
824 if (PMI->getOperand(0).getReg() == HasPhiUse)
851 Register OrigBase = I.getInstr()->getOperand(BasePos).getReg();
2104 Register BaseReg = MI->getOperand(BasePosLd).getReg();
2130 int64_t LoadOffset = MI->getOperand(OffsetPosLd).getImm();
2131 int64_t StoreOffset = PrevDef->getOperand(OffsetPos1).getImm();
2133 NewMI->getOperand(OffsetPosLd).setImm(LoadOffset + StoreOffset);
2159 Register BaseReg = MI->getOperand(BasePos).getReg();
2169 NewMI->getOperand(BasePos).setReg(RegAndOffset.first);
2174 MI->getOperand(OffsetPos).getImm() + RegAndOffset.second * OffsetDiff;
2175 NewMI->getOperand(OffsetPos).setImm(NewOffset);
2193 if (Def->getOperand(i + 1).getMBB() == BB) {
2194 Def = MRI.getVRegDef(Def->getOperand(i).getReg());
2473 MachineOperand &MO = MI->getOperand(i);
2480 if (MI->getOperand(BasePos).getReg() == Reg)
2629 MachineOperand &DMO = Def->getOperand(i);
2766 const MachineOperand &MO = MI->getOperand(i);
2779 NewMI->getOperand(BasePos).setReg(NewBaseReg);
2781 MI->getOperand(OffsetPos).getImm() - It->second.second;
2782 NewMI->getOperand(OffsetPos).setImm(NewOffset);
2797 OverlapReg = MI->getOperand(TiedUseIdx).getReg();
2799 NewBaseReg = MI->getOperand(i).getReg();
lib/CodeGen/MachineRegisterInfo.cpp 136 unsigned OpNo = &MO - &MI->getOperand(0);
230 MachineOperand *MO0 = &MI->getOperand(0);
553 UseMI->getOperand(0).setReg(0U);
lib/CodeGen/MachineSSAUpdater.cpp 98 Register SrcReg = I->getOperand(i).getReg();
99 MachineBasicBlock *SrcBB = I->getOperand(i+1).getMBB();
106 return I->getOperand(0).getReg();
155 return NewDef->getOperand(0).getReg();
207 return InsertedPHI->getOperand(0).getReg();
267 unsigned getIncomingValue() { return PHI->getOperand(idx).getReg(); }
270 return PHI->getOperand(idx+1).getMBB();
298 return NewDef->getOperand(0).getReg();
309 return PHI->getOperand(0).getReg();
344 return PHI->getOperand(0).getReg();
lib/CodeGen/MachineScheduler.cpp 1691 const MachineOperand &SrcOp = Copy->getOperand(1);
1696 const MachineOperand &DstOp = Copy->getOperand(0);
lib/CodeGen/MachineSink.cpp 206 Register SrcReg = MI.getOperand(1).getReg();
207 Register DstReg = MI.getOperand(0).getReg();
267 unsigned OpNo = &MO - &UseInst->getOperand(0);
270 UseInst->getOperand(OpNo+1).getMBB() == DefMBB)) {
281 unsigned OpNo = &MO - &UseInst->getOperand(0);
286 UseBlock = UseInst->getOperand(OpNo+1).getMBB();
410 MachineOperand &MO = MI.getOperand(0);
439 const MachineOperand &MO = MI.getOperand(i);
638 const MachineOperand &MO = MI.getOperand(i);
799 MachineOperand DbgMO = DbgMI->getOperand(0);
800 DbgMI->getOperand(0).setReg(0);
831 DbgMI->getOperand(0).setReg(SrcMO->getReg());
832 DbgMI->getOperand(0).setSubReg(SrcMO->getSubReg());
879 const MachineOperand &MO = MI.getOperand(I);
986 assert(MI.getOperand(1).isReg());
1004 assert(User.getOperand(0).isReg() &&
1013 User->getOperand(0).setReg(MI.getOperand(1).getReg());
1013 User->getOperand(0).setReg(MI.getOperand(1).getReg());
1014 User->getOperand(0).setSubReg(MI.getOperand(1).getSubReg());
1014 User->getOperand(0).setSubReg(MI.getOperand(1).getSubReg());
1148 MachineOperand &MO = MI->getOperand(U);
1172 Register Reg = MI->getOperand(U).getReg();
1185 MachineOperand &MO = MI->getOperand(i);
1256 auto &MO = MI->getOperand(0);
1279 if (!MI->isCopy() || !MI->getOperand(0).isRenamable()) {
lib/CodeGen/ModuloSchedule.cpp 42 if (Phi.getOperand(i + 1).getMBB() != Loop)
43 InitVal = Phi.getOperand(i).getReg();
45 LoopVal = Phi.getOperand(i).getReg();
53 if (Phi.getOperand(i + 1).getMBB() != LoopBB)
54 return Phi.getOperand(i).getReg();
61 if (Phi.getOperand(i + 1).getMBB() == LoopBB)
62 return Phi.getOperand(i).getReg();
77 MachineOperand &Op = MI->getOperand(i);
385 Register Def = BBI->getOperand(0).getReg();
624 MachineOperand &MO = BBI->getOperand(i);
767 Register reg = MI->getOperand(0).getReg();
789 Register Def = PHI.getOperand(0).getReg();
837 if (MI.getOperand(i + 1).getMBB() == Incoming) {
985 const auto &MO = OldMI->getOperand(i);
1008 int64_t NewOffset = OldMI->getOperand(OffsetPos).getImm();
1012 NewMI->getOperand(OffsetPos).setImm(NewOffset);
1026 MachineOperand &MO = NewMI->getOperand(i);
1065 if (Def->getOperand(i + 1).getMBB() == BB) {
1066 Def = MRI.getVRegDef(Def->getOperand(i).getReg());
1114 Register PhiDef = PHI.getOperand(0).getReg();
1152 if (!Phi->isPHI() && UseMI->getOperand(0).getReg() == NewReg)
1224 if (MRI.use_empty(MI.getOperand(0).getReg())) {
1230 MRI.constrainRegClass(MI.getOperand(1).getReg(),
1231 MRI.getRegClass(MI.getOperand(0).getReg()));
1232 MRI.replaceRegWith(MI.getOperand(0).getReg(),
1233 MI.getOperand(1).getReg());
1334 Register R = MI->getOperand(0).getReg();
1473 MI->getOperand(1).setReg(InitReg.getValue());
1532 MO = &MI->getOperand(1);
1539 MO = &MI->getOperand(3);
1544 MO = MI->getOperand(2).getMBB() == BB ? &MI->getOperand(1)
1544 MO = MI->getOperand(2).getMBB() == BB ? &MI->getOperand(1)
1545 : &MI->getOperand(3);
1639 Register Reg = MI.getOperand(1).getReg();
1679 auto RC = MRI.getRegClass(MI.getOperand(0).getReg());
1680 Register OldR = MI.getOperand(3).getReg();
1716 return BlockMIs[{BB, CanonicalMIs[MI]}]->getOperand(OpIdx).getReg();
1723 Register PhiR = MI->getOperand(0).getReg();
1724 Register R = MI->getOperand(3).getReg();
1727 R = MI->getOperand(1).getReg();
1748 Register Reg = getEquivalentRegisterIn(UseMI.getOperand(0).getReg(),
lib/CodeGen/OptimizePHIs.cpp 100 Register DstReg = MI->getOperand(0).getReg();
112 Register SrcReg = MI->getOperand(i).getReg();
118 if (SrcMI && SrcMI->isCopy() && !SrcMI->getOperand(0).getSubReg() &&
119 !SrcMI->getOperand(1).getSubReg() &&
120 Register::isVirtualRegister(SrcMI->getOperand(1).getReg())) {
121 SrcReg = SrcMI->getOperand(1).getReg();
144 Register DstReg = MI->getOperand(0).getReg();
179 Register OldReg = MI->getOperand(0).getReg();
lib/CodeGen/PHIElimination.cpp 173 Register DefReg = DefMI->getOperand(0).getReg();
250 Register DestReg = MPhi->getOperand(0).getReg();
251 assert(MPhi->getOperand(0).getSubReg() == 0 && "Can't handle sub-reg PHIs");
252 bool isDead = MPhi->getOperand(0).isDead();
369 --VRegPHIUseCount[BBVRegPair(MPhi->getOperand(i+1).getMBB()->getNumber(),
370 MPhi->getOperand(i).getReg())];
376 Register SrcReg = MPhi->getOperand(i * 2 + 1).getReg();
377 unsigned SrcSubReg = MPhi->getOperand(i*2+1).getSubReg();
378 bool SrcUndef = MPhi->getOperand(i*2+1).isUndef() ||
385 MachineBasicBlock &opBlock = *MPhi->getOperand(i*2+2).getMBB();
575 Register Reg = BBI->getOperand(i).getReg();
576 MachineBasicBlock *PreMBB = BBI->getOperand(i+1).getMBB();
lib/CodeGen/PeepholeOptimizer.cpp 590 Copy->getOperand(0).setSubReg(SubIdx);
591 Copy->getOperand(0).setIsUndef();
772 MIB.addMBB(OrigPHI.getOperand(MBBOpIdx).getMBB());
844 const MachineOperand &MOSrc = CopyLike.getOperand(1);
847 const MachineOperand &MODef = CopyLike.getOperand(0);
855 MachineOperand &MOSrc = CopyLike.getOperand(CurrentSrcIdx);
882 while (CopyLike.getOperand(CurrentSrcIdx).isDead()) {
890 const MachineOperand &MODef = CopyLike.getOperand(CurrentSrcIdx);
927 const MachineOperand &MOInsertedReg = CopyLike.getOperand(2);
929 const MachineOperand &MODef = CopyLike.getOperand(0);
937 (unsigned)CopyLike.getOperand(3).getImm());
945 MachineOperand &MO = CopyLike.getOperand(CurrentSrcIdx);
974 const MachineOperand &MOExtractedReg = CopyLike.getOperand(1);
980 CopyLike.getOperand(2).getImm());
983 const MachineOperand &MODef = CopyLike.getOperand(0);
993 CopyLike.getOperand(CurrentSrcIdx).setReg(NewReg);
1009 CopyLike.getOperand(CurrentSrcIdx + 1).setImm(NewSubReg);
1050 const MachineOperand &MOInsertedReg = CopyLike.getOperand(CurrentSrcIdx);
1058 Dst.SubReg = CopyLike.getOperand(CurrentSrcIdx + 1).getImm();
1060 const MachineOperand &MODef = CopyLike.getOperand(0);
1072 MachineOperand &MO = CopyLike.getOperand(CurrentSrcIdx);
1149 const MachineOperand &MODef = NewPHI.getOperand(0);
1171 const MachineOperand &MODef = MI.getOperand(0);
1240 NewCopy->getOperand(0).setSubReg(Def.SubReg);
1241 NewCopy->getOperand(0).setIsUndef();
1318 Register Reg = MI.getOperand(0).getReg();
1322 if (!MI.getOperand(0).getSubReg() && Register::isVirtualRegister(Reg) &&
1338 Register Reg = MI.getOperand(0).getReg();
1355 MachineOperand &MO = MI.getOperand(i);
1395 Register SrcReg = MI.getOperand(1).getReg();
1399 Register DstReg = MI.getOperand(0).getReg();
1411 unsigned SrcSubReg = MI.getOperand(1).getSubReg();
1412 unsigned PrevSrcSubReg = PrevCopy->getOperand(1).getSubReg();
1418 Register PrevDstReg = PrevCopy->getOperand(0).getReg();
1445 Register DstReg = MI.getOperand(0).getReg();
1446 Register SrcReg = MI.getOperand(1).getReg();
1468 Register PrevDstReg = PrevCopy->second->getOperand(0).getReg();
1520 MachineOperand &DefOp = MI.getOperand(0);
1567 MachineOperand &MO = PHI.getOperand(Idx);
1574 if (findTargetRecurrence(PHI.getOperand(0).getReg(), TargetRegs, RC)) {
1758 const MachineOperand &MOp = MI->getOperand(i);
lib/CodeGen/ProcessImplicitDefs.cpp 76 Register Reg = MI->getOperand(0).getReg();
lib/CodeGen/PrologEpilogInserter.cpp 187 if (MI.getOperand(0).isFI()) {
324 unsigned ExtraInfo = I->getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1199 if (!MI.getOperand(i).isFI())
1209 unsigned FrameIdx = MI.getOperand(0).getIndex();
1214 MI.getOperand(0).ChangeToRegister(Reg, false /*isDef*/);
1215 MI.getOperand(0).setIsDebug();
1237 MI.getOperand(1).ChangeToRegister(0, false);
1240 MI.getOperand(3).setMetadata(DIExpr);
1254 MachineOperand &Offset = MI.getOperand(i + 1);
1256 MF, MI.getOperand(i).getIndex(), Reg, /*IgnoreSPUpdates*/ false);
1258 MI.getOperand(i).ChangeToRegister(Reg, false /*isDef*/);
lib/CodeGen/ReachingDefAnalysis.cpp 105 MachineOperand &MO = MI->getOperand(i);
lib/CodeGen/RegAllocFast.cpp 370 MachineOperand &MO = LR.LastUse->getOperand(LR.LastOpNum);
635 Reg = VRegDef->getOperand(1).getReg();
796 if (LRI->LastUse != &MI || LRI->LastUse->getOperand(LRI->LastOpNum).isUse())
816 MachineOperand &MO = MI.getOperand(OpNum);
920 MachineOperand &MO = MI.getOperand(I);
946 const MachineOperand &MO = MI.getOperand(I);
955 if (setPhysReg(MI, MI.getOperand(I), PhysReg))
1021 CopyDstReg = MI.getOperand(0).getReg();
1022 CopySrcReg = MI.getOperand(1).getReg();
1023 CopyDstSub = MI.getOperand(0).getSubReg();
1024 CopySrcSub = MI.getOperand(1).getSubReg();
1039 MachineOperand &MO = MI.getOperand(i);
1095 MachineOperand &MO = MI.getOperand(I);
1166 const MachineOperand &MO = MI.getOperand(I);
1179 const MachineOperand &MO = MI.getOperand(I);
1188 if (setPhysReg(MI, MI.getOperand(I), PhysReg)) {
1211 MachineOperand &MO = MI.getOperand(0);
lib/CodeGen/RegisterCoalescer.cpp 662 ValSEndInst->getOperand(UIdx).setIsKill(false);
804 MachineOperand &NewDstMO = DefMI->getOperand(NewDstIdx);
818 unsigned OpNo = &MO - &UseMI->getOperand(0);
888 if (UseMI->getOperand(0).getReg() != IntB.reg ||
889 UseMI->getOperand(0).getSubReg())
1066 if (DefMI->getOperand(0).getReg() != IntA.reg ||
1067 DefMI->getOperand(1).getReg() != IntB.reg ||
1242 MachineOperand &DstOperand = CopyMI->getOperand(0);
1261 DefMI->getOperand(0).getSubReg());
1292 MachineOperand &DefMO = NewMI.getOperand(0);
1316 MachineOperand &MO = CopyMI->getOperand(I);
1336 MachineOperand &MO = NewMI.getOperand(i);
1345 unsigned NewIdx = NewMI.getOperand(0).getSubReg();
1363 NewMI.getOperand(0).setSubReg(NewIdx);
1368 NewMI.getOperand(0).setIsUndef(false);
1386 CurrIdx.getRegSlot(NewMI.getOperand(0).isEarlyClobber());
1428 } else if (NewMI.getOperand(0).getReg() != CopyDstReg) {
1433 NewMI.getOperand(0).setIsDead(true);
1453 for (MCRegUnitIterator Units(NewMI.getOperand(0).getReg(), TRI);
1459 if (NewMI.getOperand(0).getSubReg())
1460 NewMI.getOperand(0).setIsUndef();
1554 MachineOperand &MO = CopyMI->getOperand(i-1);
1695 MachineOperand &MO = UseMI->getOperand(Ops[i]);
2414 Register SrcReg = MI->getOperand(1).getReg();
3192 Register Reg = MI->getOperand(1).getReg();
3463 if (Copy->getOperand(1).isUndef())
3466 Register SrcReg = Copy->getOperand(1).getReg();
3467 Register DstReg = Copy->getOperand(0).getReg();
lib/CodeGen/RegisterScavenging.cpp 452 while (!MI.getOperand(i).isFI()) {
lib/CodeGen/RenameIndependentSubregs.cpp 253 MI->getOperand(TiedIdx).setReg(VReg);
lib/CodeGen/ScheduleDAGInstrs.cpp 230 const MachineOperand &MO = SU->getInstr()->getOperand(OperIdx);
286 MachineOperand &MO = MI->getOperand(OperIdx);
390 MachineOperand &MO = MI->getOperand(OperIdx);
408 const MachineOperand &OtherMO = MI->getOperand(I);
838 const MachineOperand &MO = MI.getOperand(j);
851 const MachineOperand &MO = MI.getOperand(j);
lib/CodeGen/SelectionDAG/InstrEmitter.cpp 347 MIB->getOperand(Idx-1).isReg() &&
348 MIB->getOperand(Idx-1).isImplicit())
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp 572 bool hasFI = MI->getOperand(0).isFI();
574 hasFI ? TRI.getFrameRegister(*MF) : MI->getOperand(0).getReg();
600 assert(MI->getOperand(1).getImm() == 0 &&
628 CopyUseMI->getOperand(0).getReg(), Variable, Expr);
lib/CodeGen/StackSlotColoring.cpp 166 MachineOperand &MO = MI.getOperand(i);
400 MachineOperand &MO = MI.getOperand(i);
lib/CodeGen/TailDuplicator.cpp 107 MachineBasicBlock *PHIBB = MI->getOperand(i + 1).getMBB();
123 MachineBasicBlock *PHIBB = MI->getOperand(i + 1).getMBB();
238 Register Dst = Copy->getOperand(0).getReg();
239 Register Src = Copy->getOperand(1).getReg();
301 if (MI->getOperand(i + 1).getMBB() == SrcBB)
343 Register DefReg = MI->getOperand(0).getReg();
346 Register SrcReg = MI->getOperand(SrcOpIdx).getReg();
347 unsigned SrcSubReg = MI->getOperand(SrcOpIdx).getSubReg();
378 MI->getOperand(0).getCFIIndex());
384 MachineOperand &MO = NewMI.getOperand(i);
471 MachineOperand &MO = MI.getOperand(i + 1);
479 MachineOperand &MO0 = MI.getOperand(Idx);
486 MachineOperand &MO = MI.getOperand(i + 1);
513 MI.getOperand(Idx).setReg(SrcReg);
514 MI.getOperand(Idx + 1).setMBB(SrcBB);
525 MI.getOperand(Idx).setReg(Reg);
526 MI.getOperand(Idx + 1).setMBB(SrcBB);
643 MachineOperand &PU = I.getOperand(Idx);
lib/CodeGen/TargetInstrInfo.cpp 161 if (HasDef && !MI.getOperand(0).isReg())
170 assert(MI.getOperand(Idx1).isReg() && MI.getOperand(Idx2).isReg() &&
170 assert(MI.getOperand(Idx1).isReg() && MI.getOperand(Idx2).isReg() &&
173 Register Reg0 = HasDef ? MI.getOperand(0).getReg() : Register();
174 Register Reg1 = MI.getOperand(Idx1).getReg();
175 Register Reg2 = MI.getOperand(Idx2).getReg();
176 unsigned SubReg0 = HasDef ? MI.getOperand(0).getSubReg() : 0;
177 unsigned SubReg1 = MI.getOperand(Idx1).getSubReg();
178 unsigned SubReg2 = MI.getOperand(Idx2).getSubReg();
179 bool Reg1IsKill = MI.getOperand(Idx1).isKill();
180 bool Reg2IsKill = MI.getOperand(Idx2).isKill();
181 bool Reg1IsUndef = MI.getOperand(Idx1).isUndef();
182 bool Reg2IsUndef = MI.getOperand(Idx2).isUndef();
183 bool Reg1IsInternal = MI.getOperand(Idx1).isInternalRead();
184 bool Reg2IsInternal = MI.getOperand(Idx2).isInternalRead();
188 ? MI.getOperand(Idx1).isRenamable()
191 ? MI.getOperand(Idx2).isRenamable()
217 CommutedMI->getOperand(0).setReg(Reg0);
218 CommutedMI->getOperand(0).setSubReg(SubReg0);
220 CommutedMI->getOperand(Idx2).setReg(Reg1);
221 CommutedMI->getOperand(Idx1).setReg(Reg2);
222 CommutedMI->getOperand(Idx2).setSubReg(SubReg1);
223 CommutedMI->getOperand(Idx1).setSubReg(SubReg2);
224 CommutedMI->getOperand(Idx2).setIsKill(Reg1IsKill);
225 CommutedMI->getOperand(Idx1).setIsKill(Reg2IsKill);
226 CommutedMI->getOperand(Idx2).setIsUndef(Reg1IsUndef);
227 CommutedMI->getOperand(Idx1).setIsUndef(Reg2IsUndef);
228 CommutedMI->getOperand(Idx2).setIsInternalRead(Reg1IsInternal);
229 CommutedMI->getOperand(Idx1).setIsInternalRead(Reg2IsInternal);
233 CommutedMI->getOperand(Idx2).setIsRenamable(Reg1IsRenamable);
235 CommutedMI->getOperand(Idx1).setIsRenamable(Reg2IsRenamable);
333 MachineOperand &MO = MI.getOperand(i);
414 MI->substituteRegister(MI->getOperand(0).getReg(), DestReg, SubIdx, TRI);
506 MIB.add(MI.getOperand(i));
509 MachineOperand &MO = MI.getOperand(i);
537 Flags |= MI.getOperand(OpIdx).isDef() ? MachineMemOperand::MOStore
557 if (auto SubReg = MI.getOperand(OpIdx).getSubReg()) {
609 const MachineOperand &MO = MI.getOperand(1 - Ops[0]);
626 assert(MI.getOperand(OpIdx).isUse() && "Folding load into def!");
706 MRI.hasOneNonDBGUse(MI1->getOperand(0).getReg());
802 MachineOperand &OpA = Prev.getOperand(OpIdx[Row][0]);
803 MachineOperand &OpB = Root.getOperand(OpIdx[Row][1]);
804 MachineOperand &OpX = Prev.getOperand(OpIdx[Row][2]);
805 MachineOperand &OpY = Root.getOperand(OpIdx[Row][3]);
806 MachineOperand &OpC = Root.getOperand(0);
867 Prev = MRI.getUniqueVRegDef(Root.getOperand(1).getReg());
871 Prev = MRI.getUniqueVRegDef(Root.getOperand(2).getReg());
lib/CodeGen/TargetLoweringBase.cpp 1039 MachineOperand &MO = MI->getOperand(OperIdx);
1050 MIB.add(MI->getOperand(i));
1060 MIB.add(MI->getOperand(OperIdx));
1066 MIB.add(MI->getOperand(OperIdx));
1071 MIB.add(MI->getOperand(i));
1107 MIB.add(MI.getOperand(OpIdx));
1122 MIB.add(MI.getOperand(OpIdx));
lib/CodeGen/TwoAddressInstructionPass.cpp 299 MachineOperand &MO = OtherMI.getOperand(i);
372 TmpReg = Def->getOperand(1).getReg();
413 DstReg = MI.getOperand(0).getReg();
414 SrcReg = MI.getOperand(1).getReg();
416 DstReg = MI.getOperand(0).getReg();
417 SrcReg = MI.getOperand(2).getReg();
504 const MachineOperand &MO = MI.getOperand(i);
509 DstReg = MI.getOperand(ti).getReg();
685 Register RegC = MI->getOperand(RegCIdx).getReg();
702 Register RegA = MI->getOperand(DstIdx).getReg();
932 if (End->isCopy() && regOverlapsSet(Defs, End->getOperand(1).getReg(), TRI))
933 Defs.push_back(End->getOperand(0).getReg());
1209 Register DstOpReg = MI->getOperand(DstOpIdx).getReg();
1210 Register BaseOpReg = MI->getOperand(BaseOpIdx).getReg();
1218 if (OtherOpIdx == BaseOpIdx || !MI->getOperand(OtherOpIdx).isReg() ||
1222 Register OtherOpReg = MI->getOperand(OtherOpIdx).getReg();
1277 Register regA = MI.getOperand(DstIdx).getReg();
1278 Register regB = MI.getOperand(SrcIdx).getReg();
1313 regB = MI.getOperand(SrcIdx).getReg();
1394 if (NewMIs[1]->getOperand(NewSrcIdx).isKill()) {
1399 MachineOperand &MO = MI.getOperand(i);
1472 MachineOperand &SrcMO = MI->getOperand(SrcIdx);
1473 MachineOperand &DstMO = MI->getOperand(DstIdx);
1507 const MachineOperand &DstMO = MI->getOperand(TiedPairs[tpi].second);
1521 const MachineOperand &DstMO = MI->getOperand(DstIdx);
1526 RegB = MI->getOperand(SrcIdx).getReg();
1527 SubRegB = MI->getOperand(SrcIdx).getSubReg();
1547 !MI->getOperand(i).isReg() ||
1548 MI->getOperand(i).getReg() != RegA);
1591 MachineOperand &MO = MI->getOperand(SrcIdx);
1742 Register SrcReg = mi->getOperand(SrcIdx).getReg();
1743 Register DstReg = mi->getOperand(DstIdx).getReg();
1765 unsigned SubIdx = mi->getOperand(3).getImm();
1767 assert(mi->getOperand(0).getSubReg() == 0 && "Unexpected subreg idx");
1768 mi->getOperand(0).setSubReg(SubIdx);
1769 mi->getOperand(0).setIsUndef(mi->getOperand(1).isUndef());
1769 mi->getOperand(0).setIsUndef(mi->getOperand(1).isUndef());
1801 Register DstReg = MI.getOperand(0).getReg();
1802 if (MI.getOperand(0).getSubReg() || Register::isPhysicalRegister(DstReg) ||
1810 OrigRegs.push_back(MI.getOperand(0).getReg());
1812 OrigRegs.push_back(MI.getOperand(i).getReg());
1817 MachineOperand &UseMO = MI.getOperand(i);
1819 unsigned SubIdx = MI.getOperand(i+1).getImm();
1829 if (MI.getOperand(j).getReg() == SrcReg) {
1830 MI.getOperand(j).setIsKill();
1845 CopyMI->getOperand(0).setIsUndef(true);
lib/CodeGen/UnreachableBlockElim.cpp 135 if (start->getOperand(i).isMBB() &&
136 start->getOperand(i).getMBB() == BB) {
168 if (!preds.count(phi->getOperand(i).getMBB())) {
175 const MachineOperand &Input = phi->getOperand(1);
176 const MachineOperand &Output = phi->getOperand(0);
lib/CodeGen/VirtRegMap.cpp 386 if (MI.getOperand(1).isUndef() || MI.getNumOperands() > 2) {
lib/Target/AArch64/AArch64A53Fix835769.cpp 69 return MI->getOperand(3).getReg() != AArch64::XZR;
lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp 574 MachineOperand &MO = I.getOperand(0);
614 Register DestReg = MI->getOperand(0).getReg();
627 Register DestReg = MI->getOperand(0).getReg();
628 Register AccumReg = MI->getOperand(3).getReg();
630 maybeKillChain(MI->getOperand(1), Idx, ActiveChains);
631 maybeKillChain(MI->getOperand(2), Idx, ActiveChains);
633 maybeKillChain(MI->getOperand(0), Idx, ActiveChains);
644 if (MI->getOperand(3).isKill()) {
659 maybeKillChain(MI->getOperand(3), Idx, ActiveChains);
lib/Target/AArch64/AArch64AdvSIMDScalarPass.cpp 134 return &MI->getOperand(1);
137 if (MI->getOpcode() == AArch64::UMOVvi64 && MI->getOperand(2).getImm() == 0) {
139 return &MI->getOperand(1);
144 if (isFPR64(MI->getOperand(0).getReg(), MI->getOperand(0).getSubReg(),
144 if (isFPR64(MI->getOperand(0).getReg(), MI->getOperand(0).getSubReg(),
146 isGPR64(MI->getOperand(1).getReg(), MI->getOperand(1).getSubReg(), MRI))
146 isGPR64(MI->getOperand(1).getReg(), MI->getOperand(1).getSubReg(), MRI))
147 return &MI->getOperand(1);
148 if (isGPR64(MI->getOperand(0).getReg(), MI->getOperand(0).getSubReg(),
148 if (isGPR64(MI->getOperand(0).getReg(), MI->getOperand(0).getSubReg(),
150 isFPR64(MI->getOperand(1).getReg(), MI->getOperand(1).getSubReg(),
150 isFPR64(MI->getOperand(1).getReg(), MI->getOperand(1).getSubReg(),
152 SubReg = MI->getOperand(1).getSubReg();
153 return &MI->getOperand(1);
296 Register OrigSrc0 = MI.getOperand(1).getReg();
297 Register OrigSrc1 = MI.getOperand(2).getReg();
369 insertCopy(TII, MI, MI.getOperand(0).getReg(), Dst, true);
lib/Target/AArch64/AArch64CallLowering.cpp 181 ->getOperand(0)
649 Register CopyRHS = RegDef->getOperand(1).getReg();
896 MIB->getOperand(1).setImm(FPDiff);
911 MIB->getOperand(0).setReg(constrainOperandRegClass(
997 MIB->getOperand(0).setReg(constrainOperandRegClass(
lib/Target/AArch64/AArch64CleanupLocalDynamicTLSPass.cpp 72 if (!I->getOperand(0).isSymbol() ||
73 strcmp(I->getOperand(0).getSymbolName(), "_TLS_MODULE_BASE_"))
lib/Target/AArch64/AArch64CompressJumpTables.cpp 89 int JTIdx = MI.getOperand(4).getIndex();
lib/Target/AArch64/AArch64CondBrTuning.cpp 93 MachineOperand &MO = MI.getOperand(I);
101 Register NewDestReg = MI.getOperand(0).getReg();
102 if (MRI->hasOneNonDBGUse(MI.getOperand(0).getReg()))
108 MIB.add(MI.getOperand(I));
192 MI.getOperand(1).getImm() != 31)
252 MI.getOperand(1).getImm() != 63)
321 MachineInstr *DefMI = getOperandDef(MI.getOperand(0));
lib/Target/AArch64/AArch64ConditionOptimizer.cpp 173 unsigned ShiftAmt = AArch64_AM::getShiftValue(I->getOperand(3).getImm());
174 if (!I->getOperand(2).isImm()) {
177 } else if (I->getOperand(2).getImm() << ShiftAmt >= 0xfff) {
181 } else if (!MRI->use_empty(I->getOperand(0).getReg())) {
255 const int OldImm = (int)CmpMI->getOperand(2).getImm();
280 .add(CmpMI->getOperand(0))
281 .add(CmpMI->getOperand(1))
283 .add(CmpMI->getOperand(3));
293 .add(BrMI.getOperand(1));
385 const int HeadImm = (int)HeadCmpMI->getOperand(2).getImm();
386 const int TrueImm = (int)TrueCmpMI->getOperand(2).getImm();
lib/Target/AArch64/AArch64ConditionalCompares.cpp 222 MachineBasicBlock *MBB = I.getOperand(oi + 1).getMBB();
223 Register Reg = I.getOperand(oi).getReg();
248 if (I.getOperand(oi - 1).getMBB() == CmpBB) {
330 if (I->getOperand(3).getImm() || !isUInt<5>(I->getOperand(2).getImm())) {
330 if (I->getOperand(3).getImm() || !isUInt<5>(I->getOperand(2).getImm())) {
340 if (isDeadDef(I->getOperand(0).getReg()))
690 MRI->constrainRegClass(CmpMI->getOperand(FirstOp).getReg(),
692 if (CmpMI->getOperand(FirstOp + 1).isReg())
693 MRI->constrainRegClass(CmpMI->getOperand(FirstOp + 1).getReg(),
696 .add(CmpMI->getOperand(FirstOp)); // Register Rn
700 MIB.add(CmpMI->getOperand(FirstOp + 1)); // Register Rm / Immediate
710 .add(CmpMI->getOperand(1)); // Branch target.
lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp 143 MachineOperand &MO = MI.getOperand(I);
lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp 97 const MachineOperand &MO = OldMI.getOperand(i);
112 Register DstReg = MI.getOperand(0).getReg();
113 uint64_t Imm = MI.getOperand(1).getImm();
136 .add(MI.getOperand(0))
144 bool DstIsDead = MI.getOperand(0).isDead();
153 Register DstReg = MI.getOperand(0).getReg();
154 bool DstIsDead = MI.getOperand(0).isDead();
176 const MachineOperand &Dest = MI.getOperand(0);
177 Register StatusReg = MI.getOperand(1).getReg();
178 bool StatusDead = MI.getOperand(1).isDead();
181 assert(!MI.getOperand(2).isUndef() && "cannot handle undef");
182 Register AddrReg = MI.getOperand(2).getReg();
183 Register DesiredReg = MI.getOperand(3).getReg();
184 Register NewReg = MI.getOperand(4).getReg();
255 MachineOperand &DestLo = MI.getOperand(0);
256 MachineOperand &DestHi = MI.getOperand(1);
257 Register StatusReg = MI.getOperand(2).getReg();
258 bool StatusDead = MI.getOperand(2).isDead();
261 assert(!MI.getOperand(3).isUndef() && "cannot handle undef");
262 Register AddrReg = MI.getOperand(3).getReg();
263 Register DesiredLoReg = MI.getOperand(4).getReg();
264 Register DesiredHiReg = MI.getOperand(5).getReg();
265 Register NewLoReg = MI.getOperand(6).getReg();
266 Register NewHiReg = MI.getOperand(7).getReg();
348 Register SizeReg = MI.getOperand(2).getReg();
349 Register AddressReg = MI.getOperand(3).getReg();
467 MI.getOperand(0).getReg())
468 .add(MI.getOperand(1))
469 .add(MI.getOperand(2))
478 Register DstReg = MI.getOperand(0).getReg();
479 const MachineOperand &MO1 = MI.getOperand(1);
507 unsigned DstFlags = MI.getOperand(0).getTargetFlags();
513 unsigned DstReg = MI.getOperand(0).getReg();
515 .add(MI.getOperand(0))
551 Register DstReg = MI.getOperand(0).getReg();
554 .add(MI.getOperand(1));
556 if (MI.getOperand(1).getTargetFlags() & AArch64II::MO_TAGGED) {
564 auto Tag = MI.getOperand(1);
575 .add(MI.getOperand(0))
577 .add(MI.getOperand(2))
587 .add(MI.getOperand(0))
588 .add(MI.getOperand(1))
589 .add(MI.getOperand(2))
595 Register DstReg = MI.getOperand(0).getReg();
659 .add(MI.getOperand(0))
660 .add(MI.getOperand(1));
683 SrcReg = MI.getOperand(0).getReg();
688 .add(MI.getOperand(0))
690 .add(MI.getOperand(2));
696 .add(MI.getOperand(0))
697 .add(MI.getOperand(1))
698 .add(MI.getOperand(2))
699 .add(MI.getOperand(4));
lib/Target/AArch64/AArch64FalkorHWPFFix.cpp 745 MachineOperand &MO = MI.getOperand(OpI);
774 MachineOperand &BaseOpnd = MI.getOperand(LdI.BaseRegIdx);
782 MI.getOperand(0).setReg(
lib/Target/AArch64/AArch64FastISel.cpp 2053 ResultReg = std::prev(I)->getOperand(0).getReg();
4545 Register LoadReg = MI->getOperand(1).getReg();
4568 MI->getOperand(1).getSubReg() == AArch64::sub_32) &&
4570 Reg = MI->getOperand(1).getReg();
lib/Target/AArch64/AArch64FrameLowering.cpp 281 uint64_t CalleePopAmount = IsDestroy ? I->getOperand(1).getImm() : 0;
286 int64_t Amount = I->getOperand(0).getImm();
491 int Imm = MBBI->getOperand(ImmIdx).getImm();
503 unsigned Reg0 = RegInfo->getSEHRegNum(MBBI->getOperand(1).getReg());
504 unsigned Reg1 = RegInfo->getSEHRegNum(MBBI->getOperand(2).getReg());
516 Register Reg0 = MBBI->getOperand(1).getReg();
517 Register Reg1 = MBBI->getOperand(2).getReg();
534 unsigned Reg = RegInfo->getSEHRegNum(MBBI->getOperand(1).getReg());
545 unsigned Reg = RegInfo->getSEHRegNum(MBBI->getOperand(1).getReg());
554 unsigned Reg0 = RegInfo->getSEHRegNum(MBBI->getOperand(0).getReg());
555 unsigned Reg1 = RegInfo->getSEHRegNum(MBBI->getOperand(1).getReg());
565 Register Reg0 = MBBI->getOperand(0).getReg();
566 Register Reg1 = MBBI->getOperand(1).getReg();
581 int Reg = RegInfo->getSEHRegNum(MBBI->getOperand(0).getReg());
590 unsigned Reg = RegInfo->getSEHRegNum(MBBI->getOperand(0).getReg());
615 ImmOpnd = &MBBI->getOperand(ImmIdx);
635 assert(MBBI->getOperand(0).getReg() != AArch64::SP);
700 MIB.add(MBBI->getOperand(OpndIdx));
702 assert(MBBI->getOperand(OpndIdx).getImm() == 0 &&
705 assert(MBBI->getOperand(OpndIdx - 1).getReg() == AArch64::SP &&
739 assert(MI.getOperand(0).getReg() != AArch64::SP);
766 assert(MI.getOperand(OffsetIdx - 1).getReg() == AArch64::SP &&
769 MachineOperand &OffsetOpnd = MI.getOperand(OffsetIdx);
1359 MachineOperand &StackAdjust = MBBI->getOperand(1);
1426 const MachineOperand &OffsetOp = Pop->getOperand(Pop->getNumOperands() - 1);
1547 Prev->getOperand(0).getReg() == AArch64::SP)
lib/Target/AArch64/AArch64ISelLowering.cpp 1342 Register DestReg = MI.getOperand(0).getReg();
1343 Register IfTrueReg = MI.getOperand(1).getReg();
1344 Register IfFalseReg = MI.getOperand(2).getReg();
1345 unsigned CondCode = MI.getOperand(3).getImm();
1346 bool NZCVKilled = MI.getOperand(4).isKill();
lib/Target/AArch64/AArch64InstrInfo.cpp 133 Target = LastInst->getOperand(1).getMBB();
134 Cond.push_back(LastInst->getOperand(0));
140 Target = LastInst->getOperand(1).getMBB();
143 Cond.push_back(LastInst->getOperand(0));
149 Target = LastInst->getOperand(2).getMBB();
152 Cond.push_back(LastInst->getOperand(0));
153 Cond.push_back(LastInst->getOperand(1));
228 TBB = LastInst->getOperand(0).getMBB();
252 TBB = LastInst->getOperand(0).getMBB();
268 FBB = LastInst->getOperand(0).getMBB();
275 TBB = SecondLastInst->getOperand(0).getMBB();
1058 MachineOperand &MO = Instr.getOperand(OpIdx);
1216 if (!MRI->use_nodbg_empty(CmpInstr.getOperand(0).getReg()))
1482 MachineBasicBlock *TargetMBB = MI.getOperand(0).getMBB();
1501 Register Reg = MI.getOperand(0).getReg();
2038 MachineOperand &OfsOp = LdSt.getOperand(LdSt.getNumExplicitOperands() - 1);
3195 Register DstReg = MI.getOperand(0).getReg();
3196 Register SrcReg = MI.getOperand(1).getReg();
3239 const MachineOperand &DstMO = MI.getOperand(0);
3240 const MachineOperand &SrcMO = MI.getOperand(1);
3342 MachineOperand &LoadDst = LoadMI.getOperand(0);
3465 Offset += StackOffset(MI.getOperand(ImmIdx).getImm(), MVT::i8);
3467 MI.getOperand(0).getReg(), FrameReg, Offset, TII,
3482 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
3486 MI.getOperand(ImmIdx).ChangeToImmediate(NewOffset);
3606 if (!MRI.hasOneNonDBGUse(MI->getOperand(0).getReg()))
3610 assert(MI->getNumOperands() >= 4 && MI->getOperand(0).isReg() &&
3611 MI->getOperand(1).isReg() && MI->getOperand(2).isReg() &&
3611 MI->getOperand(1).isReg() && MI->getOperand(2).isReg() &&
3612 MI->getOperand(3).isReg() && "MAdd/MSub must have a least 4 regs");
3614 if (MI->getOperand(3).getReg() != ZeroReg)
3687 if (canCombineWithMUL(MBB, Root.getOperand(Operand), Opcode, ZeroReg)) {
3699 assert(Root.getOperand(1).isReg() && Root.getOperand(2).isReg() &&
3699 assert(Root.getOperand(1).isReg() && Root.getOperand(2).isReg() &&
3745 if (canCombineWithFMUL(MBB, Root.getOperand(Operand), Opcode)) {
3759 assert(Root.getOperand(1).isReg() && Root.getOperand(2).isReg() &&
3759 assert(Root.getOperand(1).isReg() && Root.getOperand(2).isReg() &&
3766 assert(Root.getOperand(1).isReg() && Root.getOperand(2).isReg() &&
3766 assert(Root.getOperand(1).isReg() && Root.getOperand(2).isReg() &&
3992 MachineInstr *MUL = MRI.getUniqueVRegDef(Root.getOperand(IdxMulOpd).getReg());
3993 Register ResultReg = Root.getOperand(0).getReg();
3994 Register SrcReg0 = MUL->getOperand(1).getReg();
3995 bool Src0IsKill = MUL->getOperand(1).isKill();
3996 Register SrcReg1 = MUL->getOperand(2).getReg();
3997 bool Src1IsKill = MUL->getOperand(2).isKill();
4006 SrcReg2 = Root.getOperand(IdxOtherOpd).getReg();
4007 Src2IsKill = Root.getOperand(IdxOtherOpd).isKill();
4030 .addImm(MUL->getOperand(3).getImm());
4069 MachineInstr *MUL = MRI.getUniqueVRegDef(Root.getOperand(IdxMulOpd).getReg());
4070 Register ResultReg = Root.getOperand(0).getReg();
4071 Register SrcReg0 = MUL->getOperand(1).getReg();
4072 bool Src0IsKill = MUL->getOperand(1).isKill();
4073 Register SrcReg1 = MUL->getOperand(2).getReg();
4074 bool Src1IsKill = MUL->getOperand(2).isKill();
4172 uint64_t Imm = Root.getOperand(2).getImm();
4174 if (Root.getOperand(3).isImm()) {
4175 unsigned Val = Root.getOperand(3).getImm();
4218 .add(Root.getOperand(2));
4264 uint64_t Imm = Root.getOperand(2).getImm();
4265 if (Root.getOperand(3).isImm()) {
4266 unsigned Val = Root.getOperand(3).getImm();
4541 .add(Root.getOperand(2));
4588 .add(Root.getOperand(2));
4648 .add(Root.getOperand(2));
4668 .add(Root.getOperand(2));
4688 .add(Root.getOperand(2));
4778 if (IsTestAndBranch && MI.getOperand(1).getImm())
4786 Register VReg = MI.getOperand(0).getReg();
4794 Register CopyVReg = DefMI->getOperand(1).getReg();
4817 DefMI->getOperand(2).getImm(), Is32Bit ? 32 : 64);
4821 MachineOperand &MO = DefMI->getOperand(1);
4829 MachineBasicBlock *TBB = MI.getOperand(1).getMBB();
4848 NewMI->getOperand(0).setSubReg(AArch64::sub_32);
4855 if (!(DefMI->getOperand(1).getReg() == AArch64::WZR &&
4856 DefMI->getOperand(2).getReg() == AArch64::WZR) &&
4857 !(DefMI->getOperand(1).getReg() == AArch64::XZR &&
4858 DefMI->getOperand(2).getReg() == AArch64::XZR))
4864 AArch64CC::CondCode CC = (AArch64CC::CondCode)DefMI->getOperand(3).getImm();
4871 MachineBasicBlock *TBB = MI.getOperand(TargetBBInMI).getMBB();
5494 int64_t Imm = MI.getOperand(0).getImm();
5546 .add(Call->getOperand(0))
lib/Target/AArch64/AArch64InstructionSelector.cpp 601 MachineOperand &RegOp = I.getOperand(1);
606 if (!Register::isPhysicalRegister(I.getOperand(0).getReg()))
607 RBI.constrainGenericRegister(I.getOperand(0).getReg(), *To, MRI);
620 Register DstReg = I.getOperand(0).getReg();
621 Register SrcReg = I.getOperand(1).getReg();
646 Register DstReg = I.getOperand(0).getReg();
647 Register SrcReg = I.getOperand(1).getReg();
675 (!Register::isPhysicalRegister(I.getOperand(0).getReg()) &&
676 !Register::isPhysicalRegister(I.getOperand(1).getReg()))) &&
730 MachineOperand &RegOp = I.getOperand(1);
834 bool IsFP = (RBI.getRegBank(I.getOperand(0).getReg(), MRI, TRI)->getID() !=
836 LLT Ty = MRI.getType(I.getOperand(0).getReg());
848 const ConstantFP *FPImm = getConstantFPVRegVal(I.getOperand(3).getReg(), MRI);
850 unsigned OpSize = MRI.getType(I.getOperand(2).getReg()).getSizeInBits();
955 const Register CondReg = I.getOperand(0).getReg();
956 MachineBasicBlock *DestMBB = I.getOperand(1).getMBB();
959 CCMI = MRI.getVRegDef(CCMI->getOperand(1).getReg());
963 Register LHS = CCMI->getOperand(2).getReg();
964 Register RHS = CCMI->getOperand(3).getReg();
973 if (!emitIntegerCompare(CCMI->getOperand(2), CCMI->getOperand(3),
973 if (!emitIntegerCompare(CCMI->getOperand(2), CCMI->getOperand(3),
974 CCMI->getOperand(1), MIB))
977 (CmpInst::Predicate)CCMI->getOperand(1).getPredicate());
987 const auto Pred = (CmpInst::Predicate)CCMI->getOperand(1).getPredicate();
1012 Register DstReg = I.getOperand(0).getReg();
1014 Register Src1Reg = I.getOperand(1).getReg();
1015 Register Src2Reg = I.getOperand(2).getReg();
1042 Register DstReg = I.getOperand(0).getReg();
1044 Register Src1Reg = I.getOperand(1).getReg();
1045 Register Src2Reg = I.getOperand(2).getReg();
1091 Register ListReg = I.getOperand(0).getReg();
1123 MovZ->addOperand(MF, I.getOperand(1));
1124 MovZ->getOperand(1).setTargetFlags(OpFlags | AArch64II::MO_G0 |
1137 GV, MovZ->getOperand(1).getOffset(), Flags));
1141 MovZ->getOperand(1).getOffset(), Flags));
1150 BuildMovK(DstReg, AArch64II::MO_G3, 48, I.getOperand(0).getReg());
1169 Register SrcReg = I.getOperand(1).getReg();
1170 Register ShiftReg = I.getOperand(2).getReg();
1186 I.getOperand(2).setReg(Trunc.getReg(0));
1204 const auto &MO = I.getOperand(2);
1209 const LLT DstTy = MRI.getType(I.getOperand(0).getReg());
1222 {I.getOperand(0).getReg()}, {I.getOperand(1).getReg()});
1222 {I.getOperand(0).getReg()}, {I.getOperand(1).getReg()});
1250 MachineInstr *Def = getDefIgnoringCopies(I.getOperand(0).getReg(), MRI);
1253 Register DefDstReg = Def->getOperand(0).getReg();
1255 Register StoreSrcReg = I.getOperand(0).getReg();
1272 I.getOperand(0).setReg(DefDstReg);
1288 if (I.getOperand(1).isCImm())
1289 IsZero = I.getOperand(1).getCImm()->getZExtValue() == 0;
1290 else if (I.getOperand(1).isImm())
1291 IsZero = I.getOperand(1).getImm() == 0;
1296 Register DefReg = I.getOperand(0).getReg();
1302 I.getOperand(1).ChangeToRegister(AArch64::XZR, false);
1305 I.getOperand(1).ChangeToRegister(AArch64::WZR, false);
1333 const Register DefReg = I.getOperand(0).getReg();
1389 I.getOperand(0).isReg() ? MRI.getType(I.getOperand(0).getReg()) : LLT{};
1389 I.getOperand(0).isReg() ? MRI.getType(I.getOperand(0).getReg()) : LLT{};
1404 const Register CondReg = I.getOperand(0).getReg();
1405 MachineBasicBlock *DestMBB = I.getOperand(1).getMBB();
1449 Register DstReg = I.getOperand(0).getReg();
1494 const Register DefReg = I.getOperand(0).getReg();
1517 if (I.getOperand(1).getFPImm()->getValueAPF().isExactlyValue(0.0))
1553 MachineOperand &RegOp = I.getOperand(0);
1563 MachineOperand &ImmOp = I.getOperand(1);
1567 } else if (I.getOperand(1).isCImm()) {
1568 uint64_t Val = I.getOperand(1).getCImm()->getZExtValue();
1569 I.getOperand(1).ChangeToImmediate(Val);
1570 } else if (I.getOperand(1).isImm()) {
1571 uint64_t Val = I.getOperand(1).getImm();
1572 I.getOperand(1).ChangeToImmediate(Val);
1580 Register DstReg = I.getOperand(0).getReg();
1581 Register SrcReg = I.getOperand(1).getReg();
1605 unsigned Offset = I.getOperand(2).getImm();
1619 MachineInstrBuilder(MF, I).addImm(I.getOperand(2).getImm() +
1630 MIB.buildInstr(TargetOpcode::COPY, {I.getOperand(0).getReg()}, {})
1632 RBI.constrainGenericRegister(I.getOperand(0).getReg(),
1634 I.getOperand(0).setReg(DstReg);
1640 LLT SrcTy = MRI.getType(I.getOperand(2).getReg());
1641 LLT DstTy = MRI.getType(I.getOperand(0).getReg());
1649 unsigned LSB = I.getOperand(3).getImm();
1650 unsigned Width = MRI.getType(I.getOperand(2).getReg()).getSizeInBits();
1651 I.getOperand(3).setImm((DstSize - LSB) % DstSize);
1665 .addUse(I.getOperand(2).getReg())
1667 RBI.constrainGenericRegister(I.getOperand(2).getReg(),
1669 I.getOperand(2).setReg(SrcReg);
1690 auto GV = I.getOperand(1).getGlobal();
1697 I.getOperand(1).setTargetFlags(OpFlags);
1705 I.getOperand(1).setTargetFlags(OpFlags);
1708 I.getOperand(1).setTargetFlags(OpFlags | AArch64II::MO_PAGE);
1710 MIB.addGlobalAddress(GV, I.getOperand(1).getOffset(),
1722 LLT PtrTy = MRI.getType(I.getOperand(1).getReg());
1744 const Register PtrReg = I.getOperand(1).getReg();
1754 const Register ValReg = I.getOperand(0).getReg();
1769 if (auto COff = getConstantVRegVal(PtrMI->getOperand(2).getReg(), MRI)) {
1774 Register Ptr2Reg = PtrMI->getOperand(1).getReg();
1775 I.getOperand(1).setReg(Ptr2Reg);
1785 I.getOperand(1).ChangeToFrameIndex(PtrMI->getOperand(1).getIndex());
1785 I.getOperand(1).ChangeToFrameIndex(PtrMI->getOperand(1).getIndex());
1793 I.getOperand(0).setReg(AArch64::WZR);
1795 I.getOperand(0).setReg(AArch64::XZR);
1806 Register DstReg = I.getOperand(0).getReg();
1807 I.getOperand(0).setReg(LdReg);
1827 const Register DefReg = I.getOperand(0).getReg();
1855 if (MRI.getType(I.getOperand(0).getReg()).isVector())
1860 MRI.getType(I.getOperand(0).getReg()).isVector())
1871 const Register DefReg = I.getOperand(0).getReg();
1888 emitADD(I.getOperand(0).getReg(), I.getOperand(1), I.getOperand(2),
1888 emitADD(I.getOperand(0).getReg(), I.getOperand(1), I.getOperand(2),
1888 emitADD(I.getOperand(0).getReg(), I.getOperand(1), I.getOperand(2),
1913 AddsOpc, {I.getOperand(0).getReg()},
1914 {I.getOperand(2).getReg(), I.getOperand(3).getReg()});
1914 {I.getOperand(2).getReg(), I.getOperand(3).getReg()});
1922 .buildInstr(AArch64::CSINCWr, {I.getOperand(1).getReg()},
1931 uint64_t Align = I.getOperand(2).getImm();
1937 I.getOperand(2).setImm(AArch64_AM::encodeLogicalImmediate(Mask, 64));
1943 const LLT DstTy = MRI.getType(I.getOperand(0).getReg());
1944 const LLT SrcTy = MRI.getType(I.getOperand(1).getReg());
1946 const Register DstReg = I.getOperand(0).getReg();
1947 const Register SrcReg = I.getOperand(1).getReg();
1983 I.getOperand(1).setSubReg(AArch64::sub_32);
2014 const Register DstReg = I.getOperand(0).getReg();
2015 const Register SrcReg = I.getOperand(1).getReg();
2052 I.getOperand(1).setReg(ExtSrc);
2061 const Register DefReg = I.getOperand(0).getReg();
2062 const Register SrcReg = I.getOperand(1).getReg();
2131 const LLT DstTy = MRI.getType(I.getOperand(0).getReg()),
2132 SrcTy = MRI.getType(I.getOperand(1).getReg());
2158 if (MRI.getType(I.getOperand(1).getReg()) != LLT::scalar(1)) {
2164 const Register CondReg = I.getOperand(1).getReg();
2165 const Register TReg = I.getOperand(2).getReg();
2166 const Register FReg = I.getOperand(3).getReg();
2179 .addDef(I.getOperand(0).getReg())
2201 if (!emitIntegerCompare(I.getOperand(2), I.getOperand(3), I.getOperand(1),
2201 if (!emitIntegerCompare(I.getOperand(2), I.getOperand(3), I.getOperand(1),
2201 if (!emitIntegerCompare(I.getOperand(2), I.getOperand(3), I.getOperand(1),
2204 emitCSetForICMP(I.getOperand(0).getReg(), I.getOperand(1).getPredicate(),
2204 emitCSetForICMP(I.getOperand(0).getReg(), I.getOperand(1).getPredicate(),
2225 (CmpInst::Predicate)I.getOperand(1).getPredicate(), CC1, CC2);
2230 .addUse(I.getOperand(2).getReg());
2236 CmpMI = CmpMI.addUse(I.getOperand(3).getReg());
2238 const Register DefReg = I.getOperand(0).getReg();
2281 const LLT DstTy = MRI.getType(I.getOperand(0).getReg());
2282 const Register DstReg = I.getOperand(0).getReg();
2291 materializeLargeCMVal(I, I.getOperand(1).getBlockAddress(), 0);
2297 I.getOperand(0).getReg())
2298 .addBlockAddress(I.getOperand(1).getBlockAddress(),
2301 I.getOperand(1).getBlockAddress(), /* Offset */ 0,
2335 Register JTAddr = I.getOperand(0).getReg();
2336 unsigned JTI = I.getOperand(1).getIndex();
2337 Register Index = I.getOperand(2).getReg();
2355 assert(I.getOperand(1).isJTI() && "Jump table op should have a JTI!");
2357 Register DstReg = I.getOperand(0).getReg();
2358 unsigned JTI = I.getOperand(1).getIndex();
2376 const GlobalValue &GV = *I.getOperand(1).getGlobal();
2393 MIB.buildCopy(I.getOperand(0).getReg(), Register(AArch64::X0));
2394 RBI.constrainGenericRegister(I.getOperand(0).getReg(), AArch64::GPR64RegClass,
2402 const LLT SrcTy = MRI.getType(I.getOperand(0).getReg());
2457 const LLT SrcTy = MRI.getType(I.getOperand(0).getReg());
2512 Register DstReg = I.getOperand(0).getReg();
2514 Register SrcReg = I.getOperand(2).getReg();
2515 Register Src2Reg = I.getOperand(3).getReg();
2543 CmpInst::Predicate Pred = (CmpInst::Predicate)I.getOperand(1).getPredicate();
2712 const LLT DstTy = MRI.getType(I.getOperand(0).getReg());
2713 const LLT SrcTy = MRI.getType(I.getOperand(1).getReg());
2715 const RegisterBank &RB = *RBI.getRegBank(I.getOperand(1).getReg(), MRI, TRI);
2725 Register DstReg = I.getOperand(0).getReg();
2726 Register Src1Reg = I.getOperand(1).getReg();
2727 Register Src2Reg = I.getOperand(2).getReg();
2733 MachineInstr *Ins2MI = emitLaneInsert(DstReg, InsMI->getOperand(0).getReg(),
2755 .addUse(I.getOperand(1).getReg())
2763 .addUse(I.getOperand(2).getReg())
2767 .addDef(I.getOperand(0).getReg())
2852 InsertReg = ScalarToVector->getOperand(0).getReg();
2868 Register DstReg = I.getOperand(0).getReg();
2870 const Register SrcReg = I.getOperand(1).getReg();
2878 MachineOperand &LaneIdxOp = I.getOperand(2);
2907 Register SrcReg = I.getOperand(NumElts).getReg();
2908 const LLT NarrowTy = MRI.getType(I.getOperand(0).getReg());
2922 *RBI.getRegBank(I.getOperand(0).getReg(), MRI, TRI);
2924 Register Dst = I.getOperand(OpIdx).getReg();
2940 if (RBI.getRegBank(I.getOperand(0).getReg(), MRI, TRI)->getID() !=
2942 RBI.getRegBank(I.getOperand(1).getReg(), MRI, TRI)->getID() !=
2952 Register SrcReg = I.getOperand(NumElts).getReg();
2953 const LLT NarrowTy = MRI.getType(I.getOperand(0).getReg());
3017 Register CopyTo = I.getOperand(0).getReg();
3025 Register CopyTo = I.getOperand(LaneIdx).getReg();
3038 MRI.getRegClassOrNull(I.getOperand(1).getReg());
3053 Register Dst = I.getOperand(0).getReg();
3054 Register Op1 = I.getOperand(1).getReg();
3055 Register Op2 = I.getOperand(2).getReg();
3323 .buildInstr(InsertOpc, {*Dst}, {WidenedOp1->getOperand(0).getReg()})
3325 .addUse(WidenedOp2->getOperand(0).getReg())
3335 MachineOperand &ImmOp = I.getOperand(1);
3336 unsigned DefSize = MRI.getType(I.getOperand(0).getReg()).getSizeInBits();
3401 MachineInstr *CondDef = MRI.getVRegDef(I.getOperand(1).getReg());
3404 if (!MRI.hasOneUse(CondDef->getOperand(0).getReg()))
3415 Register::isPhysicalRegister(CondDef->getOperand(1).getReg()))
3418 CondDef = MRI.getVRegDef(CondDef->getOperand(1).getReg());
3432 (CmpInst::Predicate)CondDef->getOperand(1).getPredicate());
3433 if (!emitIntegerCompare(CondDef->getOperand(2), CondDef->getOperand(3),
3433 if (!emitIntegerCompare(CondDef->getOperand(2), CondDef->getOperand(3),
3434 CondDef->getOperand(1), MIB)) {
3442 (CmpInst::Predicate)CondDef->getOperand(1).getPredicate(), CondCode,
3458 auto Cmp = MIB.buildInstr(CmpOpc, {}, {CondDef->getOperand(2).getReg()});
3460 Cmp.addUse(CondDef->getOperand(3).getReg());
3467 MIB.buildInstr(CSelOpc, {I.getOperand(0).getReg()},
3468 {I.getOperand(2).getReg(), I.getOperand(3).getReg()})
3468 {I.getOperand(2).getReg(), I.getOperand(3).getReg()})
3507 getConstantVRegValWithLookThrough(DefMI->getOperand(1).getReg(), MRI);
3530 return emitCMN(LHSDef->getOperand(2), RHS, MIRBuilder);
3543 return emitCMN(LHS, RHSDef->getOperand(2), MIRBuilder);
3560 return emitTST(LHSDef->getOperand(1).getReg(),
3561 LHSDef->getOperand(2).getReg(), MIRBuilder);
3589 getOpcodeDef(G_INSERT_VECTOR_ELT, I.getOperand(1).getReg(), MRI);
3594 getOpcodeDef(G_IMPLICIT_DEF, InsMI->getOperand(1).getReg(), MRI);
3598 Register ScalarReg = InsMI->getOperand(2).getReg();
3602 if (!mi_match(InsMI->getOperand(3).getReg(), MRI, m_ICst(Index)) || Index)
3606 const Constant *Mask = I.getOperand(3).getShuffleMask();
3611 LLT VecTy = MRI.getType(I.getOperand(0).getReg());
3629 ScalarReg = Widen->getOperand(0).getReg();
3631 auto Dup = MIB.buildInstr(Opc, {I.getOperand(0).getReg()}, {ScalarReg});
3651 const LLT DstTy = MRI.getType(I.getOperand(0).getReg());
3652 Register Src1Reg = I.getOperand(1).getReg();
3654 Register Src2Reg = I.getOperand(2).getReg();
3656 const Constant *ShuffleMask = I.getOperand(3).getShuffleMask();
3708 IndexLoad->getOperand(0).getReg(), MIRBuilder);
3712 {Concat->getOperand(0).getReg(), IndexLoad->getOperand(0).getReg()});
3712 {Concat->getOperand(0).getReg(), IndexLoad->getOperand(0).getReg()});
3717 .buildInstr(TargetOpcode::COPY, {I.getOperand(0).getReg()}, {})
3734 MIRBuilder.buildInstr(AArch64::TBLv16i8Two, {I.getOperand(0).getReg()},
3735 {RegSeq, IndexLoad->getOperand(0).getReg()});
3761 .addUse(InsSub->getOperand(0).getReg())
3778 Register DstReg = I.getOperand(0).getReg();
3783 Register EltReg = I.getOperand(2).getReg();
3791 Register IdxReg = I.getOperand(3).getReg();
3798 Register SrcReg = I.getOperand(1).getReg();
3809 SrcReg = ScalarToVec->getOperand(0).getReg();
3821 Register DemoteVec = InsMI->getOperand(0).getReg();
3841 InsMI->getOperand(0).setReg(DstReg);
3854 const LLT DstTy = MRI.getType(I.getOperand(0).getReg());
3855 const LLT EltTy = MRI.getType(I.getOperand(1).getReg());
3859 const RegisterBank &RB = *RBI.getRegBank(I.getOperand(1).getReg(), MRI, TRI);
3865 I.getOperand(1).getReg(), MIRBuilder);
3869 Register DstVec = ScalarToVec->getOperand(0).getReg();
3878 PrevMI = &*emitLaneInsert(None, DstVec, I.getOperand(i).getReg(), i - 1, RB,
3880 DstVec = PrevMI->getOperand(0).getReg();
3906 Register DstReg = I.getOperand(0).getReg();
3910 MachineOperand &RegOp = I.getOperand(1);
3917 PrevMI->getOperand(0).setReg(I.getOperand(0).getReg());
3917 PrevMI->getOperand(0).setReg(I.getOperand(0).getReg());
3973 Register DstReg = I.getOperand(0).getReg();
3974 Register SrcReg = I.getOperand(2).getReg();
3985 MIRBuilder.buildCopy({SrcReg}, {I.getOperand(2)});
3988 RBI.constrainGenericRegister(I.getOperand(2).getReg(),
4000 if (DstReg != I.getOperand(0).getReg()) {
4003 MIRBuilder.buildCopy({I.getOperand(0)}, {DstReg});
4004 RBI.constrainGenericRegister(I.getOperand(0).getReg(),
4151 Register DefReg = MI.getOperand(0).getReg();
4206 MachineInstr *OffsetInst = getDefIgnoringCopies(Gep->getOperand(2).getReg(), MRI);
4220 Register OffsetReg = OffsetInst->getOperand(1).getReg();
4221 Register ConstantReg = OffsetInst->getOperand(2).getReg();
4261 MIB.addUse(Gep->getOperand(1).getReg());
4293 if (!MRI.hasOneUse(Gep->getOperand(0).getReg()))
4298 MIB.addUse(Gep->getOperand(1).getReg());
4301 MIB.addUse(Gep->getOperand(2).getReg());
4354 MachineOperand &OffImm = RootDef->getOperand(2);
4361 MachineOperand &RHSOp1 = RHS->getOperand(1);
4370 MachineOperand &Base = RootDef->getOperand(1);
4397 [=](MachineInstrBuilder &MIB) { MIB.add(RootDef->getOperand(1)); },
4403 MachineOperand &LHS = RootDef->getOperand(1);
4404 MachineOperand &RHS = RootDef->getOperand(2);
4408 int64_t RHSC = (int64_t)RHSDef->getOperand(1).getCImm()->getZExtValue();
4413 [=](MachineInstrBuilder &MIB) { MIB.add(LHSDef->getOperand(1)); },
4477 MachineOperand &ShiftRHS = ShiftInst->getOperand(2);
4484 MachineOperand &ShiftLHS = ShiftInst->getOperand(1);
4502 unsigned Size = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
4517 unsigned Size = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
4536 Optional<uint64_t> MaybeAndMask = getImmedFromMO(MI.getOperand(2));
4590 MachineOperand &RHS = RootDef->getOperand(2);
4598 MachineOperand &LHS = RootDef->getOperand(1);
4605 ExtReg = ExtDef->getOperand(1).getReg();
4611 ExtReg = RootDef->getOperand(1).getReg();
lib/Target/AArch64/AArch64LegalizerInfo.cpp 667 Register AmtReg = MI.getOperand(2).getReg();
673 unsigned Amount = CstMI->getOperand(1).getCImm()->getZExtValue();
679 MI.getOperand(2).setReg(ExtCst.getReg(0));
697 Register ValReg = MI.getOperand(0).getReg();
712 MIRBuilder.buildStore(Bitcast.getReg(0), MI.getOperand(1).getReg(), MMO);
715 auto NewLoad = MIRBuilder.buildLoad(NewReg, MI.getOperand(1).getReg(), MMO);
727 unsigned Align = MI.getOperand(2).getImm();
728 Register Dst = MI.getOperand(0).getReg();
729 Register ListPtr = MI.getOperand(1).getReg();
lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp 901 MachineOperand &DstMO = MIB->getOperand(SExtIdx);
919 MIBKill->getOperand(2).setImplicit();
1386 int Value = Update->getOperand(2).getImm();
1387 assert(AArch64_AM::getShiftValue(Update->getOperand(3).getImm()) == 0 &&
1451 if (!MI.getOperand(2).isImm())
1454 if (AArch64_AM::getShiftValue(MI.getOperand(3).getImm()))
1459 if (MI.getOperand(0).getReg() != BaseReg ||
1460 MI.getOperand(1).getReg() != BaseReg)
1463 int UpdateOffset = MI.getOperand(2).getImm();
lib/Target/AArch64/AArch64RedundantCopyElimination.cpp 132 MBB == CondBr.getOperand(1).getMBB()) ||
134 MBB != CondBr.getOperand(1).getMBB())) {
136 KnownRegs.push_back(RegImm(CondBr.getOperand(0).getReg(), 0));
145 AArch64CC::CondCode CC = (AArch64CC::CondCode)CondBr.getOperand(0).getImm();
149 MachineBasicBlock *BrTarget = CondBr.getOperand(1).getMBB();
184 if (!PredI.getOperand(1).isReg())
186 MCPhysReg DstReg = PredI.getOperand(0).getReg();
187 MCPhysReg SrcReg = PredI.getOperand(1).getReg();
194 if (PredI.getOperand(2).isImm() && DomBBClobberedRegs.available(SrcReg) &&
197 int32_t KnownImm = PredI.getOperand(2).getImm();
198 int32_t Shift = PredI.getOperand(3).getImm();
252 MCPhysReg DstReg = PredI.getOperand(0).getReg();
324 MCPhysReg CopyDstReg = PredI->getOperand(0).getReg();
325 MCPhysReg CopySrcReg = PredI->getOperand(1).getReg();
382 Register DefReg = MI->getOperand(0).getReg();
383 Register SrcReg = IsCopy ? MI->getOperand(1).getReg() : Register();
384 int64_t SrcImm = IsMoveImm ? MI->getOperand(1).getImm() : 0;
lib/Target/AArch64/AArch64RegisterInfo.cpp 336 for (unsigned i = 0; !MI->getOperand(i).isFI(); ++i)
434 while (!MI.getOperand(i).isFI()) {
459 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
461 MI.getOperand(FIOperandNum).getTargetFlags() & AArch64II::MO_TAGGED;
471 Offset += StackOffset(MI.getOperand(FIOperandNum + 1).getImm(), MVT::i8);
472 MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false /*isDef*/);
473 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset.getBytes());
478 MachineOperand &FI = MI.getOperand(FIOperandNum);
488 FrameReg = MI.getOperand(3).getReg();
510 MI.getOperand(FIOperandNum)
535 MI.getOperand(FIOperandNum).ChangeToRegister(ScratchReg, false, false, true);
lib/Target/AArch64/AArch64SIMDInstrOpt.cpp 326 CurrentMI->getOperand(1).getReg() == SrcReg &&
327 CurrentMI->getOperand(2).getImm() == LaneNumber) {
328 *DestReg = CurrentMI->getOperand(0).getReg();
429 Register MulDest = MI.getOperand(0).getReg();
430 Register SrcReg0 = MI.getOperand(1).getReg();
431 unsigned Src0IsKill = getKillRegState(MI.getOperand(1).isKill());
432 Register SrcReg1 = MI.getOperand(2).getReg();
433 unsigned Src1IsKill = getKillRegState(MI.getOperand(2).isKill());
438 Register SrcReg2 = MI.getOperand(3).getReg();
439 unsigned Src2IsKill = getKillRegState(MI.getOperand(3).isKill());
440 unsigned LaneNumber = MI.getOperand(4).getImm();
455 unsigned LaneNumber = MI.getOperand(3).getImm();
517 SeqReg = MI.getOperand(0).getReg();
518 AddrReg = MI.getOperand(1).getReg();
638 StReg[i] = DefiningMI->getOperand(2*i+1).getReg();
639 StRegKill[i] = getKillRegState(DefiningMI->getOperand(2*i+1).isKill());
642 if (DefiningMI->getOperand(2*i+2).isImm()) {
643 switch (DefiningMI->getOperand(2*i+2).getImm()) {
lib/Target/AArch64/AArch64SpeculationHardening.cpp 565 Register DstReg = MI.getOperand(0).getReg();
566 Register SrcReg = MI.getOperand(1).getReg();
lib/Target/AArch64/AArch64StackTaggingPreRA.cpp 154 if (UseI->getOperand(OpIdx).isReg() &&
155 UseI->getOperand(OpIdx).getReg() == TaggedReg) {
156 UseI->getOperand(OpIdx).ChangeToFrameIndex(FI);
157 UseI->getOperand(OpIdx).setTargetFlags(AArch64II::MO_TAGGED);
160 Register::isVirtualRegister(UseI->getOperand(0).getReg())) {
161 uncheckUsesOf(UseI->getOperand(0).getReg(), FI);
168 unsigned TaggedReg = I->getOperand(0).getReg();
169 int FI = I->getOperand(1).getIndex();
194 int FI = I.getOperand(1).getIndex();
197 assert(I.getOperand(2).getImm() == 0);
lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp 117 const MachineOperand &Src = I.getOperand(1);
118 MachineOperand &Dst = I.getOperand(0);
181 const Register DefReg = I.getOperand(0).getReg();
263 MachineOperand &Dst = I.getOperand(0);
264 MachineOperand &Src0 = I.getOperand(1);
265 MachineOperand &Src1 = I.getOperand(2);
302 Register DstReg = I.getOperand(0).getReg();
314 .add(I.getOperand(1))
315 .add(I.getOperand(2));
334 .add(I.getOperand(1))
335 .add(I.getOperand(2))
348 MachineOperand Lo1(getSubOperand64(I.getOperand(1), HalfRC, AMDGPU::sub0));
349 MachineOperand Lo2(getSubOperand64(I.getOperand(2), HalfRC, AMDGPU::sub0));
350 MachineOperand Hi1(getSubOperand64(I.getOperand(1), HalfRC, AMDGPU::sub1));
351 MachineOperand Hi2(getSubOperand64(I.getOperand(2), HalfRC, AMDGPU::sub1));
401 Register Dst0Reg = I.getOperand(0).getReg();
402 Register Dst1Reg = I.getOperand(1).getReg();
416 Register Src0Reg = I.getOperand(2).getReg();
417 Register Src1Reg = I.getOperand(3).getReg();
420 .add(I.getOperand(2))
421 .add(I.getOperand(3));
439 unsigned Offset = I.getOperand(2).getImm();
446 I.getOperand(0).getReg())
447 .addReg(I.getOperand(1).getReg(), 0, SubReg);
462 Register DstReg = MI.getOperand(0).getReg();
464 LLT SrcTy = MRI->getType(MI.getOperand(1).getReg());
482 MachineOperand &Src = MI.getOperand(I + 1);
503 MachineOperand &Src = MI.getOperand(NumDst);
506 Register DstReg0 = MI.getOperand(0).getReg();
527 MachineOperand &Dst = MI.getOperand(I);
546 const MachineOperand &MO = I.getOperand(0);
563 Register DstReg = I.getOperand(0).getReg();
564 Register Src0Reg = I.getOperand(1).getReg();
565 Register Src1Reg = I.getOperand(2).getReg();
571 int64_t Offset = I.getOperand(3).getImm();
622 .add(I.getOperand(0))
623 .add(I.getOperand(2))
624 .add(I.getOperand(3));
626 Register DstReg = I.getOperand(0).getReg();
627 Register Src0Reg = I.getOperand(2).getReg();
628 Register Src1Reg = I.getOperand(3).getReg();
720 Register SrcReg = I.getOperand(2).getReg();
723 auto Pred = (CmpInst::Predicate)I.getOperand(1).getPredicate();
725 Register CCReg = I.getOperand(0).getReg();
731 .add(I.getOperand(2))
732 .add(I.getOperand(3));
747 I.getOperand(0).getReg())
748 .add(I.getOperand(2))
749 .add(I.getOperand(3));
750 RBI.constrainGenericRegister(ICmp->getOperand(0).getReg(),
809 const MachineOperand &Op = Def->getOperand(1);
821 if (mi_match(Def->getOperand(1).getReg(), MRI, m_ICst(Offset)))
822 return std::make_tuple(Def->getOperand(0).getReg(), Offset, Def);
825 if (mi_match(Def->getOperand(1).getReg(), MRI, m_Copy(m_ICst(Offset))))
826 return std::make_tuple(Def->getOperand(0).getReg(), Offset, Def);
982 Register VData = MI.getOperand(1).getReg();
993 Register RSrc = MI.getOperand(2).getReg();
994 Register VOffset = MI.getOperand(3).getReg();
995 Register SOffset = MI.getOperand(4).getReg();
996 unsigned AuxiliaryData = MI.getOperand(5).getImm();
1038 int64_t Tgt = I.getOperand(1).getImm();
1039 int64_t Enabled = I.getOperand(2).getImm();
1040 int64_t Done = I.getOperand(7).getImm();
1041 int64_t VM = I.getOperand(8).getImm();
1043 MachineInstr *Exp = buildEXP(TII, &I, Tgt, I.getOperand(3).getReg(),
1044 I.getOperand(4).getReg(),
1045 I.getOperand(5).getReg(),
1046 I.getOperand(6).getReg(),
1054 int64_t Tgt = I.getOperand(1).getImm();
1055 int64_t Enabled = I.getOperand(2).getImm();
1056 Register Reg0 = I.getOperand(3).getReg();
1057 Register Reg1 = I.getOperand(4).getReg();
1059 int64_t Done = I.getOperand(5).getImm();
1060 int64_t VM = I.getOperand(6).getImm();
1074 .add(I.getOperand(1));
1076 Register Reg = I.getOperand(1).getReg();
1096 Register DstReg = I.getOperand(0).getReg();
1099 const MachineOperand &CCOp = I.getOperand(1);
1113 .add(I.getOperand(2))
1114 .add(I.getOperand(3));
1129 .add(I.getOperand(3))
1131 .add(I.getOperand(2))
1132 .add(I.getOperand(1));
1166 Register DstReg = I.getOperand(0).getReg();
1167 Register SrcReg = I.getOperand(1).getReg();
1197 I.getOperand(1).setSubReg(SubRegIdx);
1221 const Register DstReg = I.getOperand(0).getReg();
1222 const Register SrcReg = I.getOperand(1).getReg();
1372 Register Src = I.getOperand(1).getReg();
1377 Register DstReg = I.getOperand(0).getReg();
1400 MachineOperand &ImmOp = I.getOperand(1);
1410 Register DstReg = I.getOperand(0).getReg();
1413 const RegisterBank *RB = MRI->getRegBankOrNull(I.getOperand(0).getReg());
1435 APInt Imm(Size, I.getOperand(1).getImm());
1440 .addImm(I.getOperand(1).getImm());
1464 TRI.getConstrainedRegClassForOperand(ResInst->getOperand(0), *MRI);
1541 const LLT PtrTy = MRI->getType(I.getOperand(1).getReg());
1558 MachineOperand &CondOp = I.getOperand(0);
1594 .addMBB(I.getOperand(1).getMBB());
1601 Register DstReg = I.getOperand(0).getReg();
1613 uint64_t Align = I.getOperand(2).getImm();
1618 Register DstReg = I.getOperand(0).getReg();
1619 Register SrcReg = I.getOperand(1).getReg();
1786 Src = MI->getOperand(1).getReg();
1792 Src = MI->getOperand(1).getReg();
lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp 1218 Register Dst = MI.getOperand(0).getReg();
1219 Register Src = MI.getOperand(1).getReg();
1321 Register Src = MI.getOperand(1).getReg();
1339 B.buildSelect(MI.getOperand(0).getReg(), Cond, Src, Tmp2);
1351 Register Src = MI.getOperand(1).getReg();
1368 B.buildFAdd(MI.getOperand(0).getReg(), Trunc, Add);
1397 Register Src = MI.getOperand(1).getReg();
1430 B.buildSelect(MI.getOperand(0).getReg(), ExpGt51, Src, Tmp1);
1439 Register Dst = MI.getOperand(0).getReg();
1440 Register Src = MI.getOperand(1).getReg();
1497 Optional<int64_t> IdxVal = getConstantVRegVal(MI.getOperand(2).getReg(), MRI);
1501 Register Dst = MI.getOperand(0).getReg();
1502 Register Vec = MI.getOperand(1).getReg();
1526 Optional<int64_t> IdxVal = getConstantVRegVal(MI.getOperand(3).getReg(), MRI);
1530 Register Dst = MI.getOperand(0).getReg();
1531 Register Vec = MI.getOperand(1).getReg();
1532 Register Ins = MI.getOperand(2).getReg();
1554 Register DstReg = MI.getOperand(0).getReg();
1555 Register SrcReg = MI.getOperand(1).getReg();
1637 Register DstReg = MI.getOperand(0).getReg();
1641 const GlobalValue *GV = MI.getOperand(1).getGlobal();
1709 auto Cast = B.buildAddrSpaceCast(ConstPtr, MI.getOperand(1).getReg());
1711 MI.getOperand(1).setReg(Cast.getReg(0));
1719 LLT Ty = MRI.getType(MI.getOperand(0).getReg());
1739 Register DstReg = MI.getOperand(0).getReg();
1740 Register PtrReg = MI.getOperand(1).getReg();
1741 Register CmpVal = MI.getOperand(2).getReg();
1742 Register NewVal = MI.getOperand(3).getReg();
1767 Register CondDef = MI.getOperand(0).getReg();
1851 if (loadInputValue(MI.getOperand(0).getReg(), B, Arg)) {
1863 Register Dst = MI.getOperand(0).getReg();
1879 Register Res = MI.getOperand(0).getReg();
1880 Register LHS = MI.getOperand(1).getReg();
1881 Register RHS = MI.getOperand(2).getReg();
1940 Register Res = MI.getOperand(0).getReg();
1941 Register LHS = MI.getOperand(1).getReg();
1942 Register RHS = MI.getOperand(2).getReg();
1973 Register Res = MI.getOperand(0).getReg();
1974 Register LHS = MI.getOperand(2).getReg();
1975 Register RHS = MI.getOperand(3).getReg();
2019 Register DstReg = MI.getOperand(0).getReg();
2045 auto Hi32 = B.buildExtract(LLT::scalar(32), MI.getOperand(2).getReg(), 32);
2046 B.buildICmp(ICmpInst::ICMP_EQ, MI.getOperand(0), Hi32, ApertureReg);
2079 Register VData = MI.getOperand(1).getReg();
2090 MI.getOperand(1).setReg(AnyExt);
2097 MI.getOperand(1).setReg(handleD16VData(B, MRI, VData));
2118 Register Def = MI.getOperand(1).getReg();
2119 Register Use = MI.getOperand(3).getReg();
2123 .addMBB(BrCond->getOperand(1).getMBB());
2140 Register Reg = MI.getOperand(2).getReg();
2143 .addMBB(BrCond->getOperand(1).getMBB());
2195 B.buildConstant(MI.getOperand(0), ST.getWavefrontSize());
lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp 309 return PHI.getOperand(Index * 2 + 2).getMBB();
314 PHI.getOperand(Index * 2 + 2).setMBB(NewPred);
319 return PHI.getOperand(Index * 2 + 1).getReg();
324 return PHI.getOperand(0).getReg();
2866 assert(Instr.getOperand(i * 2 + 1).isReg() &&
lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp 965 assert(MI.getOperand(Op).isUse());
966 Register Reg = MI.getOperand(Op).getReg();
1001 Register Reg = MI.getOperand(OpIdx).getReg();
1017 MI.getOperand(OpIdx).setReg(SGPR);
1040 Register DstReg = MI.getOperand(0).getReg();
1053 Register PtrReg = MI.getOperand(1).getReg();
1070 LLT PtrTy = MRI.getType(MI.getOperand(1).getReg());
1096 LegalizedInst->getOperand(0).setReg(TmpReg);
1125 if (!MI.getOperand(I).isReg())
1144 OpdMapper.getMI().getOperand(OpIdx).setReg(SrcReg[0]);
1256 Register VData = MI.getOperand(1).getReg();
1270 Register RSrc = MI.getOperand(2).getReg();
1271 Register VOffset = MI.getOperand(3).getReg();
1272 Register SOffset = MI.getOperand(4).getReg();
1273 unsigned CachePolicy = MI.getOperand(5).getImm();
1333 Register DstReg = MI.getOperand(0).getReg();
1353 Src0Regs.push_back(MI.getOperand(1).getReg());
1359 split64BitValueForMapping(B, Src1Regs, HalfTy, MI.getOperand(2).getReg());
1365 split64BitValueForMapping(B, Src2Regs, HalfTy, MI.getOperand(3).getReg());
1383 Register DstReg = MI.getOperand(0).getReg();
1409 split64BitValueForMapping(B, Src0Regs, HalfTy, MI.getOperand(1).getReg());
1414 split64BitValueForMapping(B, Src1Regs, HalfTy, MI.getOperand(2).getReg());
1437 Register DstReg = MI.getOperand(0).getReg();
1462 Register DstReg = MI.getOperand(0).getReg();
1495 Register SrcReg = MI.getOperand(1).getReg();
1502 Register DstReg = MI.getOperand(0).getReg();
1593 Register DstReg = MI.getOperand(0).getReg();
1608 Register Lo = MI.getOperand(1).getReg();
1609 Register Hi = MI.getOperand(2).getReg();
1662 Register DstReg = MI.getOperand(0).getReg();
1663 Register SrcReg = MI.getOperand(1).getReg();
1664 Register IdxReg = MI.getOperand(2).getReg();
1728 Register DstReg = MI.getOperand(0).getReg();
1729 Register SrcReg = MI.getOperand(1).getReg();
1730 Register InsReg = MI.getOperand(2).getReg();
1731 Register IdxReg = MI.getOperand(3).getReg();
lib/Target/AMDGPU/AMDILCFGStructurizer.cpp 435 switch (I->getOperand(2).getImm()) {
437 I->getOperand(2).setImm(R600::PRED_SETNE_INT);
440 I->getOperand(2).setImm(R600::PRED_SETE_INT);
443 I->getOperand(2).setImm(R600::PRED_SETNE);
446 I->getOperand(2).setImm(R600::PRED_SETE);
497 MIB.addReg(OldMI->getOperand(1).getReg(), false);
554 return MI->getOperand(0).getMBB();
559 MI->getOperand(0).setMBB(MBB);
lib/Target/AMDGPU/GCNDPPCombine.cpp 145 auto &Op1 = Def->getOperand(1);
212 DPPInst->getOperand(NumOperands).setIsKill(false);
459 Register FwdReg = OrigMI.getOperand(0).getReg();
470 if (OrigMI.getOperand(OpNo).getReg() == DPPMovReg) {
471 FwdSubReg = OrigMI.getOperand(OpNo + 1).getImm();
542 if (MRI->use_nodbg_empty(S.first->getOperand(0).getReg())) {
547 S.first->getOperand(S.second.pop_back_val()).setIsUndef(true);
lib/Target/AMDGPU/GCNHazardRecognizer.cpp 733 TRI->regsOverlap(MI->getOperand(DataIdx).getReg(), Reg);
775 const MachineOperand &Op = IA->getOperand(I);
933 !MI->getOperand(0).getImm()));
998 return (MI->getOperand(1).getImm() == 0) &&
999 (MI->getOperand(0).getReg() == AMDGPU::SGPR_NULL);
1001 const int64_t Imm = MI->getOperand(0).getImm();
1059 (MI->getOperand(0).getImm() & 0xfffe) == 0xfffe)
1093 I->getOperand(0).getReg() == AMDGPU::SGPR_NULL &&
1094 !I->getOperand(1).getImm()));
1115 I->getOperand(0).getReg() == AMDGPU::SGPR_NULL &&
1116 !I->getOperand(1).getImm();
1262 Register DstReg = MI->getOperand(0).getReg();
1308 Register DstReg = MI->getOperand(0).getReg();
1334 Register DstReg = MI->getOperand(0).getReg();
lib/Target/AMDGPU/R600ClauseMergePass.cpp 111 CFAlu.getOperand(CntIdx).setImm(getCFAluSize(CFAlu) + getCFAluSize(MI));
137 RootCFAlu.getOperand(Mode0Idx).getImm() &&
139 RootCFAlu.getOperand(KBank0Idx).getImm() ||
141 RootCFAlu.getOperand(KBank0LineIdx).getImm())) {
153 RootCFAlu.getOperand(Mode1Idx).getImm() &&
155 RootCFAlu.getOperand(KBank1Idx).getImm() ||
157 RootCFAlu.getOperand(KBank1LineIdx).getImm())) {
162 RootCFAlu.getOperand(Mode0Idx).setImm(
164 RootCFAlu.getOperand(KBank0Idx).setImm(
166 RootCFAlu.getOperand(KBank0LineIdx)
170 RootCFAlu.getOperand(Mode1Idx).setImm(
172 RootCFAlu.getOperand(KBank1Idx).setImm(
174 RootCFAlu.getOperand(KBank1LineIdx)
177 RootCFAlu.getOperand(CntIdx).setImm(CumuledInsts);
206 assert(MI.getOperand(8).getImm() && "CF ALU instruction disabled");
lib/Target/AMDGPU/R600ControlFlowFinalizer.cpp 378 MachineOperand &Operand = MI.getOperand(
464 ClauseHead.getOperand(7).setImm(ClauseContent.size() - 1);
482 Clause.first->getOperand(0).setImm(0);
493 MI.getOperand(0).setImm(Addr + MI.getOperand(0).getImm());
493 MI.getOperand(0).setImm(Addr + MI.getOperand(0).getImm());
637 IfOrElseInst->getOperand(1).setImm(1);
687 .addImm(Alu->getOperand(0).getImm())
688 .addImm(Alu->getOperand(1).getImm())
689 .addImm(Alu->getOperand(2).getImm())
690 .addImm(Alu->getOperand(3).getImm())
691 .addImm(Alu->getOperand(4).getImm())
692 .addImm(Alu->getOperand(5).getImm())
693 .addImm(Alu->getOperand(6).getImm())
694 .addImm(Alu->getOperand(7).getImm())
695 .addImm(Alu->getOperand(8).getImm());
lib/Target/AMDGPU/R600ExpandSpecialInstrs.cpp 100 MachineOperand &DstOp = MI.getOperand(DstIdx);
109 Mov->getOperand(MovPredSelIdx).setReg(
110 MI.getOperand(LDSPredSelIdx).getReg());
117 uint64_t Flags = MI.getOperand(3).getImm();
121 MI.getOperand(2).getImm(), // opcode
122 MI.getOperand(0).getReg(), // dst
123 MI.getOperand(1).getReg(), // src0
138 Register DstReg = MI.getOperand(0).getReg();
159 BMI->getOperand(TII->getOperandIdx(Opcode, R600::OpName::src0))
162 BMI->getOperand(TII->getOperandIdx(Opcode, R600::OpName::src1))
209 MI.getOperand(TII->getOperandIdx(MI, R600::OpName::dst)).getReg();
211 MI.getOperand(TII->getOperandIdx(MI, R600::OpName::src0)).getReg();
218 Src1 = MI.getOperand(Src1Idx).getReg();
lib/Target/AMDGPU/R600ISelLowering.cpp 307 if (!MRI.use_empty(MI.getOperand(DstIdx).getReg()) ||
314 NewMI.add(MI.getOperand(i));
323 *BB, I, R600::MOV, MI.getOperand(0).getReg(),
324 MI.getOperand(1).getReg());
331 *BB, I, R600::MOV, MI.getOperand(0).getReg(),
332 MI.getOperand(1).getReg());
338 Register maskedRegister = MI.getOperand(0).getReg();
346 TII->buildMovImm(*BB, I, MI.getOperand(0).getReg(), MI.getOperand(1)
346 TII->buildMovImm(*BB, I, MI.getOperand(0).getReg(), MI.getOperand(1)
354 TII->buildMovImm(*BB, I, MI.getOperand(0).getReg(),
355 MI.getOperand(1).getImm());
361 *BB, MI, R600::MOV, MI.getOperand(0).getReg(), R600::ALU_LITERAL_X);
364 MIB->getOperand(Idx) = MI.getOperand(1);
364 MIB->getOperand(Idx) = MI.getOperand(1);
370 *BB, MI, R600::MOV, MI.getOperand(0).getReg(), R600::ALU_CONST);
372 MI.getOperand(1).getImm());
380 .add(MI.getOperand(0))
381 .add(MI.getOperand(1))
387 .add(MI.getOperand(0))
388 .add(MI.getOperand(1))
389 .add(MI.getOperand(2))
395 .add(MI.getOperand(0));
402 .add(MI.getOperand(1))
407 .add(MI.getOperand(0))
416 .add(MI.getOperand(1))
421 .add(MI.getOperand(0))
430 unsigned InstExportType = MI.getOperand(1).getImm();
436 unsigned CurrentInstExportType = NextExportInst->getOperand(1)
449 .add(MI.getOperand(0))
450 .add(MI.getOperand(1))
451 .add(MI.getOperand(2))
452 .add(MI.getOperand(3))
453 .add(MI.getOperand(4))
454 .add(MI.getOperand(5))
455 .add(MI.getOperand(6))
lib/Target/AMDGPU/R600InstrInfo.cpp 90 NewMI->getOperand(getOperandIdx(*NewMI, R600::OpName::src0))
295 MI.getOperand(getOperandIdx(MI.getOpcode(), OpTable[j][0]));
299 MI.getOperand(getOperandIdx(MI.getOpcode(), OpTable[j][1]));
318 MachineOperand &MO = MI.getOperand(SrcIdx);
322 MI.getOperand(getOperandIdx(MI.getOpcode(), OpTable[j][1]));
328 MI.getOperand(getOperandIdx(MI.getOpcode(), R600::OpName::literal));
551 IG[i]->getOperand(Op).getImm());
707 TBB = LastInst.getOperand(0).getMBB();
714 TBB = LastInst.getOperand(0).getMBB();
715 Cond.push_back(predSet->getOperand(1));
716 Cond.push_back(predSet->getOperand(2));
733 TBB = SecondLastInst.getOperand(0).getMBB();
734 FBB = LastInst.getOperand(0).getMBB();
735 Cond.push_back(predSet->getOperand(1));
736 Cond.push_back(predSet->getOperand(2));
773 PredSet->getOperand(2).setImm(Cond[1].getImm());
789 PredSet->getOperand(2).setImm(Cond[1].getImm());
976 MI.getOperand(8).setImm(0);
981 MI.getOperand(getOperandIdx(MI, R600::OpName::pred_sel_X))
983 MI.getOperand(getOperandIdx(MI, R600::OpName::pred_sel_Y))
985 MI.getOperand(getOperandIdx(MI, R600::OpName::pred_sel_Z))
987 MI.getOperand(getOperandIdx(MI, R600::OpName::pred_sel_W))
995 MachineOperand &PMO = MI.getOperand(PIdx);
1037 unsigned RegIndex = MI.getOperand(RegOpIdx).getImm();
1038 unsigned Channel = MI.getOperand(ChanOpIdx).getImm();
1040 Register OffsetReg = MI.getOperand(OffsetOpIdx).getReg();
1042 buildMovInstr(MBB, MI, MI.getOperand(DstOpIdx).getReg(),
1045 buildIndirectRead(MBB, MI, MI.getOperand(DstOpIdx).getReg(), Address,
1051 unsigned RegIndex = MI.getOperand(RegOpIdx).getImm();
1052 unsigned Channel = MI.getOperand(ChanOpIdx).getImm();
1054 Register OffsetReg = MI.getOperand(OffsetOpIdx).getReg();
1057 MI.getOperand(ValOpIdx).getReg());
1059 buildIndirectWrite(MBB, MI, MI.getOperand(ValOpIdx).getReg(),
1072 buildIndirectRead(MI.getParent(), MI, MI.getOperand(0).getReg(),
1073 RI.getHWRegIndex(MI.getOperand(1).getReg()), // Address
1074 MI.getOperand(2).getReg(),
1075 RI.getHWRegChan(MI.getOperand(1).getReg()));
1079 buildIndirectWrite(MI.getParent(), MI, MI.getOperand(2).getReg(), // Value
1080 RI.getHWRegIndex(MI.getOperand(1).getReg()), // Address
1081 MI.getOperand(3).getReg(), // Offset
1082 RI.getHWRegChan(MI.getOperand(1).getReg())); // Channel
1326 MachineOperand &Src0 = MI->getOperand(
1328 MachineOperand &Src1 = MI->getOperand(
1349 MachineOperand &MO = MI->getOperand(getOperandIdx(MI->getOpcode(),
1351 MIB->getOperand(getOperandIdx(Opcode, R600::OpName::pred_sel))
1355 MachineOperand &MO = MI->getOperand(
1360 MIB->getOperand(20).setImm(0);
1392 assert(MI.getOperand(Idx).isImm());
1393 MI.getOperand(Idx).setImm(Imm);
1460 MachineOperand &FlagOp = MI.getOperand(FlagIndex);
lib/Target/AMDGPU/R600MachineScheduler.cpp 186 return !Register::isVirtualRegister(MI->getOperand(1).getReg());
234 if (MI->getOperand(1).isUndef()) {
258 unsigned DestSubReg = MI->getOperand(0).getSubReg();
273 Register DestReg = MI->getOperand(0).getReg();
360 Register DestReg = MI->getOperand(DstIndex).getReg();
lib/Target/AMDGPU/R600OptimizeVectorRegisters.cpp 78 MachineOperand &MO = Instr->getOperand(i);
79 unsigned Chan = Instr->getOperand(i + 1).getImm();
200 Register Reg = RSI->Instr->getOperand(0).getReg();
205 Register SrcVec = BaseRSI->Instr->getOperand(0).getReg();
272 unsigned Swizzle = MI.getOperand(i + Offset).getImm() + 1;
275 MI.getOperand(i + Offset).setImm(RemapChan[j].second - 1);
353 Register Reg = MI.getOperand(1).getReg();
366 Register Reg = MI.getOperand(0).getReg();
lib/Target/AMDGPU/R600Packetizer.cpp 87 if (OperandIdx > -1 && BI->getOperand(OperandIdx).getImm() == 0)
93 Register Dst = BI->getOperand(DstIdx).getReg();
139 Register Src = MI.getOperand(OperandIdx).getReg();
142 MI.getOperand(OperandIdx).setReg(It->second);
189 Register PredI = (OpI > -1)?MII->getOperand(OpI).getReg() : Register(),
190 PredJ = (OpJ > -1)?MIJ->getOperand(OpJ).getReg() : Register();
201 if (MII->getOperand(0).getReg() != MIJ->getOperand(0).getReg())
201 if (MII->getOperand(0).getReg() != MIJ->getOperand(0).getReg())
223 MI->getOperand(LastOp).setImm(Bit);
304 MI->getOperand(Op).setImm(BS[i]);
308 MI.getOperand(Op).setImm(BS.back());
357 (MI->getOpcode() == R600::CF_ALU && !MI->getOperand(8).getImm())) {
lib/Target/AMDGPU/SIFixSGPRCopies.cpp 205 auto &Src = MI.getOperand(1);
206 Register DstReg = MI.getOperand(0).getReg();
245 Register DstReg = MI.getOperand(0).getReg();
257 if (Register::isPhysicalRegister(CopyUse.getOperand(0).getReg()))
270 unsigned SubReg = CopyUse.getOperand(1).getSubReg();
284 MI.getOperand(0).setReg(CopyUse.getOperand(0).getReg());
284 MI.getOperand(0).setReg(CopyUse.getOperand(0).getReg());
288 Register SrcReg = MI.getOperand(I).getReg();
289 unsigned SrcSubReg = MI.getOperand(I).getSubReg();
302 .add(MI.getOperand(I));
315 MI.getOperand(I).setReg(TmpReg);
611 Register DstReg = MI.getOperand(0).getReg();
627 .add(MI.getOperand(1));
628 MI.getOperand(1).setReg(TmpReg);
635 Register SrcReg = MI.getOperand(1).getReg();
647 MI.getOperand(1).ChangeToImmediate(Imm);
676 DstRC = MRI->getRegClass(MI.getOperand(0).getReg());
677 Src0RC = MRI->getRegClass(MI.getOperand(1).getReg());
678 Src1RC = MRI->getRegClass(MI.getOperand(2).getReg());
703 MachineOperand &Src0 = MI.getOperand(Src0Idx);
704 MachineOperand &Src1 = MI.getOperand(Src1Idx);
721 const MachineOperand &Def = DefMI->getOperand(0);
725 const MachineOperand &Copied = DefMI->getOperand(1);
802 Register PHIRes = MI.getOperand(0).getReg();
811 unsigned InputReg = MI.getOperand(i).getReg();
815 unsigned SrcReg = Def->getOperand(1).getReg();
825 TRI->isVectorRegister(*MRI, Def->getOperand(1).getReg())) {
lib/Target/AMDGPU/SIFixupVectorISel.cpp 101 Worklist.push_back(&DefInst->getOperand(1));
106 Worklist.push_back(&DefInst->getOperand(1));
107 Worklist.push_back(&DefInst->getOperand(3));
113 if (DefInst->getOperand(2).getSubReg() != AMDGPU::NoSubRegister)
115 BaseReg = DefInst->getOperand(2).getReg();
116 if (DefInst->getOperand(3).getSubReg() != AMDGPU::NoSubRegister)
118 IndexReg = DefInst->getOperand(3).getReg();
127 IdxRC = MRI.getRegClass(MI->getOperand(1).getReg());
130 IndexReg = MI->getOperand(1).getReg();
136 BaseReg = MI->getOperand(1).getReg();
188 NewGlob->addOperand(MF, MI.getOperand(0));
lib/Target/AMDGPU/SIFoldOperands.cpp 190 MachineOperand &Old = MI->getOperand(Fold.UseOpNo);
211 MachineOperand &Mod = MI->getOperand(ModIdx);
251 MachineOperand &Dst0 = MI->getOperand(0);
252 MachineOperand &Dst1 = MI->getOperand(1);
391 if (CanCommute && (!MI->getOperand(CommuteIdx0).isReg() ||
392 !MI->getOperand(CommuteIdx1).isReg()))
409 MachineOperand &OtherOp = MI->getOperand(OtherIdx);
414 assert(MI->getOperand(1).isDef());
457 MachineOperand *Sub = &Def->getOperand(I);
464 MachineOperand *Op = &SubDef->getOperand(1);
475 Defs.push_back(std::make_pair(Sub, Def->getOperand(I + 1).getImm()));
498 UseMI->getOperand(UseOpIdx).ChangeToImmediate(OpToFold.getImm());
547 const MachineOperand &UseOp = UseMI->getOperand(UseOpIdx);
562 Register RegSeqDstReg = UseMI->getOperand(0).getReg();
563 unsigned RegSeqDstSubReg = UseMI->getOperand(UseOpIdx + 1).getImm();
573 if (tryToFoldACImm(TII, UseMI->getOperand(0), RSUseMI,
604 UseMI->getOperand(UseOpIdx).ChangeToFrameIndex(OpToFold.getIndex());
613 Register DestReg = UseMI->getOperand(0).getReg();
623 Register SrcReg = UseMI->getOperand(1).getReg();
634 Use.getOperandNo(), &UseMI->getOperand(1));
647 UseMI->getOperand(1).ChangeToImmediate(OpToFold.getImm());
670 UseMI->getOperand(0).getReg().isVirtual() &&
671 !UseMI->getOperand(1).getSubReg()) {
676 UseMI->getOperand(1).setReg(UseReg);
677 UseMI->getOperand(1).setSubReg(OpToFold.getSubReg());
678 UseMI->getOperand(1).setIsKill(false);
687 if (Size > 4 && TRI->isAGPR(*MRI, UseMI->getOperand(0).getReg()) &&
763 if (TRI->isAGPR(*MRI, UseMI->getOperand(0).getReg()) &&
764 TRI->isVGPR(*MRI, UseMI->getOperand(1).getReg()))
766 else if (TRI->isVGPR(*MRI, UseMI->getOperand(0).getReg()) &&
767 TRI->isAGPR(*MRI, UseMI->getOperand(1).getReg()))
783 UseMI->getOperand(UseOpIdx).getReg(),
791 UseMI->getOperand(1).setSubReg(0);
793 UseMI->getOperand(1).ChangeToImmediate(OpToFold.getImm());
795 UseMI->getOperand(1).ChangeToFrameIndex(OpToFold.getIndex());
802 UseMI->getOperand(UseOpIdx).getReg(),
812 UseMI->getOperand(1).setReg(OpToFold.getReg());
813 UseMI->getOperand(1).setSubReg(OpToFold.getSubReg());
814 UseMI->getOperand(1).setIsKill(false);
953 MachineOperand &ImmSrc = Def->getOperand(1);
972 MI->getOperand(1).ChangeToImmediate(~ImmOp->getImm());
982 MachineOperand *Src0 = getImmOrMaterializedImm(MRI, MI->getOperand(Src0Idx));
983 MachineOperand *Src1 = getImmOrMaterializedImm(MRI, MI->getOperand(Src1Idx));
1010 bool IsSGPR = TRI.isSGPRReg(MRI, MI->getOperand(0).getReg());
1014 MI->getOperand(Src0Idx).ChangeToImmediate(NewImm);
1091 (Src1ModIdx == -1 || !MI->getOperand(Src1ModIdx).getImm()) &&
1092 (Src0ModIdx == -1 || !MI->getOperand(Src0ModIdx).getImm())) {
1120 MachineOperand &Dst = MI.getOperand(0);
1315 MRI->replaceRegWith(MI.getOperand(0).getReg(), Def->getOperand(0).getReg());
1315 MRI->replaceRegWith(MI.getOperand(0).getReg(), Def->getOperand(0).getReg());
1437 MRI->replaceRegWith(MI.getOperand(0).getReg(), Def->getOperand(0).getReg());
1437 MRI->replaceRegWith(MI.getOperand(0).getReg(), Def->getOperand(0).getReg());
1485 if (MI.getOperand(0).getReg() == AMDGPU::M0) {
1486 MachineOperand &NewM0Val = MI.getOperand(1);
1498 MachineOperand &OpToFold = MI.getOperand(1);
1515 MachineOperand &Dst = MI.getOperand(0);
lib/Target/AMDGPU/SIFrameLowering.cpp 1101 int64_t Amount = I->getOperand(0).getImm();
1110 uint64_t CalleePopAmount = IsDestroy ? I->getOperand(1).getImm() : 0;
lib/Target/AMDGPU/SIISelLowering.cpp 3234 SetOn->getOperand(3).setIsUndef();
3286 Register DstReg = MI.getOperand(0).getReg();
3359 SetOn->getOperand(3).setIsUndef();
3370 SetOn->getOperand(3).setIsUndef();
3397 Register Dst = MI.getOperand(0).getReg();
3488 Register Dst = MI.getOperand(0).getReg();
3606 MachineOperand &Dest = MI.getOperand(0);
3607 MachineOperand &Src0 = MI.getOperand(1);
3608 MachineOperand &Src1 = MI.getOperand(2);
3648 .add(MI.getOperand(0));
3656 .addImm(MI.getOperand(0).getImm());
3664 .addImm(MI.getOperand(0).getImm());
3678 Register InputReg = MI.getOperand(0).getReg();
3685 I->getOperand(0).getReg() != InputReg)
3706 .addImm((MI.getOperand(1).getImm() & Mask) | 0x70000);
3728 .add(MI.getOperand(0))
3753 Register Dst = MI.getOperand(0).getReg();
3754 Register Src0 = MI.getOperand(1).getReg();
3755 Register Src1 = MI.getOperand(2).getReg();
3757 Register SrcCond = MI.getOperand(3).getReg();
3791 .add(MI.getOperand(0));
3792 Br->getOperand(1).setIsUndef(true); // read undef SCC
3819 MIB.add(MI.getOperand(I));
3838 auto I = BuildMI(*BB, MI, DL, TII->get(Opc), MI.getOperand(0).getReg());
3844 I.add(MI.getOperand(1))
3845 .add(MI.getOperand(2));
10406 MachineOperand &Op = MI.getOperand(I);
10414 !TRI->isSGPRReg(MRI, Src->getOperand(1).getReg()))
10447 Register Def = MI.getOperand(0).getReg();
lib/Target/AMDGPU/SIInsertSkips.cpp 194 switch (MI.getOperand(2).getImm()) {
251 assert(MI.getOperand(0).isReg());
254 MI.getOperand(0).getReg())) {
257 .add(MI.getOperand(1))
258 .add(MI.getOperand(0));
265 .add(MI.getOperand(1))
267 .add(MI.getOperand(0));
277 const MachineOperand &Op = MI.getOperand(0);
278 int64_t KillVal = MI.getOperand(1).getImm();
323 MachineBasicBlock *DestBB = MI.getOperand(0).getMBB();
371 MachineOperand &Op1 = A->getOperand(1);
372 MachineOperand &Op2 = A->getOperand(2);
396 !M->getOperand(1).isImm() ||
397 M->getOperand(1).getImm() != -1)
402 A->getOperand(2).ChangeToImmediate(-1);
470 ExecBranchStack.push_back(MI.getOperand(0).getMBB());
477 if (MBB.isLayoutSuccessor(MI.getOperand(0).getMBB())) {
lib/Target/AMDGPU/SIInsertWaitcnts.cpp 572 const MachineOperand &Op = Inst.getOperand(I);
619 MachineOperand &DefMO = Inst.getOperand(I);
628 MachineOperand &MO = Inst.getOperand(I);
867 ((MI.getOperand(0).getImm() & AMDGPU::SendMsg::ID_MASK_) ==
988 const MachineOperand &Op = MI.getOperand(I);
1024 MachineOperand &Def = MI.getOperand(I);
1076 int64_t Imm = II->getOperand(0).getImm();
1080 assert(II->getOperand(0).getReg() == AMDGPU::SGPR_NULL);
1082 AMDGPU::Waitcnt(0, 0, 0, II->getOperand(1).getImm()));
1113 unsigned IEnc = II->getOperand(0).getImm();
1120 II->getOperand(0).setImm(NewEnc);
1128 assert(II->getOperand(0).getReg() == AMDGPU::SGPR_NULL);
1130 unsigned ICnt = II->getOperand(1).getImm();
1135 II->getOperand(1).setImm(Wait.VsCnt);
1382 Inst.getOperand(0).isReg() &&
1383 Inst.getOperand(0).getReg() == AMDGPU::SGPR_NULL)) {
lib/Target/AMDGPU/SIInstrInfo.cpp 622 MachineOperand &DefOp = Def->getOperand(1);
1419 Register Dst = MI.getOperand(0).getReg();
1423 const MachineOperand &SrcOp = MI.getOperand(1);
1455 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), MI.getOperand(0).getReg())
1456 .add(MI.getOperand(2));
1468 MI.getOperand(0).getReg())
1469 .add(MI.getOperand(2));
1482 Register VecReg = MI.getOperand(0).getReg();
1483 bool IsUndef = MI.getOperand(1).isUndef();
1484 unsigned SubReg = AMDGPU::sub0 + MI.getOperand(3).getImm();
1485 assert(VecReg == MI.getOperand(1).getReg());
1490 .add(MI.getOperand(2))
1505 Register Reg = MI.getOperand(0).getReg();
1518 .add(MI.getOperand(1)));
1522 MIB.add(MI.getOperand(2));
1571 Register Dst = MI.getOperand(0).getReg();
1587 const MachineOperand &SrcOp = MI.getOperand(I);
1604 MovDPP.addImm(MI.getOperand(I).getImm());
1612 .addReg(Split[0]->getOperand(0).getReg())
1614 .addReg(Split[1]->getOperand(0).getReg())
1681 MachineOperand &Src0 = MI.getOperand(Src0Idx);
1682 MachineOperand &Src1 = MI.getOperand(Src1Idx);
1909 TBB = I->getOperand(0).getMBB();
1916 CondBB = I->getOperand(1).getMBB();
1917 Cond.push_back(I->getOperand(0));
1923 CondBB = I->getOperand(0).getMBB();
1925 Cond.push_back(I->getOperand(1)); // Save the branch register.
1937 FBB = I->getOperand(0).getMBB();
1995 MachineBasicBlock *MaskBrDest = I->getOperand(0).getMBB();
2078 preserveCondRegFlags(CondBr->getOperand(1), Cond[1]);
2093 MachineOperand &CondReg = CondBr->getOperand(1);
2181 preserveCondRegFlags(Select->getOperand(3), Cond[1]);
2191 preserveCondRegFlags(Select->getOperand(3), Cond[1]);
2244 preserveCondRegFlags(Select->getOperand(3), Cond[1]);
2333 bool isVGPRCopy = RI.isVGPR(*MRI, UseMI.getOperand(0).getReg());
2335 if (RI.isAGPR(*MRI, UseMI.getOperand(0).getReg())) {
2341 UseMI.getOperand(1).ChangeToImmediate(ImmOp->getImm());
2435 isInlineConstant(Def->getOperand(1)) &&
2437 Src0->ChangeToImmediate(Def->getOperand(1).getImm());
2453 isInlineConstant(Def->getOperand(1)) &&
2456 Src0->ChangeToImmediate(Def->getOperand(1).getImm());
2600 Def->getOperand(1).isImm())
2601 return Def->getOperand(1).getImm();
2631 const MachineOperand *Src0 = &MI.getOperand(Src0Idx);
3069 Inst32.add(MI.getOperand(0));
3071 assert(((MI.getOperand(0).getReg() == AMDGPU::VCC) ||
3072 (MI.getOperand(0).getReg() == AMDGPU::VCC_LO)) &&
3827 MachineOperand &MO = MI.getOperand(OpIdx);
3908 MachineOperand Op1 = Inst.getOperand(1);
4018 MachineOperand &Src0 = MI.getOperand(Src0Idx);
4021 MachineOperand &Src1 = MI.getOperand(Src1Idx);
4137 MachineOperand &Src1 = MI.getOperand(VOP3Idx[1]);
4138 MachineOperand &Src2 = MI.getOperand(VOP3Idx[2]);
4168 MachineOperand &MO = MI.getOperand(Idx);
4305 if (Def->getOperand(1).getReg().isPhysical())
4307 Def = MRI.getUniqueVRegDef(Def->getOperand(1).getReg());
4542 if (!MI.getOperand(i).isReg() ||
4543 !Register::isVirtualRegister(MI.getOperand(i).getReg()))
4546 MRI.getRegClass(MI.getOperand(i).getReg());
4578 MachineOperand &Op = MI.getOperand(I);
4583 MachineBasicBlock *InsertBB = MI.getOperand(I + 1).getMBB();
4603 MachineOperand &Op = MI.getOperand(I);
4623 Register Dst = MI.getOperand(0).getReg();
4624 Register Src0 = MI.getOperand(1).getReg();
4629 MachineOperand &Op = MI.getOperand(1);
4637 MachineOperand &Src = MI.getOperand(0);
4670 MachineOperand *Rsrc = &MI.getOperand(RsrcIdx);
5013 MachineOperand &Op = Inst.getOperand(i);
5039 const MachineOperand &OffsetWidthOp = Inst.getOperand(2);
5053 bool HasDst = Inst.getOperand(0).isReg() && Inst.getOperand(0).isDef();
5053 bool HasDst = Inst.getOperand(0).isReg() && Inst.getOperand(0).isDef();
5056 Register DstReg = Inst.getOperand(0).getReg();
5066 Register::isVirtualRegister(Inst.getOperand(1).getReg()) &&
5067 NewDstRC == RI.getRegClassForReg(MRI, Inst.getOperand(1).getReg())) {
5075 MRI.replaceRegWith(DstReg, Inst.getOperand(1).getReg());
5076 MRI.clearKillFlags(Inst.getOperand(1).getReg());
5077 Inst.getOperand(0).setReg(DstReg);
5111 Register OldDstReg = Inst.getOperand(0).getReg();
5120 assert(Inst.getOperand(3).getReg() == AMDGPU::SCC);
5143 MachineOperand &Dest = Inst.getOperand(0);
5144 MachineOperand &Src = Inst.getOperand(1);
5170 MachineOperand &Dest = Inst.getOperand(0);
5171 MachineOperand &Src0 = Inst.getOperand(1);
5172 MachineOperand &Src1 = Inst.getOperand(2);
5236 MachineOperand &Dest = Inst.getOperand(0);
5237 MachineOperand &Src0 = Inst.getOperand(1);
5238 MachineOperand &Src1 = Inst.getOperand(2);
5265 MachineOperand &Dest = Inst.getOperand(0);
5266 MachineOperand &Src0 = Inst.getOperand(1);
5267 MachineOperand &Src1 = Inst.getOperand(2);
5292 MachineOperand &Dest = Inst.getOperand(0);
5293 MachineOperand &Src0 = Inst.getOperand(1);
5356 MachineOperand &Dest = Inst.getOperand(0);
5357 MachineOperand &Src0 = Inst.getOperand(1);
5358 MachineOperand &Src1 = Inst.getOperand(2);
5418 MachineOperand &Dest = Inst.getOperand(0);
5419 MachineOperand &Src0 = Inst.getOperand(1);
5420 MachineOperand &Src1 = Inst.getOperand(2);
5482 MachineOperand &Dest = Inst.getOperand(0);
5483 MachineOperand &Src0 = Inst.getOperand(1);
5484 MachineOperand &Src1 = Inst.getOperand(2);
5526 MachineOperand &Dest = Inst.getOperand(0);
5527 MachineOperand &Src = Inst.getOperand(1);
5562 MachineOperand &Dest = Inst.getOperand(0);
5563 uint32_t Imm = Inst.getOperand(2).getImm();
5579 .addReg(Inst.getOperand(1).getReg(), 0, AMDGPU::sub0)
5598 MachineOperand &Src = Inst.getOperand(1);
5657 MachineOperand &Src0 = Inst.getOperand(1);
5658 MachineOperand &Src1 = Inst.getOperand(2);
5709 MachineOperand &Dest = Inst.getOperand(0);
5858 return &MI.getOperand(Idx);
6078 .add(Branch->getOperand(0))
6079 .add(Branch->getOperand(1));
6124 .add(Branch->getOperand(0));
6382 if (MI.getOperand(1 + 2 * I + 1).getImm() == SubReg) {
6383 auto &RegOp = MI.getOperand(1 + 2 * I);
6402 if (RSR.SubReg == (unsigned)MI.getOperand(3).getImm())
6404 RSR = getRegOrUndef(MI.getOperand(2));
6406 auto R1 = getRegOrUndef(MI.getOperand(1));
6429 auto &Op1 = MI->getOperand(1);
lib/Target/AMDGPU/SILoadStoreOptimizer.cpp 456 Offset0 = I->getOperand(OffsetIdx).getImm();
501 AddrReg[i] = &I->getOperand(AddrIdx[i]);
517 Offset1 = Paired->getOperand(OffsetIdx).getImm();
658 CI.I->getOperand(Idx).getImm() != CI.Paired->getOperand(Idx).getImm())
658 CI.I->getOperand(Idx).getImm() != CI.Paired->getOperand(Idx).getImm())
768 if (Swizzled != -1 && CI.I->getOperand(Swizzled).getImm())
1055 MIB.add((*CI.I).getOperand(I));
1446 !Def->getOperand(1).isImm())
1449 return Def->getOperand(1).getImm();
1472 MachineOperand BaseLo = Def->getOperand(1);
1473 MachineOperand BaseHi = Def->getOperand(3);
lib/Target/AMDGPU/SILowerControlFlow.cpp 139 MachineOperand &ImpDefSCC = MI.getOperand(3);
182 MachineOperand &SaveExec = MI->getOperand(0);
191 J->getOperand(1).isReg() && J->getOperand(1).getReg() == SaveExecReg) {
191 J->getOperand(1).isReg() && J->getOperand(1).getReg() == SaveExecReg) {
192 SaveExecReg = J->getOperand(0).getReg();
203 MachineOperand& Cond = MI.getOperand(1);
206 MachineOperand &ImpDefSCC = MI.getOperand(4);
250 .add(MI.getOperand(2));
287 bool ExecModified = MI.getOperand(3).getImm() != 0;
296 .add(MI.getOperand(1)); // Saved EXEC
306 MachineBasicBlock *DestBB = MI.getOperand(2).getMBB();
364 if (MI.getOperand(1).isReg()) {
365 if (MachineInstr *Def = MRI->getUniqueVRegDef(MI.getOperand(1).getReg())) {
377 .add(MI.getOperand(1));
380 .add(MI.getOperand(2));
383 .add(MI.getOperand(1))
384 .add(MI.getOperand(2));
402 .add(MI.getOperand(0));
406 .add(MI.getOperand(1));
419 unsigned CFMask = MI.getOperand(0).getReg();
428 .add(MI.getOperand(0));
443 MachineOperand &Op = MI.getOperand(OpNo);
459 !(I->isCopy() && I->getOperand(0).getReg() != Exec))
487 Register Reg = MI.getOperand(OpToReplace).getReg();
lib/Target/AMDGPU/SILowerI1Copies.cpp 509 Register DstReg = MI.getOperand(0).getReg();
510 Register SrcReg = MI.getOperand(1).getReg();
522 assert(!MI.getOperand(0).getSubReg());
554 if (isVreg1(MI.getOperand(0).getReg()))
569 Register DstReg = MI->getOperand(0).getReg();
576 Register IncomingReg = MI->getOperand(i).getReg();
577 MachineBasicBlock *IncomingMBB = MI->getOperand(i + 1).getMBB();
581 IncomingReg = IncomingDef->getOperand(1).getReg();
583 assert(!IncomingDef->getOperand(1).getSubReg());
680 Register DstReg = MI.getOperand(0).getReg();
697 Register SrcReg = MI.getOperand(1).getReg();
698 assert(!MI.getOperand(1).getSubReg());
707 MI.getOperand(1).setReg(TmpReg);
lib/Target/AMDGPU/SILowerSGPRSpills.cpp 280 int FI = MI.getOperand(FIOp).getIndex();
lib/Target/AMDGPU/SIMemoryLegalizer.cpp 109 MachineOperand &Bit = MI->getOperand(BitIdx);
611 static_cast<AtomicOrdering>(MI->getOperand(0).getImm());
613 SyncScope::ID SSID = static_cast<SyncScope::ID>(MI->getOperand(1).getImm());
lib/Target/AMDGPU/SIOptimizeExecMasking.cpp 305 if (CopyToExecInst->getOperand(1).isKill() &&
309 PrepareExecInst->getOperand(0).setReg(Exec);
325 Register CopyFromExec = CopyFromExecInst->getOperand(0).getReg();
388 MachineOperand &Src0 = SaveExecInst->getOperand(1);
389 MachineOperand &Src1 = SaveExecInst->getOperand(2);
lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp 210 !And->getOperand(1).isReg() || !And->getOperand(2).isReg())
210 !And->getOperand(1).isReg() || !And->getOperand(2).isReg())
213 MachineOperand *AndCC = &And->getOperand(1);
217 AndCC = &And->getOperand(2);
220 } else if (And->getOperand(2).getReg() != ExecReg) {
260 And->getOperand(0).getReg())
416 Register SavedExec = SaveExec->getOperand(0).getReg();
lib/Target/AMDGPU/SIPeepholeSDWA.cpp 410 Src = &MI.getOperand(TiedIdx);
1134 auto Tied = MI.getOperand(TiedIdx);
lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp 192 RegsAssigned |= processDef(MI.getOperand(0));
lib/Target/AMDGPU/SIRegisterInfo.cpp 762 Register SuperReg = MI->getOperand(0).getReg();
763 bool IsKill = MI->getOperand(0).isKill();
881 Register SuperReg = MI->getOperand(0).getReg();
939 MIB.addReg(MI->getOperand(0).getReg(), RegState::ImplicitDefine);
995 MachineOperand &FIOp = MI->getOperand(FIOperandNum);
996 int Index = MI->getOperand(FIOperandNum).getIndex();
1107 MI->getOperand(0).getReg() :
lib/Target/AMDGPU/SIShrinkInstructions.cpp 78 MachineOperand &Src0 = MI.getOperand(Src0Idx);
84 MachineOperand &MovSrc = Def->getOperand(1);
185 if (!MI.getOperand(0).isReg())
188 const MachineOperand &Src1 = MI.getOperand(1);
253 const MachineOperand &Op = MI.getOperand(VAddr0Idx + i);
274 unsigned TFEVal = MI.getOperand(TFEIdx).getImm();
275 unsigned LWEVal = MI.getOperand(LWEIdx).getImm();
280 if (MI.getOperand(i).isReg() && MI.getOperand(i).isTied() &&
280 if (MI.getOperand(i).isReg() && MI.getOperand(i).isTied() &&
281 MI.getOperand(i).isImplicit()) {
296 MI.getOperand(VAddr0Idx).setReg(RC->getRegister(VgprBase));
297 MI.getOperand(VAddr0Idx).setIsUndef(IsUndef);
298 MI.getOperand(VAddr0Idx).setIsKill(IsKill);
320 const MachineOperand *Dest = &MI.getOperand(0);
321 MachineOperand *Src0 = &MI.getOperand(1);
322 MachineOperand *Src1 = &MI.getOperand(2);
375 MI.getOperand(2).ChangeToRegister(Dest->getReg(), false);
460 Register T = MovT.getOperand(0).getReg();
461 unsigned Tsub = MovT.getOperand(0).getSubReg();
462 MachineOperand &Xop = MovT.getOperand(1);
482 MovY.getOperand(1).getSubReg() != Tsub)
485 Register Y = MovY.getOperand(0).getReg();
486 unsigned Ysub = MovY.getOperand(0).getSubReg();
511 I->getOperand(0).getReg() != X ||
512 I->getOperand(0).getSubReg() != Xsub) {
578 MachineOperand &Src = MI.getOperand(1);
580 Register::isPhysicalRegister(MI.getOperand(0).getReg())) {
613 uint8_t Nop0 = MI.getOperand(0).getImm() + 1;
614 uint8_t Nop1 = NextMI.getOperand(0).getImm() + 1;
618 NextMI.getOperand(0).setImm(Nop0 + Nop1 - 1);
632 const MachineOperand *Dest = &MI.getOperand(0);
633 MachineOperand *Src0 = &MI.getOperand(1);
634 MachineOperand *Src1 = &MI.getOperand(2);
669 const MachineOperand &Dst = MI.getOperand(0);
670 MachineOperand &Src = MI.getOperand(1);
720 Register DstReg = MI.getOperand(0).getReg();
730 MRI.setRegAllocationHint(MI.getOperand(0).getReg(), 0, VCCReg);
lib/Target/AMDGPU/SIWholeQuadMode.cpp 359 MachineOperand &Inactive = MI.getOperand(2);
763 MI.getOperand(3).setImm(1);
843 Register Dest = MI->getOperand(0).getReg();
858 const Register Reg = MI->getOperand(0).getReg();
lib/Target/ARC/ARCBranchFinalize.cpp 115 unsigned CC = getCCForBRcc(MI->getOperand(3).getImm());
119 .addMBB(MI->getOperand(0).getMBB())
120 .addReg(MI->getOperand(1).getReg())
121 .add(MI->getOperand(2))
122 .addImm(getCCForBRcc(MI->getOperand(3).getImm()));
134 .addReg(MI->getOperand(1).getReg())
135 .add(MI->getOperand(2));
137 .addMBB(MI->getOperand(0).getMBB())
138 .addImm(MI->getOperand(3).getImm());
lib/Target/ARC/ARCExpandPseudos.cpp 64 isUInt<6>(SI.getOperand(2).getImm()) ? ARC::ADD_rru6 : ARC::ADD_rrlimm;
66 .addReg(SI.getOperand(1).getReg())
67 .addImm(SI.getOperand(2).getImm());
70 .addReg(SI.getOperand(0).getReg())
lib/Target/ARC/ARCFrameLowering.cpp 476 unsigned Amt = Old.getOperand(0).getImm();
lib/Target/ARC/ARCInstrInfo.cpp 199 TBB = I->getOperand(0).getMBB();
207 TBB = I->getOperand(0).getMBB();
208 Cond.push_back(I->getOperand(1));
209 Cond.push_back(I->getOperand(2));
210 Cond.push_back(I->getOperand(3));
lib/Target/ARC/ARCOptAddrMode.cpp 149 MachineBasicBlock *MBB = User->getOperand(BBOperandIdx).getMBB();
198 MachineOperand &Base = Ldst.getOperand(BasePos);
199 MachineOperand &Offset = Ldst.getOperand(OffsetPos);
232 if (!canFixPastUses(Uses, Add.getOperand(2), B))
254 unsigned NewBaseReg = Add.getOperand(0).getReg();
255 changeToAddrMode(Ldst, NewOpcode, NewBaseReg, Add.getOperand(2));
286 Register BaseReg = Ldst->getOperand(BasePos).getReg();
294 if (Ldst->mayStore() && Ldst->getOperand(0).isReg()) {
295 Register StReg = Ldst->getOperand(0).getReg();
296 if (Add->getOperand(0).getReg() == StReg || BaseReg == StReg) {
375 MachineOperand &MO = MI->getOperand(OffPos);
383 MI->getOperand(BasePos).setReg(NewBase);
384 MI->getOperand(OffPos).setImm(NewOffset);
425 Register ValReg = IsLoad ? Ldst->getOperand(0).getReg() : Register();
448 Register BaseReg = Ldst.getOperand(BasePos).getReg();
454 Src = Ldst.getOperand(BasePos - 1);
lib/Target/ARC/ARCRegisterInfo.cpp 107 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill()))
170 MachineOperand &FrameOp = MI.getOperand(FIOperandNum);
194 MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false /*isDef*/);
195 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
200 Offset += MI.getOperand(FIOperandNum + 1).getImm();
209 Register Reg = MI.getOperand(0).getReg();
lib/Target/ARM/A15SDOptimizer.cpp 164 if (MI->isCopy() && usesRegClass(MI->getOperand(1),
166 SReg = MI->getOperand(1).getReg();
244 return optimizeAllLanesPattern(MI, MI->getOperand(1).getReg());
248 Register DPRReg = MI->getOperand(1).getReg();
249 Register SPRReg = MI->getOperand(2).getReg();
252 MachineInstr *DPRMI = MRI->getVRegDef(MI->getOperand(1).getReg());
253 MachineInstr *SPRMI = MRI->getVRegDef(MI->getOperand(2).getReg());
265 EC->getOperand(1).getSubReg() == ARM::ssub_0) {
270 Register FullReg = SPRMI->getOperand(1).getReg();
272 MRI->getRegClass(MI->getOperand(1).getReg());
281 return optimizeAllLanesPattern(MI, MI->getOperand(2).getReg());
285 return optimizeAllLanesPattern(MI, MI->getOperand(0).getReg());
288 if (MI->isRegSequence() && usesRegClass(MI->getOperand(1),
296 if (!MI->getOperand(I).isReg())
299 Register OpReg = MI->getOperand(I).getReg();
310 NonImplicitReg = MI->getOperand(I).getReg();
316 return optimizeAllLanesPattern(MI, MI->getOperand(0).getReg());
327 if (MI->isCopy() && usesRegClass(MI->getOperand(1), &ARM::SPRRegClass))
330 if (MI->isInsertSubreg() && usesRegClass(MI->getOperand(2),
334 if (MI->isRegSequence() && usesRegClass(MI->getOperand(1), &ARM::SPRRegClass))
345 if (!Register::isVirtualRegister(MI->getOperand(1).getReg()))
347 MachineInstr *Def = MRI->getVRegDef(MI->getOperand(1).getReg());
372 Register Reg = MI->getOperand(I).getReg();
382 if (!Register::isVirtualRegister(MI->getOperand(1).getReg()))
384 MachineInstr *NewMI = MRI->getVRegDef(MI->getOperand(1).getReg());
553 bool UsesQPR = usesRegClass(MI->getOperand(0), &ARM::QPRRegClass) ||
554 usesRegClass(MI->getOperand(0), &ARM::DPairRegClass);
625 Register DPRDefReg = MI->getOperand(0).getReg();
lib/Target/ARM/ARMBaseInstrInfo.cpp 172 const MachineOperand &WB = isLoad ? MI.getOperand(1) : MI.getOperand(0);
172 const MachineOperand &WB = isLoad ? MI.getOperand(1) : MI.getOperand(0);
173 const MachineOperand &Base = MI.getOperand(2);
174 const MachineOperand &Offset = MI.getOperand(NumOps - 3);
178 unsigned OffImm = MI.getOperand(NumOps - 2).getImm();
179 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI.getOperand(NumOps - 1).getImm();
242 BuildMI(MF, MI.getDebugLoc(), get(MemOpc), MI.getOperand(0).getReg())
248 .addReg(MI.getOperand(1).getReg())
258 BuildMI(MF, MI.getDebugLoc(), get(MemOpc), MI.getOperand(0).getReg())
264 .addReg(MI.getOperand(1).getReg())
270 UpdateMI->getOperand(0).setIsDead();
278 MachineOperand &MO = MI.getOperand(i);
345 TBB = I->getOperand(0).getMBB();
353 TBB = I->getOperand(0).getMBB();
354 Cond.push_back(I->getOperand(1));
355 Cond.push_back(I->getOperand(2));
511 MachineOperand &PMO = MI.getOperand(PIdx);
513 MI.getOperand(PIdx+1).setReg(Pred[1].getReg());
549 const MachineOperand &MO = MI.getOperand(i);
1522 if (isThumb1 || !MI->getOperand(1).isDead()) {
1523 MachineOperand LDWb(MI->getOperand(1));
1532 if (isThumb1 || !MI->getOperand(0).isDead()) {
1533 MachineOperand STWb(MI->getOperand(0));
1542 MachineOperand LDBase(MI->getOperand(3));
1545 MachineOperand STBase(MI->getOperand(2));
1552 ScratchRegs.push_back(MI->getOperand(I).getReg());
1590 Register DstRegS = MI.getOperand(0).getReg();
1591 Register SrcRegS = MI.getOperand(1).getReg();
1610 if (MI.getOperand(0).isDead())
1625 MI.getOperand(0).setReg(DstRegD);
1626 MI.getOperand(1).setReg(SrcRegD);
1633 MI.getOperand(1).setIsUndef();
1638 if (MI.getOperand(1).isKill()) {
1639 MI.getOperand(1).setIsKill(false);
1730 unsigned CPI = I->getOperand(1).getIndex();
1732 I->getOperand(1).setIndex(CPI);
1733 I->getOperand(2).setImm(PCLabelId);
2166 CommutedMI->getOperand(CommutedMI->findFirstPredOperandIdx())
2192 const MachineOperand &MO = MI->getOperand(i);
2240 MachineInstr *DefMI = canFoldIntoMOVCC(MI.getOperand(2).getReg(), MRI, this);
2243 DefMI = canFoldIntoMOVCC(MI.getOperand(1).getReg(), MRI, this);
2248 MachineOperand FalseReg = MI.getOperand(Invert ? 2 : 1);
2249 Register DestReg = MI.getOperand(0).getReg();
2263 NewMI.add(DefMI->getOperand(i));
2265 unsigned CondCode = MI.getOperand(3).getImm();
2270 NewMI.add(MI.getOperand(4));
2420 assert((IsT1PushPop || (MI->getOperand(0).getReg() == ARM::SP &&
2421 MI->getOperand(1).getReg() == ARM::SP)) &&
2456 MachineOperand &MO = MI->getOperand(i);
2533 Offset += MI.getOperand(FrameRegIdx+1).getImm();
2537 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
2550 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
2551 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
2567 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal);
2576 InstrOffs = MI.getOperand(ImmIdx).getImm();
2581 InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm());
2582 if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
2588 InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm());
2589 if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
2599 InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm());
2600 if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
2607 InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm());
2608 if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
2617 InstrOffs = MI.getOperand(ImmIdx).getImm();
2636 MachineOperand &ImmOp = MI.getOperand(ImmIdx);
2641 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
2719 if (CmpMask != MI->getOperand(2).getImm())
2721 if (SrcReg == MI->getOperand(CommonUse ? 1 : 0).getReg())
3114 (SrcReg2 != 0 && SubAdd->getOperand(OpI).getReg() == SrcReg2 &&
3115 SubAdd->getOperand(OpI + 1).getReg() == SrcReg)) {
3124 std::make_pair(&((*I).getOperand(IO - 1)), NewCC));
3166 MI->getOperand(5).setReg(ARM::CPSR);
3167 MI->getOperand(5).setIsDef(true);
3208 if (!DefMI.getOperand(1).isImm())
3218 const MachineOperand &MO = DefMI.getOperand(NumOps - 1);
3228 if (UseMI.getOperand(NumOps - 1).getReg() == ARM::CPSR)
3236 uint32_t ImmVal = (uint32_t)DefMI.getOperand(1).getImm();
3249 Commute = UseMI.getOperand(2).getReg() != Reg;
3315 Register Reg1 = UseMI.getOperand(OpIdx).getReg();
3316 bool isKill = UseMI.getOperand(OpIdx).isKill();
3325 UseMI.getOperand(1).setReg(NewReg);
3326 UseMI.getOperand(1).setIsKill();
3327 UseMI.getOperand(2).ChangeToImmediate(SOImmValV2);
4775 Register Reg = MI->getOperand(0).getReg();
4949 DstReg = MI.getOperand(0).getReg();
4950 SrcReg = MI.getOperand(1).getReg();
4968 DstReg = MI.getOperand(0).getReg();
4969 SrcReg = MI.getOperand(1).getReg();
4995 DstReg = MI.getOperand(0).getReg();
4996 SrcReg = MI.getOperand(1).getReg();
5028 DstReg = MI.getOperand(0).getReg();
5029 SrcReg = MI.getOperand(1).getReg();
5202 const MachineOperand &MO = MI.getOperand(OpNum);
5381 Register Reg = CmpMI->getOperand(0).getReg();
5384 if (Pred != ARMCC::AL || CmpMI->getOperand(1).getImm() != 0)
lib/Target/ARM/ARMBaseRegisterInfo.cpp 550 for (unsigned i = 0; !MI->getOperand(i).isFI(); ++i) {
668 while (!MI.getOperand(i).isFI()) {
761 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
810 ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm();
811 Register PredReg = (PIdx == -1) ? Register() : MI.getOperand(PIdx+1).getReg();
820 MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false, false, false);
832 MI.getOperand(FIOperandNum).ChangeToRegister(ScratchReg, false, false,true);
lib/Target/ARM/ARMCallLowering.cpp 534 MIB->getOperand(CalleeIdx).setReg(constrainOperandRegClass(
lib/Target/ARM/ARMConstantIslandPass.cpp 468 if (CPE.CPEMI && CPE.CPEMI->getOperand(1).isCPI())
593 MI->getOperand(NumOps - (MI->isPredicable() ? 2 : 1));
770 if (I.getOperand(op).isCPI() || I.getOperand(op).isJTI()) {
770 if (I.getOperand(op).isCPI() || I.getOperand(op).isJTI()) {
836 unsigned CPI = I.getOperand(op).getIndex();
837 if (I.getOperand(op).isJTI()) {
1035 unsigned Size = U.CPEMI->getOperand(2).getImm();
1071 dbgs() << "User of CPE#" << CPEMI->getOperand(0).getImm()
1096 return PredMI->getOperand(0).getMBB() == Succ;
1161 if (UserMI->getOperand(j).isCPI()) {
1162 UserMI->getOperand(j).setIndex(CPEs[i].CPI);
1379 CPEMI->getOperand(2).getImm();
1400 EndInsertOffset += U.CPEMI->getOperand(2).getImm();
1427 (MI->getOperand(2).getTargetFlags() & ARMII::MO_OPTION_MASK) ==
1431 (MI->getOperand(1).getTargetFlags() & ARMII::MO_OPTION_MASK) ==
1453 unsigned Size = CPEMI->getOperand(2).getImm();
1526 .add(CPEMI->getOperand(1))
1543 if (UserMI->getOperand(i).isCPI()) {
1544 UserMI->getOperand(i).setIndex(ID);
1560 unsigned Size = CPEMI->getOperand(2).getImm();
1605 MachineBasicBlock *DestBB = MI->getOperand(0).getMBB();
1650 MachineBasicBlock *DestBB = MI->getOperand(0).getMBB();
1659 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(1).getImm();
1661 Register CCReg = MI->getOperand(2).getReg();
1681 MachineBasicBlock *NewDest = BMI->getOperand(0).getMBB();
1686 BMI->getOperand(0).setMBB(DestBB);
1687 MI->getOperand(0).setMBB(NewDest);
1688 MI->getOperand(1).setImm(CC);
1747 MI->getOperand(2).getReg() == ARM::PC &&
1751 .add(MI->getOperand(0))
1752 .add(MI->getOperand(1));
1756 MI->getOperand(2).getReg() == ARM::LR &&
1779 if (isARMLowRegister(U.MI->getOperand(0).getReg())) {
1786 if (isARMLowRegister(U.MI->getOperand(0).getReg())) {
1842 MachineBasicBlock *DestBB = Br.MI->getOperand(0).getMBB();
1906 MachineBasicBlock *DestBB = Br.MI->getOperand(0).getMBB();
1920 MIB.add(Br.MI->getOperand(0));
1935 MachineBasicBlock *DestBB = Br.MI->getOperand(0).getMBB();
1939 MBB->back().getOperand(0).getMBB();
1954 Register Reg = Cmp.MI->getOperand(0).getReg();
1975 .addMBB(DestBB, Br.MI->getOperand(0).getTargetFlags());
2007 if (I.getOperand(0).getReg() != EntryReg)
2010 if (I.getOperand(1).getReg() != BaseReg)
2047 Register EntryReg = JumpMI->getOperand(0).getReg();
2048 Register BaseReg = LEAMI->getOperand(0).getReg();
2061 const MachineOperand &MO = I->getOperand(K);
2080 const MachineOperand &MO = I->getOperand(K);
2125 Register EntryReg = JumpMI->getOperand(0).getReg();
2130 if (I->getOpcode() == ARM::t2ADDrs && I->getOperand(0).getReg() == EntryReg)
2141 const MachineOperand &MO = J->getOperand(K);
2172 MachineOperand JTOP = MI->getOperand(JTOpIdx);
2200 if (!MI->getOperand(0).isKill()) // FIXME: needed now?
2210 IdxReg = MI->getOperand(1).getReg();
2211 IdxRegKill = MI->getOperand(1).isKill();
2222 Register BaseReg = User.MI->getOperand(0).getReg();
2228 Shift->getOperand(3).getImm() != 2 ||
2229 !Shift->getOperand(2).isKill())
2231 IdxReg = Shift->getOperand(2).getReg();
2232 Register ShiftedIdxReg = Shift->getOperand(0).getReg();
2243 if (Load->getOperand(1).getReg() != BaseReg ||
2244 Load->getOperand(2).getReg() != ShiftedIdxReg ||
2245 !Load->getOperand(2).isKill())
2262 Add->getOperand(2).getReg() != BaseReg ||
2263 Add->getOperand(3).getReg() != Load->getOperand(0).getReg() ||
2263 Add->getOperand(3).getReg() != Load->getOperand(0).getReg() ||
2264 !Add->getOperand(3).isKill())
2266 if (Add->getOperand(0).getReg() != MI->getOperand(0).getReg())
2266 if (Add->getOperand(0).getReg() != MI->getOperand(0).getReg())
2274 if (Load->getOperand(0).getReg() != MI->getOperand(0).getReg())
2274 if (Load->getOperand(0).getReg() != MI->getOperand(0).getReg())
2297 .addReg(User.MI->getOperand(0).getReg(),
2301 .addImm(CPEMI->getOperand(0).getImm());
2308 NewJTMI->getOperand(0).setReg(ARM::PC);
2309 NewJTMI->getOperand(0).setIsKill(false);
2366 MachineOperand JTOP = MI->getOperand(JTOpIdx);
lib/Target/ARM/ARMExpandPseudoInsts.cpp 97 const MachineOperand &MO = OldMI.getOperand(i);
483 bool DstIsDead = MI.getOperand(OpIdx).isDead();
484 Register DstReg = MI.getOperand(OpIdx++).getReg();
512 MIB.add(MI.getOperand(OpIdx++));
515 MIB.add(MI.getOperand(OpIdx++));
516 MIB.add(MI.getOperand(OpIdx++));
527 const MachineOperand &AM6Offset = MI.getOperand(OpIdx++);
558 MIB.add(MI.getOperand(OpIdx++));
559 MIB.add(MI.getOperand(OpIdx++));
564 MachineOperand MO = MI.getOperand(SrcOpIdx);
594 MIB.add(MI.getOperand(OpIdx++));
597 MIB.add(MI.getOperand(OpIdx++));
598 MIB.add(MI.getOperand(OpIdx++));
608 const MachineOperand &AM6Offset = MI.getOperand(OpIdx++);
625 bool SrcIsKill = MI.getOperand(OpIdx).isKill();
626 bool SrcIsUndef = MI.getOperand(OpIdx).isUndef();
627 Register SrcReg = MI.getOperand(OpIdx++).getReg();
639 MIB.add(MI.getOperand(OpIdx++));
640 MIB.add(MI.getOperand(OpIdx++));
672 unsigned Lane = MI.getOperand(MI.getDesc().getNumOperands() - 3).getImm();
686 DstIsDead = MI.getOperand(OpIdx).isDead();
687 DstReg = MI.getOperand(OpIdx++).getReg();
699 MIB.add(MI.getOperand(OpIdx++));
702 MIB.add(MI.getOperand(OpIdx++));
703 MIB.add(MI.getOperand(OpIdx++));
706 MIB.add(MI.getOperand(OpIdx++));
709 MachineOperand MO = MI.getOperand(OpIdx++);
729 MIB.add(MI.getOperand(OpIdx++));
730 MIB.add(MI.getOperand(OpIdx++));
756 MIB.add(MI.getOperand(OpIdx++));
758 MachineOperand VdSrc(MI.getOperand(OpIdx++));
762 bool SrcIsKill = MI.getOperand(OpIdx).isKill();
763 Register SrcReg = MI.getOperand(OpIdx++).getReg();
769 MachineOperand VmSrc(MI.getOperand(OpIdx++));
773 MIB.add(MI.getOperand(OpIdx++));
774 MIB.add(MI.getOperand(OpIdx++));
832 Register DstReg = MI.getOperand(0).getReg();
833 bool DstIsDead = MI.getOperand(0).isDead();
835 const MachineOperand &MO = MI.getOperand(isCC ? 2 : 1);
862 LO16.add(makeImplicit(MI.getOperand(1)));
917 LO16.add(makeImplicit(MI.getOperand(1)));
935 const MachineOperand &Dest = MI.getOperand(0);
936 Register TempReg = MI.getOperand(1).getReg();
939 assert(!MI.getOperand(2).isUndef() && "cannot handle undef");
940 Register AddrReg = MI.getOperand(2).getReg();
941 Register DesiredReg = MI.getOperand(3).getReg();
942 Register NewReg = MI.getOperand(4).getReg();
1054 MachineOperand &Dest = MI.getOperand(0);
1055 Register TempReg = MI.getOperand(1).getReg();
1058 assert(!MI.getOperand(2).isUndef() && "cannot handle undef");
1059 Register AddrReg = MI.getOperand(2).getReg();
1060 Register DesiredReg = MI.getOperand(3).getReg();
1061 MachineOperand New = MI.getOperand(4);
1174 MachineOperand &JumpTarget = MBBI->getOperand(0);
1206 NewMI->addOperand(MBBI->getOperand(i));
1220 MI.getOperand(1).getReg())
1221 .add(MI.getOperand(2))
1222 .addImm(MI.getOperand(3).getImm()) // 'pred'
1223 .add(MI.getOperand(4))
1224 .add(makeImplicit(MI.getOperand(1)));
1233 MI.getOperand(1).getReg())
1234 .add(MI.getOperand(2))
1235 .addImm(MI.getOperand(3).getImm()) // 'pred'
1236 .add(MI.getOperand(4))
1238 .add(makeImplicit(MI.getOperand(1)));
1245 (MI.getOperand(1).getReg()))
1246 .add(MI.getOperand(2))
1247 .addImm(MI.getOperand(3).getImm())
1248 .addImm(MI.getOperand(4).getImm()) // 'pred'
1249 .add(MI.getOperand(5))
1251 .add(makeImplicit(MI.getOperand(1)));
1258 (MI.getOperand(1).getReg()))
1259 .add(MI.getOperand(2))
1260 .add(MI.getOperand(3))
1261 .addImm(MI.getOperand(4).getImm())
1262 .addImm(MI.getOperand(5).getImm()) // 'pred'
1263 .add(MI.getOperand(6))
1265 .add(makeImplicit(MI.getOperand(1)));
1274 MI.getOperand(1).getReg())
1275 .addImm(MI.getOperand(2).getImm())
1276 .addImm(MI.getOperand(3).getImm()) // 'pred'
1277 .add(MI.getOperand(4))
1278 .add(makeImplicit(MI.getOperand(1)));
1286 MI.getOperand(1).getReg())
1287 .addImm(MI.getOperand(2).getImm())
1288 .addImm(MI.getOperand(3).getImm()) // 'pred'
1289 .add(MI.getOperand(4))
1291 .add(makeImplicit(MI.getOperand(1)));
1300 MI.getOperand(1).getReg())
1301 .addImm(MI.getOperand(2).getImm())
1302 .addImm(MI.getOperand(3).getImm()) // 'pred'
1303 .add(MI.getOperand(4))
1305 .add(makeImplicit(MI.getOperand(1)));
1323 MI.getOperand(1).getReg())
1324 .add(MI.getOperand(2))
1325 .addImm(MI.getOperand(3).getImm())
1326 .addImm(MI.getOperand(4).getImm()) // 'pred'
1327 .add(MI.getOperand(5))
1329 .add(makeImplicit(MI.getOperand(1)));
1385 MI.getOperand(0).getReg())
1386 .add(MI.getOperand(1))
1398 MI.getOperand(0).getReg())
1399 .add(MI.getOperand(1))
1419 Register Reg = MI.getOperand(0).getReg();
1450 Register DstReg = MI.getOperand(0).getReg();
1451 bool DstIsDead = MI.getOperand(0).isDead();
1454 .add(MI.getOperand(1))
1461 .add(MI.getOperand(2));
1472 Register DstReg = MI.getOperand(0).getReg();
1473 bool DstIsDead = MI.getOperand(0).isDead();
1474 const MachineOperand &MO1 = MI.getOperand(1);
1530 Register DstReg = MI.getOperand(0).getReg();
1531 bool DstIsDead = MI.getOperand(0).isDead();
1532 const MachineOperand &MO1 = MI.getOperand(1);
1578 .add(MI.getOperand(0))
1579 .add(MI.getOperand(1))
1580 .add(MI.getOperand(2))
1593 bool DstIsDead = MI.getOperand(OpIdx).isDead();
1594 Register DstReg = MI.getOperand(OpIdx++).getReg();
1597 MIB.add(MI.getOperand(OpIdx++));
1600 MIB.add(MI.getOperand(OpIdx++));
1601 MIB.add(MI.getOperand(OpIdx++));
1624 bool SrcIsKill = MI.getOperand(OpIdx).isKill();
1625 Register SrcReg = MI.getOperand(OpIdx++).getReg();
1628 MachineOperand Dst(MI.getOperand(OpIdx++));
1632 MIB.add(MI.getOperand(OpIdx++));
1633 MIB.add(MI.getOperand(OpIdx++));
1927 Register Reg = MI.getOperand(0).getReg();
1950 for (unsigned i = 1; i < MI.getNumOperands(); ++i) MIB.add(MI.getOperand(i));
lib/Target/ARM/ARMFastISel.cpp 2920 if (MI->getNumOperands() < 3 || !MI->getOperand(2).isImm())
2922 const uint64_t Imm = MI->getOperand(2).getImm();
2940 Register ResultReg = MI->getOperand(0).getReg();
lib/Target/ARM/ARMFrameLowering.cpp 152 if (!isCalleeSavedRegister(MI.getOperand(i).getReg(), CSRegs))
159 isCalleeSavedRegister(MI.getOperand(0).getReg(), CSRegs) &&
160 MI.getOperand(1).getReg() == ARM::SP)
1518 if (!MI.getOperand(i).isFI())
2173 : (ARMCC::CondCodes)Old.getOperand(PIdx).getImm();
lib/Target/ARM/ARMHazardRecognizer.cpp 29 return MI->readsRegister(DefMI->getOperand(0).getReg(), &TRI);
lib/Target/ARM/ARMISelLowering.cpp 9490 MCSymbol *Sym = II->getOperand(0).getMCSymbol();
10017 Register dest = MI.getOperand(0).getReg();
10018 Register src = MI.getOperand(1).getReg();
10019 unsigned SizeVal = MI.getOperand(2).getImm();
10020 unsigned Align = MI.getOperand(3).getImm();
10219 MIB->getOperand(5).setReg(ARM::CPSR);
10220 MIB->getOperand(5).setIsDef(true);
10349 .addReg(MI.getOperand(0).getReg())
10411 MachineOperand Def(MI.getOperand(1));
10414 .add(MI.getOperand(2)) // Rn
10415 .add(MI.getOperand(3)) // PredImm
10416 .add(MI.getOperand(4)) // PredReg
10417 .add(MI.getOperand(0)) // Rt
10441 unsigned Offset = MI.getOperand(4).getImm();
10449 .add(MI.getOperand(0)) // Rn_wb
10450 .add(MI.getOperand(1)) // Rt
10451 .add(MI.getOperand(2)) // Rn
10453 .add(MI.getOperand(5)) // pred
10454 .add(MI.getOperand(6))
10471 MIB.add(MI.getOperand(i));
10515 .addImm(MI.getOperand(3).getImm())
10516 .addReg(MI.getOperand(4).getReg());
10530 BuildMI(*BB, BB->begin(), dl, TII->get(ARM::PHI), MI.getOperand(0).getReg())
10531 .addReg(MI.getOperand(1).getReg())
10533 .addReg(MI.getOperand(2).getReg())
10549 Register LHS1 = MI.getOperand(1).getReg();
10550 Register LHS2 = MI.getOperand(2).getReg();
10560 Register RHS1 = MI.getOperand(3).getReg();
10561 Register RHS2 = MI.getOperand(4).getReg();
10571 MachineBasicBlock *destMBB = MI.getOperand(RHSisZero ? 3 : 5).getMBB();
10573 if (MI.getOperand(0).getImm() == ARMCC::NE)
10622 Register ABSSrcReg = MI.getOperand(1).getReg();
10623 Register ABSDstReg = MI.getOperand(0).getReg();
10624 bool ABSSrcKIll = MI.getOperand(1).isKill();
10701 MI.getOperand(0).setIsDead(true);
10704 MI.getOperand(1).setIsDead(true);
10708 for (unsigned I = 0; I != MI.getOperand(4).getImm(); ++I) {
10750 MI.addOperand(MI.getOperand(1));
10756 const MachineOperand& op = MI.getOperand(i);
10784 const MachineOperand &MO = MI.getOperand(i);
10799 assert(!MI.getOperand(ccOutIdx).getReg() &&
10808 MachineOperand &MO = MI.getOperand(ccOutIdx);
lib/Target/ARM/ARMInstrInfo.cpp 120 Register Reg = MI->getOperand(0).getReg();
lib/Target/ARM/ARMInstructionSelector.cpp 213 Register DstReg = I.getOperand(0).getReg();
239 Register VReg0 = MIB->getOperand(0).getReg();
244 Register VReg1 = MIB->getOperand(1).getReg();
249 Register VReg2 = MIB->getOperand(2).getReg();
271 Register VReg0 = MIB->getOperand(0).getReg();
276 Register VReg1 = MIB->getOperand(1).getReg();
281 Register VReg2 = MIB->getOperand(2).getReg();
530 auto ResReg = MIB->getOperand(0).getReg();
535 static_cast<CmpInst::Predicate>(MIB->getOperand(1).getPredicate());
542 auto LHSReg = MIB->getOperand(2).getReg();
543 auto RHSReg = MIB->getOperand(3).getReg();
615 auto GV = MIB->getOperand(1).getGlobal();
683 MIB->getOperand(1).setTargetFlags(TargetFlags);
687 auto ResultReg = MIB->getOperand(0).getReg();
690 MIB->getOperand(0).setReg(AddressReg);
773 auto CondReg = MIB->getOperand(1).getReg();
785 auto ResReg = MIB->getOperand(0).getReg();
786 auto TrueReg = MIB->getOperand(2).getReg();
787 auto FalseReg = MIB->getOperand(3).getReg();
864 assert(MRI.getType(I.getOperand(0).getReg()).getSizeInBits() <= 32 &&
867 LLT SrcTy = MRI.getType(I.getOperand(1).getReg());
876 Register SExtResult = I.getOperand(0).getReg();
880 I.getOperand(0).setReg(AndResult);
914 auto SrcReg = I.getOperand(1).getReg();
915 auto DstReg = I.getOperand(0).getReg();
960 if (!MRI.getType(I.getOperand(0).getReg()).isPointer()) {
966 auto &Val = I.getOperand(1);
988 unsigned Size = MRI.getType(I.getOperand(0).getReg()).getSizeInBits() / 8;
996 ConstPool->getConstantPoolIndex(I.getOperand(1).getFPImm(), Alignment);
1009 auto SrcReg = I.getOperand(1).getReg();
1010 auto DstReg = I.getOperand(0).getReg();
1041 Register OpReg = I.getOperand(2).getReg();
1084 Register Reg = I.getOperand(0).getReg();
1099 Register OriginalValue = I.getOperand(0).getReg();
1102 I.getOperand(0).setReg(ValueToStore);
1134 if (!validReg(MRI, I.getOperand(0).getReg(), 1, ARM::GPRRegBankID)) {
1142 .addReg(I.getOperand(0).getReg())
1151 .add(I.getOperand(1))
1161 Register DstReg = I.getOperand(0).getReg();
lib/Target/ARM/ARMLegalizerInfo.cpp 374 Register OriginalResult = MI.getOperand(0).getReg();
390 {{MI.getOperand(1).getReg(), ArgTy},
391 {MI.getOperand(2).getReg(), ArgTy}});
397 assert(MRI.getType(MI.getOperand(2).getReg()) ==
398 MRI.getType(MI.getOperand(3).getReg()) &&
400 auto OpSize = MRI.getType(MI.getOperand(2).getReg()).getSizeInBits();
402 auto OriginalResult = MI.getOperand(0).getReg();
404 static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate());
426 {{MI.getOperand(2).getReg(), ArgTy},
427 {MI.getOperand(3).getReg(), ArgTy}});
464 MI.getOperand(1).getFPImm()->getValueAPF().bitcastToAPInt();
465 MIRBuilder.buildConstant(MI.getOperand(0).getReg(),
lib/Target/ARM/ARMLoadStoreOptimizer.cpp 507 MBBI->getOperand(MBBI->getDesc().getNumOperands() - 3);
524 MBBI->getOperand(MBBI->getDesc().getNumOperands() - 3);
1263 const MachineOperand &BaseOP = MI->getOperand(0);
1274 if (MI->getOperand(i).getReg() == Base)
1302 if (MI->getOperand(i).getReg() >= ARM::R8) {
1324 MIB.add(MI->getOperand(OpNum));
1398 if (MI->getOperand(2).getImm() != 0)
1400 if (isAM5 && ARM_AM::getAM5Offset(MI->getOperand(2).getImm()) != 0)
1405 if (MI->getOperand(0).getReg() == Base)
1440 MachineOperand &MO = MI->getOperand(0);
1452 BuildMI(MBB, MBBI, DL, TII->get(NewOpc), MI->getOperand(0).getReg())
1458 BuildMI(MBB, MBBI, DL, TII->get(NewOpc), MI->getOperand(0).getReg())
1468 BuildMI(MBB, MBBI, DL, TII->get(NewOpc), MI->getOperand(0).getReg())
1476 MachineOperand &MO = MI->getOperand(0);
1509 if (MI.getOperand(3).getImm() != 0)
1514 const MachineOperand &BaseOp = MI.getOperand(2);
1516 const MachineOperand &Reg0Op = MI.getOperand(0);
1517 const MachineOperand &Reg1Op = MI.getOperand(1);
1657 const MachineOperand &BaseOp = MI->getOperand(2);
1659 Register EvenReg = MI->getOperand(0).getReg();
1660 Register OddReg = MI->getOperand(1).getReg();
1678 MI->getOperand(0).isDead() : MI->getOperand(0).isKill();
1678 MI->getOperand(0).isDead() : MI->getOperand(0).isKill();
1679 bool EvenUndef = MI->getOperand(0).isUndef();
1681 MI->getOperand(1).isDead() : MI->getOperand(1).isKill();
1681 MI->getOperand(1).isDead() : MI->getOperand(1).isKill();
1682 bool OddUndef = MI->getOperand(1).isUndef();
1685 assert((isT2 || MI->getOperand(3).getReg() == ARM::NoRegister) &&
1785 const MachineOperand &MO = MBBI->getOperand(0);
1813 if (TRI->regsOverlap(Reg, E.MI->getOperand(0).getReg())) {
1943 MachineOperand &MO = PrevMI.getOperand(PrevMI.getNumOperands() - 1);
2121 MachineOperand &MO = I->getOperand(j);
2205 FirstReg = Op0->getOperand(0).getReg();
2206 SecondReg = Op1->getOperand(0).getReg();
2209 BaseReg = Op0->getOperand(1).getReg();
2286 MemRegs.insert(Ops[i]->getOperand(0).getReg());
2418 Register Base = MI.getOperand(1).getReg();
lib/Target/ARM/ARMLowOverheadLoops.cpp 151 MI->getOperand(0).getReg() == ARM::LR &&
152 MI->getOperand(1).getReg() == Reg &&
153 MI->getOperand(2).getImm() == ARMCC::AL;
157 unsigned CountReg = Start->getOperand(0).getReg();
190 if (Start->getOperand(0).getReg() == ARM::LR)
319 if (!End->getOperand(1).isMBB())
324 if (End->getOperand(1).getMBB() != ML->getHeader()) {
338 BBUtils->getOffsetOf(Start->getOperand(1).getMBB()) ||
339 !BBUtils->isBBInRange(Start, Start->getOperand(1).getMBB(), 4094))) {
364 MIB.add(MI->getOperand(0));
369 MachineBasicBlock *DestBB = MI->getOperand(1).getMBB();
374 MIB.add(MI->getOperand(1)); // branch target
398 MIB.add(MI->getOperand(1));
399 MIB.add(MI->getOperand(2));
405 MIB->getOperand(5).setIsDef(true);
428 MachineBasicBlock *DestBB = MI->getOperand(1).getMBB();
435 MIB.add(MI->getOperand(1)); // branch target
455 MIB.add(Start->getOperand(0));
457 MIB.add(Start->getOperand(1));
473 MIB.add(End->getOperand(0));
474 MIB.add(End->getOperand(1));
491 MachineBasicBlock *Succ = Terminator->getOperand(0).getMBB();
lib/Target/ARM/ARMOptimizeBarriersPass.cpp 71 if (MI.getOperand(0).getImm() == DMBType) {
76 DMBType = MI.getOperand(0).getImm();
81 DMBType = MI.getOperand(0).getImm();
lib/Target/ARM/MLxExpansionPass.cpp 89 Register Reg = MI->getOperand(1).getReg();
99 Reg = DefMI->getOperand(1).getReg();
105 Reg = DefMI->getOperand(2).getReg();
117 Register Reg = MI->getOperand(0).getReg();
127 Reg = UseMI->getOperand(0).getReg();
141 Register Reg = MI->getOperand(1).getReg();
154 if (DefMI->getOperand(i + 1).getMBB() == MBB) {
155 Register SrcReg = DefMI->getOperand(i).getReg();
163 Reg = DefMI->getOperand(1).getReg();
169 Reg = DefMI->getOperand(2).getReg();
272 Register DstReg = MI->getOperand(0).getReg();
273 bool DstDead = MI->getOperand(0).isDead();
274 Register AccReg = MI->getOperand(1).getReg();
275 Register Src1Reg = MI->getOperand(2).getReg();
276 Register Src2Reg = MI->getOperand(3).getReg();
277 bool Src1Kill = MI->getOperand(2).isKill();
278 bool Src2Kill = MI->getOperand(3).isKill();
279 unsigned LaneImm = HasLane ? MI->getOperand(4).getImm() : 0;
281 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NextOp).getImm();
282 Register PredReg = MI->getOperand(++NextOp).getReg();
lib/Target/ARM/MVEVPTBlockPass.cpp 159 if (registerDefinedBetween(CmpMI->getOperand(1).getReg(), std::next(CmpMI),
162 if (registerDefinedBetween(CmpMI->getOperand(2).getReg(), std::next(CmpMI),
238 MIBuilder.add(VCMP->getOperand(1));
239 MIBuilder.add(VCMP->getOperand(2));
240 MIBuilder.add(VCMP->getOperand(3));
lib/Target/ARM/Thumb1FrameLowering.cpp 456 if (MI.getOpcode() == ARM::tLDRspi && MI.getOperand(1).isFI() &&
457 isCalleeSavedRegister(MI.getOperand(0).getReg(), CSRegs))
462 Register Dst = MI.getOperand(0).getReg();
463 Register Src = MI.getOperand(1).getReg();
lib/Target/ARM/Thumb2ITBlockPass.cpp 144 assert(MI->getOperand(0).getSubReg() == 0 &&
145 MI->getOperand(1).getSubReg() == 0 &&
148 Register DstReg = MI->getOperand(0).getReg();
149 Register SrcReg = MI->getOperand(1).getReg();
173 MI->getOperand(MCID.getNumOperands() - 1).getReg() == ARM::CPSR)
lib/Target/ARM/Thumb2InstrInfo.cpp 89 unsigned Mask = MBBI->getOperand(1).getImm();
95 MBBI->getOperand(1).setImm((Mask & MaskOff) | MaskOn);
482 Offset += MI.getOperand(FrameRegIdx+1).getImm();
489 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
510 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
511 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
520 (!HasCCOut || MI.getOperand(MI.getNumOperands()-1).getReg() == 0)) {
523 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
524 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
542 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal);
555 Register OffsetReg = MI.getOperand(FrameRegIdx + 1).getReg();
557 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
562 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(0);
573 Offset += MI.getOperand(FrameRegIdx+1).getImm();
585 const MachineOperand &OffOp = MI.getOperand(FrameRegIdx+1);
599 const MachineOperand &OffOp = MI.getOperand(FrameRegIdx+1);
614 Offset += MI.getOperand(FrameRegIdx + 1).getImm();
626 Offset += MI.getOperand(FrameRegIdx + 1).getImm() * 4;
632 Offset += MI.getOperand(FrameRegIdx + 1).getImm() * 4;
643 MachineOperand &ImmOp = MI.getOperand(FrameRegIdx+1);
662 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
lib/Target/ARM/Thumb2SizeReduction.cpp 380 const MachineOperand &MO = MI->getOperand(i);
423 if (MI->getOperand(1).getReg() == ARM::SP) {
467 Register Rt = MI->getOperand(IsStore ? 1 : 0).getReg();
468 Register Rn = MI->getOperand(IsStore ? 0 : 1).getReg();
469 unsigned Offset = MI->getOperand(3).getImm();
470 unsigned PredImm = MI->getOperand(4).getImm();
471 Register PredReg = MI->getOperand(5).getReg();
499 Register BaseReg = MI->getOperand(0).getReg();
506 if (MI->getOperand(i).getReg() == BaseReg) {
522 if (!MI->getOperand(0).isKill())
527 Register BaseReg = MI->getOperand(1).getReg();
540 Register BaseReg = MI->getOperand(1).getReg();
561 OffsetReg = MI->getOperand(2).getReg();
562 OffsetKill = MI->getOperand(2).isKill();
563 OffsetInternal = MI->getOperand(2).isInternalRead();
565 if (MI->getOperand(3).getImm())
572 OffsetImm = MI->getOperand(2).getImm();
587 MIB.addReg(MI->getOperand(0).getReg(), RegState::Define | RegState::Dead);
590 MIB.add(MI->getOperand(0));
591 MIB.add(MI->getOperand(1));
605 MIB.add(MI->getOperand(OpNum));
629 if (MI->getOperand(1).getReg() != ARM::SP) {
635 unsigned Imm = MI->getOperand(2).getImm();
641 if (!isARMLowRegister(MI->getOperand(0).getReg()))
643 if (MI->getOperand(3).getImm() != ARMCC::AL)
647 MI->getOperand(MCID.getNumOperands()-1).getReg() == ARM::CPSR)
653 .add(MI->getOperand(0))
654 .add(MI->getOperand(1))
699 if (MI->getOperand(2).getImm() == 0)
705 if (MI->getOperand(1).isImm())
727 if (MI->getOperand(0).isKill())
746 Register Reg0 = MI->getOperand(0).getReg();
747 Register Reg1 = MI->getOperand(1).getReg();
750 Register Reg2 = MI->getOperand(2).getReg();
770 MI->getOperand(CommOpIdx2).getReg() != Reg0)
780 unsigned Imm = MI->getOperand(2).getImm();
785 Register Reg2 = MI->getOperand(2).getReg();
808 HasCC = (MI->getOperand(NumOps-1).getReg() == ARM::CPSR);
809 if (HasCC && MI->getOperand(NumOps-1).isDead())
824 MIB.add(MI->getOperand(0));
835 MIB.add(MI->getOperand(i));
869 const MachineOperand &MO = MI->getOperand(i);
900 HasCC = (MI->getOperand(NumOps-1).getReg() == ARM::CPSR);
901 if (HasCC && MI->getOperand(NumOps-1).isDead())
921 MIB.add(MI->getOperand(0));
922 MIB->getOperand(0).setIsKill(false);
923 MIB->getOperand(0).setIsDef(true);
924 MIB->getOperand(0).setIsDead(true);
928 MIB.add(MI->getOperand(0));
930 MIB.add(MI->getOperand(0));
951 const MachineOperand &MO = MI->getOperand(i);
lib/Target/ARM/ThumbRegisterInfo.cpp 374 Offset += MI.getOperand(FrameRegIdx+1).getImm();
375 Register DestReg = MI.getOperand(0).getReg();
386 int InstrOffs = MI.getOperand(ImmIdx).getImm();
394 MachineOperand &ImmOp = MI.getOperand(ImmIdx);
400 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
441 while (!MI.getOperand(i).isFI()) {
467 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
488 MI.getOperand(FIOperandNum). ChangeToRegister(FrameReg, false /*isDef*/);
489 MI.getOperand(FIOperandNum+1).ChangeToImmediate(Offset);
513 Register TmpReg = MI.getOperand(0).getReg();
529 MI.getOperand(FIOperandNum).ChangeToRegister(TmpReg, false, false, true);
533 MI.getOperand(FIOperandNum+1).ChangeToRegister(FrameReg, false, false,
551 MI.getOperand(FIOperandNum).ChangeToRegister(VReg, false, false, true);
555 MI.getOperand(FIOperandNum+1).ChangeToRegister(FrameReg, false, false,
lib/Target/AVR/AVRExpandPseudoInsts.cpp 143 Register DstReg = MI.getOperand(0).getReg();
144 Register SrcReg = MI.getOperand(2).getReg();
145 bool DstIsDead = MI.getOperand(0).isDead();
146 bool DstIsKill = MI.getOperand(1).isKill();
147 bool SrcIsKill = MI.getOperand(2).isKill();
148 bool ImpIsDead = MI.getOperand(3).isDead();
163 MIBHI->getOperand(3).setIsDead();
166 MIBHI->getOperand(4).setIsKill();
176 Register DstReg = MI.getOperand(0).getReg();
177 Register SrcReg = MI.getOperand(2).getReg();
178 bool DstIsDead = MI.getOperand(0).isDead();
179 bool DstIsKill = MI.getOperand(1).isKill();
180 bool SrcIsKill = MI.getOperand(2).isKill();
181 bool ImpIsDead = MI.getOperand(3).isDead();
191 MIBLO->getOperand(3).setIsDead();
199 MIBHI->getOperand(3).setIsDead();
223 Register DstReg = MI.getOperand(0).getReg();
224 bool DstIsDead = MI.getOperand(0).isDead();
225 bool SrcIsKill = MI.getOperand(1).isKill();
226 bool ImpIsDead = MI.getOperand(3).isDead();
227 unsigned Imm = MI.getOperand(2).getImm();
239 MIBLO->getOperand(3).setIsDead();
249 MIBHI->getOperand(3).setIsDead();
275 unsigned DstReg = MI.getOperand(0).getReg();
276 bool DstIsDead = MI.getOperand(0).isDead();
277 bool SrcIsKill = MI.getOperand(1).isKill();
278 bool ImpIsDead = MI.getOperand(3).isDead();
289 switch (MI.getOperand(2).getType()) {
291 const GlobalValue *GV = MI.getOperand(2).getGlobal();
292 int64_t Offs = MI.getOperand(2).getOffset();
293 unsigned TF = MI.getOperand(2).getTargetFlags();
299 unsigned Imm = MI.getOperand(2).getImm();
309 MIBHI->getOperand(3).setIsDead();
312 MIBHI->getOperand(4).setIsKill();
327 unsigned DstReg = MI.getOperand(0).getReg();
328 bool DstIsDead = MI.getOperand(0).isDead();
329 bool SrcIsKill = MI.getOperand(1).isKill();
330 bool ImpIsDead = MI.getOperand(3).isDead();
331 unsigned Imm = MI.getOperand(2).getImm();
344 MIBLO->getOperand(4).setIsKill();
352 MIBHI->getOperand(3).setIsDead();
355 MIBHI->getOperand(4).setIsKill();
390 unsigned DstReg = MI.getOperand(0).getReg();
391 bool DstIsDead = MI.getOperand(0).isDead();
392 bool DstIsKill = MI.getOperand(1).isKill();
393 bool ImpIsDead = MI.getOperand(2).isDead();
403 MIBLO->getOperand(2).setIsDead();
410 MIBHI->getOperand(2).setIsDead();
420 unsigned DstReg = MI.getOperand(0).getReg();
421 unsigned SrcReg = MI.getOperand(1).getReg();
422 bool DstIsKill = MI.getOperand(0).isKill();
423 bool SrcIsKill = MI.getOperand(1).isKill();
424 bool ImpIsDead = MI.getOperand(2).isDead();
440 MIBHI->getOperand(2).setIsDead();
443 MIBHI->getOperand(3).setIsKill();
453 unsigned DstReg = MI.getOperand(0).getReg();
454 unsigned SrcReg = MI.getOperand(1).getReg();
455 bool DstIsKill = MI.getOperand(0).isKill();
456 bool SrcIsKill = MI.getOperand(1).isKill();
457 bool ImpIsDead = MI.getOperand(2).isDead();
468 MIBLO->getOperand(3).setIsKill();
475 MIBHI->getOperand(2).setIsDead();
478 MIBHI->getOperand(3).setIsKill();
488 unsigned DstReg = MI.getOperand(0).getReg();
489 bool DstIsDead = MI.getOperand(0).isDead();
500 switch (MI.getOperand(1).getType()) {
502 const GlobalValue *GV = MI.getOperand(1).getGlobal();
503 int64_t Offs = MI.getOperand(1).getOffset();
504 unsigned TF = MI.getOperand(1).getTargetFlags();
511 const BlockAddress *BA = MI.getOperand(1).getBlockAddress();
512 unsigned TF = MI.getOperand(1).getTargetFlags();
519 unsigned Imm = MI.getOperand(1).getImm();
537 unsigned DstReg = MI.getOperand(0).getReg();
538 bool DstIsDead = MI.getOperand(0).isDead();
549 switch (MI.getOperand(1).getType()) {
551 const GlobalValue *GV = MI.getOperand(1).getGlobal();
552 int64_t Offs = MI.getOperand(1).getOffset();
553 unsigned TF = MI.getOperand(1).getTargetFlags();
560 unsigned Imm = MI.getOperand(1).getImm();
581 unsigned DstReg = MI.getOperand(0).getReg();
583 unsigned SrcReg = MI.getOperand(1).getReg();
584 bool SrcIsKill = MI.getOperand(1).isKill();
630 unsigned DstReg = MI.getOperand(0).getReg();
631 unsigned SrcReg = MI.getOperand(1).getReg();
632 bool DstIsDead = MI.getOperand(0).isDead();
633 bool SrcIsDead = MI.getOperand(1).isKill();
661 unsigned DstReg = MI.getOperand(0).getReg();
662 unsigned SrcReg = MI.getOperand(1).getReg();
663 bool DstIsDead = MI.getOperand(0).isDead();
664 bool SrcIsDead = MI.getOperand(1).isKill();
692 unsigned DstReg = MI.getOperand(0).getReg();
694 unsigned SrcReg = MI.getOperand(1).getReg();
695 unsigned Imm = MI.getOperand(2).getImm();
696 bool SrcIsKill = MI.getOperand(1).isKill();
747 unsigned DstReg = MI.getOperand(0).getReg();
749 unsigned SrcReg = MI.getOperand(1).getReg();
750 bool SrcIsKill = MI.getOperand(1).isKill();
826 auto Op1 = MI.getOperand(0);
827 auto Op2 = MI.getOperand(1);
846 auto Op1 = MI.getOperand(0);
847 auto Op2 = MI.getOperand(1);
970 unsigned SrcReg = MI.getOperand(1).getReg();
971 bool SrcIsKill = MI.getOperand(1).isKill();
981 switch (MI.getOperand(0).getType()) {
983 const GlobalValue *GV = MI.getOperand(0).getGlobal();
984 int64_t Offs = MI.getOperand(0).getOffset();
985 unsigned TF = MI.getOperand(0).getTargetFlags();
992 unsigned Imm = MI.getOperand(0).getImm();
1016 unsigned DstReg = MI.getOperand(0).getReg();
1017 unsigned SrcReg = MI.getOperand(1).getReg();
1018 bool SrcIsKill = MI.getOperand(1).isKill();
1044 unsigned DstReg = MI.getOperand(0).getReg();
1045 unsigned SrcReg = MI.getOperand(2).getReg();
1046 unsigned Imm = MI.getOperand(3).getImm();
1047 bool DstIsDead = MI.getOperand(0).isDead();
1048 bool SrcIsKill = MI.getOperand(2).isKill();
1078 unsigned DstReg = MI.getOperand(0).getReg();
1079 unsigned SrcReg = MI.getOperand(2).getReg();
1080 unsigned Imm = MI.getOperand(3).getImm();
1081 bool DstIsDead = MI.getOperand(0).isDead();
1082 bool SrcIsKill = MI.getOperand(2).isKill();
1112 unsigned DstReg = MI.getOperand(0).getReg();
1113 unsigned SrcReg = MI.getOperand(2).getReg();
1114 unsigned Imm = MI.getOperand(1).getImm();
1115 bool DstIsKill = MI.getOperand(0).isKill();
1116 bool SrcIsKill = MI.getOperand(2).isKill();
1146 unsigned Imm = MI.getOperand(1).getImm();
1147 unsigned DstReg = MI.getOperand(0).getReg();
1148 bool DstIsDead = MI.getOperand(0).isDead();
1176 unsigned Imm = MI.getOperand(0).getImm();
1177 unsigned SrcReg = MI.getOperand(1).getReg();
1178 bool SrcIsKill = MI.getOperand(1).isKill();
1207 unsigned SrcReg = MI.getOperand(0).getReg();
1208 bool SrcIsKill = MI.getOperand(0).isKill();
1232 unsigned DstReg = MI.getOperand(0).getReg();
1249 unsigned DstReg = MI.getOperand(0).getReg();
1250 bool DstIsDead = MI.getOperand(0).isDead();
1251 bool DstIsKill = MI.getOperand(1).isKill();
1252 bool ImpIsDead = MI.getOperand(2).isDead();
1269 MIBHI->getOperand(3).setIsDead();
1272 MIBHI->getOperand(4).setIsKill();
1282 unsigned DstReg = MI.getOperand(0).getReg();
1283 bool DstIsDead = MI.getOperand(0).isDead();
1284 bool DstIsKill = MI.getOperand(1).isKill();
1285 bool ImpIsDead = MI.getOperand(2).isDead();
1300 MIBLO->getOperand(2).setIsDead();
1303 MIBLO->getOperand(3).setIsKill();
1325 unsigned DstReg = MI.getOperand(0).getReg();
1326 bool DstIsDead = MI.getOperand(0).isDead();
1327 bool DstIsKill = MI.getOperand(1).isKill();
1328 bool ImpIsDead = MI.getOperand(2).isDead();
1343 MIBLO->getOperand(2).setIsDead();
1346 MIBLO->getOperand(3).setIsKill();
1368 unsigned DstReg = MI.getOperand(0).getReg();
1369 unsigned SrcReg = MI.getOperand(1).getReg();
1370 bool DstIsDead = MI.getOperand(0).isDead();
1371 bool SrcIsKill = MI.getOperand(1).isKill();
1372 bool ImpIsDead = MI.getOperand(2).isDead();
1381 MOV->getOperand(1).setIsKill();
1402 SBC->getOperand(3).setIsDead();
1405 SBC->getOperand(4).setIsKill();
1422 unsigned DstReg = MI.getOperand(0).getReg();
1423 unsigned SrcReg = MI.getOperand(1).getReg();
1424 bool DstIsDead = MI.getOperand(0).isDead();
1425 bool SrcIsKill = MI.getOperand(1).isKill();
1426 bool ImpIsDead = MI.getOperand(2).isDead();
1441 EOR->getOperand(3).setIsDead();
1451 unsigned DstReg = MI.getOperand(0).getReg();
1452 bool DstIsDead = MI.getOperand(0).isDead();
1478 unsigned SrcReg = MI.getOperand(1).getReg();
1479 bool SrcIsKill = MI.getOperand(1).isKill();
lib/Target/AVR/AVRFrameLowering.cpp 136 MI->getOperand(3).setIsDead();
212 MI->getOperand(3).setIsDead();
323 assert(MI.getOperand(0).getReg() == AVR::SP &&
327 Register SrcReg = MI.getOperand(2).getReg();
328 bool SrcIsKill = MI.getOperand(2).isKill();
355 MI.getOperand(0).setReg(AVR::R29R28);
406 New->getOperand(3).setIsDead();
lib/Target/AVR/AVRISelLowering.cpp 1522 Register ShiftAmtSrcReg = MI.getOperand(2).getReg();
1523 Register SrcReg = MI.getOperand(1).getReg();
1524 Register DstReg = MI.getOperand(0).getReg();
1571 Register SrcReg = I->getOperand(1).getReg();
1662 AVRCC::CondCodes CC = (AVRCC::CondCodes)MI.getOperand(3).getImm();
1673 BuildMI(*trueMBB, trueMBB->begin(), dl, TII.get(AVR::PHI), MI.getOperand(0).getReg())
1674 .addReg(MI.getOperand(1).getReg())
1676 .addReg(MI.getOperand(2).getReg())
lib/Target/AVR/AVRInstrInfo.cpp 297 TBB = I->getOperand(0).getMBB();
310 if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
319 TBB = I->getOperand(0).getMBB();
331 MachineBasicBlock *TargetBB = I->getOperand(0).getMBB();
356 .addMBB(UnCondBrIter->getOperand(0).getMBB());
370 TBB = I->getOperand(0).getMBB();
382 if (TBB != I->getOperand(0).getMBB()) {
lib/Target/AVR/AVRRegisterInfo.cpp 109 if (DstReg != MI.getOperand(0).getReg()) {
116 Offset += -MI.getOperand(2).getImm();
119 Offset += MI.getOperand(2).getImm();
141 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
147 Offset += MI.getOperand(FIOperandNum + 1).getImm();
154 MI.getOperand(FIOperandNum).ChangeToRegister(AVR::R29R28, false);
161 Register DstReg = MI.getOperand(0).getReg();
199 New->getOperand(3).setIsDead();
227 New->getOperand(3).setIsDead();
243 MI.getOperand(FIOperandNum).ChangeToRegister(AVR::R29R28, false);
245 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
lib/Target/AVR/AVRRelaxMemOperations.cpp 91 MachineOperand &Ptr = MI.getOperand(0);
92 MachineOperand &Src = MI.getOperand(2);
93 int64_t Imm = MI.getOperand(1).getImm();
lib/Target/BPF/BPFISelLowering.cpp 677 int CC = MI.getOperand(3).getImm();
701 Register LHS = MI.getOperand(1).getReg();
718 Register RHS = MI.getOperand(2).getReg();
725 int64_t imm32 = MI.getOperand(2).getImm();
744 BuildMI(*BB, BB->begin(), DL, TII.get(BPF::PHI), MI.getOperand(0).getReg())
745 .addReg(MI.getOperand(5).getReg())
747 .addReg(MI.getOperand(4).getReg())
lib/Target/BPF/BPFInstrInfo.cpp 46 Register DstReg = MI->getOperand(0).getReg();
47 Register SrcReg = MI->getOperand(1).getReg();
48 uint64_t CopyLen = MI->getOperand(2).getImm();
49 uint64_t Alignment = MI->getOperand(3).getImm();
50 Register ScratchReg = MI->getOperand(4).getReg();
190 TBB = I->getOperand(0).getMBB();
201 if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
209 TBB = I->getOperand(0).getMBB();
lib/Target/BPF/BPFMIPeephole.cpp 80 MachineInstr *DefInsn = MRI->getVRegDef(MovMI->getOperand(1).getReg());
90 MachineOperand &opnd = DefInsn->getOperand(i);
103 MachineOperand &opnd = DefInsn->getOperand(1);
137 MI.getOperand(2).getImm() == 32) {
138 Register DstReg = MI.getOperand(0).getReg();
139 Register ShfReg = MI.getOperand(1).getReg();
148 SllMI->getOperand(2).getImm() != 32)
154 MachineInstr *MovMI = MRI->getVRegDef(SllMI->getOperand(1).getReg());
163 Register SubReg = MovMI->getOperand(1).getReg();
261 Register dst = MI.getOperand(0).getReg();
262 Register src = MI.getOperand(1).getReg();
378 MI.getOperand(2).getImm() == 32) {
379 SrcReg = MI.getOperand(1).getReg();
381 DstReg = MI.getOperand(0).getReg();
385 MI2->getOperand(2).getImm() != 32)
389 SrcReg = MI2->getOperand(1).getReg();
395 SrcReg = MI.getOperand(1).getReg();
396 DstReg = MI.getOperand(0).getReg();
402 int64_t imm = MI.getOperand(2).getImm();
417 MachineOperand &opnd = DefMI->getOperand(i);
lib/Target/BPF/BPFMISimplifyPatchable.cpp 94 if (!MI.getOperand(0).isReg() || !MI.getOperand(1).isReg())
94 if (!MI.getOperand(0).isReg() || !MI.getOperand(1).isReg())
97 if (!MI.getOperand(2).isImm() || MI.getOperand(2).getImm())
97 if (!MI.getOperand(2).isImm() || MI.getOperand(2).getImm())
100 Register DstReg = MI.getOperand(0).getReg();
101 Register SrcReg = MI.getOperand(1).getReg();
109 const MachineOperand &MO = DefInst->getOperand(1);
117 assert(MI.getOperand(2).getImm() == 0);
lib/Target/BPF/BPFRegisterInfo.cpp 75 while (!MI.getOperand(i).isFI()) {
81 int FrameIndex = MI.getOperand(i).getIndex();
88 MI.getOperand(i).ChangeToRegister(FrameReg, false);
89 Register reg = MI.getOperand(i - 1).getReg();
97 MI.getOperand(i + 1).getImm();
108 Register reg = MI.getOperand(i - 1).getReg();
119 MI.getOperand(i).ChangeToRegister(FrameReg, false);
120 MI.getOperand(i + 1).ChangeToImmediate(Offset);
lib/Target/Hexagon/HexagonBitSimplify.cpp 978 assert(!UseI->getOperand(0).getSubReg());
979 Register DR = UseI->getOperand(0).getReg();
1220 Register DefR = UseI.getOperand(0).getReg();
1318 BitTracker::RegisterRef RD = MI->getOperand(0);
1666 BitTracker::RegisterRef RD = MI.getOperand(0);
1667 assert(MI.getOperand(0).getSubReg() == 0);
1673 BitTracker::RegisterRef RS = MI.getOperand(1);
1698 BitTracker::RegisterRef RH = MI.getOperand(1), RL = MI.getOperand(2);
1698 BitTracker::RegisterRef RH = MI.getOperand(1), RL = MI.getOperand(2);
1708 BitTracker::RegisterRef RS = MI.getOperand(SrcX);
1918 MachineOperand &ValOp = MI->getOperand(2);
1953 if (!MI->getOperand(0).isReg())
1955 MachineOperand &OffOp = MI->getOperand(1);
1964 BitTracker::RegisterRef RS = MI->getOperand(2);
2119 if (Opc == Hexagon::A2_andir && MI->getOperand(2).isImm()) {
2120 int32_t Imm = MI->getOperand(2).getImm();
2280 MachineOperand &Op1 = In->getOperand(1);
2283 if (In->getOperand(2).getImm() != ImmOp)
2286 MachineOperand &Op0 = In->getOperand(0);
2329 unsigned BN = MI->getOperand(2).getImm();
2330 BitTracker::RegisterRef RS = MI->getOperand(1);
2534 const MachineOperand &SrcOp = MI->getOperand(1);
2580 MachineOperand &CmpOp = MI->getOperand(2);
2596 BitTracker::RegisterRef SR = MI->getOperand(1);
2663 MachineOperand &Src1 = InpDef->getOperand(2);
2664 MachineOperand &Src2 = InpDef->getOperand(3);
2680 .addReg(InpDef->getOperand(1).getReg())
2722 const MachineOperand &Op0 = MI->getOperand(0);
2948 const MachineOperand &OpB = P.getOperand(i+1);
2950 LR = P.getOperand(i);
2954 PR = P.getOperand(i);
3175 if (UseI->getOperand(Idx+1).getMBB() != C.LB)
lib/Target/Hexagon/HexagonBranchRelaxation.cpp 170 TBB = FirstTerm->getOperand(HII->getCExtOpNum(*FirstTerm)).getMBB();
212 MachineOperand &MO = MI.getOperand(ExtOpNum);
lib/Target/Hexagon/HexagonCFGOptimizer.cpp 103 MI.getOperand(1).setMBB(NewTarget);
179 CondBranchTarget = MI.getOperand(1).getMBB();
192 LayoutSucc->front().getOperand(0).getMBB();
lib/Target/Hexagon/HexagonConstExtenders.cpp 331 return UseMI->getOperand(OpNum);
334 return UseMI->getOperand(OpNum);
1162 ED.Rd = MI.getOperand(OpNum-1);
1170 ED.Expr.Rs = MI.getOperand(OpNum-1);
1173 ED.Expr.Rs = MI.getOperand(OpNum-2);
1174 ED.Expr.S = MI.getOperand(OpNum-1).getImm();
1182 ED.Rd = MI.getOperand(0);
1187 ED.Rd = { MI.getOperand(0).getReg(), Hexagon::isub_hi };
1191 ED.Rd = { MI.getOperand(0).getReg(), Hexagon::isub_lo };
1195 ED.Rd = MI.getOperand(0);
1196 ED.Expr.Rs = MI.getOperand(OpNum-1);
1201 ED.Expr.Rs = MI.getOperand(OpNum-1);
1204 ED.Rd = MI.getOperand(0);
1205 ED.Expr.Rs = MI.getOperand(OpNum+1);
1209 ED.Expr.Rs = MI.getOperand(OpNum+1);
1598 .add(MI.getOperand(0))
1599 .add(MI.getOperand(1))
1605 .add(MI.getOperand(0))
1608 .add(MI.getOperand(2))
1619 .add(MI.getOperand(0))
1621 .add(MI.getOperand(1));
1632 MIB.add(MI.getOperand(i));
1658 Shift = MI.getOperand(MI.mayLoad() ? 2 : 1).getImm();
1682 MIB.add(MI.getOperand(BaseP)); // RegBase
1727 OffsetRange R = getOffsetRange(MI.getOperand(0));
1732 .add(MI.getOperand(0))
1740 OffsetRange Uses = getOffsetRange(MI.getOperand(0));
1759 const MachineOperand &RegOp = MI.getOperand(IsAddi ? 1 : 2);
1760 const MachineOperand &ImmOp = MI.getOperand(IsAddi ? 2 : 1);
1765 .add(MI.getOperand(0))
1782 Register Rs = MI.getOperand(IsSub ? 3 : 2);
1783 ExtValue V = MI.getOperand(IsSub ? 2 : 3);
1789 .add(MI.getOperand(0))
1790 .add(MI.getOperand(1))
1876 P.first->getOperand(J+1).isImm());
1877 MachineOperand &ImmOp = P.first->getOperand(J+1);
lib/Target/Hexagon/HexagonConstPropagation.cpp 856 if (PN->getOperand(N+1).getMBB() == From) {
2961 RegisterSubReg DefR(MI.getOperand(0));
2963 RegisterSubReg R2(MI.getOperand(2));
2964 RegisterSubReg R3(MI.getOperand(3));
2977 MachineOperand &Acc = MI.getOperand(1);
3000 const MachineOperand &OpR2 = Swap ? MI.getOperand(3)
3001 : MI.getOperand(2);
3013 const MachineOperand &Src1 = MI.getOperand(1);
3025 RegisterSubReg R1(MI.getOperand(1));
3026 RegisterSubReg R2(MI.getOperand(2));
3043 MachineOperand &SO = MI.getOperand(CopyOf);
3045 RegisterSubReg DefR(MI.getOperand(0));
3061 RegisterSubReg R1(MI.getOperand(1));
3062 RegisterSubReg R2(MI.getOperand(2));
3075 MachineOperand &SO = MI.getOperand(CopyOf);
3077 RegisterSubReg DefR(MI.getOperand(0));
lib/Target/Hexagon/HexagonCopyToCombine.cpp 132 const MachineOperand &Op0 = MI.getOperand(0);
133 const MachineOperand &Op1 = MI.getOperand(1);
145 const MachineOperand &Op0 = MI.getOperand(0);
146 const MachineOperand &Op1 = MI.getOperand(1);
216 return (HighRegInst.getOperand(1).isImm() &&
217 LowRegInst.getOperand(1).isImm());
239 MachineOperand &Op = MI.getOperand(I);
268 Register I2UseReg = UseReg(I2.getOperand(1));
335 Register I1UseReg = UseReg(I1.getOperand(1));
406 MachineOperand &Op = MI.getOperand(OpdIdx);
531 Register I1DestReg = I1.getOperand(0).getReg();
547 Register I2DestReg = I2->getOperand(0).getReg();
582 Register I1DestReg = I1.getOperand(0).getReg();
583 Register I2DestReg = I2.getOperand(0).getReg();
604 MachineOperand &LoOperand = IsI1Loreg ? I1.getOperand(1) : I2.getOperand(1);
604 MachineOperand &LoOperand = IsI1Loreg ? I1.getOperand(1) : I2.getOperand(1);
605 MachineOperand &HiOperand = IsI1Loreg ? I2.getOperand(1) : I1.getOperand(1);
605 MachineOperand &HiOperand = IsI1Loreg ? I2.getOperand(1) : I1.getOperand(1);
lib/Target/Hexagon/HexagonEarlyIfConv.cpp 740 MachineBasicBlock *TB = MI->getOperand(0).getMBB();
819 const MachineOperand &RO = PN->getOperand(i), &BO = PN->getOperand(i+1);
819 const MachineOperand &RO = PN->getOperand(i), &BO = PN->getOperand(i+1);
840 Register DR = PN->getOperand(0).getReg();
990 MachineOperand &UO = PN->getOperand(1);
992 Register DefR = PN->getOperand(0).getReg();
lib/Target/Hexagon/HexagonExpandCondsets.cpp 319 MachineOperand &Op = MI->getOperand(i);
497 MachineOperand &Op = DefI->getOperand(i);
671 MachineOperand &MD = MI.getOperand(0); // Definition
672 MachineOperand &MP = MI.getOperand(1); // Predicate register
687 MachineOperand &ST = MI.getOperand(2);
688 MachineOperand &SF = MI.getOperand(3);
877 MachineOperand &MO = MI.getOperand(Ox);
888 MachineOperand &MO = MI.getOperand(Ox);
943 MachineOperand &MD = TfrI.getOperand(0);
944 MachineOperand &MP = TfrI.getOperand(1);
945 MachineOperand &MS = TfrI.getOperand(2);
1080 if (RegisterRef(I->getOperand(0)) == RegisterRef(I->getOperand(2))) {
1080 if (RegisterRef(I->getOperand(0)) == RegisterRef(I->getOperand(2))) {
1193 MachineOperand &S1 = MI->getOperand(2), &S2 = MI->getOperand(3);
1193 MachineOperand &S1 = MI->getOperand(2), &S2 = MI->getOperand(3);
1201 RegisterRef RD = CI->getOperand(0);
1202 RegisterRef RP = CI->getOperand(1);
1203 MachineOperand &S1 = CI->getOperand(2), &S2 = CI->getOperand(3);
1203 MachineOperand &S1 = CI->getOperand(2), &S2 = CI->getOperand(3);
lib/Target/Hexagon/HexagonFixupHwLoops.cpp 145 assert(MII->getOperand(0).isMBB() &&
147 MachineBasicBlock *TargetBB = MII->getOperand(0).getMBB();
194 MIB.add(MII->getOperand(i));
lib/Target/Hexagon/HexagonFrameLowering.cpp 1573 Register DstR = MI->getOperand(0).getReg();
1574 Register SrcR = MI->getOperand(1).getReg();
1580 BuildMI(B, It, DL, HII.get(TargetOpcode::COPY), TmpR).add(MI->getOperand(1));
1593 if (!MI->getOperand(0).isFI())
1598 Register SrcR = MI->getOperand(2).getReg();
1599 bool IsKill = MI->getOperand(2).isKill();
1600 int FI = MI->getOperand(0).getIndex();
1626 if (!MI->getOperand(1).isFI())
1631 Register DstR = MI->getOperand(0).getReg();
1632 int FI = MI->getOperand(1).getIndex();
1657 if (!MI->getOperand(0).isFI())
1661 Register SrcR = MI->getOperand(2).getReg();
1662 bool IsKill = MI->getOperand(2).isKill();
1663 int FI = MI->getOperand(0).getIndex();
1694 if (!MI->getOperand(1).isFI())
1698 Register DstR = MI->getOperand(0).getReg();
1699 int FI = MI->getOperand(1).getIndex();
1732 if (!MI->getOperand(0).isFI())
1748 Register SrcR = MI->getOperand(2).getReg();
1751 bool IsKill = MI->getOperand(2).isKill();
1752 int FI = MI->getOperand(0).getIndex();
1792 if (!MI->getOperand(1).isFI())
1796 Register DstR = MI->getOperand(0).getReg();
1799 int FI = MI->getOperand(1).getIndex();
1832 if (!MI->getOperand(0).isFI())
1837 Register SrcR = MI->getOperand(2).getReg();
1838 bool IsKill = MI->getOperand(2).isKill();
1839 int FI = MI->getOperand(0).getIndex();
1861 if (!MI->getOperand(1).isFI())
1866 Register DstR = MI->getOperand(0).getReg();
1867 int FI = MI->getOperand(1).getIndex();
2116 const MachineOperand &Op = In.getOperand(i);
2122 if (i+1 >= n || !In.getOperand(i+1).isImm() ||
2123 In.getOperand(i+1).getImm() != 0)
2251 MachineOperand &SrcOp = SI.getOperand(2);
2302 Register DstR = MI.getOperand(0).getReg();
2303 assert(MI.getOperand(0).getSubReg() == 0);
2334 unsigned A = AI->getOperand(2).getImm();
2351 MachineOperand &RdOp = AI->getOperand(0);
2352 MachineOperand &RsOp = AI->getOperand(1);
lib/Target/Hexagon/HexagonGenMux.cpp 242 Register DR = MI->getOperand(0).getReg();
245 MachineOperand &PredOp = MI->getOperand(1);
305 MachineOperand *Src1 = &Def1.getOperand(2), *Src2 = &Def2.getOperand(2);
305 MachineOperand *Src1 = &Def1.getOperand(2), *Src2 = &Def2.getOperand(2);
lib/Target/Hexagon/HexagonGenPredicate.cpp 214 if (isPredReg(MI->getOperand(1).getReg())) {
215 RegisterSubReg RD = MI->getOperand(0);
258 assert(DefI->getOperand(0).isDef() && DefI->getOperand(1).isUse());
258 assert(DefI->getOperand(0).isDef() && DefI->getOperand(1).isUse());
259 RegisterSubReg PR = DefI->getOperand(1);
374 MachineOperand &MO = MI->getOperand(i);
404 RegisterSubReg PR = getPredRegFor(MI->getOperand(1));
413 MachineOperand &Op0 = MI->getOperand(0);
426 RegisterSubReg GPR = MI->getOperand(i);
472 RegisterSubReg DR = MI.getOperand(0);
473 RegisterSubReg SR = MI.getOperand(1);
lib/Target/Hexagon/HexagonHardwareLoops.cpp 435 if (Phi->getOperand(i+1).getMBB() != Latch)
438 Register PhiOpReg = Phi->getOperand(i).getReg();
444 Register IndReg = DI->getOperand(1).getReg();
445 MachineOperand &Opnd2 = DI->getOperand(2);
448 Register UpdReg = DI->getOperand(0).getReg();
607 MachineBasicBlock *MBB = IV_Phi->getOperand(i+1).getMBB();
609 InitialValue = &IV_Phi->getOperand(i);
611 IVReg = IV_Phi->getOperand(i).getReg(); // Want IV reg after bump.
672 const MachineOperand &Op1 = CondI->getOperand(1);
673 const MachineOperand &Op2 = CondI->getOperand(2);
1057 const MachineOperand &OPO = OnePhi->getOperand(j);
1092 const MachineOperand &MO = MI->getOperand(i);
1105 UseMI->getOperand(0).setReg(0U);
1288 MachineBasicBlock *BranchTarget = LastI->getOperand(1).getMBB();
1336 Register PredR = CmpI->getOperand(0).getReg();
1342 MachineOperand &MO = In->getOperand(i);
1393 if (isLoopFeeder(L, MBB, Phi, &(Phi->getOperand(i)), LoopFeederPhi))
1394 if (loopCountMayWrapOrUnderFlow(&(Phi->getOperand(i)), EndVal,
1446 if (Def->isCopy() && !loopCountMayWrapOrUnderFlow(&(Def->getOperand(1)),
1525 if (!checkForImmediate(DI->getOperand(1), TV))
1533 const MachineOperand &S1 = DI->getOperand(1);
1534 const MachineOperand &S2 = DI->getOperand(2);
1542 const MachineOperand &S1 = DI->getOperand(1);
1543 const MachineOperand &S3 = DI->getOperand(3);
1547 unsigned Sub2 = DI->getOperand(2).getImm();
1548 unsigned Sub4 = DI->getOperand(4).getImm();
1634 if (Phi->getOperand(i+1).getMBB() != Latch)
1637 Register PhiReg = Phi->getOperand(i).getReg();
1643 Register IndReg = DI->getOperand(1).getReg();
1644 MachineOperand &Opnd2 = DI->getOperand(2);
1647 Register UpdReg = DI->getOperand(0).getReg();
1719 MachineOperand &MO = PredDef->getOperand(i);
1768 MachineOperand &MO = PredDef->getOperand(i);
1789 nonIndI->getOperand(2).isImm() &&
1790 nonIndI->getOperand(2).getImm() == - RB.second) {
1794 nonIndMO->setReg(nonIndI->getOperand(1).getReg());
1835 MachineOperand &MO = PredDef->getOperand(i);
1906 Register PR = PN->getOperand(0).getReg();
1914 Register PredR = PN->getOperand(i).getReg();
1915 unsigned PredRSub = PN->getOperand(i).getSubReg();
1916 MachineBasicBlock *PredB = PN->getOperand(i+1).getMBB();
1929 MachineBasicBlock *PredB = PN->getOperand(i+1).getMBB();
1950 MachineOperand &MO = PN->getOperand(i+1);
lib/Target/Hexagon/HexagonHazardRecognizer.cpp 50 MachineOperand &MO = MI->getOperand(MI->getNumOperands() - 1);
lib/Target/Hexagon/HexagonInstrInfo.cpp 172 if (Opc == EndLoopOp && I->getOperand(0).getMBB() != TargetBB)
428 I->getOperand(0).isMBB();
431 MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
463 if (LastOpcode == Hexagon::J2_jump && !LastInst->getOperand(0).isMBB())
466 !SecondLastInst->getOperand(0).isMBB())
472 if (LastOpcodeHasJMP_c && !LastInst->getOperand(1).isMBB())
478 TBB = LastInst->getOperand(0).getMBB();
482 TBB = LastInst->getOperand(0).getMBB();
484 Cond.push_back(LastInst->getOperand(0));
488 TBB = LastInst->getOperand(1).getMBB();
490 Cond.push_back(LastInst->getOperand(0));
495 TBB = LastInst->getOperand(2).getMBB();
497 Cond.push_back(LastInst->getOperand(0));
498 Cond.push_back(LastInst->getOperand(1));
510 if (!SecondLastInst->getOperand(1).isMBB())
512 TBB = SecondLastInst->getOperand(1).getMBB();
514 Cond.push_back(SecondLastInst->getOperand(0));
515 FBB = LastInst->getOperand(0).getMBB();
523 TBB = SecondLastInst->getOperand(2).getMBB();
525 Cond.push_back(SecondLastInst->getOperand(0));
526 Cond.push_back(SecondLastInst->getOperand(1));
527 FBB = LastInst->getOperand(0).getMBB();
534 TBB = SecondLastInst->getOperand(0).getMBB();
543 TBB = SecondLastInst->getOperand(0).getMBB();
545 Cond.push_back(SecondLastInst->getOperand(0));
546 FBB = LastInst->getOperand(0).getMBB();
622 Loop->getOperand(0).setMBB(TBB);
664 Loop->getOperand(0).setMBB(TBB);
695 : Loop->getOperand(1).getImm();
697 LoopCount = Loop->getOperand(1).getReg();
716 Cond.push_back(NewCmp->getOperand(0));
733 int64_t TripCount = Loop->getOperand(1).getImm() + TripCountAdjust;
735 Loop->getOperand(1).setImm(TripCount);
741 Register LoopCount = Loop->getOperand(1).getReg();
747 Loop->getOperand(1).setReg(NewLoopCount);
762 LoopBB, I->getOpcode(), I->getOperand(0).getMBB(), VisitedBBs);
1030 Register Mx = MI.getOperand(MxOp).getReg();
1033 .add(MI.getOperand((HasImm ? 5 : 4)));
1034 auto MIB = BuildMI(MBB, MI, DL, get(Opc)).add(MI.getOperand(0))
1035 .add(MI.getOperand(1)).add(MI.getOperand(2)).add(MI.getOperand(3));
1035 .add(MI.getOperand(1)).add(MI.getOperand(2)).add(MI.getOperand(3));
1035 .add(MI.getOperand(1)).add(MI.getOperand(2)).add(MI.getOperand(3));
1037 MIB.add(MI.getOperand(4));
1045 MachineOperand &MD = MI.getOperand(0);
1046 MachineOperand &MS = MI.getOperand(1);
1056 BuildMI(MBB, MI, DL, get(Hexagon::A2_andir), MI.getOperand(0).getReg())
1058 .addImm(-MI.getOperand(1).getImm());
1062 Register SrcReg = MI.getOperand(1).getReg();
1063 Register DstReg = MI.getOperand(0).getReg();
1064 unsigned Kill = getKillRegState(MI.getOperand(1).isKill());
1072 Register SrcReg = MI.getOperand(1).getReg();
1073 Register DstReg = MI.getOperand(0).getReg();
1075 copyPhysReg(MBB, MI, DL, DstReg, SrcSubLo, MI.getOperand(1).isKill());
1081 Register SrcReg = MI.getOperand(1).getReg();
1082 Register DstReg = MI.getOperand(0).getReg();
1084 copyPhysReg(MBB, MI, DL, DstReg, SrcSubHi, MI.getOperand(1).isKill());
1092 Register SrcReg = MI.getOperand(2).getReg();
1099 .add(MI.getOperand(0))
1100 .addImm(MI.getOperand(1).getImm())
1103 MI1New->getOperand(0).setIsKill(false);
1105 .add(MI.getOperand(0))
1107 .addImm(MI.getOperand(1).getImm() + Offset)
1116 Register DstReg = MI.getOperand(0).getReg();
1122 .add(MI.getOperand(1))
1123 .addImm(MI.getOperand(2).getImm())
1125 MI1New->getOperand(1).setIsKill(false);
1127 .add(MI.getOperand(1))
1129 .addImm(MI.getOperand(2).getImm() + Offset)
1135 Register Reg = MI.getOperand(0).getReg();
1143 Register Reg = MI.getOperand(0).getReg();
1151 BuildMI(MBB, MI, DL, get(Hexagon::V6_veqw), MI.getOperand(0).getReg())
1158 BuildMI(MBB, MI, DL, get(Hexagon::V6_vgtw), MI.getOperand(0).getReg())
1165 Register Vd = MI.getOperand(0).getReg();
1174 Register DstReg = MI.getOperand(0).getReg();
1175 Register Src1Reg = MI.getOperand(1).getReg();
1176 Register Src2Reg = MI.getOperand(2).getReg();
1198 Register DstReg = MI.getOperand(0).getReg();
1199 Register Src1Reg = MI.getOperand(1).getReg();
1200 Register Src2Reg = MI.getOperand(2).getReg();
1201 Register Src3Reg = MI.getOperand(3).getReg();
1228 const MachineOperand &Op0 = MI.getOperand(0);
1229 const MachineOperand &Op1 = MI.getOperand(1);
1230 const MachineOperand &Op2 = MI.getOperand(2);
1231 const MachineOperand &Op3 = MI.getOperand(3);
1252 const MachineOperand &Op0 = MI.getOperand(0);
1253 const MachineOperand &Op1 = MI.getOperand(1);
1254 const MachineOperand &Op2 = MI.getOperand(2);
1255 const MachineOperand &Op3 = MI.getOperand(3);
1286 MachineOperand &Op0 = MI.getOperand(0);
1287 MachineOperand &Op1 = MI.getOperand(1);
1288 MachineOperand &Op2 = MI.getOperand(2);
1289 MachineOperand &Op3 = MI.getOperand(3);
1443 .add(MI.getOperand(1))
1444 .add(MI.getOperand(2))
1445 .add(MI.getOperand(3));
1447 .add(MI.getOperand(0))
1455 .add(MI.getOperand(1))
1456 .add(MI.getOperand(2))
1457 .add(MI.getOperand(3));
1459 .add(MI.getOperand(0))
1467 .add(MI.getOperand(1))
1468 .add(MI.getOperand(2))
1469 .add(MI.getOperand(3));
1471 .add(MI.getOperand(0))
1479 .add(MI.getOperand(1))
1480 .add(MI.getOperand(2))
1481 .add(MI.getOperand(3))
1482 .add(MI.getOperand(4));
1484 .add(MI.getOperand(0))
1492 .add(MI.getOperand(1))
1493 .add(MI.getOperand(2))
1494 .add(MI.getOperand(3))
1495 .add(MI.getOperand(4));
1497 .add(MI.getOperand(0))
1505 .add(MI.getOperand(1))
1506 .add(MI.getOperand(2))
1507 .add(MI.getOperand(3))
1508 .add(MI.getOperand(4));
1510 .add(MI.getOperand(0))
1582 MachineOperand &Op = MI.getOperand(NOp);
1595 T.add(MI.getOperand(NOp++));
1601 MI.addOperand(T->getOperand(i));
1622 MachineOperand MO = MI.getOperand(oper);
4357 MachineOperand &MO = MI.getOperand(ExtOpNum);
4375 while ((TargetPos > -1) && !MI.getOperand(TargetPos).isMBB())
4377 assert((TargetPos >= 0) && MI.getOperand(TargetPos).isMBB());
4378 MI.getOperand(TargetPos).setMBB(NewTarget);
4434 MachineOperand &Operand = MIB->getOperand(0);
lib/Target/Hexagon/HexagonNewValueJump.cpp 176 if (II->getOperand(i).isReg() &&
177 (II->getOperand(i).isUse() || II->getOperand(i).isDef())) {
177 (II->getOperand(i).isUse() || II->getOperand(i).isDef())) {
180 Register Reg = II->getOperand(i).getReg();
250 const MachineOperand &Op2 = MI.getOperand(2);
279 cmpReg1 = MI.getOperand(1).getReg();
282 cmpOp2 = MI.getOperand(2).getReg();
518 predReg = MI.getOperand(0).getReg();
547 if (!MI.getOperand(1).isMBB())
549 jmpTarget = MI.getOperand(1).getMBB();
565 if (foundJump && !foundCompare && MI.getOperand(0).isReg() &&
566 MI.getOperand(0).getReg() == predReg) {
572 isSecondOpReg = MI.getOperand(2).isReg();
584 cmpReg1 = MI.getOperand(1).getReg();
587 cmpOp2 = MI.getOperand(2).getReg();
589 cmpOp2 = MI.getOperand(2).getImm();
601 if (MI.getOperand(0).isReg() && MI.getOperand(0).isDef() &&
601 if (MI.getOperand(0).isReg() && MI.getOperand(0).isDef() &&
602 (MI.getOperand(0).getReg() == cmpReg1 ||
604 MI.getOperand(0).getReg() == (unsigned)cmpOp2))) {
606 Register feederReg = MI.getOperand(0).getReg();
705 if (cmpInstr->getOperand(0).isReg() &&
706 cmpInstr->getOperand(0).isKill())
707 cmpInstr->getOperand(0).setIsKill(false);
708 if (cmpInstr->getOperand(1).isReg() &&
709 cmpInstr->getOperand(1).isKill())
710 cmpInstr->getOperand(1).setIsKill(false);
lib/Target/Hexagon/HexagonOptAddrMode.cpp 132 MachineOperand StOp = MI.getOperand(MI.getNumOperands() - 1);
161 const MachineOperand &OffsetOp = MI.getOperand(3);
165 Register OffsetReg = MI.getOperand(2).getReg();
200 if (UseMID.mayStore() && UseMI.getOperand(2).isReg() &&
201 UseMI.getOperand(2).getReg() == MI.getOperand(0).getReg())
201 UseMI.getOperand(2).getReg() == MI.getOperand(0).getReg())
351 Register AddDefR = AddMI->getOperand(0).getReg();
362 MachineOperand BaseOp = MID.mayLoad() ? MI->getOperand(1)
363 : MI->getOperand(0);
368 MachineOperand OffsetOp = MID.mayLoad() ? MI->getOperand(2)
369 : MI->getOperand(1);
373 int64_t newOffset = OffsetOp.getImm() + AddMI->getOperand(2).getImm();
384 Register BaseReg = AddMI->getOperand(1).getReg();
412 const MachineOperand ImmOp = AddMI->getOperand(2);
413 const MachineOperand AddRegOp = AddMI->getOperand(1);
417 MachineOperand &BaseOp = MID.mayLoad() ? UseMI->getOperand(1)
418 : UseMI->getOperand(0);
419 MachineOperand &OffsetOp = MID.mayLoad() ? UseMI->getOperand(2)
420 : UseMI->getOperand(1);
498 MIB.add(OldMI->getOperand(0));
499 MIB.add(OldMI->getOperand(2));
500 MIB.add(OldMI->getOperand(3));
505 OldMI->getOperand(2).isImm()) {
509 .add(OldMI->getOperand(0));
511 int64_t Offset = ImmOp.getOffset() + OldMI->getOperand(2).getImm();
522 if (OldMI->getOperand(3).isImm() && OldMI->getOperand(3).getImm() == 0) {
522 if (OldMI->getOperand(3).isImm() && OldMI->getOperand(3).getImm() == 0) {
526 MIB.add(OldMI->getOperand(0));
527 MIB.add(OldMI->getOperand(1));
538 MIB.add(OldMI->getOperand(i));
558 MIB.add(OldMI->getOperand(1));
559 MIB.add(OldMI->getOperand(2));
561 MIB.add(OldMI->getOperand(3));
568 int64_t Offset = ImmOp.getOffset() + OldMI->getOperand(1).getImm();
570 MIB.add(OldMI->getOperand(2));
576 } else if (ImmOpNum == 1 && OldMI->getOperand(2).getImm() == 0) {
580 MIB.add(OldMI->getOperand(0));
589 MIB.add(OldMI->getOperand(i));
640 MIB.add(UseMI->getOperand(0));
641 MIB.add(AddAslMI->getOperand(2));
642 MIB.add(AddAslMI->getOperand(3));
644 MIB.addGlobalAddress(GV, UseMI->getOperand(2).getImm()+ImmOp.getOffset(),
648 MIB.add(AddAslMI->getOperand(2));
649 MIB.add(AddAslMI->getOperand(3));
651 MIB.addGlobalAddress(GV, UseMI->getOperand(1).getImm()+ImmOp.getOffset(),
653 MIB.add(UseMI->getOperand(2));
659 MIB.add(UseMI->getOperand(i));
670 const MachineOperand ImmOp = TfrMI->getOperand(1);
696 !MI->getOperand(1).isGlobal()) &&
698 !MI->getOperand(2).isImm() || HII->isConstExtended(*MI)))
727 Register DefR = MI->getOperand(0).getReg();
755 const MachineOperand &op = UseMI->getOperand(j);
lib/Target/Hexagon/HexagonPeephole.cpp 137 MachineOperand &Dst = MI.getOperand(0);
138 MachineOperand &Src = MI.getOperand(1);
155 MachineOperand &Dst = MI.getOperand(0);
156 MachineOperand &Src1 = MI.getOperand(1);
157 MachineOperand &Src2 = MI.getOperand(2);
172 MachineOperand &Dst = MI.getOperand(0);
173 MachineOperand &Src1 = MI.getOperand(1);
174 MachineOperand &Src2 = MI.getOperand(2);
186 MachineOperand &Dst = MI.getOperand(0);
187 MachineOperand &Src = MI.getOperand(1);
204 MachineOperand &Dst = MI.getOperand(0);
205 MachineOperand &Src = MI.getOperand(1);
239 MachineOperand &Op0 = MI.getOperand(0);
249 MI.getOperand(0).setReg(PeepholeSrc);
278 Register PSrc = MI.getOperand(PR).getReg();
281 QII->get(NewOp), MI.getOperand(0).getReg())
283 .add(MI.getOperand(S2))
284 .add(MI.getOperand(S1));
lib/Target/Hexagon/HexagonRDFOpt.cpp 193 if (&MI->getOperand(i) == &Op)
208 RA.Addr->setRegRef(&MI->getOperand(N), DFG);
210 RA.Addr->setRegRef(&MI->getOperand(N-1), DFG);
256 MachineOperand &Op = MI.getOperand(OpNum);
273 MI.getOperand(OpNum+2).setImm(0);
lib/Target/Hexagon/HexagonRegisterInfo.cpp 195 int FI = MI.getOperand(FIOp).getIndex();
200 int RealOffset = Offset + MI.getOperand(FIOp+1).getImm();
207 MI.getOperand(FIOp).ChangeToImmediate(RealOffset);
230 MI.getOperand(FIOp).ChangeToRegister(BP, false, false, IsKill);
231 MI.getOperand(FIOp+1).ChangeToImmediate(RealOffset);
252 Register DstReg = MI->getOperand(0).getReg();
253 Register SrcReg = MI->getOperand(1).getReg();
lib/Target/Hexagon/HexagonSplitConst32AndConst64.cpp 79 Register DestReg = MI.getOperand(0).getReg();
80 uint64_t ImmValue = MI.getOperand(1).getImm();
86 Register DestReg = MI.getOperand(0).getReg();
87 int64_t ImmValue = MI.getOperand(1).getImm();
lib/Target/Hexagon/HexagonSplitDouble.cpp 257 MachineOperand &MO = UseI->getOperand(i);
641 MachineOperand &AdrOp = MI->getOperand(AdrX);
643 MachineOperand &ValOp = Load ? MI->getOperand(0)
644 : (PostInc ? MI->getOperand(3)
645 : MI->getOperand(2));
651 int64_t Off = PostInc ? 0 : MI->getOperand(2).getImm();
660 int64_t Off = PostInc ? 0 : MI->getOperand(1).getImm();
673 int64_t Inc = Load ? MI->getOperand(3).getImm()
674 : MI->getOperand(2).getImm();
675 MachineOperand &UpdOp = Load ? MI->getOperand(1) : MI->getOperand(0);
675 MachineOperand &UpdOp = Load ? MI->getOperand(1) : MI->getOperand(0);
702 MachineOperand &Op0 = MI->getOperand(0);
703 MachineOperand &Op1 = MI->getOperand(1);
729 MachineOperand &Op0 = MI->getOperand(0);
730 MachineOperand &Op1 = MI->getOperand(1);
731 MachineOperand &Op2 = MI->getOperand(2);
759 MachineOperand &Op0 = MI->getOperand(0);
760 MachineOperand &Op1 = MI->getOperand(1);
781 MachineOperand &Op0 = MI->getOperand(0);
782 MachineOperand &Op1 = MI->getOperand(1);
783 MachineOperand &Op2 = MI->getOperand(2);
905 MachineOperand &Op0 = MI->getOperand(0);
906 MachineOperand &Op1 = MI->getOperand(1);
907 MachineOperand &Op2 = MI->getOperand(2);
908 MachineOperand &Op3 = MI->getOperand(3);
1005 Register DstR = MI->getOperand(0).getReg();
lib/Target/Hexagon/HexagonStoreWidening.cpp 405 MachineOperand &SO = MI->getOperand(2); // Source.
431 MachineOperand &MR = FirstSt->getOperand(0);
432 int64_t Off = FirstSt->getOperand(1).getImm();
454 MachineOperand &MR = FirstSt->getOperand(0);
455 int64_t Off = FirstSt->getOperand(1).getImm();
lib/Target/Hexagon/HexagonSubtarget.cpp 347 Register DReg = DstInst->getOperand(0).getReg();
351 const MachineOperand &MO = DDst->getOperand(OpNum);
426 const MachineOperand &MO = SrcI->getOperand(OpNum);
434 const MachineOperand &MO = DstI->getOperand(OpNum);
lib/Target/Hexagon/HexagonVExtract.cpp 72 Register ExtIdxR = ExtI->getOperand(2).getReg();
73 unsigned ExtIdxS = ExtI->getOperand(2).getSubReg();
79 unsigned V = DI->getOperand(1).getImm();
91 .add(ExtI->getOperand(2))
114 Register VecR = MI.getOperand(1).getReg();
142 unsigned SR = ExtI->getOperand(1).getSubReg();
143 assert(ExtI->getOperand(1).getReg() == VecR);
153 Register ExtR = ExtI->getOperand(0).getReg();
lib/Target/Hexagon/HexagonVLIWPacketizer.cpp 387 if (MO.isReg() && MO.getReg() == MI->getOperand(0).getReg())
481 MachineOperand &Off = MI.getOperand(1);
502 MachineOperand &Off = MI.getOperand(1);
519 Register Reg = MI.getOperand(BPI).getReg();
520 if (Reg != MJ.getOperand(BPJ).getReg())
533 int64_t Offset = MI.getOperand(OPI).getImm();
537 MI.getOperand(OPI).setImm(Offset + Incr);
548 MI.getOperand(OP).setImm(ChangedOffset);
1353 const MachineOperand &NOp0 = NextMI.getOperand(0);
1354 const MachineOperand &NOp1 = NextMI.getOperand(1);
1356 if (NOp1.isReg() && I.getOperand(0).getReg() == NOp1.getReg())
1562 if (I.getOperand(0).getReg() == HRI->getStackRegister()) {
lib/Target/Hexagon/RDFGraph.cpp 1291 MachineOperand &Op = In.getOperand(OpN);
1319 MachineOperand &Op = In.getOperand(OpN);
1336 MachineOperand &Op = In.getOperand(OpN);
1365 MachineOperand &Op = In.getOperand(OpN);
lib/Target/Lanai/LanaiDelaySlotFiller.cpp 108 assert(RI->getOpcode() == Lanai::LDW_RI && RI->getOperand(0).isReg() &&
109 RI->getOperand(0).getReg() == Lanai::FP &&
110 RI->getOperand(1).isReg() &&
111 RI->getOperand(1).getReg() == Lanai::FP &&
112 RI->getOperand(2).isImm() && RI->getOperand(2).getImm() == -8);
112 RI->getOperand(2).isImm() && RI->getOperand(2).getImm() == -8);
115 RI->getOperand(0).isReg() &&
116 RI->getOperand(0).getReg() == Lanai::SP &&
117 RI->getOperand(1).isReg() &&
118 RI->getOperand(1).getReg() == Lanai::FP);
204 const MachineOperand &MO = MI->getOperand(I);
233 const MachineOperand &MO = MI->getOperand(I);
lib/Target/Lanai/LanaiFrameLowering.cpp 75 Register Dst = MI.getOperand(0).getReg();
76 Register Src = MI.getOperand(1).getReg();
lib/Target/Lanai/LanaiInstrInfo.cpp 210 ((OI->getOperand(1).getReg() == SrcReg &&
211 OI->getOperand(2).getReg() == SrcReg2) ||
212 (OI->getOperand(1).getReg() == SrcReg2 &&
213 OI->getOperand(2).getReg() == SrcReg)))
220 OI->getOperand(1).getReg() == SrcReg &&
221 OI->getOperand(2).getImm() == ImmValue)
382 if (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
383 Sub->getOperand(2).getReg() == SrcReg) {
385 std::make_pair(&((*I).getOperand(IO - 1)), NewCC));
472 const MachineOperand &MO = MI->getOperand(i);
498 MachineInstr *DefMI = canFoldIntoSelect(MI.getOperand(1).getReg(), MRI);
501 DefMI = canFoldIntoSelect(MI.getOperand(2).getReg(), MRI);
506 MachineOperand FalseReg = MI.getOperand(Invert ? 1 : 2);
507 Register DestReg = MI.getOperand(0).getReg();
520 NewMI.add(DefMI->getOperand(i));
522 unsigned CondCode = MI.getOperand(3).getImm();
592 TrueBlock = Instruction->getOperand(0).getMBB();
605 if (MBB.isLayoutSuccessor(Instruction->getOperand(0).getMBB())) {
613 TrueBlock = Instruction->getOperand(0).getMBB();
626 static_cast<LPCC::CondCode>(Instruction->getOperand(1).getImm());
630 TrueBlock = Instruction->getOperand(0).getMBB();
lib/Target/Lanai/LanaiMemAluCombiner.cpp 241 MachineOperand Dest = MemInstr->getOperand(0);
242 MachineOperand Base = MemInstr->getOperand(1);
243 MachineOperand MemOffset = MemInstr->getOperand(2);
244 MachineOperand AluOffset = AluInstr->getOperand(2);
292 MachineOperand &Dest = AluIter->getOperand(0);
293 MachineOperand &Op1 = AluIter->getOperand(1);
294 MachineOperand &Op2 = AluIter->getOperand(2);
331 MachineOperand *Base = &MemInstr->getOperand(1);
332 MachineOperand *Offset = &MemInstr->getOperand(2);
372 MachineOperand AluOperand = MBBIter->getOperand(3);
373 unsigned int DestReg = MBBIter->getOperand(0).getReg(),
374 BaseReg = MBBIter->getOperand(1).getReg();
lib/Target/Lanai/LanaiRegisterInfo.cpp 148 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
151 MI.getOperand(FIOperandNum + 1).getImm();
203 MI.getOperand(0).getReg())
215 assert((MI.getOperand(3).getImm() == LPAC::ADD) &&
217 MI.getOperand(3).setImm(LPAC::SUB);
222 MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, /*isDef=*/false);
223 MI.getOperand(FIOperandNum + 1)
239 MI.getOperand(0).getReg())
244 MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, /*isDef=*/false);
245 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
lib/Target/MSP430/MSP430BranchSelector.cpp 128 MachineBasicBlock *DestBB = MI->getOperand(0).getMBB();
192 Cond.push_back(MI->getOperand(1));
lib/Target/MSP430/MSP430FrameLowering.cpp 101 MI->getOperand(3).setIsDead();
164 MI->getOperand(3).setIsDead();
173 MI->getOperand(3).setIsDead();
264 New->getOperand(3).setIsDead();
280 New->getOperand(3).setIsDead();
lib/Target/MSP430/MSP430ISelLowering.cpp 1452 Register SrcReg = MI.getOperand(1).getReg();
1453 Register DstReg = MI.getOperand(0).getReg();
1489 Register ShiftAmtSrcReg = MI.getOperand(2).getReg();
1490 Register SrcReg = MI.getOperand(1).getReg();
1491 Register DstReg = MI.getOperand(0).getReg();
1586 .addImm(MI.getOperand(3).getImm());
1600 BuildMI(*BB, BB->begin(), dl, TII.get(MSP430::PHI), MI.getOperand(0).getReg())
1601 .addReg(MI.getOperand(2).getReg())
1603 .addReg(MI.getOperand(1).getReg())
lib/Target/MSP430/MSP430InstrInfo.cpp 206 TBB = I->getOperand(0).getMBB();
217 if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
225 TBB = I->getOperand(0).getMBB();
232 static_cast<MSP430CC::CondCodes>(I->getOperand(1).getImm());
239 TBB = I->getOperand(0).getMBB();
251 if (TBB != I->getOperand(0).getMBB())
lib/Target/MSP430/MSP430RegisterInfo.cpp 113 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
127 Offset += MI.getOperand(FIOperandNum + 1).getImm();
136 MI.getOperand(FIOperandNum).ChangeToRegister(BasePtr, false);
142 Register DstReg = MI.getOperand(0).getReg();
153 MI.getOperand(FIOperandNum).ChangeToRegister(BasePtr, false);
154 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
lib/Target/Mips/MicroMipsSizeReduction.cpp 310 if (!MI->getOperand(Op).isImm())
312 Imm = MI->getOperand(Op).getImm();
364 Register reg = MI->getOperand(0).getReg();
371 if (ReduceToLwp && (MI->getOperand(0).getReg() == MI->getOperand(1).getReg()))
371 if (ReduceToLwp && (MI->getOperand(0).getReg() == MI->getOperand(1).getReg()))
406 Register Reg1 = MI1->getOperand(0).getReg();
407 Register Reg2 = MI2->getOperand(0).getReg();
448 if (!IsSP(MI->getOperand(1)))
478 Register Reg1 = MI1->getOperand(1).getReg();
479 Register Reg2 = MI2->getOperand(1).getReg();
500 if (!isMMThreeBitGPRegister(MI->getOperand(0)) ||
501 !isMMThreeBitGPRegister(MI->getOperand(1)) ||
502 !isMMThreeBitGPRegister(MI->getOperand(2)))
517 if (!isMMThreeBitGPRegister(MI->getOperand(0)) || !IsSP(MI->getOperand(1)))
517 if (!isMMThreeBitGPRegister(MI->getOperand(0)) || !IsSP(MI->getOperand(1)))
535 if (!IsSP(MI->getOperand(0)) || !IsSP(MI->getOperand(1)))
535 if (!IsSP(MI->getOperand(0)) || !IsSP(MI->getOperand(1)))
549 if (!isMMThreeBitGPRegister(MI->getOperand(0)) ||
550 !isMMThreeBitGPRegister(MI->getOperand(1)))
564 if (!isMMSourceRegister(MI->getOperand(0)) ||
565 !isMMThreeBitGPRegister(MI->getOperand(1)))
624 Register RegDstMI1 = MI1->getOperand(0).getReg();
625 Register RegSrcMI1 = MI1->getOperand(1).getReg();
636 Register RegDstMI2 = MI2->getOperand(0).getReg();
637 Register RegSrcMI2 = MI2->getOperand(1).getReg();
659 if (!isMMThreeBitGPRegister(MI->getOperand(0)) ||
660 !isMMThreeBitGPRegister(MI->getOperand(1)) ||
661 !isMMThreeBitGPRegister(MI->getOperand(2)))
664 if (!(MI->getOperand(0).getReg() == MI->getOperand(2).getReg()) &&
664 if (!(MI->getOperand(0).getReg() == MI->getOperand(2).getReg()) &&
665 !(MI->getOperand(0).getReg() == MI->getOperand(1).getReg()))
665 !(MI->getOperand(0).getReg() == MI->getOperand(1).getReg()))
714 MIB.add(MI->getOperand(2));
717 MIB.add(MI->getOperand(0));
718 MIB.add(MI->getOperand(2));
722 if (MI->getOperand(0).getReg() == MI->getOperand(2).getReg()) {
722 if (MI->getOperand(0).getReg() == MI->getOperand(2).getReg()) {
723 MIB.add(MI->getOperand(0));
724 MIB.add(MI->getOperand(1));
725 MIB.add(MI->getOperand(2));
727 MIB.add(MI->getOperand(0));
728 MIB.add(MI->getOperand(2));
729 MIB.add(MI->getOperand(1));
737 MIB.add(MI->getOperand(0));
738 MIB.add(MI2->getOperand(0));
739 MIB.add(MI->getOperand(1));
741 MIB.add(MI2->getOperand(1));
743 MIB.add(MI->getOperand(2));
745 MIB.add(MI2->getOperand(0));
746 MIB.add(MI->getOperand(0));
747 MIB.add(MI2->getOperand(1));
749 MIB.add(MI->getOperand(1));
751 MIB.add(MI2->getOperand(2));
lib/Target/Mips/Mips16ISelLowering.cpp 547 .addReg(MI.getOperand(3).getReg())
563 BuildMI(*BB, BB->begin(), DL, TII->get(Mips::PHI), MI.getOperand(0).getReg())
564 .addReg(MI.getOperand(1).getReg())
566 .addReg(MI.getOperand(2).getReg())
610 .addReg(MI.getOperand(3).getReg())
611 .addReg(MI.getOperand(4).getReg());
627 BuildMI(*BB, BB->begin(), DL, TII->get(Mips::PHI), MI.getOperand(0).getReg())
628 .addReg(MI.getOperand(1).getReg())
630 .addReg(MI.getOperand(2).getReg())
676 .addReg(MI.getOperand(3).getReg())
677 .addImm(MI.getOperand(4).getImm());
693 BuildMI(*BB, BB->begin(), DL, TII->get(Mips::PHI), MI.getOperand(0).getReg())
694 .addReg(MI.getOperand(1).getReg())
696 .addReg(MI.getOperand(2).getReg())
711 Register regX = MI.getOperand(0).getReg();
712 Register regY = MI.getOperand(1).getReg();
713 MachineBasicBlock *target = MI.getOperand(2).getMBB();
728 Register regX = MI.getOperand(0).getReg();
729 int64_t imm = MI.getOperand(1).getImm();
730 MachineBasicBlock *target = MI.getOperand(2).getMBB();
761 Register CC = MI.getOperand(0).getReg();
762 Register regX = MI.getOperand(1).getReg();
763 Register regY = MI.getOperand(2).getReg();
780 Register CC = MI.getOperand(0).getReg();
781 Register regX = MI.getOperand(1).getReg();
782 int64_t Imm = MI.getOperand(2).getImm();
lib/Target/Mips/Mips16InstrInfo.cpp 359 MachineOperand &MO = II->getOperand(i);
375 MachineOperand &MO = II->getOperand(i);
lib/Target/Mips/Mips16RegisterInfo.cpp 109 if ((MI.getNumOperands()> OpNo+2) && MI.getOperand(OpNo+2).isReg())
110 FrameReg = MI.getOperand(OpNo+2).getReg();
127 Offset += MI.getOperand(OpNo + 1).getImm();
143 MI.getOperand(OpNo).ChangeToRegister(FrameReg, false, false, IsKill);
144 MI.getOperand(OpNo + 1).ChangeToImmediate(Offset);
lib/Target/Mips/MipsBranchExpansion.cpp 343 MachineOperand &MO = Br->getOperand(I);
lib/Target/Mips/MipsCallLowering.cpp 578 CalleeGlobalValue->getOperand(1).setTargetFlags(MipsII::MO_GOT_CALL);
lib/Target/Mips/MipsConstantIslandPass.cpp 740 if (MI.getOperand(op).isCPI()) {
768 unsigned CPI = MI.getOperand(op).getIndex();
948 unsigned Size = U.CPEMI->getOperand(2).getImm();
984 dbgs() << "User of CPE#" << CPEMI->getOperand(0).getImm()
1007 return PredMI->getOperand(0).getMBB() == Succ;
1059 unsigned CPI = CPEMI->getOperand(1).getIndex();
1076 if (UserMI->getOperand(j).isCPI()) {
1077 UserMI->getOperand(j).setIndex(CPEs[i].CPI);
1115 unsigned CPI = CPEMI->getOperand(1).getIndex();
1132 if (UserMI->getOperand(j).isCPI()) {
1133 UserMI->getOperand(j).setIndex(CPEs[i].CPI);
1276 CPEMI->getOperand(2).getImm();
1297 EndInsertOffset += U.CPEMI->getOperand(2).getImm();
1313 unsigned CPI = CPEMI->getOperand(1).getIndex();
1314 unsigned Size = CPEMI->getOperand(2).getImm();
1402 if (UserMI->getOperand(i).isCPI()) {
1403 UserMI->getOperand(i).setIndex(ID);
1418 unsigned Size = CPEMI->getOperand(2).getImm();
1487 MachineBasicBlock *DestBB = MI->getOperand(TargetOperand).getMBB();
1506 MachineBasicBlock *DestBB = MI->getOperand(0).getMBB();
1546 MachineBasicBlock *DestBB = MI->getOperand(TargetOperand).getMBB();
1587 BMI->getOperand(BMITargetOperand).getMBB();
1593 BMI->getOperand(BMITargetOperand).setMBB(DestBB);
1594 MI->getOperand(TargetOperand).setMBB(NewDest);
1619 .addReg(MI->getOperand(0).getReg())
1652 MachineOperand& Literal = I->getOperand(1);
1660 I->getOperand(2).ChangeToImmediate(index);
lib/Target/Mips/MipsDelaySlotFiller.cpp 328 const MachineOperand &MO = Filler->getOperand(I);
710 baseRegNeedsLoadStoreMask(CurrI->getOperand(AddrIdx).getReg())) ||
lib/Target/Mips/MipsExpandPseudo.cpp 102 Register Dest = I->getOperand(0).getReg();
103 Register Ptr = I->getOperand(1).getReg();
104 Register Mask = I->getOperand(2).getReg();
105 Register ShiftCmpVal = I->getOperand(3).getReg();
106 Register Mask2 = I->getOperand(4).getReg();
107 Register ShiftNewVal = I->getOperand(5).getReg();
108 Register ShiftAmnt = I->getOperand(6).getReg();
109 Register Scratch = I->getOperand(7).getReg();
110 Register Scratch2 = I->getOperand(8).getReg();
243 Register Dest = I->getOperand(0).getReg();
244 Register Ptr = I->getOperand(1).getReg();
245 Register OldVal = I->getOperand(2).getReg();
246 Register NewVal = I->getOperand(3).getReg();
247 Register Scratch = I->getOperand(4).getReg();
377 Register Dest = I->getOperand(0).getReg();
378 Register Ptr = I->getOperand(1).getReg();
379 Register Incr = I->getOperand(2).getReg();
380 Register Mask = I->getOperand(3).getReg();
381 Register Mask2 = I->getOperand(4).getReg();
382 Register ShiftAmnt = I->getOperand(5).getReg();
383 Register OldVal = I->getOperand(6).getReg();
384 Register BinOpRes = I->getOperand(7).getReg();
385 Register StoreVal = I->getOperand(8).getReg();
516 Register OldVal = I->getOperand(0).getReg();
517 Register Ptr = I->getOperand(1).getReg();
518 Register Incr = I->getOperand(2).getReg();
519 Register Scratch = I->getOperand(3).getReg();
lib/Target/Mips/MipsFrameLowering.cpp 143 int64_t Amount = I->getOperand(0).getImm();
lib/Target/Mips/MipsISelLowering.cpp 1273 MachineOperand &Divisor = MI.getOperand(2);
1282 MIB->getOperand(0).setSubReg(Mips::sub_32);
1478 Register OldVal = MI.getOperand(0).getReg();
1479 Register Ptr = MI.getOperand(1).getReg();
1480 Register Incr = MI.getOperand(2).getReg();
1582 Register Dest = MI.getOperand(0).getReg();
1583 Register Ptr = MI.getOperand(1).getReg();
1584 Register Incr = MI.getOperand(2).getReg();
1739 Register Dest = MI.getOperand(0).getReg();
1740 Register Ptr = MI.getOperand(1).getReg();
1741 Register OldVal = MI.getOperand(2).getReg();
1742 Register NewVal = MI.getOperand(3).getReg();
1791 Register Dest = MI.getOperand(0).getReg();
1792 Register Ptr = MI.getOperand(1).getReg();
1793 Register CmpVal = MI.getOperand(2).getReg();
1794 Register NewVal = MI.getOperand(3).getReg();
4458 .addReg(MI.getOperand(1).getReg())
4463 .addReg(MI.getOperand(1).getReg())
4481 BuildMI(*BB, BB->begin(), DL, TII->get(Mips::PHI), MI.getOperand(0).getReg())
4482 .addReg(MI.getOperand(2).getReg())
4484 .addReg(MI.getOperand(3).getReg())
4533 .addReg(MI.getOperand(2).getReg())
4551 BuildMI(*BB, BB->begin(), DL, TII->get(Mips::PHI), MI.getOperand(0).getReg())
4552 .addReg(MI.getOperand(3).getReg())
4554 .addReg(MI.getOperand(5).getReg())
4556 BuildMI(*BB, BB->begin(), DL, TII->get(Mips::PHI), MI.getOperand(1).getReg())
4557 .addReg(MI.getOperand(4).getReg())
4559 .addReg(MI.getOperand(6).getReg())
lib/Target/Mips/MipsInstrInfo.cpp 238 TBB = LastInst->getOperand(0).getMBB();
261 TBB = SecondLastInst->getOperand(0).getMBB();
273 FBB = LastInst->getOperand(0).getMBB();
451 if (I->getOperand(1).getReg() == Subtarget.getABI().GetZeroReg())
466 (I->getOperand(0).isReg() &&
467 (I->getOperand(0).getReg() == Mips::ZERO ||
468 I->getOperand(0).getReg() == Mips::ZERO_64)) &&
469 (I->getOperand(1).isReg() &&
470 (I->getOperand(1).getReg() == Mips::ZERO ||
471 I->getOperand(1).getReg() == Mips::ZERO_64)))
484 else if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
484 else if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
491 else if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
491 else if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
495 if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
495 if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
499 if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
499 if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
509 if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
509 if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
513 if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
513 if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
519 if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
519 if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
523 if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
523 if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
651 MIB.add(I->getOperand(J));
660 const MachineOperand &MO = I->getOperand(J);
671 MIB.add(I->getOperand(J));
lib/Target/Mips/MipsInstructionSelector.cpp 89 Register DstReg = I.getOperand(0).getReg();
168 const Register DestReg = I.getOperand(0).getReg();
243 (RBI.getRegBank(I.getOperand(0).getReg(), MRI, TRI)->getID() ==
246 .add(I.getOperand(0))
247 .add(I.getOperand(1))
248 .add(I.getOperand(2));
251 Mul->getOperand(3).setIsDead(true);
252 Mul->getOperand(4).setIsDead(true);
271 .add(I.getOperand(1))
272 .add(I.getOperand(2));
277 .addDef(I.getOperand(0).getReg())
287 .add(I.getOperand(0))
288 .add(I.getOperand(1))
289 .add(I.getOperand(2));
299 .add(I.getOperand(0))
300 .add(I.getOperand(1))
306 .add(I.getOperand(0))
308 .add(I.getOperand(1));
320 .addUse(I.getOperand(2).getReg())
328 .addUse(I.getOperand(0).getReg())
338 .addJumpTableIndex(I.getOperand(1).getIndex(), MipsII::MO_ABS_LO)
346 LW->getOperand(0).setReg(DestTmp);
367 .add(I.getOperand(0));
371 const Register DestReg = I.getOperand(0).getReg();
392 MachineOperand BaseAddr = I.getOperand(1);
401 MachineInstr *Addr = MRI.getVRegDef(I.getOperand(1).getReg());
403 MachineInstr *Offset = MRI.getVRegDef(Addr->getOperand(2).getReg());
405 APInt OffsetValue = Offset->getOperand(1).getCImm()->getValue();
407 BaseAddr = Addr->getOperand(1);
414 .add(I.getOperand(0))
432 .add(I.getOperand(1))
433 .add(I.getOperand(2));
439 .addDef(I.getOperand(0).getReg())
450 .add(I.getOperand(0))
451 .add(I.getOperand(2))
452 .add(I.getOperand(1))
453 .add(I.getOperand(3));
458 .add(I.getOperand(0));
461 MRI.setRegClass(MI->getOperand(0).getReg(),
463 MRI.getType(I.getOperand(0).getReg()).getSizeInBits(),
464 *RBI.getRegBank(I.getOperand(0).getReg(), MRI, TRI),
470 if (!materialize32BitImm(I.getOperand(0).getReg(),
471 I.getOperand(1).getCImm()->getValue(), B))
478 const APFloat &FPimm = I.getOperand(1).getFPImm()->getValueAPF();
480 unsigned Size = MRI.getType(I.getOperand(0).getReg()).getSizeInBits();
489 B.buildInstr(Mips::MTC1, {I.getOperand(0).getReg()}, {GPRReg});
504 {I.getOperand(0).getReg()}, {GPRRegLow, GPRRegHigh});
513 unsigned Size = MRI.getType(I.getOperand(0).getReg()).getSizeInBits();
518 .add(I.getOperand(0))
519 .add(I.getOperand(1));
523 unsigned FromSize = MRI.getType(I.getOperand(1).getReg()).getSizeInBits();
524 unsigned ToSize = MRI.getType(I.getOperand(0).getReg()).getSizeInBits();
538 .addUse(I.getOperand(1).getReg());
543 .addDef(I.getOperand(0).getReg())
552 const llvm::GlobalValue *GVal = I.getOperand(1).getGlobal();
555 .addDef(I.getOperand(0).getReg())
563 if (I.getOperand(1).getTargetFlags() == MipsII::MO_GOT_CALL)
564 LWGOT->getOperand(2).setTargetFlags(MipsII::MO_GOT_CALL);
566 LWGOT->getOperand(2).setTargetFlags(MipsII::MO_GOT);
575 LWGOT->getOperand(0).setReg(LWGOTDef);
579 .addDef(I.getOperand(0).getReg())
582 ADDiu->getOperand(2).setTargetFlags(MipsII::MO_ABS_LO);
592 LUi->getOperand(1).setTargetFlags(MipsII::MO_ABS_HI);
598 .addDef(I.getOperand(0).getReg())
601 ADDiu->getOperand(2).setTargetFlags(MipsII::MO_ABS_LO);
611 .addDef(I.getOperand(0).getReg())
614 .addJumpTableIndex(I.getOperand(1).getIndex(), MipsII::MO_GOT)
621 .addDef(I.getOperand(0).getReg())
622 .addJumpTableIndex(I.getOperand(1).getIndex(), MipsII::MO_ABS_HI);
641 Register ICMPReg = I.getOperand(0).getReg();
643 Register LHS = I.getOperand(2).getReg();
644 Register RHS = I.getOperand(3).getReg();
646 static_cast<CmpInst::Predicate>(I.getOperand(1).getPredicate());
710 I.getOperand(1).getPredicate())) {
762 unsigned Size = MRI.getType(I.getOperand(2).getReg()).getSizeInBits();
767 .addUse(I.getOperand(2).getReg())
768 .addUse(I.getOperand(3).getReg())
774 .addDef(I.getOperand(0).getReg())
803 .addUse(I.getOperand(0).getReg())
lib/Target/Mips/MipsLegalizerInfo.cpp 256 Register Dst = MI.getOperand(0).getReg();
257 Register Src = MI.getOperand(1).getReg();
304 .add(MI.getOperand(0))
305 .add(MI.getOperand(2))
306 .add(MI.getOperand(3))
319 .add(MI.getOperand(0))
320 .add(MI.getOperand(2))
321 .add(MI.getOperand(3));
331 .add(MI.getOperand(0))
332 .add(MI.getOperand(2));
364 MIRBuilder.buildLoad(Tmp, MI.getOperand(2),
367 MIRBuilder.buildStore(Tmp, MI.getOperand(1),
lib/Target/Mips/MipsOptimizePICCall.cpp 128 MachineOperand &MO = MI.getOperand(0);
154 Register SrcReg = I->getOperand(0).getReg();
158 I->getOperand(0).setReg(DstReg);
167 MVT::SimpleValueType Ty = getRegTy(MI.getOperand(0).getReg(), MF);
171 MachineOperand &MO = MI.getOperand(I);
290 unsigned Flags = DefMI->getOperand(2).getTargetFlags();
lib/Target/Mips/MipsRegisterBankInfo.cpp 179 !Register::isPhysicalRegister(NonCopyInstr->getOperand(0).getReg()))
180 addDefUses(NonCopyInstr->getOperand(0).getReg(), MRI);
201 !Register::isPhysicalRegister(Ret->getOperand(0).getReg()) &&
202 MRI.hasOneUse(Ret->getOperand(0).getReg())) {
203 Ret = &(*MRI.use_instr_begin(Ret->getOperand(0).getReg()));
215 !Register::isPhysicalRegister(Ret->getOperand(1).getReg()))
216 Ret = MRI.getVRegDef(Ret->getOperand(1).getReg());
627 Register Dest = MI.getOperand(0).getReg();
lib/Target/Mips/MipsRegisterInfo.cpp 266 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
lib/Target/Mips/MipsSEFrameLowering.cpp 171 assert(I->getOperand(0).isReg() && I->getOperand(1).isFI());
171 assert(I->getOperand(0).isReg() && I->getOperand(1).isFI());
175 Register Dst = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex();
175 Register Dst = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex();
186 assert(I->getOperand(0).isReg() && I->getOperand(1).isFI());
186 assert(I->getOperand(0).isReg() && I->getOperand(1).isFI());
190 Register Src = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex();
190 Register Src = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex();
193 .addReg(Src, getKillRegState(I->getOperand(0).isKill()));
204 assert(I->getOperand(0).isReg() && I->getOperand(1).isFI());
204 assert(I->getOperand(0).isReg() && I->getOperand(1).isFI());
209 Register Dst = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex();
209 Register Dst = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex();
229 assert(I->getOperand(0).isReg() && I->getOperand(1).isFI());
229 assert(I->getOperand(0).isReg() && I->getOperand(1).isFI());
234 Register Src = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex();
234 Register Src = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex();
235 unsigned SrcKill = getKillRegState(I->getOperand(0).isKill());
245 Register Src = I->getOperand(1).getReg();
261 unsigned Dst = I->getOperand(0).getReg(), Src = I->getOperand(1).getReg();
261 unsigned Dst = I->getOperand(0).getReg(), Src = I->getOperand(1).getReg();
267 unsigned SrcKill = getKillRegState(I->getOperand(1).isKill());
305 if (I->getNumOperands() == 4 && I->getOperand(3).isReg()
306 && I->getOperand(3).getReg() == Mips::SP) {
307 Register DstReg = I->getOperand(0).getReg();
308 Register LoReg = I->getOperand(1).getReg();
309 Register HiReg = I->getOperand(2).getReg();
326 TII.storeRegToStack(MBB, I, LoReg, I->getOperand(1).isKill(), FI, RC,
328 TII.storeRegToStack(MBB, I, HiReg, I->getOperand(2).isKill(), FI, RC,
345 const MachineOperand &Op1 = I->getOperand(1);
346 const MachineOperand &Op2 = I->getOperand(2);
349 Register DstReg = I->getOperand(0).getReg();
370 if (I->getNumOperands() == 4 && I->getOperand(3).isReg()
371 && I->getOperand(3).getReg() == Mips::SP) {
372 Register DstReg = I->getOperand(0).getReg();
lib/Target/Mips/MipsSEISelDAGToDAG.cpp 54 unsigned Mask = MI.getOperand(1).getImm();
182 if (MI.getOperand(0).isGlobal() &&
183 MI.getOperand(0).getGlobal()->getGlobalIdentifier() == "_mcount")
189 if (MI.getOperand(2).isMCSymbol() &&
190 MI.getOperand(2).getMCSymbol()->getName() == "_mcount")
194 if (MI.getOperand(3).isMCSymbol() &&
195 MI.getOperand(3).getMCSymbol()->getName() == "_mcount")
lib/Target/Mips/MipsSEISelLowering.cpp 3079 MI.getOperand(0).getReg())
3132 .addReg(MI.getOperand(1).getReg())
3148 MI.getOperand(0).getReg())
3174 Register Fd = MI.getOperand(0).getReg();
3175 Register Ws = MI.getOperand(1).getReg();
3176 unsigned Lane = MI.getOperand(2).getImm();
3219 Register Fd = MI.getOperand(0).getReg();
3220 Register Ws = MI.getOperand(1).getReg();
3221 unsigned Lane = MI.getOperand(2).getImm() * 2;
3249 Register Wd = MI.getOperand(0).getReg();
3250 Register Wd_in = MI.getOperand(1).getReg();
3251 unsigned Lane = MI.getOperand(2).getImm();
3252 Register Fs = MI.getOperand(3).getReg();
3285 Register Wd = MI.getOperand(0).getReg();
3286 Register Wd_in = MI.getOperand(1).getReg();
3287 unsigned Lane = MI.getOperand(2).getImm();
3288 Register Fs = MI.getOperand(3).getReg();
3331 Register Wd = MI.getOperand(0).getReg();
3332 Register SrcVecReg = MI.getOperand(1).getReg();
3333 Register LaneReg = MI.getOperand(2).getReg();
3334 Register SrcValReg = MI.getOperand(3).getReg();
3445 Register Wd = MI.getOperand(0).getReg();
3446 Register Fs = MI.getOperand(1).getReg();
3480 Register Wd = MI.getOperand(0).getReg();
3481 Register Fs = MI.getOperand(1).getReg();
3514 Register Ws = MI.getOperand(0).getReg();
3515 Register Rt = MI.getOperand(1).getReg();
3523 MI.getOperand(1).isReg() ? RegInfo.getRegClass(MI.getOperand(1).getReg())
3523 MI.getOperand(1).isReg() ? RegInfo.getRegClass(MI.getOperand(1).getReg())
3569 Register Wd = MI.getOperand(0).getReg();
3575 MI.getOperand(1).isReg() ? RegInfo.getRegClass(MI.getOperand(1).getReg())
3575 MI.getOperand(1).isReg() ? RegInfo.getRegClass(MI.getOperand(1).getReg())
3585 MIB.add(MI.getOperand(i));
3663 Register Wd = MI.getOperand(0).getReg();
3664 Register Fs = MI.getOperand(1).getReg();
3768 Register Fd = MI.getOperand(0).getReg();
3769 Register Ws = MI.getOperand(1).getReg();
3831 BuildMI(*BB, MI, DL, TII->get(Mips::FEXP2_W), MI.getOperand(0).getReg())
3833 .addReg(MI.getOperand(1).getReg());
3860 BuildMI(*BB, MI, DL, TII->get(Mips::FEXP2_D), MI.getOperand(0).getReg())
3862 .addReg(MI.getOperand(1).getReg());
lib/Target/Mips/MipsSEInstrInfo.cpp 715 BuildMI(MBB, I, I->getDebugLoc(), get(NewOpc), I->getOperand(0).getReg());
730 const MachineOperand &SrcLo = I->getOperand(1), &SrcHi = I->getOperand(2);
730 const MachineOperand &SrcLo = I->getOperand(1), &SrcHi = I->getOperand(2);
737 Register DstReg = I->getOperand(0).getReg();
753 const MachineOperand &Dst = I->getOperand(0), &Src = I->getOperand(1);
753 const MachineOperand &Dst = I->getOperand(0), &Src = I->getOperand(1);
776 Register DstReg = I->getOperand(0).getReg();
777 Register SrcReg = I->getOperand(1).getReg();
778 unsigned N = I->getOperand(2).getImm();
818 Register DstReg = I->getOperand(0).getReg();
819 unsigned LoReg = I->getOperand(1).getReg(), HiReg = I->getOperand(2).getReg();
819 unsigned LoReg = I->getOperand(1).getReg(), HiReg = I->getOperand(2).getReg();
886 Register OffsetReg = I->getOperand(0).getReg();
887 Register TargetReg = I->getOperand(1).getReg();
lib/Target/Mips/MipsSERegisterInfo.cpp 204 Offset += MI.getOperand(OpNo + 1).getImm();
214 getLoadStoreOffsetSizeInBits(MI.getOpcode(), MI.getOperand(OpNo - 1));
256 MI.getOperand(OpNo).ChangeToRegister(FrameReg, false, false, IsKill);
257 MI.getOperand(OpNo + 1).ChangeToImmediate(Offset);
lib/Target/NVPTX/NVPTXInstrInfo.cpp 111 TBB = LastInst.getOperand(0).getMBB();
115 TBB = LastInst.getOperand(1).getMBB();
116 Cond.push_back(LastInst.getOperand(0));
133 TBB = SecondLastInst.getOperand(1).getMBB();
134 Cond.push_back(SecondLastInst.getOperand(0));
135 FBB = LastInst.getOperand(0).getMBB();
143 TBB = SecondLastInst.getOperand(0).getMBB();
lib/Target/NVPTX/NVPTXPeephole.cpp 81 auto &Op = Root.getOperand(1);
96 auto &BaseAddrOp = GenericAddrDef->getOperand(1);
109 auto &Prev = *MRI.getUniqueVRegDef(Root.getOperand(1).getReg());
113 Root.getOperand(0).getReg())
115 .add(Prev.getOperand(2));
120 if (MRI.hasOneNonDBGUse(Prev.getOperand(0).getReg())) {
lib/Target/NVPTX/NVPTXPrologEpilogPass.cpp 61 if (!MI.getOperand(i).isFI())
72 TFI.getFrameIndexReference(MF, MI.getOperand(0).getIndex(), Reg);
73 MI.getOperand(0).ChangeToRegister(Reg, /*isDef=*/false);
74 MI.getOperand(0).setIsDebug();
77 MI.getOperand(3).setMetadata(DIExpr);
lib/Target/NVPTX/NVPTXRegisterInfo.cpp 118 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
122 MI.getOperand(FIOperandNum + 1).getImm();
125 MI.getOperand(FIOperandNum).ChangeToRegister(NVPTX::VRFrame, false);
126 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
lib/Target/NVPTX/NVPTXReplaceImageHandles.cpp 86 MachineOperand &TexHandle = MI.getOperand(4);
90 MachineOperand &SampHandle = MI.getOperand(5);
100 MachineOperand &SurfHandle = MI.getOperand(VecSize);
107 MachineOperand &SurfHandle = MI.getOperand(0);
114 MachineOperand &Handle = MI.getOperand(1);
153 assert(TexHandleDef.getOperand(6).isSymbol() && "Load is not a symbol!");
154 StringRef Sym = TexHandleDef.getOperand(6).getSymbolName();
169 assert(TexHandleDef.getOperand(1).isGlobal() && "Load is not a global!");
170 const GlobalValue *GV = TexHandleDef.getOperand(1).getGlobal();
178 bool Res = findIndexForHandle(TexHandleDef.getOperand(1), MF, Idx);
lib/Target/PowerPC/PPCBranchCoalescing.cpp 403 MachineOperand &MO = PHIInst.getOperand(i);
lib/Target/PowerPC/PPCBranchSelector.cpp 304 if (I->getOpcode() == PPC::BCC && !I->getOperand(2).isImm())
305 Dest = I->getOperand(2).getMBB();
307 !I->getOperand(1).isImm())
308 Dest = I->getOperand(1).getMBB();
311 !I->getOperand(0).isImm())
312 Dest = I->getOperand(0).getMBB();
338 PPC::Predicate Pred = (PPC::Predicate)I->getOperand(0).getImm();
339 Register CRReg = I->getOperand(1).getReg();
345 Register CRBit = I->getOperand(0).getReg();
348 Register CRBit = I->getOperand(0).getReg();
lib/Target/PowerPC/PPCEarlyReturn.cpp 77 if (J->getOperand(0).getMBB() == &ReturnMBB) {
89 if (J->getOperand(2).getMBB() == &ReturnMBB) {
93 .addImm(J->getOperand(0).getImm())
94 .addReg(J->getOperand(1).getReg())
103 if (J->getOperand(1).getMBB() == &ReturnMBB) {
109 .addReg(J->getOperand(0).getReg())
123 if (J->getOperand(i).isMBB() &&
124 J->getOperand(i).getMBB() == &ReturnMBB)
lib/Target/PowerPC/PPCExpandISEL.cpp 183 if (!useSameRegister(PrevPushedMI->getOperand(3), MI->getOperand(3)))
183 if (!useSameRegister(PrevPushedMI->getOperand(3), MI->getOperand(3)))
205 MachineOperand &Dest = (*I)->getOperand(0);
206 MachineOperand &TrueValue = (*I)->getOperand(1);
207 MachineOperand &FalseValue = (*I)->getOperand(2);
272 MachineOperand &Dest = (*MI)->getOperand(0);
273 MachineOperand &TrueValue = (*MI)->getOperand(1);
274 MachineOperand &FalseValue = (*MI)->getOperand(2);
422 .add(BIL.back()->getOperand(3))
439 MachineOperand &Dest = MI->getOperand(0); // location to store to
440 MachineOperand &TrueValue = MI->getOperand(1); // Value to store if
442 MachineOperand &FalseValue = MI->getOperand(2); // Value to store if
444 MachineOperand &ConditionRegister = MI->getOperand(3); // Condition
lib/Target/PowerPC/PPCFastISel.cpp 2309 unsigned MB = MI->getOperand(3).getImm();
2320 unsigned MB = MI->getOperand(3).getImm();
2355 Register ResultReg = MI->getOperand(0).getReg();
lib/Target/PowerPC/PPCFrameLowering.cpp 381 Register SrcReg = MI.getOperand(1).getReg();
382 Register DstReg = MI.getOperand(0).getReg();
573 MachineOperand &MO = MBBI->getOperand(I);
1476 MachineOperand &StackAdjust = MBBI->getOperand(1);
1737 MachineOperand &JumpTarget = MBBI->getOperand(0);
1742 assert(MBBI->getOperand(0).isReg() && "Expecting register operand.");
1746 MachineOperand &JumpTarget = MBBI->getOperand(0);
1750 MachineOperand &JumpTarget = MBBI->getOperand(0);
1755 assert(MBBI->getOperand(0).isReg() && "Expecting register operand.");
1759 MachineOperand &JumpTarget = MBBI->getOperand(0);
2315 if (int CalleeAmt = I->getOperand(1).getImm()) {
lib/Target/PowerPC/PPCISelLowering.cpp10335 Register dest = MI.getOperand(0).getReg();
10336 Register ptrA = MI.getOperand(1).getReg();
10337 Register ptrB = MI.getOperand(2).getReg();
10338 Register incr = MI.getOperand(3).getReg();
10439 Register dest = MI.getOperand(0).getReg();
10440 Register ptrA = MI.getOperand(1).getReg();
10441 Register ptrB = MI.getOperand(2).getReg();
10442 Register incr = MI.getOperand(3).getReg();
10622 Register DstReg = MI.getOperand(0).getReg();
10679 Register BufReg = MI.getOperand(1).getReg();
10783 Register BufReg = MI.getOperand(0).getReg();
10894 Cond.push_back(MI.getOperand(4));
10897 Cond.push_back(MI.getOperand(1));
10900 TII->insertSelect(*BB, MI, dl, MI.getOperand(0).getReg(), Cond,
10901 MI.getOperand(2).getReg(), MI.getOperand(3).getReg());
10901 MI.getOperand(2).getReg(), MI.getOperand(3).getReg());
10969 .addReg(MI.getOperand(1).getReg())
10972 unsigned SelectPred = MI.getOperand(4).getImm();
10975 .addReg(MI.getOperand(1).getReg())
10991 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::PHI), MI.getOperand(0).getReg())
10992 .addReg(MI.getOperand(3).getReg())
10994 .addReg(MI.getOperand(2).getReg())
11025 Register LoReg = MI.getOperand(0).getReg();
11026 Register HiReg = MI.getOperand(1).getReg();
11174 Register dest = MI.getOperand(0).getReg();
11175 Register ptrA = MI.getOperand(1).getReg();
11176 Register ptrB = MI.getOperand(2).getReg();
11177 Register oldval = MI.getOperand(3).getReg();
11178 Register newval = MI.getOperand(4).getReg();
11253 Register dest = MI.getOperand(0).getReg();
11254 Register ptrA = MI.getOperand(1).getReg();
11255 Register ptrB = MI.getOperand(2).getReg();
11256 Register oldval = MI.getOperand(3).getReg();
11257 Register newval = MI.getOperand(4).getReg();
11434 Register Dest = MI.getOperand(0).getReg();
11435 Register Src1 = MI.getOperand(1).getReg();
11436 Register Src2 = MI.getOperand(2).getReg();
11471 .addReg(MI.getOperand(1).getReg())
11474 MI.getOperand(0).getReg())
11482 MI.getOperand(0).getReg())
11486 unsigned Imm = MI.getOperand(1).getImm();
11489 MI.getOperand(0).getReg())
11493 Register OldFPSCRReg = MI.getOperand(0).getReg();
11507 unsigned Mode = MI.getOperand(1).getImm();
11574 Register OldFPSCRReg = MI.getOperand(0).getReg();
11587 MachineOperand SrcOp = MI.getOperand(1);
lib/Target/PowerPC/PPCInstrInfo.cpp 382 if (MI.getOperand(3).getImm() != 0)
395 Register Reg0 = MI.getOperand(0).getReg();
396 Register Reg1 = MI.getOperand(1).getReg();
397 Register Reg2 = MI.getOperand(2).getReg();
398 unsigned SubReg1 = MI.getOperand(1).getSubReg();
399 unsigned SubReg2 = MI.getOperand(2).getSubReg();
400 bool Reg1IsKill = MI.getOperand(1).isKill();
401 bool Reg2IsKill = MI.getOperand(2).isKill();
409 assert(MI.getOperand(0).getSubReg() == SubReg1 && "Tied subreg mismatch");
415 unsigned MB = MI.getOperand(4).getImm();
416 unsigned ME = MI.getOperand(5).getImm();
425 Register Reg0 = ChangeReg0 ? Reg2 : MI.getOperand(0).getReg();
426 bool Reg0IsDead = MI.getOperand(0).isDead();
436 MI.getOperand(0).setReg(Reg2);
437 MI.getOperand(0).setSubReg(SubReg2);
439 MI.getOperand(2).setReg(Reg1);
440 MI.getOperand(1).setReg(Reg2);
441 MI.getOperand(2).setSubReg(SubReg1);
442 MI.getOperand(1).setSubReg(SubReg2);
443 MI.getOperand(2).setIsKill(Reg1IsKill);
444 MI.getOperand(1).setIsKill(Reg2IsKill);
447 MI.getOperand(4).setImm((ME + 1) & 31);
448 MI.getOperand(5).setImm((MB - 1) & 31);
514 MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
530 if (!LastInst.getOperand(0).isMBB())
532 TBB = LastInst.getOperand(0).getMBB();
535 if (!LastInst.getOperand(2).isMBB())
538 TBB = LastInst.getOperand(2).getMBB();
539 Cond.push_back(LastInst.getOperand(0));
540 Cond.push_back(LastInst.getOperand(1));
543 if (!LastInst.getOperand(1).isMBB())
546 TBB = LastInst.getOperand(1).getMBB();
548 Cond.push_back(LastInst.getOperand(0));
551 if (!LastInst.getOperand(1).isMBB())
554 TBB = LastInst.getOperand(1).getMBB();
556 Cond.push_back(LastInst.getOperand(0));
560 if (!LastInst.getOperand(0).isMBB())
564 TBB = LastInst.getOperand(0).getMBB();
571 if (!LastInst.getOperand(0).isMBB())
575 TBB = LastInst.getOperand(0).getMBB();
596 if (!SecondLastInst.getOperand(2).isMBB() ||
597 !LastInst.getOperand(0).isMBB())
599 TBB = SecondLastInst.getOperand(2).getMBB();
600 Cond.push_back(SecondLastInst.getOperand(0));
601 Cond.push_back(SecondLastInst.getOperand(1));
602 FBB = LastInst.getOperand(0).getMBB();
606 if (!SecondLastInst.getOperand(1).isMBB() ||
607 !LastInst.getOperand(0).isMBB())
609 TBB = SecondLastInst.getOperand(1).getMBB();
611 Cond.push_back(SecondLastInst.getOperand(0));
612 FBB = LastInst.getOperand(0).getMBB();
616 if (!SecondLastInst.getOperand(1).isMBB() ||
617 !LastInst.getOperand(0).isMBB())
619 TBB = SecondLastInst.getOperand(1).getMBB();
621 Cond.push_back(SecondLastInst.getOperand(0));
622 FBB = LastInst.getOperand(0).getMBB();
627 if (!SecondLastInst.getOperand(0).isMBB() ||
628 !LastInst.getOperand(0).isMBB())
632 TBB = SecondLastInst.getOperand(0).getMBB();
636 FBB = LastInst.getOperand(0).getMBB();
641 if (!SecondLastInst.getOperand(0).isMBB() ||
642 !LastInst.getOperand(0).isMBB())
646 TBB = SecondLastInst.getOperand(0).getMBB();
650 FBB = LastInst.getOperand(0).getMBB();
657 if (!SecondLastInst.getOperand(0).isMBB())
659 TBB = SecondLastInst.getOperand(0).getMBB();
1331 if (!DefMI.getOperand(1).isImm())
1333 if (DefMI.getOperand(1).getImm() != 0)
1348 if (UseMI.getOperand(UseIdx).isReg() &&
1349 UseMI.getOperand(UseIdx).getReg() == Reg)
1384 UseMI.getOperand(UseIdx).setReg(ZeroReg);
1465 MachineBasicBlock *MBB = MI.getOperand(0).getMBB();
1473 MachineBasicBlock *MBB = MI.getOperand(0).getMBB();
1481 MachineBasicBlock *MBB = MI.getOperand(0).getMBB();
1568 const MachineOperand &MO = MI.getOperand(i);
1643 Register CRReg = CmpInstr.getOperand(0).getReg();
1703 PPC::Predicate Pred = (PPC::Predicate)UseMI->getOperand(0).getImm();
1710 unsigned SubIdx = UseMI->getOperand(3).getSubReg();
1768 PPC::Predicate Pred = (PPC::Predicate)UseMI->getOperand(0).getImm();
1791 PredsToUpdate.push_back(std::make_pair(&(UseMI->getOperand(0)), Pred));
1865 ShouldSwap = SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
1866 Sub->getOperand(2).getReg() == SrcReg;
1879 PPC::Predicate Pred = (PPC::Predicate) UseMI->getOperand(0).getImm();
1885 PredsToUpdate.push_back(std::make_pair(&(UseMI->getOperand(0)),
1889 unsigned NewSubReg = UseMI->getOperand(3).getSubReg();
1898 SubRegsToUpdate.push_back(std::make_pair(&(UseMI->getOperand(3)),
1932 Register GPRRes = MI->getOperand(0).getReg();
1933 int64_t SH = MI->getOperand(2).getImm();
1934 int64_t MB = MI->getOperand(3).getImm();
1935 int64_t ME = MI->getOperand(4).getImm();
1962 MI->getOperand(2).setImm(Mask);
1965 } else if (MIOpC == PPC::RLDICL && MI->getOperand(2).getImm() == 0) {
1966 int64_t MB = MI->getOperand(3).getImm();
1971 MI->getOperand(2).setImm(Mask);
2117 Register TargetReg = MI.getOperand(0).getReg();
2154 assert(MI.getOperand(2).isReg() &&
2155 isAnImmediateOperand(MI.getOperand(1)) &&
2166 assert(MI.getOperand(2).isReg() && MI.getOperand(1).isReg() &&
2166 assert(MI.getOperand(2).isReg() && MI.getOperand(1).isReg() &&
2174 assert(MI.getOperand(2).isReg() && MI.getOperand(1).isReg() &&
2174 assert(MI.getOperand(2).isReg() && MI.getOperand(1).isReg() &&
2179 Register TargetReg = MI.getOperand(0).getReg();
2189 Register SrcReg = MI.getOperand(0).getReg();
2201 Register TargetReg = MI.getOperand(0).getReg();
2209 Register SrcReg = MI.getOperand(0).getReg();
2221 auto Val = MI.getOperand(0).getReg();
2272 assert(MI.getOperand(OpNo).isReg() && "Operand must be a REG");
2274 Register InUseReg = MI.getOperand(OpNo).getReg();
2275 MI.getOperand(OpNo).ChangeToImmediate(Imm);
2285 MachineOperand &MO = MI.getOperand(UseOpIdx);
2352 if (!MI.getOperand(i).isReg())
2354 Register Reg = MI.getOperand(i).getReg();
2382 bool IsVFReg = (MI.getNumOperands() && MI.getOperand(0).isReg())
2383 ? isVFRegister(MI.getOperand(0).getReg())
2390 MI.getOperand(1).getReg() == MI.getOperand(2).getReg())
2390 MI.getOperand(1).getReg() == MI.getOperand(2).getReg())
2393 MachineOperand &MO = MI.getOperand(i);
2396 Register Reg = MI.getOperand(i).getReg();
2467 MachineOperand &MO = MI.getOperand(Index);
2478 EndMI.getOperand(UseIndex).setIsKill(true);
2600 unsigned ToBeChangedReg = ADDIMI->getOperand(0).getReg();
2601 unsigned ScaleReg = ADDMI->getOperand(ScaleRegIdx).getReg();
2624 ADDIMI->getOperand(2).setImm(OffsetAddi + OffsetImm);
2628 MI.getOperand(III.ImmOpNo)
2630 ADDMI->getOperand(ScaleRegIdx).isKill());
2632 MI.getOperand(III.OpNoForForwarding)
2652 Imm = ADDIMI.getOperand(2).getImm();
2682 if (!instrHasImmForm(XFormOpcode, isVFRegister(MI.getOperand(0).getReg()),
2689 MachineOperand ImmOperand = MI.getOperand(III.ImmOpNo);
2690 MachineOperand RegOperand = MI.getOperand(III.OpNoForForwarding);
2712 MachineOperand &MO = ADDMI->getOperand(Index);
2765 bool IsForwardingOperandKilled = MI.getOperand(ForwardingOperand).isKill();
2767 Register ForwardingOperandReg = MI.getOperand(ForwardingOperand).getReg();
2772 bool IsVFReg = MI.getOperand(0).isReg()
2773 ? isVFRegister(MI.getOperand(0).getReg())
2785 !DefMI->getOperand(1).isImm())
2788 int64_t Immediate = DefMI->getOperand(1).getImm();
2823 Register DefReg = MI.getOperand(0).getReg();
2824 int64_t Comparand = MI.getOperand(2).getImm();
2832 unsigned CRSubReg = CompareUseMI.getOperand(3).getSubReg();
2833 Register TrueReg = CompareUseMI.getOperand(1).getReg();
2834 Register FalseReg = CompareUseMI.getOperand(2).getReg();
2872 int64_t Addend = MI.getOperand(2).getImm();
2886 int64_t SH = MI.getOperand(2).getImm();
2887 int64_t MB = MI.getOperand(3).getImm();
2910 int64_t SH = MI.getOperand(2).getImm();
2911 int64_t MB = MI.getOperand(3).getImm();
2912 int64_t ME = MI.getOperand(4).getImm();
2937 int64_t LogicalImm = MI.getOperand(2).getImm();
2965 if (MRI->hasOneUse(DefMI->getOperand(0).getReg()))
2966 DefMI->getOperand(1).setImm(NewImm);
2970 else if (MRI->use_empty(MI.getOperand(0).getReg())) {
3412 MachineOperand MOp1 = MI.getOperand(MinOp);
3413 MachineOperand MOp2 = MI.getOperand(MaxOp);
3428 MOps.push_back(MI.getOperand(i));
3472 if (MI.getOperand(III.ZeroIsSpecialOrig).getReg() != PPC::ZERO &&
3473 MI.getOperand(III.ZeroIsSpecialOrig).getReg() != PPC::ZERO8)
3495 RegMO = &DefMI.getOperand(1);
3496 ImmMO = &DefMI.getOperand(2);
3637 if (PostRA && MI.getOperand(OpNoForForwarding).isKill())
3638 ForwardKilledOperandReg = MI.getOperand(OpNoForForwarding).getReg();
3649 MI.getOperand(III.OpNoForForwarding).ChangeToRegister(RegMO->getReg(),
3674 MOps.push_back(MI.getOperand(i));
3742 Register OrigZeroReg = MI.getOperand(PosForOrigZero).getReg();
3743 Register NewZeroReg = MI.getOperand(III.ZeroIsSpecialNew).getReg();
3756 if (PostRA && MI.getOperand(ConstantOpNo).isKill())
3757 ForwardKilledOperandReg = MI.getOperand(ConstantOpNo).getReg();
3836 Register RegToModify = MI.getOperand(III.ZeroIsSpecialNew).getReg();
4174 TripCount = LoopCount->getOperand(1).getImm();
4210 int64_t TripCount = LoopCount->getOperand(1).getImm() + TripCountAdjust;
4211 LoopCount->getOperand(1).setImm(TripCount);
4239 Register LoopCountReg = LoopInst->getOperand(0).getReg();
lib/Target/PowerPC/PPCMIPeephole.cpp 165 return MI->getOperand(3).getImm();
168 MI->getOperand(3).getImm() <= 63 - MI->getOperand(2).getImm())
168 MI->getOperand(3).getImm() <= 63 - MI->getOperand(2).getImm())
169 return MI->getOperand(3).getImm();
174 MI->getOperand(3).getImm() <= MI->getOperand(4).getImm())
174 MI->getOperand(3).getImm() <= MI->getOperand(4).getImm())
175 return 32 + MI->getOperand(3).getImm();
178 uint16_t Imm = MI->getOperand(2).getImm();
332 int Immed = MI.getOperand(3).getImm();
343 TRI->lookThruCopyLike(MI.getOperand(1).getReg(), MRI);
345 TRI->lookThruCopyLike(MI.getOperand(2).getReg(), MRI);
359 TRI->lookThruCopyLike(DefMI->getOperand(1).getReg(), MRI);
373 MI.getOperand(0).getReg())
374 .add(MI.getOperand(1));
383 unsigned FeedImmed = DefMI->getOperand(3).getImm();
385 TRI->lookThruCopyLike(DefMI->getOperand(1).getReg(), MRI);
387 TRI->lookThruCopyLike(DefMI->getOperand(2).getReg(), MRI);
394 MI.getOperand(0).getReg())
395 .add(MI.getOperand(1));
407 MI.getOperand(1).setReg(DefMI->getOperand(1).getReg());
407 MI.getOperand(1).setReg(DefMI->getOperand(1).getReg());
408 MI.getOperand(2).setReg(DefMI->getOperand(2).getReg());
408 MI.getOperand(2).setReg(DefMI->getOperand(2).getReg());
409 MI.getOperand(3).setImm(3 - Immed);
419 MI.getOperand(0).getReg())
420 .add(DefMI->getOperand(1));
425 (DefMI->getOperand(2).getImm() == 0 ||
426 DefMI->getOperand(2).getImm() == 3)) {
429 DefMI->getOperand(0).setReg(MI.getOperand(0).getReg());
429 DefMI->getOperand(0).setReg(MI.getOperand(0).getReg());
445 TRI->lookThruCopyLike(MI.getOperand(OpNo).getReg(), MRI);
455 Register ConvReg = DefMI->getOperand(1).getReg();
475 MI.getOperand(0).getReg())
476 .add(MI.getOperand(OpNo));
483 Register ShiftRes = DefMI->getOperand(0).getReg();
484 Register ShiftOp1 = DefMI->getOperand(1).getReg();
485 Register ShiftOp2 = DefMI->getOperand(2).getReg();
486 unsigned ShiftImm = DefMI->getOperand(3).getImm();
487 unsigned SplatImm = MI.getOperand(2).getImm();
499 MI.getOperand(1).setReg(ShiftOp1);
500 MI.getOperand(2).setImm(NewElem);
508 TRI->lookThruCopyLike(MI.getOperand(1).getReg(), MRI);
517 TRI->lookThruCopyLike(DefMI->getOperand(1).getReg(), MRI);
519 TRI->lookThruCopyLike(DefMI->getOperand(2).getReg(), MRI);
533 MRI->hasOneNonDBGUse(RoundInstr->getOperand(0).getReg())) {
535 Register ConvReg1 = RoundInstr->getOperand(1).getReg();
536 Register FRSPDefines = RoundInstr->getOperand(0).getReg();
539 if (Use.getOperand(i).isReg() &&
540 Use.getOperand(i).getReg() == FRSPDefines)
541 Use.getOperand(i).setReg(ConvReg1);
568 Register NarrowReg = MI.getOperand(1).getReg();
577 if (!MRI->hasOneNonDBGUse(SrcMI->getOperand(0).getReg()))
601 SrcMI->getOperand(0).setReg(MI.getOperand(0).getReg());
601 SrcMI->getOperand(0).setReg(MI.getOperand(0).getReg());
612 Register NarrowReg = MI.getOperand(1).getReg();
621 if (!MRI->hasOneNonDBGUse(SrcMI->getOperand(0).getReg()))
645 SrcMI->getOperand(0).setReg(MI.getOperand(0).getReg());
645 SrcMI->getOperand(0).setReg(MI.getOperand(0).getReg());
659 MI.getOperand(0).getReg())
678 if (MI.getOperand(2).getImm() != 0)
681 Register SrcReg = MI.getOperand(1).getReg();
687 SrcMI->getOperand(0).isReg() && SrcMI->getOperand(1).isReg()))
687 SrcMI->getOperand(0).isReg() && SrcMI->getOperand(1).isReg()))
691 ImpDefMI = MRI->getVRegDef(SrcMI->getOperand(1).getReg());
692 SubRegMI = MRI->getVRegDef(SrcMI->getOperand(2).getReg());
697 Register CopyReg = SubRegMI->getOperand(1).getReg();
703 if (MI.getOperand(3).getImm() <= KnownZeroCount) {
706 MI.getOperand(0).getReg())
726 MRI->hasOneNonDBGUse(DefPhiMI->getOperand(0).getReg());
740 getVRegDefOrNull(&DefPhiMI->getOperand(i), MRI);
743 || !MRI->hasOneNonDBGUse(LiMI->getOperand(0).getReg()) ||
751 MachineOperand Op1 = MI.getOperand(1);
752 MachineOperand Op2 = MI.getOperand(2);
769 MachineInstr *LiMI = getVRegDefOrNull(&DefPhiMI->getOperand(i), MRI);
782 auto LiImm = LiMI->getOperand(1).getImm(); // save the imm of LI
796 MI.getOperand(0).getReg())
833 PPC::Predicate Pred = (PPC::Predicate)BI->getOperand(0).getImm();
866 uint64_t Imm = CMPI->getOperand(2).getImm();
871 PPC::Predicate Pred = (PPC::Predicate)BI->getOperand(0).getImm();
885 uint64_t Imm = CMPI->getOperand(2).getImm();
890 PPC::Predicate Pred = (PPC::Predicate)BI->getOperand(0).getImm();
905 MachineOperand &MO = Phi->getOperand(I);
907 return Phi->getOperand(I-1).getReg();
928 NextReg = Inst->getOperand(1).getReg();
949 (*BII).getOperand(1).isReg()) {
951 Register CndReg = (*BII).getOperand(1).getReg();
1013 MachineInstr *CMPI = MRI->getVRegDef(BI->getOperand(1).getReg());
1015 if (CMPI->getOperand(I).isReg()) {
1016 MachineInstr *Inst = MRI->getVRegDef(CMPI->getOperand(I).getReg());
1112 MachineInstr *CMPI1 = MRI->getVRegDef(BI1->getOperand(1).getReg());
1115 MachineInstr *CMPI2 = MRI->getVRegDef(BI2->getOperand(1).getReg());
1140 if (!I->getOperand(2).isImm())
1142 int16_t Imm = (int16_t)I->getOperand(2).getImm();
1155 if (CMPI1->getOperand(2).isReg() && CMPI2->getOperand(2).isReg()) {
1155 if (CMPI1->getOperand(2).isReg() && CMPI2->getOperand(2).isReg()) {
1158 unsigned Cmp1Operand1 = getSrcVReg(CMPI1->getOperand(1).getReg(),
1160 unsigned Cmp1Operand2 = getSrcVReg(CMPI1->getOperand(2).getReg(),
1162 unsigned Cmp2Operand1 = getSrcVReg(CMPI2->getOperand(1).getReg(),
1164 unsigned Cmp2Operand2 = getSrcVReg(CMPI2->getOperand(2).getReg(),
1173 PPC::Predicate Pred = (PPC::Predicate)BI2->getOperand(0).getImm();
1181 else if (CMPI1->getOperand(2).isImm() && CMPI2->getOperand(2).isImm()) {
1181 else if (CMPI1->getOperand(2).isImm() && CMPI2->getOperand(2).isImm()) {
1184 unsigned Cmp1Operand1 = getSrcVReg(CMPI1->getOperand(1).getReg(),
1186 unsigned Cmp2Operand1 = getSrcVReg(CMPI2->getOperand(1).getReg(),
1191 NewImm1 = Imm1 = (int16_t)CMPI1->getOperand(2).getImm();
1192 NewImm2 = Imm2 = (int16_t)CMPI2->getOperand(2).getImm();
1259 BI1->getOperand(0).setImm(NewPredicate1);
1262 BI2->getOperand(0).setImm(NewPredicate2);
1265 CMPI1->getOperand(2).setImm(NewImm1);
1272 Register Op1 = CMPI2->getOperand(1).getReg();
1273 Register Op2 = CMPI2->getOperand(2).getReg();
1274 CMPI2->getOperand(1).setReg(Op2);
1275 CMPI2->getOperand(2).setReg(Op1);
1278 CMPI2->getOperand(2).setImm(NewImm2);
1281 if (CMPI2->getOperand(I).isReg()) {
1282 MachineInstr *Inst = MRI->getVRegDef(CMPI2->getOperand(I).getReg());
1289 CMPI2->getOperand(I).setReg(SrcReg);
1299 .addReg(BI1->getOperand(1).getReg()).addMBB(MBB1)
1300 .addReg(BI2->getOperand(1).getReg()).addMBB(MBBtoMoveCmp);
1301 BI2->getOperand(1).setReg(NewVReg);
1305 BI2->getOperand(1).setReg(BI1->getOperand(1).getReg());
1305 BI2->getOperand(1).setReg(BI1->getOperand(1).getReg());
1308 BI2->getOperand(1).setIsKill(true);
1309 BI1->getOperand(1).setIsKill(false);
1335 Register SrcReg = MI.getOperand(1).getReg();
1343 MachineOperand MOpSHSrc = SrcMI->getOperand(2);
1344 MachineOperand MOpMBSrc = SrcMI->getOperand(3);
1345 MachineOperand MOpSHMI = MI.getOperand(2);
1346 MachineOperand MOpMEMI = MI.getOperand(3);
1374 MI.getOperand(1).setReg(SrcMI->getOperand(1).getReg());
1374 MI.getOperand(1).setReg(SrcMI->getOperand(1).getReg());
1375 MI.getOperand(2).setImm(NewSH);
1376 MI.getOperand(3).setImm(NewMB);
1405 MachineOperand MOpSHMI = MI.getOperand(2);
1406 MachineOperand MOpMEMI = MI.getOperand(3);
1415 Register SrcReg = MI.getOperand(1).getReg();
1430 assert(SrcMI->getOperand(1).isReg() &&
1432 if (!Register::isVirtualRegister(SrcMI->getOperand(1).getReg()))
1443 MI.getOperand(0).getReg())
1444 .add(SrcMI->getOperand(1))
lib/Target/PowerPC/PPCPreEmitPeephole.cpp 89 if (!BBI->getOperand(1).isImm())
91 assert(BBI->getOperand(0).isReg() &&
96 Register Reg = BBI->getOperand(0).getReg();
97 int64_t Imm = BBI->getOperand(1).getImm();
99 if (BBI->getOperand(0).isDead()) {
100 DeadOrKillToUnset = &BBI->getOperand(0);
114 DeadOrKillToUnset = &AfterBBI->getOperand(KillIdx);
126 assert(AfterBBI->getOperand(0).isReg() &&
130 if (!AfterBBI->getOperand(1).isImm() ||
131 AfterBBI->getOperand(1).getImm() != Imm)
180 MI.getOperand(0).getReg() == MI.getOperand(1).getReg() &&
180 MI.getOperand(0).getReg() == MI.getOperand(1).getReg() &&
181 MI.getOperand(0).getReg() == MI.getOperand(2).getReg()) {
181 MI.getOperand(0).getReg() == MI.getOperand(2).getReg()) {
189 MI.getOperand(0).getReg() == MI.getOperand(1).getReg()) {
189 MI.getOperand(0).getReg() == MI.getOperand(1).getReg()) {
226 Register CRBit = Br->getOperand(0).getReg();
234 It->getOperand(0).getReg() == CRBit)
248 MBB.removeSuccessor(Br->getOperand(1).getMBB());
259 if (!MBB.isLayoutSuccessor(Br->getOperand(1).getMBB())) {
261 TII->insertBranch(MBB, Br->getOperand(1).getMBB(), nullptr,
265 if (Succ != Br->getOperand(1).getMBB()) {
lib/Target/PowerPC/PPCQPXLoadSplat.cpp 82 Register SplatReg = SMI->getOperand(0).getReg();
83 Register SrcReg = SMI->getOperand(1).getReg();
104 TRI->getSubRegIndex(SrcReg, MI->getOperand(0).getReg());
109 MI->getOperand(0).setReg(SplatSubReg);
148 if (MI->getOperand(2).getImm() != 0)
153 if (!MI->getOperand(1).isKill())
lib/Target/PowerPC/PPCReduceCRLogicals.cpp 63 MachineOperand &MO = MI.getOperand(i);
66 if (MI.getOperand(i - 1).isReg()) {
67 MachineInstr *DefMI = MRI->getVRegDef(MI.getOperand(i - 1).getReg());
96 MachineOperand &MO = MI.getOperand(i);
99 MIB.addReg(MI.getOperand(i - 1).getReg()).addMBB(NewMBB);
163 MachineBasicBlock *OrigTarget = BSI.OrigBranch->getOperand(1).getMBB();
221 .addReg(BSI.SplitCond->getOperand(0).getReg())
232 assert(FirstTerminator->getOperand(0).isReg() &&
234 FirstTerminator->getOperand(0).setReg(BSI.NewCond->getOperand(0).getReg());
234 FirstTerminator->getOperand(0).setReg(BSI.NewCond->getOperand(0).getReg());
471 MachineInstr *Def1 = lookThroughCRCopy(MIParam.getOperand(1).getReg(),
474 MRI->hasOneNonDBGUse(Def1->getOperand(0).getReg());
476 MRI->hasOneNonDBGUse(Ret.CopyDefs.first->getOperand(0).getReg());
480 MachineInstr *Def2 = lookThroughCRCopy(MIParam.getOperand(2).getReg(),
484 MRI->hasOneNonDBGUse(Def2->getOperand(0).getReg());
486 MRI->hasOneNonDBGUse(Ret.CopyDefs.second->getOperand(0).getReg());
498 MRI->use_nodbg_instructions(MIParam.getOperand(0).getReg())) {
509 Ret.SingleUse = MRI->hasOneNonDBGUse(MIParam.getOperand(0).getReg()) ? 1 : 0;
544 Register CopySrc = Copy->getOperand(1).getReg();
545 Subreg = Copy->getOperand(1).getSubReg();
657 MRI->use_nodbg_begin(CRI.MI->getOperand(0).getReg())->getParent();
lib/Target/PowerPC/PPCRegisterInfo.cpp 550 bool KillNegSizeReg = MI.getOperand(1).isKill();
551 Register NegSizeReg = MI.getOperand(1).getReg();
577 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg())
602 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg())
629 MI.getOperand(0).getReg())
658 Register SrcReg = MI.getOperand(0).getReg();
663 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill()));
703 Register DestReg = MI.getOperand(0).getReg();
747 Register SrcReg = MI.getOperand(0).getReg();
789 RegState::Implicit | getKillRegState(MI.getOperand(0).isKill()));
826 Register DestReg = MI.getOperand(0).getReg();
873 Register SrcReg = MI.getOperand(0).getReg();
876 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill()));
899 Register DestReg = MI.getOperand(0).getReg();
1004 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
1047 MI.getOperand(FIOperandNum).ChangeToRegister(
1057 Offset += MI.getOperand(OffsetOperandNo).getImm();
1085 MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset);
1130 Register StackReg = MI.getOperand(FIOperandNum).getReg();
1131 MI.getOperand(OperandBase).ChangeToRegister(StackReg, false);
1132 MI.getOperand(OperandBase + 1).ChangeToRegister(SReg, false, false, true);
1193 MI->getOperand(2).getImm() == 0)
1244 while (!MI.getOperand(FIOperandNum).isFI()) {
1250 MI.getOperand(FIOperandNum).ChangeToRegister(BaseReg, false);
1252 Offset += MI.getOperand(OffsetOperandNo).getImm();
1253 MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset);
lib/Target/PowerPC/PPCTLSDynamicCall.cpp 77 Register OutReg = MI.getOperand(0).getReg();
78 Register InReg = MI.getOperand(1).getReg();
118 Addi->addOperand(MI.getOperand(2));
127 Call->addOperand(MI.getOperand(3));
lib/Target/PowerPC/PPCVSXCopy.cpp 91 MachineOperand &DstMO = MI.getOperand(0);
92 MachineOperand &SrcMO = MI.getOperand(1);
lib/Target/PowerPC/PPCVSXFMAMutate.cpp 111 LIS->getInterval(MI.getOperand(1).getReg()).Query(FMAIdx).valueIn();
129 Register AddendSrcReg = AddendMI->getOperand(1).getReg();
131 if (MRI.getRegClass(AddendMI->getOperand(0).getReg()) !=
137 if (!MRI.getRegClass(AddendMI->getOperand(0).getReg())
163 if (J->readsVirtualRegister(AddendMI->getOperand(0).getReg())) {
185 Register OldFMAReg = MI.getOperand(0).getReg();
189 Register Reg2 = MI.getOperand(2).getReg();
190 Register Reg3 = MI.getOperand(3).getReg();
217 Register KilledProdReg = MI.getOperand(KilledProdOp).getReg();
218 Register OtherProdReg = MI.getOperand(OtherProdOp).getReg();
220 unsigned AddSubReg = AddendMI->getOperand(1).getSubReg();
221 unsigned KilledProdSubReg = MI.getOperand(KilledProdOp).getSubReg();
222 unsigned OtherProdSubReg = MI.getOperand(OtherProdOp).getSubReg();
224 bool AddRegKill = AddendMI->getOperand(1).isKill();
225 bool KilledProdRegKill = MI.getOperand(KilledProdOp).isKill();
226 bool OtherProdRegKill = MI.getOperand(OtherProdOp).isKill();
228 bool AddRegUndef = AddendMI->getOperand(1).isUndef();
229 bool KilledProdRegUndef = MI.getOperand(KilledProdOp).isUndef();
230 bool OtherProdRegUndef = MI.getOperand(OtherProdOp).isUndef();
240 assert(OldFMAReg == AddendMI->getOperand(0).getReg() &&
245 MI.getOperand(0).setReg(KilledProdReg);
246 MI.getOperand(1).setReg(KilledProdReg);
247 MI.getOperand(3).setReg(AddendSrcReg);
249 MI.getOperand(0).setSubReg(KilledProdSubReg);
250 MI.getOperand(1).setSubReg(KilledProdSubReg);
251 MI.getOperand(3).setSubReg(AddSubReg);
253 MI.getOperand(1).setIsKill(KilledProdRegKill);
254 MI.getOperand(3).setIsKill(AddRegKill);
256 MI.getOperand(1).setIsUndef(KilledProdRegUndef);
257 MI.getOperand(3).setIsUndef(AddRegUndef);
263 if (OtherProdReg == AddendMI->getOperand(0).getReg()) {
264 MI.getOperand(2).setReg(AddendSrcReg);
265 MI.getOperand(2).setSubReg(AddSubReg);
266 MI.getOperand(2).setIsKill(AddRegKill);
267 MI.getOperand(2).setIsUndef(AddRegUndef);
269 MI.getOperand(2).setReg(OtherProdReg);
270 MI.getOperand(2).setSubReg(OtherProdSubReg);
271 MI.getOperand(2).setIsKill(OtherProdRegKill);
272 MI.getOperand(2).setIsUndef(OtherProdRegUndef);
lib/Target/PowerPC/PPCVSXSwapRemoval.cpp 295 int immed = MI.getOperand(3).getImm();
297 unsigned trueReg1 = lookThruCopyLike(MI.getOperand(1).getReg(),
299 unsigned trueReg2 = lookThruCopyLike(MI.getOperand(2).getReg(),
322 unsigned trueReg1 = lookThruCopyLike(MI.getOperand(1).getReg(),
324 unsigned trueReg2 = lookThruCopyLike(MI.getOperand(2).getReg(),
378 if (isVecReg(MI.getOperand(0).getReg()) &&
379 isVecReg(MI.getOperand(1).getReg()))
385 else if (isScalarVecReg(MI.getOperand(0).getReg()) &&
386 isScalarVecReg(MI.getOperand(1).getReg()))
397 if (isVecReg(MI.getOperand(0).getReg()) &&
398 isVecReg(MI.getOperand(2).getReg()))
400 else if (isVecReg(MI.getOperand(0).getReg()) &&
401 isScalarVecReg(MI.getOperand(2).getReg())) {
563 CopySrcReg = MI->getOperand(1).getReg();
566 CopySrcReg = MI->getOperand(2).getReg();
670 Register DefReg = MI->getOperand(0).getReg();
698 Register UseReg = MI->getOperand(0).getReg();
700 Register DefReg = DefMI->getOperand(0).getReg();
759 Register DefReg = MI->getOperand(0).getReg();
775 Register UseReg = MI->getOperand(0).getReg();
840 EltNo = MI->getOperand(2).getImm();
842 EltNo = MI->getOperand(1).getImm();
846 MI->getOperand(2).setImm(EltNo);
848 MI->getOperand(1).setImm(EltNo);
867 unsigned Selector = MI->getOperand(3).getImm();
870 MI->getOperand(3).setImm(Selector);
872 Register Reg1 = MI->getOperand(1).getReg();
873 Register Reg2 = MI->getOperand(2).getReg();
874 MI->getOperand(1).setReg(Reg2);
875 MI->getOperand(2).setReg(Reg1);
878 bool IsKill1 = MI->getOperand(1).isKill();
879 bool IsKill2 = MI->getOperand(2).isKill();
880 MI->getOperand(1).setIsKill(IsKill2);
881 MI->getOperand(2).setIsKill(IsKill1);
897 Register DstReg = MI->getOperand(0).getReg();
901 MI->getOperand(0).setReg(NewVReg);
952 MI->getOperand(0).getReg())
953 .add(MI->getOperand(1));
lib/Target/RISCV/RISCVExpandPseudoInsts.cpp 238 Register DestReg = MI.getOperand(0).getReg();
239 Register ScratchReg = MI.getOperand(1).getReg();
240 Register AddrReg = MI.getOperand(2).getReg();
241 Register IncrReg = MI.getOperand(3).getReg();
243 static_cast<AtomicOrdering>(MI.getOperand(4).getImm());
300 Register DestReg = MI.getOperand(0).getReg();
301 Register ScratchReg = MI.getOperand(1).getReg();
302 Register AddrReg = MI.getOperand(2).getReg();
303 Register IncrReg = MI.getOperand(3).getReg();
304 Register MaskReg = MI.getOperand(4).getReg();
306 static_cast<AtomicOrdering>(MI.getOperand(5).getImm());
439 Register DestReg = MI.getOperand(0).getReg();
440 Register Scratch1Reg = MI.getOperand(1).getReg();
441 Register Scratch2Reg = MI.getOperand(2).getReg();
442 Register AddrReg = MI.getOperand(3).getReg();
443 Register IncrReg = MI.getOperand(4).getReg();
444 Register MaskReg = MI.getOperand(5).getReg();
447 static_cast<AtomicOrdering>(MI.getOperand(IsSigned ? 7 : 6).getImm());
469 insertSext(TII, DL, LoopHeadMBB, Scratch2Reg, MI.getOperand(6).getReg());
477 insertSext(TII, DL, LoopHeadMBB, Scratch2Reg, MI.getOperand(6).getReg());
552 Register DestReg = MI.getOperand(0).getReg();
553 Register ScratchReg = MI.getOperand(1).getReg();
554 Register AddrReg = MI.getOperand(2).getReg();
555 Register CmpValReg = MI.getOperand(3).getReg();
556 Register NewValReg = MI.getOperand(4).getReg();
558 static_cast<AtomicOrdering>(MI.getOperand(IsMasked ? 6 : 5).getImm());
585 Register MaskReg = MI.getOperand(5).getReg();
632 Register DestReg = MI.getOperand(0).getReg();
633 const MachineOperand &Symbol = MI.getOperand(1);
lib/Target/RISCV/RISCVFrameLowering.cpp 280 if (I->mayLoad() && I->getOperand(0).isReg()) {
281 Register DestReg = I->getOperand(0).getReg();
451 int64_t Amount = MI->getOperand(0).getImm();
lib/Target/RISCV/RISCVISelLowering.cpp 1123 Register LoReg = MI.getOperand(0).getReg();
1124 Register HiReg = MI.getOperand(1).getReg();
1159 Register LoReg = MI.getOperand(0).getReg();
1160 Register HiReg = MI.getOperand(1).getReg();
1161 Register SrcReg = MI.getOperand(2).getReg();
1165 TII.storeRegToStackSlot(*BB, MI, SrcReg, MI.getOperand(2).isKill(), FI, SrcRC,
1191 Register DstReg = MI.getOperand(0).getReg();
1192 Register LoReg = MI.getOperand(1).getReg();
1193 Register HiReg = MI.getOperand(2).getReg();
1201 .addReg(LoReg, getKillRegState(MI.getOperand(1).isKill()))
1206 .addReg(HiReg, getKillRegState(MI.getOperand(2).isKill()))
1252 Register LHS = MI.getOperand(1).getReg();
1253 Register RHS = MI.getOperand(2).getReg();
1254 auto CC = static_cast<ISD::CondCode>(MI.getOperand(3).getImm());
1258 SelectDests.insert(MI.getOperand(0).getReg());
1267 if (SequenceMBBI->getOperand(1).getReg() != LHS ||
1268 SequenceMBBI->getOperand(2).getReg() != RHS ||
1269 SequenceMBBI->getOperand(3).getImm() != CC ||
1270 SelectDests.count(SequenceMBBI->getOperand(4).getReg()) ||
1271 SelectDests.count(SequenceMBBI->getOperand(5).getReg()))
1275 SelectDests.insert(SequenceMBBI->getOperand(0).getReg());
1335 TII.get(RISCV::PHI), SelectMBBI->getOperand(0).getReg())
1336 .addReg(SelectMBBI->getOperand(4).getReg())
1338 .addReg(SelectMBBI->getOperand(5).getReg())
lib/Target/RISCV/RISCVInstrInfo.cpp 208 Target = LastInst.getOperand(2).getMBB();
210 Cond.push_back(LastInst.getOperand(0));
211 Cond.push_back(LastInst.getOperand(1));
279 TBB = I->getOperand(0).getMBB();
293 FBB = I->getOperand(0).getMBB();
lib/Target/RISCV/RISCVMergeBaseOffset.cpp 83 HiLUI.getOperand(1).getTargetFlags() != RISCVII::MO_HI ||
84 HiLUI.getOperand(1).getType() != MachineOperand::MO_GlobalAddress ||
85 HiLUI.getOperand(1).getOffset() != 0 ||
86 !MRI->hasOneUse(HiLUI.getOperand(0).getReg()))
88 Register HiLuiDestReg = HiLUI.getOperand(0).getReg();
91 LoADDI->getOperand(2).getTargetFlags() != RISCVII::MO_LO ||
92 LoADDI->getOperand(2).getType() != MachineOperand::MO_GlobalAddress ||
93 LoADDI->getOperand(2).getOffset() != 0 ||
94 !MRI->hasOneUse(LoADDI->getOperand(0).getReg()))
106 HiLUI.getOperand(1).setOffset(Offset);
107 LoADDI.getOperand(2).setOffset(Offset);
110 MRI->replaceRegWith(Tail.getOperand(0).getReg(),
111 LoADDI.getOperand(0).getReg());
138 Register Rs = TailAdd.getOperand(1).getReg();
139 Register Rt = TailAdd.getOperand(2).getReg();
150 MachineOperand &AddiImmOp = OffsetTail.getOperand(2);
155 *MRI->getVRegDef(OffsetTail.getOperand(1).getReg());
156 MachineOperand &LuiImmOp = OffsetLui.getOperand(1);
159 !MRI->hasOneUse(OffsetLui.getOperand(0).getReg()))
161 int64_t OffHi = OffsetLui.getOperand(1).getImm();
172 Offset = OffsetTail.getOperand(1).getImm() << 12;
181 Register DestReg = LoADDI.getOperand(0).getReg();
192 int64_t Offset = Tail.getOperand(2).getImm();
231 if (Tail.getOperand(1).isFI())
235 Register BaseAddrReg = Tail.getOperand(1).getReg();
238 MachineOperand &TailImmOp = Tail.getOperand(2);
241 HiLUI.getOperand(1).setOffset(Offset);
244 MachineOperand &ImmOp = LoADDI.getOperand(2);
250 Tail.getOperand(1).setReg(HiLUI.getOperand(0).getReg());
250 Tail.getOperand(1).setReg(HiLUI.getOperand(0).getReg());
271 << *LoADDI->getOperand(2).getGlobal() << "\n");
lib/Target/RISCV/RISCVRegisterInfo.cpp 113 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
117 MI.getOperand(FIOperandNum + 1).getImm();
141 MI.getOperand(FIOperandNum)
143 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
lib/Target/Sparc/DelaySlotFiller.cpp 252 const MachineOperand &MO = candidate->getOperand(i);
302 const MachineOperand &Reg = MI->getOperand(0);
307 const MachineOperand &Operand1 = MI->getOperand(1);
323 const MachineOperand &MO = MI->getOperand(i);
367 const MachineOperand &MO = I->getOperand(structSizeOpNum);
383 Register reg = AddMI->getOperand(0).getReg();
396 AddMI->getOperand(0).setReg(reg - SP::I0 + SP::O0);
411 Register reg = OrMI->getOperand(0).getReg();
417 && OrMI->getOperand(1).getReg() != SP::G0
418 && OrMI->getOperand(2).getReg() != SP::G0)
422 && OrMI->getOperand(1).getReg() != SP::G0
423 && (!OrMI->getOperand(2).isImm() || OrMI->getOperand(2).getImm() != 0))
423 && (!OrMI->getOperand(2).isImm() || OrMI->getOperand(2).getImm() != 0))
435 OrMI->getOperand(0).setReg(reg - SP::I0 + SP::O0);
449 Register reg = SetHiMI->getOperand(0).getReg();
453 if (!SetHiMI->getOperand(1).isImm())
456 int64_t imm = SetHiMI->getOperand(1).getImm();
469 RestoreMI->getOperand(0).setReg(reg - SP::I0 + SP::O0);
470 RestoreMI->getOperand(1).setReg(SP::G0);
471 RestoreMI->getOperand(2).ChangeToImmediate(imm);
489 && MBBI->getOperand(0).getReg() == SP::G0
490 && MBBI->getOperand(1).getReg() == SP::G0
491 && MBBI->getOperand(2).getReg() == SP::G0);
lib/Target/Sparc/LeonPasses.cpp 87 MachineOperand &MO = MI.getOperand(0);
lib/Target/Sparc/SparcFrameLowering.cpp 209 int Size = MI.getOperand(0).getImm();
lib/Target/Sparc/SparcISelLowering.cpp 3121 unsigned CC = (SPCC::CondCodes)MI.getOperand(3).getImm();
3162 MI.getOperand(0).getReg())
3163 .addReg(MI.getOperand(1).getReg())
3165 .addReg(MI.getOperand(2).getReg())
lib/Target/Sparc/SparcInstrInfo.cpp 155 Cond.push_back(MachineOperand::CreateImm(LastInst->getOperand(1).getImm()));
156 Target = LastInst->getOperand(0).getMBB();
178 TBB = LastInst->getOperand(0).getMBB();
202 TBB = LastInst->getOperand(0).getMBB();
218 FBB = LastInst->getOperand(0).getMBB();
225 TBB = SecondLastInst->getOperand(0).getMBB();
lib/Target/Sparc/SparcRegisterInfo.cpp 118 MI.getOperand(FIOperandNum).ChangeToRegister(FramePtr, false);
119 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
140 MI.getOperand(FIOperandNum).ChangeToRegister(SP::G1, false);
141 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(LO10(Offset));
158 MI.getOperand(FIOperandNum).ChangeToRegister(SP::G1, false);
159 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(0);
171 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
180 Offset += MI.getOperand(FIOperandNum + 1).getImm();
185 Register SrcReg = MI.getOperand(2).getReg();
193 MI.getOperand(2).setReg(SrcOddReg);
197 Register DestReg = MI.getOperand(0).getReg();
206 MI.getOperand(0).setReg(DestOddReg);
lib/Target/SystemZ/SystemZElimCompare.cpp 129 if (MI.getOperand(1).getReg() == Reg)
139 if (MI.getNumOperands() > 0 && MI.getOperand(0).isReg() &&
140 MI.getOperand(0).isDef() && MI.getOperand(0).getReg() == Reg)
140 MI.getOperand(0).isDef() && MI.getOperand(0).getReg() == Reg)
153 const MachineOperand &MO = MI.getOperand(I);
176 MI.getOperand(0).isDead();
184 reg = Compare.getOperand(0).getReg();
186 reg = Compare.getOperand(1).getReg();
209 if (MI.getOperand(2).getImm() != -1)
217 Branch->getOperand(0).getImm() != SystemZ::CCMASK_ICMP ||
218 Branch->getOperand(1).getImm() != SystemZ::CCMASK_CMP_NE)
231 MachineOperand Target(Branch->getOperand(2));
236 MIB.add(MI.getOperand(0)).add(MI.getOperand(1)).add(Target);
236 MIB.add(MI.getOperand(0)).add(MI.getOperand(1)).add(Target);
261 Branch->getOperand(0).getImm() != SystemZ::CCMASK_ICMP ||
262 Branch->getOperand(1).getImm() != SystemZ::CCMASK_CMP_EQ)
279 .add(MI.getOperand(0))
280 .add(MI.getOperand(1))
281 .add(MI.getOperand(2))
282 .add(MI.getOperand(3));
359 unsigned CCValid = MI->getOperand(FirstOpNum).getImm();
360 unsigned CCMask = MI->getOperand(FirstOpNum + 1).getImm();
366 AlterMasks.push_back(&MI->getOperand(FirstOpNum));
367 AlterMasks.push_back(&MI->getOperand(FirstOpNum + 1));
415 Compare.getOperand(1).isImm() && Compare.getOperand(1).getImm() == 0;
415 Compare.getOperand(1).isImm() && Compare.getOperand(1).getImm() == 0;
525 Register SrcReg = Compare.getOperand(0).getReg();
527 Compare.getOperand(1).isReg() ? Compare.getOperand(1).getReg() : Register();
527 Compare.getOperand(1).isReg() ? Compare.getOperand(1).getReg() : Register();
535 MachineOperand CCMask(MBBI->getOperand(1));
539 MachineOperand Target(MBBI->getOperand(
543 RegMask = MBBI->getOperand(2).getRegMask();
565 MIB.add(Compare.getOperand(I));
lib/Target/SystemZ/SystemZFrameLowering.cpp 336 MI->getOperand(3).setIsDead();
493 uint64_t Offset = StackSize + MBBI->getOperand(AddrOpNo + 1).getImm();
500 emitIncrement(MBB, MBBI, DL, MBBI->getOperand(AddrOpNo).getReg(),
508 MBBI->getOperand(AddrOpNo + 1).ChangeToImmediate(Offset);
lib/Target/SystemZ/SystemZISelLowering.cpp 6575 unsigned CCValid = FirstMI->getOperand(3).getImm();
6576 unsigned CCMask = FirstMI->getOperand(4).getImm();
6589 Register DestReg = MI->getOperand(0).getReg();
6590 Register TrueReg = MI->getOperand(1).getReg();
6591 Register FalseReg = MI->getOperand(2).getReg();
6596 if (MI->getOperand(4).getImm() == (CCValid ^ CCMask))
6625 unsigned CCValid = MI.getOperand(3).getImm();
6626 unsigned CCMask = MI.getOperand(4).getImm();
6641 assert(NextMIIt->getOperand(3).getImm() == CCValid &&
6643 if (NextMIIt->getOperand(4).getImm() == CCMask ||
6644 NextMIIt->getOperand(4).getImm() == (CCValid ^ CCMask)) {
6652 if (NextMIIt->readsVirtualRegister(SelMI->getOperand(0).getReg())) {
6721 Register SrcReg = MI.getOperand(0).getReg();
6722 MachineOperand Base = MI.getOperand(1);
6723 int64_t Disp = MI.getOperand(2).getImm();
6724 Register IndexReg = MI.getOperand(3).getReg();
6725 unsigned CCValid = MI.getOperand(4).getImm();
6726 unsigned CCMask = MI.getOperand(5).getImm();
6816 Register Dest = MI.getOperand(0).getReg();
6817 MachineOperand Base = earlyUseOperand(MI.getOperand(1));
6818 int64_t Disp = MI.getOperand(2).getImm();
6819 MachineOperand Src2 = earlyUseOperand(MI.getOperand(3));
6820 Register BitShift = IsSubWord ? MI.getOperand(4).getReg() : Register();
6821 Register NegBitShift = IsSubWord ? MI.getOperand(5).getReg() : Register();
6824 BitSize = MI.getOperand(6).getImm();
6934 Register Dest = MI.getOperand(0).getReg();
6935 MachineOperand Base = earlyUseOperand(MI.getOperand(1));
6936 int64_t Disp = MI.getOperand(2).getImm();
6937 Register Src2 = MI.getOperand(3).getReg();
6938 Register BitShift = (IsSubWord ? MI.getOperand(4).getReg() : Register());
6939 Register NegBitShift = (IsSubWord ? MI.getOperand(5).getReg() : Register());
6942 BitSize = MI.getOperand(6).getImm();
7048 Register Dest = MI.getOperand(0).getReg();
7049 MachineOperand Base = earlyUseOperand(MI.getOperand(1));
7050 int64_t Disp = MI.getOperand(2).getImm();
7051 Register OrigCmpVal = MI.getOperand(3).getReg();
7052 Register OrigSwapVal = MI.getOperand(4).getReg();
7053 Register BitShift = MI.getOperand(5).getReg();
7054 Register NegBitShift = MI.getOperand(6).getReg();
7055 int64_t BitSize = MI.getOperand(7).getImm();
7172 Register Dest = MI.getOperand(0).getReg();
7173 Register Hi = MI.getOperand(1).getReg();
7174 Register Lo = MI.getOperand(2).getReg();
7200 Register Dest = MI.getOperand(0).getReg();
7201 Register Src = MI.getOperand(1).getReg();
7230 MachineOperand DestBase = earlyUseOperand(MI.getOperand(0));
7231 uint64_t DestDisp = MI.getOperand(1).getImm();
7232 MachineOperand SrcBase = earlyUseOperand(MI.getOperand(2));
7233 uint64_t SrcDisp = MI.getOperand(3).getImm();
7234 uint64_t Length = MI.getOperand(4).getImm();
7245 Register StartCountReg = MI.getOperand(5).getReg();
7410 uint64_t End1Reg = MI.getOperand(0).getReg();
7411 uint64_t Start1Reg = MI.getOperand(1).getReg();
7412 uint64_t Start2Reg = MI.getOperand(2).getReg();
7413 uint64_t CharReg = MI.getOperand(3).getReg();
7473 uint64_t Control = MI.getOperand(2).getImm();
7481 MI.getOperand(2).setImm(Control);
7517 Register SrcReg = MI.getOperand(0).getReg();
lib/Target/SystemZ/SystemZInstrInfo.cpp 76 MachineOperand &HighRegOp = EarlierMI->getOperand(0);
77 MachineOperand &LowRegOp = MI->getOperand(0);
96 MachineOperand &HighOffsetOp = EarlierMI->getOperand(2);
97 MachineOperand &LowOffsetOp = MI->getOperand(2);
101 if (EarlierMI->getOperand(0).isReg() && EarlierMI->getOperand(0).isUse())
101 if (EarlierMI->getOperand(0).isReg() && EarlierMI->getOperand(0).isUse())
102 EarlierMI->getOperand(0).setIsKill(false);
103 EarlierMI->getOperand(1).setIsKill(false);
104 EarlierMI->getOperand(3).setIsKill(false);
120 MachineOperand &OffsetMO = MI->getOperand(2);
140 Register Reg = MI.getOperand(0).getReg();
144 MI.getOperand(1).setImm(uint32_t(MI.getOperand(1).getImm()));
144 MI.getOperand(1).setImm(uint32_t(MI.getOperand(1).getImm()));
154 Register DestReg = MI.getOperand(0).getReg();
155 Register SrcReg = MI.getOperand(1).getReg();
163 SystemZ::LR, 32, MI.getOperand(1).isKill(),
164 MI.getOperand(1).isUndef());
165 MI.getOperand(1).setReg(DestReg);
177 Register Reg = MI.getOperand(0).getReg();
180 MI.getOperand(2).getImm());
189 Register Reg = MI.getOperand(0).getReg();
201 MI.getOperand(0).getReg(), MI.getOperand(1).getReg(), LowOpcode,
201 MI.getOperand(0).getReg(), MI.getOperand(1).getReg(), LowOpcode,
202 Size, MI.getOperand(1).isKill(), MI.getOperand(1).isUndef());
202 Size, MI.getOperand(1).isKill(), MI.getOperand(1).isUndef());
206 MIB.add(MI.getOperand(I));
214 const Register Reg64 = MI->getOperand(0).getReg();
293 unsigned CCValid = WorkingMI.getOperand(3).getImm();
294 unsigned CCMask = WorkingMI.getOperand(4).getImm();
295 WorkingMI.getOperand(4).setImm(CCMask ^ CCValid);
615 if (DefMI.getOperand(0).getReg() != Reg)
617 int32_t ImmVal = (int32_t)DefMI.getOperand(1).getImm();
632 if (UseMI.getOperand(2).getReg() == Reg)
634 else if (UseMI.getOperand(1).getReg() == Reg)
646 if (UseMI.getOperand(2).getReg() == Reg)
648 else if (UseMI.getOperand(1).getReg() == Reg)
665 UseMI.getOperand(UseIdx).ChangeToImmediate(ImmVal);
740 MachineOperand FirstOp = MI.getOperand(0);
741 const uint32_t *RegMask = MI.getOperand(1).getRegMask();
754 const uint32_t *RegMask = MI.getOperand(0).getRegMask();
955 uint64_t Imm = MI.getOperand(2).getImm() << And.ImmLSB;
971 MachineOperand &Dest = MI.getOperand(0);
972 MachineOperand &Src = MI.getOperand(1);
985 MachineOperand &Op = MI.getOperand(I);
1008 isInt<8>(MI.getOperand(2).getImm()) && !MI.getOperand(3).getReg()) {
1008 isInt<8>(MI.getOperand(2).getImm()) && !MI.getOperand(3).getReg()) {
1024 .addImm(MI.getOperand(2).getImm());
1040 .getRegClass(MI.getOperand(OpNum).getReg())) &&
1044 isInt<8>(MI.getOperand(2).getImm())) {
1051 .addImm(MI.getOperand(2).getImm());
1057 isInt<8>((int32_t)MI.getOperand(2).getImm())) ||
1059 isInt<8>((int64_t)MI.getOperand(2).getImm()))) {
1066 .addImm((int8_t)MI.getOperand(2).getImm());
1072 isInt<8>((int32_t)-MI.getOperand(2).getImm())) ||
1074 isInt<8>((int64_t)-MI.getOperand(2).getImm()))) {
1081 .addImm((int8_t)-MI.getOperand(2).getImm());
1095 .add(MI.getOperand(1))
1106 .add(MI.getOperand(0))
1136 .add(MI.getOperand(1))
1137 .addImm(MI.getOperand(2).getImm())
1144 .add(MI.getOperand(1))
1145 .addImm(MI.getOperand(2).getImm())
1168 Register DstReg = MI.getOperand(0).getReg();
1171 Register SrcReg = (OpNum == 2 ? MI.getOperand(1).getReg()
1173 ? MI.getOperand(2).getReg()
1193 MIB.add(MI.getOperand(0));
1195 MIB.add(MI.getOperand(2));
1198 MIB.add(MI.getOperand(I));
1372 bool DestIsHigh = SystemZ::isHighReg(MI.getOperand(0).getReg());
1373 bool SrcIsHigh = SystemZ::isHighReg(MI.getOperand(2).getReg());
1378 MI.getOperand(5).setImm(MI.getOperand(5).getImm() ^ 32);
1378 MI.getOperand(5).setImm(MI.getOperand(5).getImm() ^ 32);
lib/Target/SystemZ/SystemZLongBranch.cpp 359 .add(MI->getOperand(0))
360 .add(MI->getOperand(1))
365 .add(MI->getOperand(2));
378 .add(MI->getOperand(0))
379 .add(MI->getOperand(1));
382 .add(MI->getOperand(2))
383 .add(MI->getOperand(3));
lib/Target/SystemZ/SystemZPostRewrite.cpp 89 Register DestReg = MBBI->getOperand(0).getReg();
90 Register SrcReg = MBBI->getOperand(2).getReg();
110 Register DestReg = MBBI->getOperand(0).getReg();
111 Register Src1Reg = MBBI->getOperand(1).getReg();
112 Register Src2Reg = MBBI->getOperand(2).getReg();
124 .addReg(MBBI->getOperand(1).getReg(), getRegState(MBBI->getOperand(1)));
124 .addReg(MBBI->getOperand(1).getReg(), getRegState(MBBI->getOperand(1)));
125 MBBI->getOperand(1).setReg(DestReg);
131 .addReg(MBBI->getOperand(2).getReg(), getRegState(MBBI->getOperand(2)));
131 .addReg(MBBI->getOperand(2).getReg(), getRegState(MBBI->getOperand(2)));
132 MBBI->getOperand(2).setReg(DestReg);
164 Register DestReg = MI.getOperand(0).getReg();
165 Register SrcReg = MI.getOperand(2).getReg();
166 unsigned CCValid = MI.getOperand(3).getImm();
167 unsigned CCMask = MI.getOperand(4).getImm();
168 assert(DestReg == MI.getOperand(1).getReg() &&
201 .addReg(MI.getOperand(2).getReg(), getRegState(MI.getOperand(2)));
201 .addReg(MI.getOperand(2).getReg(), getRegState(MI.getOperand(2)));
225 Register DstReg = MI.getOperand(0).getReg();
226 MachineOperand &SrcMO = MI.getOperand(1);
lib/Target/SystemZ/SystemZRegisterInfo.cpp 106 MachineOperand &TrueMO = Use.getOperand(1);
107 MachineOperand &FalseMO = Use.getOperand(2);
113 getRC32(Use.getOperand(0), VRM, MRI));
130 if (Use.getOperand(1).getImm() == 0) {
156 if (VirtReg == Use.getOperand(0).getReg()) {
157 VRRegMO = &Use.getOperand(0);
158 OtherMO = &Use.getOperand(1);
160 CommuMO = &Use.getOperand(2);
161 } else if (VirtReg == Use.getOperand(1).getReg()) {
162 VRRegMO = &Use.getOperand(1);
163 OtherMO = &Use.getOperand(0);
164 } else if (VirtReg == Use.getOperand(2).getReg() && Use.isCommutable()) {
165 VRRegMO = &Use.getOperand(2);
166 OtherMO = &Use.getOperand(0);
265 int FrameIndex = MI->getOperand(FIOperandNum).getIndex();
268 MI->getOperand(FIOperandNum + 1).getImm());
272 MI->getOperand(FIOperandNum).ChangeToRegister(BasePtr, /*isDef*/ false);
273 MI->getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
287 MI->getOperand(FIOperandNum).ChangeToRegister(BasePtr, false);
306 && MI->getOperand(FIOperandNum + 2).getReg() == 0) {
310 MI->getOperand(FIOperandNum).ChangeToRegister(BasePtr, false);
311 MI->getOperand(FIOperandNum + 2).ChangeToRegister(ScratchReg,
328 MI->getOperand(FIOperandNum).ChangeToRegister(ScratchReg,
333 MI->getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
355 Register GR128Reg = MI->getOperand(WideOpNo).getReg();
356 Register GRNarReg = MI->getOperand((WideOpNo == 1) ? 0 : 1).getReg();
lib/Target/SystemZ/SystemZShortenInst.cpp 69 !MI.getOperand(0).isTied())
78 Register Reg = MI.getOperand(0).getReg();
93 uint64_t Imm = MI.getOperand(1).getImm();
96 MI.getOperand(0).setReg(SystemZMC::getRegAsGR64(Reg));
101 MI.getOperand(0).setReg(SystemZMC::getRegAsGR64(Reg));
102 MI.getOperand(1).setImm(Imm >> 16);
110 if (SystemZMC::getFirstReg(MI.getOperand(0).getReg()) < 16) {
120 if (SystemZMC::getFirstReg(MI.getOperand(0).getReg()) < 16 &&
121 SystemZMC::getFirstReg(MI.getOperand(1).getReg()) < 16) {
132 if (SystemZMC::getFirstReg(MI.getOperand(0).getReg()) < 16 &&
133 MI.getOperand(1).getReg() == MI.getOperand(0).getReg() &&
133 MI.getOperand(1).getReg() == MI.getOperand(0).getReg() &&
134 SystemZMC::getFirstReg(MI.getOperand(2).getReg()) < 16) {
158 if (SystemZMC::getFirstReg(MI.getOperand(0).getReg()) < 16 &&
159 SystemZMC::getFirstReg(MI.getOperand(1).getReg()) < 16) {
160 MachineOperand Dest(MI.getOperand(0));
161 MachineOperand Src(MI.getOperand(1));
162 MachineOperand Suppress(MI.getOperand(2));
163 MachineOperand Mode(MI.getOperand(3));
182 if (MI.getOperand(0).getReg() == MI.getOperand(1).getReg()) {
182 if (MI.getOperand(0).getReg() == MI.getOperand(1).getReg()) {
187 if (MI.getOperand(0).getReg() == MI.getOperand(2).getReg()) {
187 if (MI.getOperand(0).getReg() == MI.getOperand(2).getReg()) {
338 if ((MI.getOperand(0).getReg() != MI.getOperand(1).getReg()) &&
338 if ((MI.getOperand(0).getReg() != MI.getOperand(1).getReg()) &&
340 MI.getOperand(0).getReg() != MI.getOperand(2).getReg() ||
340 MI.getOperand(0).getReg() != MI.getOperand(2).getReg() ||
351 MachineOperand &ImmMO = MI.getOperand(3);
lib/Target/WebAssembly/WebAssemblyCFGStackify.cpp 321 const char *TagName = BrOnExn->getOperand(1).getSymbolName();
689 int64_t RetType = Try->getOperand(0).getImm();
694 std::prev(B)->getOperand(0).getImm() == RetType;
1019 ExnReg = Catch->getOperand(0).getReg();
1251 EndToBegin[&MI]->getOperand(0).setImm(int32_t(RetType));
lib/Target/WebAssembly/WebAssemblyCallIndirectFixup.cpp 133 Ops.push_back(MI.getOperand(MI.getDesc().getNumDefs()));
lib/Target/WebAssembly/WebAssemblyDebugValueManager.cpp 33 DBI->getOperand(0).setReg(Reg);
42 Clone->getOperand(0).setReg(NewReg);
lib/Target/WebAssembly/WebAssemblyExplicitLocals.cpp 210 Register Reg = MI.getOperand(0).getReg();
212 Reg2Local[Reg] = static_cast<unsigned>(MI.getOperand(1).getImm());
239 assert(MFI.isVRegStackified(MI.getOperand(0).getReg()));
240 assert(!MFI.isVRegStackified(MI.getOperand(1).getReg()));
241 Register OldReg = MI.getOperand(2).getReg();
251 MI.getOperand(2).setReg(NewReg);
257 getLocalId(Reg2Local, CurLocal, MI.getOperand(1).getReg());
260 MI.getOperand(0).getReg())
262 .addReg(MI.getOperand(2).getReg());
273 Register OldReg = MI.getOperand(0).getReg();
289 Drop->getOperand(0).setIsKill();
297 MI.getOperand(0).setReg(NewReg);
301 MI.getOperand(0).setIsDead(false);
360 MRI.replaceRegWith(MI.getOperand(1).getReg(),
361 MI.getOperand(0).getReg());
lib/Target/WebAssembly/WebAssemblyFixIrreducibleControlFlow.cpp 468 ->getOperand(MIB.getInstr()->getNumExplicitOperands() - 1)
lib/Target/WebAssembly/WebAssemblyFrameLowering.cpp 141 assert(!I->getOperand(0).getImm() && (hasFP(MF) || hasBP(MF)) &&
lib/Target/WebAssembly/WebAssemblyISelLowering.cpp 338 Register OutReg = MI.getOperand(0).getReg();
339 Register InReg = MI.getOperand(1).getReg();
lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp 92 if (MFI.isVRegStackified(MI.getOperand(OpIdx1).getReg()) ||
93 MFI.isVRegStackified(MI.getOperand(OpIdx2).getReg()))
123 Cond.push_back(MI.getOperand(1));
124 TBB = MI.getOperand(0).getMBB();
131 Cond.push_back(MI.getOperand(1));
132 TBB = MI.getOperand(0).getMBB();
137 TBB = MI.getOperand(0).getMBB();
139 FBB = MI.getOperand(0).getMBB();
145 Cond.push_back(MI.getOperand(2));
146 TBB = MI.getOperand(0).getMBB();
lib/Target/WebAssembly/WebAssemblyLateEHPrepare.cpp 156 MachineBasicBlock *TBB = TI->getOperand(0).getMBB();
172 Register ExnReg = Catch->getOperand(0).getReg();
244 if (MI.getOperand(0).isDead())
262 const MachineOperand &CalleeOp = MI.getOperand(0);
297 Register ExnReg = Catch->getOperand(0).getReg();
lib/Target/WebAssembly/WebAssemblyLowerBrUnless.cpp 71 Register Cond = MI->getOperand(1).getReg();
178 Cond = Def->getOperand(1).getReg();
203 .add(MI->getOperand(0))
lib/Target/WebAssembly/WebAssemblyMemIntrinsicResults.cpp 126 MI.getOperand(0).setIsDead(false);
154 MachineOperand &Op1 = MI.getOperand(1);
169 Register FromReg = MI.getOperand(2).getReg();
170 Register ToReg = MI.getOperand(0).getReg();
lib/Target/WebAssembly/WebAssemblyOptimizeLiveIntervals.cpp 98 if (MI->isImplicitDef() && MI->getOperand(0).isDead()) {
99 LiveInterval &LI = LIS.getInterval(MI->getOperand(0).getReg());
lib/Target/WebAssembly/WebAssemblyPeephole.cpp 154 MachineOperand &Op1 = MI.getOperand(1);
162 const auto &Op2 = MI.getOperand(2);
166 MachineOperand &MO = MI.getOperand(0);
lib/Target/WebAssembly/WebAssemblyRegNumbering.cpp 78 int64_t Imm = MI.getOperand(1).getImm();
79 LLVM_DEBUG(dbgs() << "Arg VReg " << MI.getOperand(0).getReg()
81 MFI.setWAReg(MI.getOperand(0).getReg(), Imm);
lib/Target/WebAssembly/WebAssemblyRegStackify.cpp 105 const auto *RegClass = MRI.getRegClass(MI->getOperand(0).getReg());
503 Def->getOperand(0).setReg(NewReg);
612 MachineOperand &DefMO = Def->getOperand(0);
lib/Target/WebAssembly/WebAssemblyRegisterInfo.cpp 62 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
78 assert(FrameOffset >= 0 && MI.getOperand(OffsetOperandNum).getImm() >= 0);
79 int64_t Offset = MI.getOperand(OffsetOperandNum).getImm() + FrameOffset;
82 MI.getOperand(OffsetOperandNum).setImm(Offset);
83 MI.getOperand(FIOperandNum)
92 MachineOperand &OtherMO = MI.getOperand(3 - FIOperandNum);
101 MRI.hasOneNonDBGUse(Def->getOperand(0).getReg())) {
102 MachineOperand &ImmMO = Def->getOperand(1);
104 MI.getOperand(FIOperandNum)
130 MI.getOperand(FIOperandNum).ChangeToRegister(FIRegOperand, /*isDef=*/false);
lib/Target/WebAssembly/WebAssemblySetP2AlignOperands.cpp 58 assert(MI.getOperand(OperandNo).getImm() == 0 &&
74 MI.getOperand(OperandNo).setImm(P2Align);
lib/Target/X86/X86AvoidStoreForwardingBlocks.cpp 299 return MI->getOperand(AddrOffset + X86::AddrBaseReg);
304 return MI->getOperand(AddrOffset + X86::AddrDisp);
314 MachineOperand &Scale = MI->getOperand(AddrOffset + X86::AddrScaleAmt);
315 MachineOperand &Index = MI->getOperand(AddrOffset + X86::AddrIndexReg);
316 MachineOperand &Segment = MI->getOperand(AddrOffset + X86::AddrSegmentReg);
429 MachineOperand &StoreSrcVReg = StoreInst->getOperand(X86::AddrNumOperands);
431 NewStore->getOperand(X86::AddrNumOperands).setIsKill(StoreSrcVReg.isKill());
541 int DefVR = MI.getOperand(0).getReg();
lib/Target/X86/X86CallFrameOptimization.cpp 291 MachineOperand ImmOp = MI->getOperand(X86::AddrNumOperands);
297 MachineOperand ImmOp = MI->getOperand(X86::AddrNumOperands);
394 if (J->isCopy() && J->getOperand(0).isReg() && J->getOperand(1).isReg() &&
394 if (J->isCopy() && J->getOperand(0).isReg() && J->getOperand(1).isReg() &&
395 J->getOperand(1).getReg() == StackPtr) {
398 StackPtr = Context.SPCopy->getOperand(0).getReg();
427 if (!I->getOperand(X86::AddrBaseReg).isReg() ||
428 (I->getOperand(X86::AddrBaseReg).getReg() != StackPtr) ||
429 !I->getOperand(X86::AddrScaleAmt).isImm() ||
430 (I->getOperand(X86::AddrScaleAmt).getImm() != 1) ||
431 (I->getOperand(X86::AddrIndexReg).getReg() != X86::NoRegister) ||
432 (I->getOperand(X86::AddrSegmentReg).getReg() != X86::NoRegister) ||
433 !I->getOperand(X86::AddrDisp).isImm())
436 int64_t StackDisp = I->getOperand(X86::AddrDisp).getImm();
509 MachineOperand PushOp = Store->getOperand(X86::AddrNumOperands);
564 Push->addOperand(DefMov->getOperand(i));
590 if (Context.SPCopy && MRI->use_empty(Context.SPCopy->getOperand(0).getReg()))
lib/Target/X86/X86CallLowering.cpp 142 ExtReg = MIB->getOperand(0).getReg();
451 MIB->getOperand(0).setReg(constrainOperandRegClass(
lib/Target/X86/X86CmovConversion.cpp 452 DepthMap[OperandToDefMap.lookup(&MI.getOperand(1))].OptDepth,
453 DepthMap[OperandToDefMap.lookup(&MI.getOperand(2))].OptDepth);
547 DepthMap[OperandToDefMap.lookup(&MI->getOperand(4))].Depth;
549 DepthMap[OperandToDefMap.lookup(&MI->getOperand(1))].Depth,
550 DepthMap[OperandToDefMap.lookup(&MI->getOperand(2))].Depth);
714 MI.getOperand(X86::getCondFromCMov(MI) == CC ? 1 : 2).getReg();
722 FalseBBRegRewriteTable[MI.getOperand(0).getReg()] = FalseReg;
755 const TargetRegisterClass *RC = MRI->getRegClass(MI.getOperand(0).getReg());
801 FalseBBRegRewriteTable[NewCMOV->getOperand(0).getReg()] = TmpReg;
813 Register DestReg = MIIt->getOperand(0).getReg();
814 Register Op1Reg = MIIt->getOperand(1).getReg();
815 Register Op2Reg = MIIt->getOperand(2).getReg();
lib/Target/X86/X86CondBrFolding.cpp 192 MachineOperand &MO = MI->getOperand(i);
506 FBB = I->getOperand(0).getMBB();
524 TBB = I->getOperand(0).getMBB();
lib/Target/X86/X86DomainReassignment.cpp 190 Bld.add(MI->getOperand(Idx));
193 .add(MI->getOperand(0))
272 .add({MI->getOperand(0), MI->getOperand(SrcOpIdx)});
272 .add({MI->getOperand(0), MI->getOperand(SrcOpIdx)});
576 auto &Op = DefMI->getOperand(OpIdx);
lib/Target/X86/X86EvexToVex.cpp 159 MachineOperand &Imm = MI.getOperand(MI.getNumExplicitOperands()-1);
174 MachineOperand &Imm = MI.getOperand(MI.getNumExplicitOperands()-1);
196 const MachineOperand &Imm = MI.getOperand(MI.getNumExplicitOperands()-1);
lib/Target/X86/X86ExpandPseudo.cpp 86 MachineOperand Selector = JTInst->getOperand(0);
87 const GlobalValue *CombinedGlobal = JTInst->getOperand(1).getGlobal();
97 JTInst->getOperand(2 + 2 * Target).getImm())
129 .add(JTInst->getOperand(3 + 2 * Target));
171 .add(JTInst->getOperand(3 + 2 * P.second));
196 MachineOperand &JumpTarget = MBBI->getOperand(0);
197 MachineOperand &StackAdjust = MBBI->getOperand(isMem ? X86::AddrNumOperands
255 MIB.addImm(MBBI->getOperand(2).getImm());
264 MIB.add(MBBI->getOperand(i));
287 MachineOperand &DestAddr = MBBI->getOperand(0);
300 int64_t StackAdj = MBBI->getOperand(0).getImm();
310 int64_t StackAdj = MBBI->getOperand(0).getImm();
330 MIB.add(MBBI->getOperand(I));
350 const MachineOperand &InArg = MBBI->getOperand(6);
351 Register SaveRbx = MBBI->getOperand(7).getReg();
365 NewInstr->addOperand(MBBI->getOperand(Idx));
lib/Target/X86/X86FixupBWInsts.cpp 181 Register OrigDestReg = OrigMI->getOperand(0).getReg();
292 MIB.add(MI->getOperand(i));
301 auto &OldDest = MI->getOperand(0);
302 auto &OldSrc = MI->getOperand(1);
345 MI->getOperand(0).getReg() == X86::AX &&
346 MI->getOperand(1).getReg() == X86::AL)
355 MIB.add(MI->getOperand(i));
lib/Target/X86/X86FixupLEAs.cpp 132 const MachineOperand &Src = MI.getOperand(1);
133 const MachineOperand &Dest = MI.getOperand(0);
163 if (!MI.getOperand(2).isImm()) {
244 MachineOperand &opnd = MI.getOperand(i);
357 const MachineOperand &Base = MI.getOperand(1 + X86::AddrBaseReg);
358 const MachineOperand &Scale = MI.getOperand(1 + X86::AddrScaleAmt);
359 const MachineOperand &Index = MI.getOperand(1 + X86::AddrIndexReg);
360 const MachineOperand &Disp = MI.getOperand(1 + X86::AddrDisp);
361 const MachineOperand &Segment = MI.getOperand(1 + X86::AddrSegmentReg);
367 Register DestReg = MI.getOperand(0).getReg();
450 MachineOperand &p = MI.getOperand(AddrOffset + X86::AddrBaseReg);
454 MachineOperand &q = MI.getOperand(AddrOffset + X86::AddrIndexReg);
485 const MachineOperand &Dst = MI.getOperand(0);
486 const MachineOperand &Base = MI.getOperand(1 + X86::AddrBaseReg);
487 const MachineOperand &Scale = MI.getOperand(1 + X86::AddrScaleAmt);
488 const MachineOperand &Index = MI.getOperand(1 + X86::AddrIndexReg);
489 const MachineOperand &Offset = MI.getOperand(1 + X86::AddrDisp);
490 const MachineOperand &Segment = MI.getOperand(1 + X86::AddrSegmentReg);
535 const MachineOperand &Dest = MI.getOperand(0);
536 const MachineOperand &Base = MI.getOperand(1 + X86::AddrBaseReg);
537 const MachineOperand &Scale = MI.getOperand(1 + X86::AddrScaleAmt);
538 const MachineOperand &Index = MI.getOperand(1 + X86::AddrIndexReg);
539 const MachineOperand &Offset = MI.getOperand(1 + X86::AddrDisp);
540 const MachineOperand &Segment = MI.getOperand(1 + X86::AddrSegmentReg);
lib/Target/X86/X86FixupSetCC.cpp 111 for (auto &Use : MRI->use_instructions(MI.getOperand(0).getReg()))
151 .addReg(MI.getOperand(0).getReg())
153 MRI->replaceRegWith(ZExt->getOperand(0).getReg(), InsertReg);
lib/Target/X86/X86FlagsCopyLowering.cpp 258 MachineBasicBlock &UnsplitSucc = *PrevI.getOperand(0).getMBB();
311 MachineOperand &OpV = MI.getOperand(OpIdx);
312 MachineOperand &OpMBB = MI.getOperand(OpIdx + 1);
361 MI.getOperand(0).getReg() == X86::EFLAGS)
367 MachineOperand &VOp = CopyI->getOperand(1);
397 if (MRI->use_empty(CopyDefI.getOperand(0).getReg()))
402 MachineOperand &DOp = CopyI->getOperand(0);
703 (MI.getOperand(0).getReg() == X86::EFLAGS ||
704 MI.getOperand(1).getReg() == X86::EFLAGS)) {
725 MI.getOperand(0).isReg() &&
726 Register::isVirtualRegister(MI.getOperand(0).getReg())) {
727 assert(MI.getOperand(0).isDef() &&
729 CondRegs[Cond] = MI.getOperand(0).getReg();
849 CMovI.getOperand(CMovI.getDesc().getNumOperands() - 1)
872 JmpI.getOperand(1).setImm(Inverted ? X86::COND_E : X86::COND_NE);
881 MRI->replaceRegWith(MI.getOperand(0).getReg(),
882 CopyDefI.getOperand(0).getReg());
897 assert(SetBI.getOperand(0).isReg() &&
904 MRI->replaceRegWith(SetBI.getOperand(0).getReg(), Reg);
909 auto &SetBRC = *MRI->getRegClass(SetBI.getOperand(0).getReg());
1027 assert(SetCCI.getOperand(0).isReg() &&
1029 MRI->replaceRegWith(SetCCI.getOperand(0).getReg(), CondReg);
1039 MIB.add(SetCCI.getOperand(i));
lib/Target/X86/X86FloatingPoint.cpp 291 Register DstReg = MI.getOperand(0).getReg();
292 Register SrcReg = MI.getOperand(1).getReg();
429 X86::RFP80RegClass.contains(MI.getOperand(0).getReg()))
449 const MachineOperand &MO = MI.getOperand(i);
1018 MachineOperand &Op = MI.getOperand(i);
1099 unsigned DestReg = getFPReg(MI.getOperand(0));
1120 unsigned Reg = getFPReg(MI.getOperand(NumOps - 1));
1181 unsigned Reg = getFPReg(MI.getOperand(1));
1191 pushReg(getFPReg(MI.getOperand(0)));
1195 duplicateToTop(Reg, getFPReg(MI.getOperand(0)), I);
1289 unsigned Dest = getFPReg(MI.getOperand(0));
1290 unsigned Op0 = getFPReg(MI.getOperand(NumOperands - 2));
1291 unsigned Op1 = getFPReg(MI.getOperand(NumOperands - 1));
1385 unsigned Op0 = getFPReg(MI.getOperand(NumOperands - 2));
1386 unsigned Op1 = getFPReg(MI.getOperand(NumOperands - 1));
1395 MI.getOperand(0).setReg(getSTReg(Op1));
1411 unsigned Op0 = getFPReg(MI.getOperand(0));
1412 unsigned Op1 = getFPReg(MI.getOperand(2));
1422 MI.getOperand(0).setReg(getSTReg(Op1));
1454 const MachineOperand &MO1 = MI.getOperand(1);
1455 const MachineOperand &MO0 = MI.getOperand(0);
1478 unsigned Reg = MI.getOperand(0).getReg() - X86::FP0;
1526 i != e && MI.getOperand(i).isImm(); i += 1 + NumOps) {
1527 unsigned Flags = MI.getOperand(i).getImm();
1532 const MachineOperand &MO = MI.getOperand(i + 1);
1594 assert((1 << getFPReg(MI.getOperand(I)) & STDefs) == 0 &&
1603 MachineOperand &Op = MI.getOperand(i);
1632 MachineOperand &Op = MI.getOperand(i);
lib/Target/X86/X86FrameLowering.cpp 176 MachineOperand &MO = MBBI->getOperand(i);
281 MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
307 MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
389 MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
423 PI->getOperand(0).getReg() == StackPtr){
424 assert(PI->getOperand(1).getReg() == StackPtr);
425 Offset = PI->getOperand(2).getImm();
427 PI->getOperand(0).getReg() == StackPtr &&
428 PI->getOperand(1).getReg() == StackPtr &&
429 PI->getOperand(2).getImm() == 1 &&
430 PI->getOperand(3).getReg() == X86::NoRegister &&
431 PI->getOperand(5).getReg() == X86::NoRegister) {
433 Offset = PI->getOperand(4).getImm();
436 PI->getOperand(0).getReg() == StackPtr) {
437 assert(PI->getOperand(1).getReg() == StackPtr);
438 Offset = -PI->getOperand(2).getImm();
506 if (MI.isCall() && MI.getOperand(0).isSymbol() &&
507 ChkStkStubSymbol == MI.getOperand(0).getSymbolName()) {
872 MI->getOperand(3).setIsDead();
1188 Register Reg = MBBI->getOperand(0).getReg();
2144 MachineBasicBlock *CatchRetTarget = CatchRet->getOperand(0).getMBB();
2624 const MachineOperand &MO = MI.getOperand(0);
2737 if (!Prev->isCall() || !Prev->getOperand(1).isRegMask())
2744 auto RegMask = Prev->getOperand(1);
2983 ->getOperand(3)
lib/Target/X86/X86ISelLowering.cpp 4247 Def->getOperand(1).isFI()) {
4248 FI = Def->getOperand(1).getIndex();
29212 Register DstReg = MI.getOperand(0).getReg();
29269 Register DestReg = MI.getOperand(0).getReg();
29270 MachineOperand &Base = MI.getOperand(1);
29271 MachineOperand &Scale = MI.getOperand(2);
29272 MachineOperand &Index = MI.getOperand(3);
29273 MachineOperand &Disp = MI.getOperand(4);
29274 MachineOperand &Segment = MI.getOperand(5);
29275 unsigned ArgSize = MI.getOperand(6).getImm();
29276 unsigned ArgMode = MI.getOperand(7).getImm();
29277 unsigned Align = MI.getOperand(8).getImm();
29547 Register CountReg = MI.getOperand(0).getReg();
29548 int64_t RegSaveFrameIndex = MI.getOperand(1).getImm();
29549 int64_t VarArgsFPOffset = MI.getOperand(2).getImm();
29561 !MI.getOperand(MI.getNumOperands() - 1).isReg() ||
29562 MI.getOperand(MI.getNumOperands() - 1).getReg() == X86::EFLAGS) &&
29578 .addReg(MI.getOperand(i).getReg())
29669 X86::CondCode CC = X86::CondCode(MIItBegin->getOperand(3).getImm());
29684 Register DestReg = MIIt->getOperand(0).getReg();
29685 Register Op1Reg = MIIt->getOperand(1).getReg();
29686 Register Op2Reg = MIIt->getOperand(2).getReg();
29691 if (MIIt->getOperand(3).getImm() == OppCC)
29835 X86::CondCode FirstCC = X86::CondCode(FirstCMOV.getOperand(3).getImm());
29839 X86::CondCode(SecondCascadedCMOV.getOperand(3).getImm());
29844 Register DestReg = FirstCMOV.getOperand(0).getReg();
29845 Register Op1Reg = FirstCMOV.getOperand(1).getReg();
29846 Register Op2Reg = FirstCMOV.getOperand(2).getReg();
29856 MIB.addReg(FirstCMOV.getOperand(2).getReg()).addMBB(FirstInsertedMBB);
29860 SecondCascadedCMOV.getOperand(0).getReg())
29861 .addReg(FirstCMOV.getOperand(0).getReg());
29923 X86::CondCode CC = X86::CondCode(MI.getOperand(3).getImm());
29936 (NextMIIt->getOperand(3).getImm() == CC ||
29937 NextMIIt->getOperand(3).getImm() == OppCC)) {
29948 NextMIIt->getOperand(2).getReg() == MI.getOperand(2).getReg() &&
29948 NextMIIt->getOperand(2).getReg() == MI.getOperand(2).getReg() &&
29949 NextMIIt->getOperand(1).getReg() == MI.getOperand(0).getReg() &&
29949 NextMIIt->getOperand(1).getReg() == MI.getOperand(0).getReg() &&
29950 NextMIIt->getOperand(1).isKill()) {
30056 sizeVReg = MI.getOperand(1).getReg(),
30133 MI.getOperand(0).getReg())
30151 MachineBasicBlock *TargetMBB = MI.getOperand(0).getMBB();
30170 MI.getOperand(0).setMBB(RestoreMBB);
30235 assert(MI.getOperand(3).isGlobal() && "This should be a global");
30250 .addGlobalAddress(MI.getOperand(3).getGlobal(), 0,
30251 MI.getOperand(3).getTargetFlags())
30262 .addGlobalAddress(MI.getOperand(3).getGlobal(), 0,
30263 MI.getOperand(3).getTargetFlags())
30274 .addGlobalAddress(MI.getOperand(3).getGlobal(), 0,
30275 MI.getOperand(3).getTargetFlags())
30364 Register CalleeVReg = MI.getOperand(0).getReg();
30403 MI.getOperand(0).ChangeToES(Symbol);
30456 MIB.addDisp(MI.getOperand(MemOpndSlot + i), SSPOffset);
30458 MIB.add(MI.getOperand(MemOpndSlot + i));
30485 DstReg = MI.getOperand(CurOp++).getReg();
30564 MIB.addDisp(MI.getOperand(MemOpndSlot + i), LabelOffset);
30566 MIB.add(MI.getOperand(MemOpndSlot + i));
30716 const MachineOperand &MO = MI.getOperand(i);
30842 const MachineOperand &MO = MI.getOperand(i);
30854 const MachineOperand &MO = MI.getOperand(i);
30869 MIB.addDisp(MI.getOperand(i), SPOffset);
30871 MIB.add(MI.getOperand(i)); // We can preserve the kill flags here, it's
31223 assert(Push->getOperand(2).getReg() == X86::EFLAGS &&
31225 Push->getOperand(2).setIsUndef();
31226 assert(Push->getOperand(3).getReg() == X86::DF &&
31228 Push->getOperand(3).setIsUndef();
31229 BuildMI(*BB, MI, DL, TII->get(Pop), MI.getOperand(0).getReg());
31241 BuildMI(*BB, MI, DL, TII->get(Push)).addReg(MI.getOperand(0).getReg());
31306 .addReg(MI.getOperand(X86::AddrNumOperands).getReg());
lib/Target/X86/X86IndirectBranchTracking.cpp 133 if (IsCallReturnTwice(I->getOperand(0)))
lib/Target/X86/X86InsertPrefetch.cpp 225 MIB.addReg(Current->getOperand(MemOpOffset + X86::AddrBaseReg).getReg())
227 Current->getOperand(MemOpOffset + X86::AddrScaleAmt).getImm())
229 Current->getOperand(MemOpOffset + X86::AddrIndexReg).getReg())
230 .addImm(Current->getOperand(MemOpOffset + X86::AddrDisp).getImm() +
232 .addReg(Current->getOperand(MemOpOffset + X86::AddrSegmentReg)
lib/Target/X86/X86InstrBuilder.h 135 MI->getOperand(Operand).ChangeToRegister(Reg, /*isDef=*/false);
136 MI->getOperand(Operand + 1).setImm(1);
137 MI->getOperand(Operand + 2).setReg(0);
138 MI->getOperand(Operand + 3).ChangeToImmediate(0);
139 MI->getOperand(Operand + 4).setReg(0);
lib/Target/X86/X86InstrInfo.cpp 674 MachineOperand &MO = MI.getOperand(i);
766 *RegInfo.getRegClass(MI.getOperand(0).getReg())) == 16) &&
791 Register Dest = MI.getOperand(0).getReg();
792 Register Src = MI.getOperand(1).getReg();
793 bool IsDead = MI.getOperand(0).isDead();
794 bool IsKill = MI.getOperand(1).isKill();
796 assert(!MI.getOperand(1).isUndef() && "Undef op doesn't need optimization");
809 unsigned ShAmt = MI.getOperand(2).getImm();
828 addRegOffset(MIB, InRegLEA, true, MI.getOperand(2).getImm());
834 Register Src2 = MI.getOperand(2).getReg();
835 bool IsKill2 = MI.getOperand(2).isKill();
836 assert(!MI.getOperand(2).isUndef() && "Undef op doesn't need optimization");
902 const MachineOperand &Dest = MI.getOperand(0);
903 const MachineOperand &Src = MI.getOperand(1);
912 if (MI.getOperand(2).isReg() && MI.getOperand(2).isUndef())
912 if (MI.getOperand(2).isReg() && MI.getOperand(2).isUndef())
1051 const MachineOperand &Src2 = MI.getOperand(2);
1084 MI.getOperand(2));
1106 NewMI = addOffset(MIB, MI.getOperand(2));
1125 if (!MI.getOperand(2).isImm())
1127 int64_t Imm = MI.getOperand(2).getImm();
1153 if (!MI.getOperand(2).isImm())
1155 int64_t Imm = MI.getOperand(2).getImm();
1244 .add(MI.getOperand(2))
1246 .add(MI.getOperand(3))
1247 .add(MI.getOperand(4))
1248 .add(MI.getOperand(5))
1249 .add(MI.getOperand(6))
1250 .add(MI.getOperand(7));
1309 .add(MI.getOperand(2))
1311 .add(MI.getOperand(3));
1429 uint8_t Imm = MI.getOperand(MI.getNumOperands()-1).getImm();
1438 MI.getOperand(MI.getNumOperands()-1).setImm(NewImm);
1554 unsigned Amt = MI.getOperand(3).getImm();
1557 WorkingMI.getOperand(3).setImm(Size - Amt);
1586 if ((MI.getOperand(3).getImm() ^ Mask) == 1) {
1621 int8_t Imm = MI.getOperand(3).getImm() & Mask;
1623 WorkingMI.getOperand(3).setImm(Mask ^ Imm);
1630 unsigned Imm = MI.getOperand(MI.getNumOperands() - 1).getImm();
1643 WorkingMI.getOperand(MI.getNumOperands() - 1).setImm(AltImm);
1683 assert(MI.getOperand(3).getImm() == 0x02 && "Unexpected immediate!");
1698 unsigned Imm = MI.getOperand(3).getImm();
1702 WorkingMI.getOperand(3).setImm((Src1Hi << 4) | (Src2Hi >> 4));
1731 unsigned Imm = MI.getOperand(MI.getNumOperands() - 1).getImm() & 0x7;
1734 WorkingMI.getOperand(MI.getNumOperands() - 1).setImm(Imm);
1743 unsigned Imm = MI.getOperand(3).getImm() & 0x7;
1746 WorkingMI.getOperand(3).setImm(Imm);
1764 unsigned Imm = MI.getOperand(MI.getNumOperands() - 1).getImm() & 0x1f;
1767 WorkingMI.getOperand(MI.getNumOperands() - 1).setImm(Imm);
1776 int8_t Imm = MI.getOperand(3).getImm() & 0xFF;
1778 WorkingMI.getOperand(3).setImm(Imm ^ 0x22);
1808 X86::CondCode CC = static_cast<X86::CondCode>(MI.getOperand(OpNo).getImm());
1809 WorkingMI.getOperand(OpNo).setImm(X86::GetOppositeBranchCondition(CC));
2531 TBB = I->getOperand(0).getMBB();
2543 if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
2552 TBB = I->getOperand(0).getMBB();
2568 MachineBasicBlock *TargetBB = I->getOperand(0).getMBB();
2592 .addMBB(UnCondBrIter->getOperand(0).getMBB())
2607 TBB = I->getOperand(0).getMBB();
2621 auto NewTBB = I->getOperand(0).getMBB();
2733 ConditionDef->getOperand(0).isIdenticalTo(ConditionDef->getOperand(1)) &&
2733 ConditionDef->getOperand(0).isIdenticalTo(ConditionDef->getOperand(1)) &&
2735 MBP.LHS = ConditionDef->getOperand(0);
3574 if (!MRI->use_nodbg_empty(CmpInstr.getOperand(0).getReg()))
3630 if (NewCC != X86::COND_INVALID && J->getOperand(1).isReg() &&
3631 J->getOperand(1).getReg() == SrcReg) {
3694 (SrcReg2 != 0 && Sub && Sub->getOperand(1).getReg() == SrcReg2 &&
3695 Sub->getOperand(2).getReg() == SrcReg);
3823 Op.first->getOperand(Op.first->getDesc().getNumOperands() - 1)
3847 MachineOperand &MO = MI.getOperand(i);
3880 Register Reg = MIB->getOperand(0).getReg();
3887 assert(MIB->getOperand(1).getReg() == Reg &&
3888 MIB->getOperand(2).getReg() == Reg && "Misplaced operand");
3910 Register Reg = MIB->getOperand(0).getReg();
3929 int64_t Imm = MIB->getOperand(1).getImm();
3953 MIB->getOperand(0)
3954 .setReg(getX86SubSuperRegister(MIB->getOperand(0).getReg(), 64));
3986 Register Reg = MIB->getOperand(0).getReg();
4024 Register DestReg = MIB->getOperand(0).getReg();
4034 MIB->getOperand(0).setReg(DestReg);
4047 Register SrcReg = MIB->getOperand(X86::AddrNumOperands).getReg();
4057 MIB->getOperand(X86::AddrNumOperands).setReg(SrcReg);
4066 int64_t ShiftAmt = MIB->getOperand(2).getImm();
4070 MIB.addReg(MIB->getOperand(1).getReg(),
4071 getUndefRegState(MIB->getOperand(1).isUndef()));
4108 Register SrcReg = MIB->getOperand(0).getReg();
4110 MIB->getOperand(0).setReg(XReg);
4120 Register SrcReg = MIB->getOperand(0).getReg();
4128 MIB->getOperand(0).setReg(SrcReg);
4134 Register SrcReg = MIB->getOperand(0).getReg();
4138 MIB->getOperand(0).setReg(XReg);
4148 MIB->getOperand(0).setReg(ZReg);
4157 Register Reg = MIB->getOperand(0).getReg();
4164 Register Reg = MIB->getOperand(0).getReg();
4174 Register Reg = MIB->getOperand(0).getReg();
4175 Register MaskReg = MIB->getOperand(1).getReg();
4176 unsigned MaskState = getRegState(MIB->getOperand(1));
4212 Register Reg = MIB->getOperand(0).getReg();
4215 MIB->getOperand(0).setReg(Reg32);
4569 Register Reg = MI.getOperand(OpNum).getReg();
4639 MachineOperand &MO = NewMI.getOperand(Idx);
4673 MachineOperand &MO = MI.getOperand(i + 2);
4677 MachineOperand &MO = MI.getOperand(i);
4700 MachineOperand &MO = MI.getOperand(i);
4738 unsigned Imm = MI.getOperand(MI.getNumOperands() - 1).getImm();
4755 NewMI->getOperand(NewMI->getNumOperands() - 1).setImm(NewImm);
4805 !MI.getOperand(1).isReg())
4813 if (MI.getOperand(1).isUndef())
4817 MachineInstr *VRegDef = RegInfo.getUniqueVRegDef(MI.getOperand(1).getReg());
4851 MI.getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS)
4874 if (isTwoAddr && NumOps >= 2 && OpNum < 2 && MI.getOperand(0).isReg() &&
4875 MI.getOperand(1).isReg() &&
4876 MI.getOperand(0).getReg() == MI.getOperand(1).getReg()) {
4876 MI.getOperand(0).getReg() == MI.getOperand(1).getReg()) {
4912 if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
4912 if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
4928 Register DstReg = NewMI->getOperand(0).getReg();
4930 NewMI->getOperand(0).setReg(RI.getSubReg(DstReg, X86::sub_32bit));
4932 NewMI->getOperand(0).setSubReg(X86::sub_32bit);
4943 Register Reg0 = HasDef ? MI.getOperand(0).getReg() : Register();
4944 Register Reg1 = MI.getOperand(CommuteOpIdx1).getReg();
4945 Register Reg2 = MI.getOperand(CommuteOpIdx2).getReg();
5017 MachineOperand &MO = MI.getOperand(Op);
5047 MI.getOperand(1).ChangeToImmediate(0);
5199 if (MI.getOperand(Op).getSubReg())
5267 MI.getOperand(1).ChangeToImmediate(0);
5273 if (LoadMI.getOperand(0).getSubReg() != MI.getOperand(Ops[0]).getSubReg())
5273 if (LoadMI.getOperand(0).getSubReg() != MI.getOperand(Ops[0]).getSubReg())
5485 MachineOperand &Op = MI.getOperand(i);
5519 MachineOperand &MO = NewMIs[0]->getOperand(i);
5556 MachineOperand &MO0 = DataMI->getOperand(0);
5557 MachineOperand &MO1 = DataMI->getOperand(1);
6697 if (MI.getOperand(NumOperands - 1).isImm()) {
6698 unsigned Imm = MI.getOperand(NumOperands - 1).getImm() & 255;
6725 MI.getOperand(NumOperands - 1).setImm(NewImm & 255);
6793 MI.getOperand(1).getReg() == MI.getOperand(2).getReg() &&
6793 MI.getOperand(1).getReg() == MI.getOperand(2).getReg() &&
6794 MI.getOperand(0).getSubReg() == 0 &&
6795 MI.getOperand(1).getSubReg() == 0 &&
6796 MI.getOperand(2).getSubReg() == 0) {
6806 unsigned Imm = MI.getOperand(3).getImm();
6810 MI.getOperand(3).setImm(NewImm);
7670 MachineOperand &OldOp1 = OldMI1.getOperand(3);
7671 MachineOperand &OldOp2 = OldMI2.getOperand(3);
7672 MachineOperand &NewOp1 = NewMI1.getOperand(3);
7673 MachineOperand &NewOp2 = NewMI2.getOperand(3);
lib/Target/X86/X86InstrInfo.h 167 I.getOperand(2).setImm(V);
169 I.getOperand(1).setImm(V);
lib/Target/X86/X86InstructionSelector.cpp 232 Register DstReg = I.getOperand(0).getReg();
236 Register SrcReg = I.getOperand(1).getReg();
260 I.getOperand(1).setReg(ExtSrc);
287 I.getOperand(1).setSubReg(getSubRegIndex(DstRC));
288 I.getOperand(1).substPhysReg(SrcReg, TRI);
506 const Register DefReg = I.getOperand(0).getReg();
533 X86SelectAddress(*MRI.getVRegDef(I.getOperand(1).getReg()), MRI, AM);
566 const Register DefReg = I.getOperand(0).getReg();
577 MachineOperand &InxOp = I.getOperand(2);
592 auto GV = I.getOperand(1).getGlobal();
619 const Register DefReg = I.getOperand(0).getReg();
638 const Register DefReg = I.getOperand(0).getReg();
645 if (I.getOperand(1).isCImm()) {
646 Val = I.getOperand(1).getCImm()->getZExtValue();
647 I.getOperand(1).ChangeToImmediate(Val);
648 } else if (I.getOperand(1).isImm()) {
649 Val = I.getOperand(1).getImm();
711 const Register DstReg = I.getOperand(0).getReg();
712 const Register SrcReg = I.getOperand(1).getReg();
764 I.getOperand(1).setSubReg(SubIdx);
775 const Register DstReg = I.getOperand(0).getReg();
776 const Register SrcReg = I.getOperand(1).getReg();
886 const Register DstReg = I.getOperand(0).getReg();
887 const Register SrcReg = I.getOperand(1).getReg();
944 (CmpInst::Predicate)I.getOperand(1).getPredicate());
946 Register LHS = I.getOperand(2).getReg();
947 Register RHS = I.getOperand(3).getReg();
978 TII.get(X86::SETCCr), I.getOperand(0).getReg()).addImm(CC);
992 Register LhsReg = I.getOperand(2).getReg();
993 Register RhsReg = I.getOperand(3).getReg();
995 (CmpInst::Predicate)I.getOperand(1).getPredicate();
1027 Register ResultReg = I.getOperand(0).getReg();
1083 const Register DstReg = I.getOperand(0).getReg();
1084 const Register CarryOutReg = I.getOperand(1).getReg();
1085 const Register Op0Reg = I.getOperand(2).getReg();
1086 const Register Op1Reg = I.getOperand(3).getReg();
1087 Register CarryInReg = I.getOperand(4).getReg();
1097 CarryInReg = Def->getOperand(1).getReg();
1143 const Register DstReg = I.getOperand(0).getReg();
1144 const Register SrcReg = I.getOperand(1).getReg();
1145 int64_t Index = I.getOperand(2).getImm();
1189 I.getOperand(2).setImm(Index);
1275 const Register DstReg = I.getOperand(0).getReg();
1276 const Register SrcReg = I.getOperand(1).getReg();
1277 const Register InsertReg = I.getOperand(2).getReg();
1278 int64_t Index = I.getOperand(3).getImm();
1323 I.getOperand(3).setImm(Index);
1335 Register SrcReg = I.getOperand(NumDefs).getReg();
1336 unsigned DefSize = MRI.getType(I.getOperand(0).getReg()).getSizeInBits();
1341 TII.get(TargetOpcode::G_EXTRACT), I.getOperand(Idx).getReg())
1360 Register DstReg = I.getOperand(0).getReg();
1361 Register SrcReg0 = I.getOperand(1).getReg();
1372 if (!emitInsertSubreg(DefReg, I.getOperand(1).getReg(), I, MRI, MF))
1382 .addReg(I.getOperand(Idx).getReg())
1407 const Register CondReg = I.getOperand(0).getReg();
1408 MachineBasicBlock *DestMBB = I.getOperand(1).getMBB();
1434 const Register DstReg = I.getOperand(0).getReg();
1443 const ConstantFP *CFP = I.getOperand(1).getFPImm();
1495 Register DstReg = I.getOperand(0).getReg();
1526 const Register DstReg = I.getOperand(0).getReg();
1527 const Register Op1Reg = I.getOperand(1).getReg();
1528 const Register Op2Reg = I.getOperand(2).getReg();
1723 if (I.getOperand(0).getIntrinsicID() != Intrinsic::trap)
lib/Target/X86/X86OptimizeLEAs.cpp 357 MRI->getRegClass(DefMI->getOperand(0).getReg()))
451 if (!isIdenticalOp(MI.getOperand(MemOpNo + X86::AddrBaseReg), MO))
458 isIdenticalOp(MI.getOperand(i), MO))
462 if (MI.getOperand(MemOpNo + X86::AddrDisp).isImm() &&
463 !isInt<32>(MI.getOperand(MemOpNo + X86::AddrDisp).getImm() +
546 MRI->clearKillFlags(DefMI->getOperand(0).getReg());
552 MI.getOperand(MemOpNo + X86::AddrBaseReg)
553 .ChangeToRegister(DefMI->getOperand(0).getReg(), false);
554 MI.getOperand(MemOpNo + X86::AddrScaleAmt).ChangeToImmediate(1);
555 MI.getOperand(MemOpNo + X86::AddrIndexReg)
557 MI.getOperand(MemOpNo + X86::AddrDisp).ChangeToImmediate(AddrDispShift);
558 MI.getOperand(MemOpNo + X86::AddrSegmentReg)
582 assert(MI.getOperand(1).getImm() == 0 && "DBG_VALUE with nonzero offset");
618 Register FirstVReg = First.getOperand(0).getReg();
619 Register LastVReg = Last.getOperand(0).getReg();
643 MachineOperand &Op = MI.getOperand(MemOpNo + X86::AddrDisp);
lib/Target/X86/X86RegisterInfo.cpp 683 MI.getOperand(2).getImm() != 1 ||
684 MI.getOperand(3).getReg() != X86::NoRegister ||
685 MI.getOperand(4).getImm() != 0 ||
686 MI.getOperand(5).getReg() != X86::NoRegister)
688 Register BasePtr = MI.getOperand(1).getReg();
694 Register NewDestReg = MI.getOperand(0).getReg();
698 MI.getOperand(1).isKill());
725 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
748 MachineOperand &FI = MI.getOperand(FIOperandNum);
763 MI.getOperand(FIOperandNum).ChangeToRegister(MachineBasePtr, false);
772 int64_t Offset = MI.getOperand(FIOperandNum + 1).getImm() + FIOffset;
773 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
777 if (MI.getOperand(FIOperandNum+3).isImm()) {
779 int Imm = (int)(MI.getOperand(FIOperandNum + 3).getImm());
784 MI.getOperand(FIOperandNum + 3).ChangeToImmediate(Offset);
788 (uint64_t)MI.getOperand(FIOperandNum+3).getOffset();
789 MI.getOperand(FIOperandNum + 3).setOffset(Offset);
lib/Target/X86/X86SpeculativeLoadHardening.cpp 240 assert(Br->getOperand(0).getMBB() == &Succ &&
242 Br->getOperand(0).setMBB(&NewMBB);
291 MachineOperand &OpV = MI.getOperand(OpIdx);
292 MachineOperand &OpMBB = MI.getOperand(OpIdx + 1);
340 if (!Preds.insert(MI.getOperand(OpIdx + 1).getMBB()).second)
711 ? UncondBr->getOperand(0).getMBB()
720 ++SuccCounts[CondBr->getOperand(0).getMBB()];
786 MachineBasicBlock &Succ = *CondBr->getOperand(0).getMBB();
1018 TargetReg = TI.getOperand(0).getReg();
1713 MI.getOperand(MemRefBeginIdx + X86::AddrBaseReg);
1715 MI.getOperand(MemRefBeginIdx + X86::AddrIndexReg);
1744 MI.getDesc().getNumDefs() == 1 && MI.getOperand(0).isReg() &&
1745 canHardenRegister(MI.getOperand(0).getReg()) &&
1749 HardenedAddrRegs.insert(MI.getOperand(0).getReg());
1786 MI.getOperand(MemRefBeginIdx + X86::AddrBaseReg);
1788 MI.getOperand(MemRefBeginIdx + X86::AddrIndexReg);
2156 Register DefReg = MI.getOperand(0).getReg();
2184 UseMI.getOperand(MemRefBeginIdx + X86::AddrBaseReg);
2186 UseMI.getOperand(MemRefBeginIdx + X86::AddrIndexReg);
2213 Register UseDefReg = UseMI.getOperand(0).getReg();
2334 auto &DefOp = MI.getOperand(0);
2611 if (!MI.getOperand(0).isReg())
2616 auto &TargetOp = MI.getOperand(0);
lib/Target/X86/X86WinAllocaExpander.cpp 82 assert(MI->getOperand(0).isReg());
84 Register AmountReg = MI->getOperand(0).getReg();
89 !Def->getOperand(1).isImm())
92 return Def->getOperand(1).getImm();
177 Offset -= MI.getOperand(0).getImm();
180 Offset += MI.getOperand(0).getImm();
249 .addReg(MI->getOperand(0).getReg());
259 .addReg(MI->getOperand(0).getReg());
264 Register AmountReg = MI->getOperand(0).getReg();
lib/Target/XCore/XCoreFrameLowering.cpp 370 Register EhStackReg = MBBI->getOperand(0).getReg();
371 Register EhHandlerReg = MBBI->getOperand(1).getReg();
404 MIB->addOperand(MBBI->getOperand(i)); // copy any variadic operands
494 uint64_t Amount = Old.getOperand(0).getImm();
lib/Target/XCore/XCoreFrameToArgsOffsetElim.cpp 58 Register Reg = OldInst.getOperand(0).getReg();
lib/Target/XCore/XCoreISelLowering.cpp 1560 .addReg(MI.getOperand(1).getReg())
1575 BuildMI(*BB, BB->begin(), dl, TII.get(XCore::PHI), MI.getOperand(0).getReg())
1576 .addReg(MI.getOperand(3).getReg())
1578 .addReg(MI.getOperand(2).getReg())
lib/Target/XCore/XCoreInstrInfo.cpp 208 TBB = LastInst->getOperand(0).getMBB();
219 TBB = LastInst->getOperand(1).getMBB();
221 Cond.push_back(LastInst->getOperand(0));
240 TBB = SecondLastInst->getOperand(1).getMBB();
242 Cond.push_back(SecondLastInst->getOperand(0));
244 FBB = LastInst->getOperand(0).getMBB();
252 TBB = SecondLastInst->getOperand(0).getMBB();
lib/Target/XCore/XCoreRegisterInfo.cpp 77 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill()))
113 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill()))
147 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill()))
190 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill()))
264 MachineOperand &FrameOp = MI.getOperand(FIOperandNum);
290 MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false /*isDef*/);
291 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
296 Offset += MI.getOperand(FIOperandNum + 1).getImm();
297 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(0);
304 Register Reg = MI.getOperand(0).getReg();
unittests/CodeGen/GlobalISel/CSETest.cpp 63 EXPECT_EQ(Splat0->getOperand(1).getReg(), Splat0->getOperand(2).getReg());
63 EXPECT_EQ(Splat0->getOperand(1).getReg(), Splat0->getOperand(2).getReg());
64 EXPECT_EQ(&*MIBCst, MRI->getVRegDef(Splat0->getOperand(1).getReg()));
68 EXPECT_EQ(FSplat->getOperand(1).getReg(), FSplat->getOperand(2).getReg());
68 EXPECT_EQ(FSplat->getOperand(1).getReg(), FSplat->getOperand(2).getReg());
69 EXPECT_EQ(&*MIBFP0, MRI->getVRegDef(FSplat->getOperand(1).getReg()));
unittests/CodeGen/GlobalISel/ConstantFoldingTest.cpp 31 bool match = mi_match(MIBCAdd->getOperand(0).getReg(), *MRI, m_ICst(Cst));
38 match = mi_match(MIBCAdd1->getOperand(0).getReg(), *MRI, m_ICst(Cst));
50 match = mi_match(MIBCSub->getOperand(0).getReg(), *MRI, m_ICst(Cst));
58 match = mi_match(MIBCSext1->getOperand(0).getReg(), *MRI, m_ICst(Cst));
66 match = mi_match(MIBCSext2->getOperand(0).getReg(), *MRI, m_ICst(Cst));
84 ConstantFoldBinOp(TargetOpcode::G_ADD, MIBCst1->getOperand(0).getReg(),
85 MIBCst2->getOperand(0).getReg(), *MRI);
89 ConstantFoldBinOp(TargetOpcode::G_ADD, MIBCst1->getOperand(0).getReg(),
90 MIBFCst2->getOperand(0).getReg(), *MRI);
96 ConstantFoldBinOp(TargetOpcode::G_AND, MIBCst1->getOperand(0).getReg(),
97 MIBCst2->getOperand(0).getReg(), *MRI);
101 ConstantFoldBinOp(TargetOpcode::G_AND, MIBCst2->getOperand(0).getReg(),
102 MIBFCst1->getOperand(0).getReg(), *MRI);
108 ConstantFoldBinOp(TargetOpcode::G_ASHR, MIBCst1->getOperand(0).getReg(),
109 MIBCst2->getOperand(0).getReg(), *MRI);
113 ConstantFoldBinOp(TargetOpcode::G_ASHR, MIBFCst2->getOperand(0).getReg(),
114 MIBCst2->getOperand(0).getReg(), *MRI);
120 ConstantFoldBinOp(TargetOpcode::G_LSHR, MIBCst1->getOperand(0).getReg(),
121 MIBCst2->getOperand(0).getReg(), *MRI);
125 ConstantFoldBinOp(TargetOpcode::G_LSHR, MIBFCst1->getOperand(0).getReg(),
126 MIBCst2->getOperand(0).getReg(), *MRI);
132 ConstantFoldBinOp(TargetOpcode::G_MUL, MIBCst1->getOperand(0).getReg(),
133 MIBCst2->getOperand(0).getReg(), *MRI);
137 ConstantFoldBinOp(TargetOpcode::G_MUL, MIBCst1->getOperand(0).getReg(),
138 MIBFCst2->getOperand(0).getReg(), *MRI);
144 ConstantFoldBinOp(TargetOpcode::G_OR, MIBCst1->getOperand(0).getReg(),
145 MIBCst2->getOperand(0).getReg(), *MRI);
149 ConstantFoldBinOp(TargetOpcode::G_OR, MIBCst1->getOperand(0).getReg(),
150 MIBFCst2->getOperand(0).getReg(), *MRI);
156 ConstantFoldBinOp(TargetOpcode::G_SHL, MIBCst1->getOperand(0).getReg(),
157 MIBCst2->getOperand(0).getReg(), *MRI);
161 ConstantFoldBinOp(TargetOpcode::G_SHL, MIBCst1->getOperand(0).getReg(),
162 MIBFCst2->getOperand(0).getReg(), *MRI);
168 ConstantFoldBinOp(TargetOpcode::G_SUB, MIBCst1->getOperand(0).getReg(),
169 MIBCst2->getOperand(0).getReg(), *MRI);
173 ConstantFoldBinOp(TargetOpcode::G_SUB, MIBCst1->getOperand(0).getReg(),
174 MIBFCst2->getOperand(0).getReg(), *MRI);
180 ConstantFoldBinOp(TargetOpcode::G_XOR, MIBCst1->getOperand(0).getReg(),
181 MIBCst2->getOperand(0).getReg(), *MRI);
185 ConstantFoldBinOp(TargetOpcode::G_XOR, MIBCst1->getOperand(0).getReg(),
186 MIBFCst2->getOperand(0).getReg(), *MRI);
192 ConstantFoldBinOp(TargetOpcode::G_UDIV, MIBCst1->getOperand(0).getReg(),
193 MIBCst2->getOperand(0).getReg(), *MRI);
197 ConstantFoldBinOp(TargetOpcode::G_UDIV, MIBCst1->getOperand(0).getReg(),
198 MIBFCst2->getOperand(0).getReg(), *MRI);
204 ConstantFoldBinOp(TargetOpcode::G_SDIV, MIBCst1->getOperand(0).getReg(),
205 MIBCst2->getOperand(0).getReg(), *MRI);
209 ConstantFoldBinOp(TargetOpcode::G_SDIV, MIBCst1->getOperand(0).getReg(),
210 MIBFCst2->getOperand(0).getReg(), *MRI);
216 ConstantFoldBinOp(TargetOpcode::G_UDIV, MIBCst1->getOperand(0).getReg(),
217 MIBCst2->getOperand(0).getReg(), *MRI);
221 ConstantFoldBinOp(TargetOpcode::G_UDIV, MIBCst1->getOperand(0).getReg(),
222 MIBFCst2->getOperand(0).getReg(), *MRI);
228 ConstantFoldBinOp(TargetOpcode::G_SREM, MIBCst1->getOperand(0).getReg(),
229 MIBCst2->getOperand(0).getReg(), *MRI);
233 ConstantFoldBinOp(TargetOpcode::G_SREM, MIBCst1->getOperand(0).getReg(),
234 MIBFCst2->getOperand(0).getReg(), *MRI);
unittests/CodeGen/GlobalISel/GISelMITest.h 132 Copies.push_back(MI.getOperand(0).getReg());
unittests/CodeGen/GlobalISel/KnownBitsTest.cpp 21 unsigned SrcReg = FinalCopy->getOperand(1).getReg();
22 unsigned DstReg = FinalCopy->getOperand(0).getReg();
41 unsigned SrcReg = FinalCopy->getOperand(1).getReg();
42 unsigned DstReg = FinalCopy->getOperand(0).getReg();
69 unsigned SrcReg = FinalCopy->getOperand(1).getReg();
85 unsigned SrcReg = FinalCopy->getOperand(1).getReg();
112 unsigned SrcReg = FinalCopy->getOperand(1).getReg();
unittests/CodeGen/GlobalISel/MachineIRBuilderTest.cpp 89 B.buildAdd(MIBAdd->getOperand(0), MIBAdd->getOperand(1), MIBAdd->getOperand(2));
89 B.buildAdd(MIBAdd->getOperand(0), MIBAdd->getOperand(1), MIBAdd->getOperand(2));
89 B.buildAdd(MIBAdd->getOperand(0), MIBAdd->getOperand(1), MIBAdd->getOperand(2));
333 Register RegC0 = B.buildConstant(S32, 0)->getOperand(0).getReg();
334 Register RegC1 = B.buildConstant(S32, 1)->getOperand(0).getReg();
335 Register RegC2 = B.buildConstant(S32, 2)->getOperand(0).getReg();
336 Register RegC3 = B.buildConstant(S32, 3)->getOperand(0).getReg();
344 B.buildMerge(V2x32, {RegC0, RegC1})->getOperand(0).getReg();
346 B.buildMerge(V2x32, {RegC2, RegC3})->getOperand(0).getReg();
unittests/CodeGen/GlobalISel/PatternMatchTest.cpp 39 bool match = mi_match(MIBCst->getOperand(0).getReg(), *MRI, m_ICst(Cst));
52 mi_match(MIBAdd->getOperand(0).getReg(), *MRI, m_GAdd(m_Reg(), m_Reg()));
55 match = mi_match(MIBAdd->getOperand(0).getReg(), *MRI,
65 match = mi_match(MIBMul->getOperand(0).getReg(), *MRI,
68 EXPECT_EQ(Src0, MIBAdd->getOperand(0).getReg());
72 match = mi_match(MIBMul->getOperand(0).getReg(), *MRI,
84 match = mi_match(MIBMul2->getOperand(0).getReg(), *MRI,
92 match = mi_match(MIBSub->getOperand(0).getReg(), *MRI,
99 match = mi_match(MIBFMul->getOperand(0).getReg(), *MRI,
108 match = mi_match(MIBFSub->getOperand(0).getReg(), *MRI,
116 match = mi_match(MIBAnd->getOperand(0).getReg(), *MRI,
125 match = mi_match(MIBOr->getOperand(0).getReg(), *MRI,
144 mi_match(MIBFabs->getOperand(0).getReg(), *MRI, m_GFabs(m_Reg()));
149 match = mi_match(MIBFNeg->getOperand(0).getReg(), *MRI, m_GFNeg(m_Reg(Src)));
151 EXPECT_EQ(Src, Copy0s32->getOperand(0).getReg());
153 match = mi_match(MIBFabs->getOperand(0).getReg(), *MRI, m_GFabs(m_Reg(Src)));
155 EXPECT_EQ(Src, Copy0s32->getOperand(0).getReg());
160 match = mi_match(MIBFCst->getOperand(0).getReg(), *MRI, m_GFCst(TmpFP));
171 match = mi_match(MIBFCst64->getOperand(0).getReg(), *MRI, m_GFCst(TmpFP64));
183 match = mi_match(MIBFCst16->getOperand(0).getReg(), *MRI, m_GFCst(TmpFP16));
208 mi_match(MIBTrunc->getOperand(0).getReg(), *MRI, m_GTrunc(m_Reg(Src0)));
212 mi_match(MIBAExt->getOperand(0).getReg(), *MRI, m_GAnyExt(m_Reg(Src0)));
214 EXPECT_EQ(Src0, MIBTrunc->getOperand(0).getReg());
216 match = mi_match(MIBSExt->getOperand(0).getReg(), *MRI, m_GSExt(m_Reg(Src0)));
218 EXPECT_EQ(Src0, MIBTrunc->getOperand(0).getReg());
220 match = mi_match(MIBZExt->getOperand(0).getReg(), *MRI, m_GZExt(m_Reg(Src0)));
222 EXPECT_EQ(Src0, MIBTrunc->getOperand(0).getReg());
225 match = mi_match(MIBAExt->getOperand(0).getReg(), *MRI,
230 match = mi_match(MIBSExt->getOperand(0).getReg(), *MRI,
235 match = mi_match(MIBZExt->getOperand(0).getReg(), *MRI,
250 EXPECT_FALSE(mi_match(MIBAdd->getOperand(0).getReg(), *MRI,
252 EXPECT_TRUE(mi_match(MIBAdd->getOperand(0).getReg(), *MRI,
259 mi_match(MIBCast->getOperand(0).getReg(), *MRI, m_GBitcast(m_Reg())));
261 mi_match(MIBCast->getOperand(0).getReg(), *MRI, m_SpecificType(v2s32)));
263 mi_match(MIBCast->getOperand(1).getReg(), *MRI, m_SpecificType(s64)));
272 bool match = mi_match(MIBPtrToInt->getOperand(0).getReg(), *MRI,
288 mi_match(MIBAdd->getOperand(0).getReg(), *MRI,
295 mi_match(MIBAdd->getOperand(0).getReg(), *MRI,
299 mi_match(MIBAdd->getOperand(0).getReg(), *MRI,
307 MIBAdd->getOperand(0).getReg(), *MRI,
unittests/MI/LiveIntervalTest.cpp 376 MI.getOperand(0).setIsUndef(false);
439 UndefSubregDef.getOperand(0).setIsUndef(false);
460 UndefSubregDef.getOperand(0).setIsUndef(false);