reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

gen/lib/Target/AArch64/AArch64GenGICombiner.inc

  103   MachineRegisterInfo &MRI = MF->getRegInfo();

gen/lib/Target/AArch64/AArch64GenGlobalISel.inc

 1021   MachineRegisterInfo &MRI = MF.getRegInfo();

gen/lib/Target/AMDGPU/AMDGPUGenGlobalISel.inc

  440   MachineRegisterInfo &MRI = MF.getRegInfo();

gen/lib/Target/ARM/ARMGenGlobalISel.inc

  809   MachineRegisterInfo &MRI = MF.getRegInfo();

gen/lib/Target/Mips/MipsGenGlobalISel.inc

  634   MachineRegisterInfo &MRI = MF.getRegInfo();

gen/lib/Target/RISCV/RISCVGenGlobalISel.inc

  280   MachineRegisterInfo &MRI = MF.getRegInfo();

gen/lib/Target/X86/X86GenGlobalISel.inc

  773   MachineRegisterInfo &MRI = MF.getRegInfo();

include/llvm/CodeGen/LiveRangeEdit.h

  142       : Parent(parent), NewRegs(newRegs), MRI(MF.getRegInfo()), LIS(lis),

include/llvm/CodeGen/MachineOutliner.h

  139     assert(MBB->getParent()->getRegInfo().tracksLiveness() &&

include/llvm/CodeGen/MachinePipeliner.h

  509       : ST(mf->getSubtarget()), MRI(mf->getRegInfo()), ProcItinResources(&ST) {}

include/llvm/CodeGen/ModuloSchedule.h

  257       : Schedule(S), MF(MF), ST(MF.getSubtarget()), MRI(MF.getRegInfo()),
  306       : Schedule(S), MF(MF), ST(MF.getSubtarget()), MRI(MF.getRegInfo()),

lib/CodeGen/AggressiveAntiDepBreaker.cpp

  128     : AntiDepBreaker(), MF(MFi), MRI(MF.getRegInfo()),
  177   for (const MCPhysReg *I = MF.getRegInfo().getCalleeSavedRegs(); *I;

lib/CodeGen/BranchFolding.cpp

  186   MachineRegisterInfo &MRI = MF.getRegInfo();

lib/CodeGen/CalcSpillWeights.cpp

   40   MachineRegisterInfo &MRI = MF.getRegInfo();
  153   MachineRegisterInfo &mri = MF.getRegInfo();

lib/CodeGen/CriticalAntiDepBreaker.cpp

   46     : AntiDepBreaker(), MF(MFi), MRI(MF.getRegInfo()),
   87   for (const MCPhysReg *I = MF.getRegInfo().getCalleeSavedRegs(); *I;

lib/CodeGen/DeadMachineInstructionElim.cpp

  102   MRI = &MF.getRegInfo();

lib/CodeGen/DetectDeadLanes.cpp

  576   MRI = &MF.getRegInfo();

lib/CodeGen/EarlyIfConversion.cpp

  170     MRI = &MF.getRegInfo();
  912   MRI = &MF.getRegInfo();
 1042   MRI = &MF.getRegInfo();

lib/CodeGen/ExecutionDomainFix.cpp

  428   const MachineRegisterInfo &MRI = mf.getRegInfo();

lib/CodeGen/GlobalISel/CSEInfo.cpp

   80   this->MRI = &MF.getRegInfo();

lib/CodeGen/GlobalISel/Combiner.cpp

  108   MRI = &MF.getRegInfo();

lib/CodeGen/GlobalISel/CombinerHelper.cpp

   37     : Builder(B), MRI(Builder.getMF().getRegInfo()), Observer(Observer),

lib/CodeGen/GlobalISel/GISelKnownBits.cpp

   33     : MF(MF), MRI(MF.getRegInfo()), TL(*MF.getSubtarget().getTargetLowering()),

lib/CodeGen/GlobalISel/IRTranslator.cpp

 2240   MRI = &MF->getRegInfo();

lib/CodeGen/GlobalISel/InstructionSelect.cpp

   86   MachineRegisterInfo &MRI = MF.getRegInfo();

lib/CodeGen/GlobalISel/InstructionSelector.cpp

   42   MachineRegisterInfo &MRI = MF.getRegInfo();

lib/CodeGen/GlobalISel/Legalizer.cpp

  155   MachineRegisterInfo &MRI = MF.getRegInfo();
  204   LegalizationArtifactCombiner ArtCombiner(*MIRBuilder.get(), MF.getRegInfo(),

lib/CodeGen/GlobalISel/LegalizerHelper.cpp

   69     : MIRBuilder(Builder), MRI(MF.getRegInfo()),
   78     : MIRBuilder(B), MRI(MF.getRegInfo()), LI(LI), Observer(Observer) {

lib/CodeGen/GlobalISel/Localizer.cpp

   34   MRI = &MF.getRegInfo();

lib/CodeGen/GlobalISel/MachineIRBuilder.cpp

   29   State.MRI = &MF.getRegInfo();

lib/CodeGen/GlobalISel/RegBankSelect.cpp

   84   MRI = &MF.getRegInfo();

lib/CodeGen/GlobalISel/Utils.cpp

  119   MachineRegisterInfo &MRI = MF.getRegInfo();

lib/CodeGen/IfConversion.cpp

  447   MRI = &MF.getRegInfo();

lib/CodeGen/ImplicitNullChecks.cpp

  298   TRI = MF.getRegInfo().getTargetRegisterInfo();

lib/CodeGen/InlineSpiller.cpp

  146         MRI(mf.getRegInfo()), TII(*mf.getSubtarget().getInstrInfo()),
  202         MRI(mf.getRegInfo()), TII(*mf.getSubtarget().getInstrInfo()),

lib/CodeGen/LiveDebugVariables.cpp

  951     userValues[i]->computeIntervals(MF->getRegInfo(), *TRI, *LIS, LS);

lib/CodeGen/LiveIntervals.cpp

  127   MRI = &MF->getRegInfo();

lib/CodeGen/LiveRangeShrink.cpp

  111   MachineRegisterInfo &MRI = MF.getRegInfo();

lib/CodeGen/LiveVariables.cpp

  622   MRI = &mf.getRegInfo();

lib/CodeGen/LocalStackSlotAllocation.cpp

  414       BaseReg = Fn.getRegInfo().createVirtualRegister(RC);

lib/CodeGen/MIRCanonicalizerPass.cpp

  224     MachineRegisterInfo *MRI = &MBB->getParent()->getRegInfo();
  308   MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
  401   MachineRegisterInfo &MRI = MF.getRegInfo();
  479   MachineRegisterInfo &MRI = MF.getRegInfo();

lib/CodeGen/MIRNamerPass.cpp

   57     NamedVRegCursor NVC(MF.getRegInfo());

lib/CodeGen/MIRParser/MIParser.cpp

  326     MachineRegisterInfo &MRI = MF.getRegInfo();
  340     Info->VReg = MF.getRegInfo().createIncompleteVirtualRegister(RegName);
 1422   MachineRegisterInfo &MRI = MF.getRegInfo();

lib/CodeGen/MIRParser/MIRParser.cpp

  338   const MachineRegisterInfo &MRI = MF.getRegInfo();
  479   MachineRegisterInfo &MRI = MF.getRegInfo();
  496   MachineRegisterInfo &RegInfo = MF.getRegInfo();
  577   MachineRegisterInfo &MRI = MF.getRegInfo();

lib/CodeGen/MIRVRegNamerUtils.cpp

   53   MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
  258   MachineRegisterInfo &MRI = MF.getRegInfo();

lib/CodeGen/MachineBasicBlock.cpp

   96   MachineRegisterInfo &RegInfo = MF.getRegInfo();
  117   N->AddRegOperandsToUseLists(MF->getRegInfo());
  129     N->RemoveRegOperandsFromUseLists(MF->getRegInfo());
  502   MachineRegisterInfo &MRI = getParent()->getRegInfo();
 1046     MachineRegisterInfo *MRI = &getParent()->getRegInfo();

lib/CodeGen/MachineCSE.cpp

  887   MRI = &MF.getRegInfo();

lib/CodeGen/MachineCombiner.cpp

  638   MRI = &MF.getRegInfo();

lib/CodeGen/MachineCopyPropagation.cpp

  648   MRI = &MF.getRegInfo();

lib/CodeGen/MachineFunction.cpp

  585   MachineRegisterInfo &MRI = getRegInfo();

lib/CodeGen/MachineInstr.cpp

  154     return &MBB->getParent()->getRegInfo();
  681   MachineRegisterInfo &MRI = MF->getRegInfo();

lib/CodeGen/MachineLICM.cpp

  314   MRI = &MF.getRegInfo();

lib/CodeGen/MachineOperand.cpp

   63     MachineRegisterInfo &MRI = MF->getRegInfo();
  106     MachineRegisterInfo &MRI = MF->getRegInfo();
  147     MF->getRegInfo().removeRegOperandFromUseList(this);
  238     RegInfo = &MF->getRegInfo();

lib/CodeGen/MachineOutliner.cpp

 1152   MF.getRegInfo().freezeReservedRegs(MF);

lib/CodeGen/MachinePipeliner.cpp

  349   MachineRegisterInfo &MRI = MF->getRegInfo();
 1547   MachineRegisterInfo &MRI = MF.getRegInfo();
 2068   MachineRegisterInfo &MRI = MF.getRegInfo();
 2107   MachineRegisterInfo &MRI = MI->getMF()->getRegInfo();

lib/CodeGen/MachineSSAUpdater.cpp

   46     MRI(&MF.getRegInfo()) {}

lib/CodeGen/MachineSink.cpp

  308   MRI = &MF.getRegInfo();
  765   const MachineRegisterInfo &MRI = MI.getMF()->getRegInfo();
  992   const MachineRegisterInfo &MRI = MI.getMF()->getRegInfo();

lib/CodeGen/MachineVerifier.cpp

  367   MRI = &MF.getRegInfo();

lib/CodeGen/ModuloSchedule.cpp

  923   MachineRegisterInfo &MRI = MF.getRegInfo();
 1282       ExitBB(L.getExitBlock()), MRI(BB->getParent()->getRegInfo()),

lib/CodeGen/OptimizePHIs.cpp

   77   MRI = &Fn.getRegInfo();

lib/CodeGen/PHIElimination.cpp

  148   MRI = &MF.getRegInfo();
  281       const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(DestReg);
  282       entry = IncomingReg = MF.getRegInfo().createVirtualRegister(RC);

lib/CodeGen/PHIEliminationUtils.cpp

   35   MachineRegisterInfo& MRI = MBB->getParent()->getRegInfo();

lib/CodeGen/PeepholeOptimizer.cpp

 1605   MRI = &MF.getRegInfo();

lib/CodeGen/ProcessImplicitDefs.cpp

  141   MRI = &MF.getRegInfo();

lib/CodeGen/PrologEpilogInserter.cpp

  388   const MCPhysReg *CSRegs = F.getRegInfo().getCalleeSavedRegs();
  505   MachineRegisterInfo &MRI = MF.getRegInfo();

lib/CodeGen/RegAllocFast.cpp

 1295   MRI = &MF.getRegInfo();

lib/CodeGen/RegAllocPBQP.cpp

  458           if (!MF.getRegInfo().isAllocatable(DstReg))
  582   const MachineRegisterInfo &MRI = G.getMetadata().MF.getRegInfo();
  745   MachineRegisterInfo &MRI = MF.getRegInfo();
  801   MF.getRegInfo().freezeReservedRegs(MF);
  879     const MachineRegisterInfo &MRI = G.getMetadata().MF.getRegInfo();

lib/CodeGen/RegUsageInfoCollector.cpp

  102   MachineRegisterInfo *MRI = &MF.getRegInfo();

lib/CodeGen/RegUsageInfoPropagate.cpp

   67                                           ->getRegInfo().getTargetRegisterInfo()

lib/CodeGen/RegisterCoalescer.cpp

 3678   MRI = &fn.getRegInfo();

lib/CodeGen/RegisterScavenging.cpp

   60   MRI = &MF.getRegInfo();
  755   MachineRegisterInfo &MRI = MF.getRegInfo();

lib/CodeGen/RenameIndependentSubregs.cpp

  378   MRI = &MF.getRegInfo();

lib/CodeGen/ResetMachineFunctionPass.cpp

   59           make_scope_exit([&MF]() { MF.getRegInfo().clearVirtRegTypes(); });

lib/CodeGen/ScheduleDAG.cpp

   56       MRI(mf.getRegInfo()) {

lib/CodeGen/SelectionDAG/FastISel.cpp

 1924     : FuncInfo(FuncInfo), MF(FuncInfo.MF), MRI(FuncInfo.MF->getRegInfo()),

lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp

   86   RegInfo = &MF->getRegInfo();
  520   MachineRegisterInfo &MRI = MF->getRegInfo();

lib/CodeGen/SelectionDAG/InstrEmitter.cpp

 1161     : MF(mbb->getParent()), MRI(&MF->getRegInfo()),

lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

  957     const MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
 5511       MachineRegisterInfo &RegInfo = MF.getRegInfo();
 7967   MachineRegisterInfo &RegInfo = MF.getRegInfo();
 8270                 DAG.getMachineFunction().getRegInfo();
 9766     MachineRegisterInfo& RegInfo = MF.getRegInfo();

lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp

  437   RegInfo = &MF->getRegInfo();
  513   MachineRegisterInfo &MRI = MF->getRegInfo();

lib/CodeGen/SplitKit.cpp

  370       MRI(vrm.getMachineFunction().getRegInfo()), MDT(mdt),

lib/CodeGen/SwiftErrorValueTracking.cpp

   37     auto VReg = MF->getRegInfo().createVirtualRegister(RC);
   59   Register VReg = MF->getRegInfo().createVirtualRegister(RC);
  133     Register VReg = MF->getRegInfo().createVirtualRegister(RC);
  243           UpwardsUse ? UUseVReg : MF->getRegInfo().createVirtualRegister(RC);

lib/CodeGen/TailDuplicator.cpp

   84   MRI = &MF->getRegInfo();

lib/CodeGen/TargetFrameLoweringImpl.cpp

   94   const MCPhysReg *CSRegs = MF.getRegInfo().getCalleeSavedRegs();
  119   const MachineRegisterInfo &MRI = MF.getRegInfo();

lib/CodeGen/TargetInstrInfo.cpp

  515         MF.getRegInfo().getRegClass(MO.getReg());
  778   MachineRegisterInfo &MRI = MF->getRegInfo();
  860   MachineRegisterInfo &MRI = Root.getMF()->getRegInfo();

lib/CodeGen/TargetLoweringBase.cpp

 2002   MF.getRegInfo().freezeReservedRegs(MF);

lib/CodeGen/TwoAddressInstructionPass.cpp

 1669   MRI = &MF->getRegInfo();

lib/CodeGen/UnreachableBlockElim.cpp

  183           MachineRegisterInfo &MRI = F.getRegInfo();

lib/CodeGen/VirtRegMap.cpp

   63   MRI = &mf.getRegInfo();
   77   unsigned NumRegs = MF->getRegInfo().getNumVirtRegs();
  123   const TargetRegisterClass* RC = MF->getRegInfo().getRegClass(virtReg);
  239   MRI = &MF->getRegInfo();

lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp

  319   MRI = &F.getRegInfo();
  320   TRI = F.getRegInfo().getTargetRegisterInfo();

lib/Target/AArch64/AArch64AdvSIMDScalarPass.cpp

  398   MRI = &mf.getRegInfo();

lib/Target/AArch64/AArch64CallLowering.cpp

  269     MachineRegisterInfo &MRI = MF.getRegInfo();
  421   MachineRegisterInfo &MRI = MF.getRegInfo();
  598   MachineRegisterInfo &MRI = MF.getRegInfo();
  783   MachineRegisterInfo &MRI = MF.getRegInfo();
  925   MachineRegisterInfo &MRI = MF.getRegInfo();

lib/Target/AArch64/AArch64CleanupLocalDynamicTLSPass.cpp

  121     MachineRegisterInfo &RegInfo = MF->getRegInfo();

lib/Target/AArch64/AArch64CondBrTuning.cpp

  301   MRI = &MF.getRegInfo();

lib/Target/AArch64/AArch64ConditionOptimizer.cpp

  336   MRI = &MF.getRegInfo();

lib/Target/AArch64/AArch64ConditionalCompares.cpp

  196     MRI = &MF.getRegInfo();
  937   MRI = &MF.getRegInfo();

lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp

  193   MRI = &MF.getRegInfo();

lib/Target/AArch64/AArch64FalkorHWPFFix.cpp

  708   MachineRegisterInfo &MRI = Fn.getRegInfo();

lib/Target/AArch64/AArch64FrameLowering.cpp

  395   const MCPhysReg *CSRegs = MF->getRegInfo().getCalleeSavedRegs();
  400   const MachineRegisterInfo &MRI = MF->getRegInfo();
 1763   bool IsLiveIn = MF.getRegInfo().isLiveIn(Reg);
 1958   const MachineRegisterInfo &MRI = MF.getRegInfo();
 2189   const MCPhysReg *CSRegs = MF.getRegInfo().getCalleeSavedRegs();
 2230   const MachineRegisterInfo &MRI = MF.getRegInfo();
 2289     if (!ExtraCSSpill || MF.getRegInfo().isPhysRegUsed(ExtraCSSpill)) {

lib/Target/AArch64/AArch64ISelLowering.cpp

 3355             MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
 3668   const MachineRegisterInfo &MRI = MF.getRegInfo();
12383   MachineRegisterInfo *MRI = &Entry->getParent()->getRegInfo();

lib/Target/AArch64/AArch64InstrInfo.cpp

  543   MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
 1054   MachineRegisterInfo *MRI = &MF->getRegInfo();
 2831         MF.getRegInfo().constrainRegClass(SrcReg, &AArch64::GPR32RegClass);
 2841         MF.getRegInfo().constrainRegClass(SrcReg, &AArch64::GPR64RegClass);
 2962         MF.getRegInfo().constrainRegClass(DestReg, &AArch64::GPR32RegClass);
 2972         MF.getRegInfo().constrainRegClass(DestReg, &AArch64::GPR64RegClass);
 3198       MF.getRegInfo().constrainRegClass(DstReg, &AArch64::GPR64RegClass);
 3202       MF.getRegInfo().constrainRegClass(SrcReg, &AArch64::GPR64RegClass);
 3237     const MachineRegisterInfo &MRI = MF.getRegInfo();
 3597   MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
 4104   MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
 4785   MachineRegisterInfo *MRI = &MF->getRegInfo();
 5309   assert(MBB.getParent()->getRegInfo().tracksLiveness() &&

lib/Target/AArch64/AArch64InstructionSelector.cpp

 1119   MachineRegisterInfo &MRI = MF.getRegInfo();
 1157   MachineRegisterInfo &MRI = MF.getRegInfo();
 1281   MachineRegisterInfo &MRI = MF.getRegInfo();
 1322   MachineRegisterInfo &MRI = MF.getRegInfo();
 3149   MachineRegisterInfo &MRI = MIRBuilder.getMF().getRegInfo();
 3173   MachineRegisterInfo &MRI = MIRBuilder.getMF().getRegInfo();
 3198   MachineRegisterInfo &MRI = MIRBuilder.getMF().getRegInfo();
 3227   MachineRegisterInfo &MRI = MIRBuilder.getMF().getRegInfo();
 3278   MachineRegisterInfo &MRI = MIRBuilder.getMF().getRegInfo();
 4132   MachineRegisterInfo &MRI = Root.getParent()->getMF()->getRegInfo();
 4181   MachineRegisterInfo &MRI = Root.getParent()->getMF()->getRegInfo();
 4283   MachineRegisterInfo &MRI = Root.getParent()->getMF()->getRegInfo();
 4316   MachineRegisterInfo &MRI = Root.getParent()->getMF()->getRegInfo();
 4342       Root.getParent()->getParent()->getParent()->getRegInfo();
 4386       Root.getParent()->getParent()->getParent()->getRegInfo();
 4461       Root.getParent()->getParent()->getParent()->getRegInfo();
 4575       Root.getParent()->getParent()->getParent()->getRegInfo();

lib/Target/AArch64/AArch64RedundantCopyElimination.cpp

  475   MRI = &MF.getRegInfo();

lib/Target/AArch64/AArch64RegisterInfo.cpp

   97   MF.getRegInfo().setCalleeSavedRegs(UpdatedCSRs);
  417   MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
  503           MF.getRegInfo().createVirtualRegister(&AArch64::GPR64RegClass);
  533       MF.getRegInfo().createVirtualRegister(&AArch64::GPR64RegClass);

lib/Target/AArch64/AArch64SIMDInstrOpt.cpp

  426   MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
  696   MRI = &MF.getRegInfo();

lib/Target/AArch64/AArch64StackTaggingPreRA.cpp

  176   MRI = &MF->getRegInfo();

lib/Target/AArch64/AArch64StorePairSuppress.cpp

  128   MRI = &MF.getRegInfo();

lib/Target/AMDGPU/AMDGPUCallLowering.cpp

  226   MachineRegisterInfo &MRI = MF.getRegInfo();
  273   MachineRegisterInfo &MRI = MF.getRegInfo();
  287   OutgoingValueHandler RetHandler(B, MF.getRegInfo(), Ret, AssignFn);
  296   MachineRegisterInfo &MRI = MF.getRegInfo();
  346   MachineRegisterInfo &MRI = MF.getRegInfo();
  411     MachineRegisterInfo &MRI = MF.getRegInfo();
  442   MachineRegisterInfo &MRI = MF.getRegInfo();
  566   MachineRegisterInfo &MRI = MF.getRegInfo();

lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp

  551         MachineRegisterInfo &MRI = CurDAG->getMachineFunction().getRegInfo();

lib/Target/AMDGPU/AMDGPUISelLowering.cpp

 4092   MachineRegisterInfo &MRI = MF.getRegInfo();

lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp

   68   MRI = &MF.getRegInfo();
  399   MachineRegisterInfo &MRI = MF->getRegInfo();
 1371   MachineRegisterInfo &MRI = MF->getRegInfo();

lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp

 2878   MRI = &(MF.getRegInfo());

lib/Target/AMDGPU/AMDILCFGStructurizer.cpp

 1311         HeadMBB->getParent()->getRegInfo().createVirtualRegister(I32RC);
 1320       HeadMBB->getParent()->getRegInfo().createVirtualRegister(I32RC);

lib/Target/AMDGPU/GCNDPPCombine.cpp

  559   MRI = &MF.getRegInfo();

lib/Target/AMDGPU/GCNIterativeScheduler.cpp

   96   const auto &MRI = BB->getParent()->getRegInfo();

lib/Target/AMDGPU/GCNNSAReassign.cpp

  228   MRI = &MF.getRegInfo();

lib/Target/AMDGPU/GCNRegBankReassign.cpp

  732   MRI = &MF.getRegInfo();

lib/Target/AMDGPU/GCNRegPressure.h

  213   auto &MRI = (*R.begin())->getParent()->getParent()->getRegInfo();

lib/Target/AMDGPU/R600ISelLowering.cpp

  293   MachineRegisterInfo &MRI = MF->getRegInfo();

lib/Target/AMDGPU/R600OptimizeVectorRegisters.cpp

  339   MRI = &Fn.getRegInfo();

lib/Target/AMDGPU/SIAddIMGInit.cpp

   63   MachineRegisterInfo &MRI = MF.getRegInfo();

lib/Target/AMDGPU/SIFixSGPRCopies.cpp

  204   MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
  590   MRI = &MF.getRegInfo();

lib/Target/AMDGPU/SIFixupVectorISel.cpp

  223   MachineRegisterInfo &MRI = MF.getRegInfo();

lib/Target/AMDGPU/SIFoldOperands.cpp

  249     MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
  404         MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
  513   MachineRegisterInfo &MRI = UseMI->getParent()->getParent()->getRegInfo();
 1446   MRI = &MF.getRegInfo();

lib/Target/AMDGPU/SIFormMemoryClauses.cpp

  314   MRI = &MF.getRegInfo();

lib/Target/AMDGPU/SIFrameLowering.cpp

  121     MF->getRegInfo(), LiveRegs, AMDGPU::VGPR_32RegClass);
  168     MF->getRegInfo(), LiveRegs, AMDGPU::VGPR_32RegClass);
  212   MachineRegisterInfo &MRI = MF.getRegInfo();
  275   MachineRegisterInfo &MRI = MF.getRegInfo();
  322   MachineRegisterInfo &MRI = MF.getRegInfo();
  407   MachineRegisterInfo &MRI = MF.getRegInfo();
  573     MF.getRegInfo().addLiveIn(GitPtrLo);
  643         MF.getRegInfo().addLiveIn(MFI->getImplicitBufferPtrUserSGPR());
  691   MachineRegisterInfo &MRI = MF.getRegInfo();
  836   MachineRegisterInfo &MRI = MF.getRegInfo();
 1039   MFI->SGPRForFPSaveRestoreCopy = findUnusedSGPRNonCalleeSaved(MF.getRegInfo());

lib/Target/AMDGPU/SIISelLowering.cpp

 1411   MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
 1618   MachineRegisterInfo &MRI = MF.getRegInfo();
 1670   MF.getRegInfo().setType(LiveInVReg, LLT::scalar(32));
 1787     MachineRegisterInfo &MRI = MF.getRegInfo();
 1911     MachineRegisterInfo &MRI = MF.getRegInfo();
 1992   MachineRegisterInfo *MRI = &Entry->getParent()->getRegInfo();
 2299         MF.getRegInfo().createVirtualRegister(&AMDGPU::CCR_SGPR_64RegClass),
 2651   const MachineRegisterInfo &MRI = MF.getRegInfo();
 3119   MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
 3281   MachineRegisterInfo &MRI = MF->getRegInfo();
 3395   MachineRegisterInfo &MRI = MF->getRegInfo();
 3486   MachineRegisterInfo &MRI = MF->getRegInfo();
 3600     MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
 3677     MachineRegisterInfo &MRI = MF->getRegInfo();
 3749     MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
10258       MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
10328     MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
10390   MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
10675   MachineRegisterInfo &MRI = MF.getRegInfo();
11029             MachineRegisterInfo &MRI = MF.getRegInfo();

lib/Target/AMDGPU/SIInsertSkips.cpp

  253     if (TRI->isVGPR(MBB.getParent()->getRegInfo(),

lib/Target/AMDGPU/SIInsertWaitcnts.cpp

 1448   MRI = &MF.getRegInfo();

lib/Target/AMDGPU/SIInstrInfo.cpp

  755   MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
  818   MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
  944   MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
  957   MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
 1073       MachineRegisterInfo &MRI = MF->getRegInfo();
 1097     MachineRegisterInfo &MRI = MF->getRegInfo();
 1198       MachineRegisterInfo &MRI = MF->getRegInfo();
 1216     MachineRegisterInfo &MRI = MF->getRegInfo();
 1244     TIDReg = RI.findUnusedRegister(MF->getRegInfo(), &AMDGPU::VGPR_32RegClass,
 1570   MachineRegisterInfo &MRI = MF->getRegInfo();
 1778   MachineRegisterInfo &MRI = MF->getRegInfo();
 2167   MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
 2657        !RI.isSGPRReg(MBB->getParent()->getRegInfo(), Src0->getReg()))) {
 3828   MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
 4408   MachineRegisterInfo &MRI = MF.getRegInfo();
 4475   MachineRegisterInfo &MRI = MF.getRegInfo();
 4516   MachineRegisterInfo &MRI = MF.getRegInfo();
 4824     MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
 5109     MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
 5139   MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
 5166   MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
 5232   MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
 5261   MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
 5290   MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
 5346   MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
 5416   MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
 5480   MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
 5521   MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
 5558   MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
 6072   MachineRegisterInfo &MRI = IfEntry->getParent()->getRegInfo();
 6098   MachineRegisterInfo &MRI = LoopEnd->getParent()->getRegInfo();
 6196   MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();

lib/Target/AMDGPU/SILoadStoreOptimizer.cpp

 1840   MRI = &MF.getRegInfo();

lib/Target/AMDGPU/SILowerControlFlow.cpp

  418   MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
  501   MRI = &MF.getRegInfo();

lib/Target/AMDGPU/SILowerI1Copies.cpp

  429   MachineRegisterInfo &MRI = MF.getRegInfo();
  455   MRI = &MF->getRegInfo();

lib/Target/AMDGPU/SILowerSGPRSpills.cpp

  185   MachineRegisterInfo &MRI = MF.getRegInfo();
  251   MachineRegisterInfo &MRI = MF.getRegInfo();

lib/Target/AMDGPU/SIMachineFunctionInfo.cpp

  272   MachineRegisterInfo &MRI = MF.getRegInfo();
  327   MachineRegisterInfo &MRI = MF.getRegInfo();

lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp

  300   MRI = &MF.getRegInfo();
  302   MachineRegisterInfo &MRI = MF.getRegInfo();

lib/Target/AMDGPU/SIPeepholeSDWA.cpp

  128     return &getParentInst()->getParent()->getParent()->getRegInfo();
 1210   MRI = &MF.getRegInfo();

lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp

  170   MRI = &MF.getRegInfo();

lib/Target/AMDGPU/SIRegisterInfo.cpp

  361   MachineRegisterInfo &MRI = MF->getRegInfo();
  560   MachineRegisterInfo &MRI = MF->getRegInfo();
  637   const TargetRegisterClass *RC = getRegClassForReg(MF->getRegInfo(), ValueReg);

lib/Target/AMDGPU/SIShrinkInstructions.cpp

  553   MachineRegisterInfo &MRI = MF.getRegInfo();

lib/Target/AMDGPU/SIWholeQuadMode.cpp

  887   MRI = &MF.getRegInfo();

lib/Target/ARC/ARCExpandPseudos.cpp

   62   unsigned AddrReg = MF.getRegInfo().createVirtualRegister(&ARC::GPR32RegClass);

lib/Target/ARC/ARCISelLowering.cpp

  452   MachineRegisterInfo &RegInfo = MF.getRegInfo();

lib/Target/ARC/ARCOptAddrMode.cpp

  492   MRI = &MF.getRegInfo();

lib/Target/ARM/A15SDOptimizer.cpp

  667   MRI = &Fn.getRegInfo();

lib/Target/ARM/ARMBaseInstrInfo.cpp

 2239   MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
 2454   const TargetRegisterInfo *TRI = MF.getRegInfo().getTargetRegisterInfo();

lib/Target/ARM/ARMBaseRegisterInfo.cpp

  357   MachineRegisterInfo *MRI = &MF.getRegInfo();
  643   MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
  822     ScratchReg = MF.getRegInfo().createVirtualRegister(RegClass);
  845   const MachineRegisterInfo &MRI = MF->getRegInfo();

lib/Target/ARM/ARMCallLowering.cpp

  261   OutgoingValueHandler RetHandler(MIRBuilder, MF.getRegInfo(), Ret, AssignFn);
  446   FormalArgHandler ArgHandler(MIRBuilder, MIRBuilder.getMF().getRegInfo(),
  509   MachineRegisterInfo &MRI = MF.getRegInfo();

lib/Target/ARM/ARMConstantIslandPass.cpp

  925   MachineRegisterInfo &MRI = MF->getRegInfo();

lib/Target/ARM/ARMFastISel.cpp

 2967   Register TempReg = MF->getRegInfo().createVirtualRegister(&ARM::rGPRRegClass);

lib/Target/ARM/ARMFrameLowering.cpp

  998       const MachineRegisterInfo &MRI = MF.getRegInfo();
 1654   MachineRegisterInfo &MRI = MF.getRegInfo();
 1925         if (!MF.getRegInfo().isLiveIn(Reg)) {
 1988           !(MF.getRegInfo().isLiveIn(ARM::LR) &&

lib/Target/ARM/ARMISelDAGToDAG.cpp

 4712     MachineRegisterInfo &MRI = MF->getRegInfo();

lib/Target/ARM/ARMISelLowering.cpp

 2634       const MachineRegisterInfo *MRI = &MF.getRegInfo();
 2668     const MachineRegisterInfo &MRI = MF.getRegInfo();
 9345   MachineRegisterInfo *MRI = &MF->getRegInfo();
 9469   MachineRegisterInfo *MRI = &MF->getRegInfo();
10024   MachineRegisterInfo &MRI = MF->getRegInfo();
10300     MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
10626     MachineRegisterInfo &MRI = Fn->getRegInfo();
10696   MachineRegisterInfo &MRI = MF->getRegInfo();
17104   MachineRegisterInfo *MRI = &Entry->getParent()->getRegInfo();

lib/Target/ARM/ARMInstructionSelector.cpp

  842   auto &MRI = MF.getRegInfo();

lib/Target/ARM/ARMLoadStoreOptimizer.cpp

 2091   MRI = &Fn.getRegInfo();

lib/Target/ARM/ARMLowOverheadLoops.cpp

   99   MRI = &MF->getRegInfo();

lib/Target/ARM/MLxExpansionPass.cpp

  376   MRI = &Fn.getRegInfo();

lib/Target/ARM/Thumb1FrameLowering.cpp

  838         !MF.getRegInfo().isLiveIn(Reg) &&
  845     if (!MF.getRegInfo().isLiveIn(ArgReg))
  849   const MachineRegisterInfo &MRI = MF.getRegInfo();

lib/Target/ARM/Thumb2InstrInfo.cpp

  163       MachineRegisterInfo *MRI = &MF.getRegInfo();
  204       MachineRegisterInfo *MRI = &MF.getRegInfo();
  656         MachineRegisterInfo *MRI = &MF.getRegInfo();

lib/Target/ARM/ThumbRegisterInfo.cpp

  146     LdReg = MF.getRegInfo().createVirtualRegister(&ARM::tGPRRegClass);
  536       VReg = MF.getRegInfo().createVirtualRegister(&ARM::tGPRRegClass);

lib/Target/AVR/AVRExpandPseudoInsts.cpp

   71   MachineRegisterInfo &getRegInfo(Block &MBB) { return MBB.getParent()->getRegInfo(); }

lib/Target/AVR/AVRFrameLowering.cpp

  514         MF.getRegInfo().createVirtualRegister(&AVR::DREGSRegClass);

lib/Target/AVR/AVRISelDAGToDAG.cpp

  209   MachineRegisterInfo &RI = MF->getRegInfo();

lib/Target/AVR/AVRISelLowering.cpp

 1442   MachineRegisterInfo &RI = F->getRegInfo();

lib/Target/BPF/BPFISelLowering.cpp

  219   MachineRegisterInfo &RegInfo = MF.getRegInfo();
  572   MachineRegisterInfo &RegInfo = F->getRegInfo();
  590   MachineRegisterInfo &MRI = MF->getRegInfo();

lib/Target/BPF/BPFMIPeephole.cpp

   73   MRI = &MF->getRegInfo();
  342   MRI = &MF->getRegInfo();

lib/Target/BPF/BPFMISimplifyPatchable.cpp

   76   MachineRegisterInfo *MRI = &MF->getRegInfo();

lib/Target/Hexagon/BitTracker.cpp

  188     : ME(E), MF(F), MRI(F.getRegInfo()), Map(*new CellMapType), Trace(false) {

lib/Target/Hexagon/HexagonBitSimplify.cpp

  954         MDT(mdt), MRI(mf.getRegInfo()) {}
 2767   MachineRegisterInfo &MRI = MF.getRegInfo();
 3316   MRI = &MF.getRegInfo();

lib/Target/Hexagon/HexagonBlockRanges.cpp

  295   MachineRegisterInfo &MRI = B.getParent()->getRegInfo();
  473   auto &MRI = MF.getRegInfo();

lib/Target/Hexagon/HexagonConstExtenders.cpp

 1957   MRI = &MF.getRegInfo();

lib/Target/Hexagon/HexagonConstPropagation.cpp

 1050   MRI = &MF.getRegInfo();
 1913   MRI = &Fn.getRegInfo();

lib/Target/Hexagon/HexagonEarlyIfConv.cpp

 1055   MRI = &MF.getRegInfo();

lib/Target/Hexagon/HexagonExpandCondsets.cpp

 1258   MRI = &MF.getRegInfo();

lib/Target/Hexagon/HexagonFrameLowering.cpp

 1397   MachineRegisterInfo &MRI = MF.getRegInfo();
 1885   MachineRegisterInfo &MRI = MF.getRegInfo();
 1952     MachineRegisterInfo &MRI = MF.getRegInfo();
 1982   auto &MRI = MF.getRegInfo();
 2013   auto &MRI = MF.getRegInfo();

lib/Target/Hexagon/HexagonGenInsert.cpp

 1517   MRI = &MF.getRegInfo();

lib/Target/Hexagon/HexagonGenPredicate.cpp

  501   MRI = &MF.getRegInfo();

lib/Target/Hexagon/HexagonHardwareLoops.cpp

  385   MRI = &MF.getRegInfo();

lib/Target/Hexagon/HexagonISelLowering.cpp

  285       auto &MRI = DAG.getMachineFunction().getRegInfo();
  697   MachineRegisterInfo &MRI = MF.getRegInfo();

lib/Target/Hexagon/HexagonInstrInfo.cpp

 1024   MachineRegisterInfo &MRI = MF.getRegInfo();
 1606   MachineRegisterInfo &MRI = B.getParent()->getRegInfo();
 1984   MachineRegisterInfo &MRI = MF->getRegInfo();

lib/Target/Hexagon/HexagonNewValueJump.cpp

  292     MachineRegisterInfo &MRI = MF.getRegInfo();

lib/Target/Hexagon/HexagonOptAddrMode.cpp

  783   MRI = &MF.getRegInfo();

lib/Target/Hexagon/HexagonPeephole.cpp

  115   MRI = &MF.getRegInfo();

lib/Target/Hexagon/HexagonRDFOpt.cpp

  295   MRI = &MF.getRegInfo();

lib/Target/Hexagon/HexagonRegisterInfo.cpp

  219     auto &MRI = MF.getRegInfo();

lib/Target/Hexagon/HexagonSplitDouble.cpp

 1198   MRI = &MF.getRegInfo();

lib/Target/Hexagon/HexagonStoreWidening.cpp

  444     Register VReg = MF->getRegInfo().createVirtualRegister(RC);
  594   MRI = &MFn.getRegInfo();

lib/Target/Hexagon/HexagonVExtract.cpp

  104   MachineRegisterInfo &MRI = MF.getRegInfo();

lib/Target/Hexagon/RDFCopy.h

   29         L(dfg.getMF().getRegInfo(), dfg) {}

lib/Target/Hexagon/RDFGraph.cpp

  894   MachineRegisterInfo &MRI = MF.getRegInfo();

lib/Target/Lanai/LanaiISelLowering.cpp

  443   MachineRegisterInfo &RegInfo = MF.getRegInfo();
  516       Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i32));

lib/Target/Lanai/LanaiInstrInfo.cpp

  497   MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();

lib/Target/Lanai/LanaiMachineFunctionInfo.cpp

   21              MF.getRegInfo().createVirtualRegister(&Lanai::GPRRegClass);

lib/Target/MSP430/MSP430ISelLowering.cpp

  608   MachineRegisterInfo &RegInfo = MF.getRegInfo();
  695         Reg = MF.getRegInfo().createVirtualRegister(
 1413   MachineRegisterInfo &RI = F->getRegInfo();

lib/Target/Mips/Mips16ISelDAGToDAG.cpp

   72   MachineRegisterInfo &RegInfo = MF.getRegInfo();

lib/Target/Mips/MipsCallLowering.cpp

  444     OutgoingValueHandler RetHandler(MIRBuilder, MF.getRegInfo(), Ret);
  496   IncomingValueHandler Handler(MIRBuilder, MF.getRegInfo());
  574         MF.getRegInfo().createGenericVirtualRegister(LLT::pointer(0, 32));
  620   OutgoingValueHandler RetHandler(MIRBuilder, MF.getRegInfo(), MIB);
  661     CallReturnHandler Handler(MIRBuilder, MF.getRegInfo(), MIB);

lib/Target/Mips/MipsConstantIslandPass.cpp

  457   MF->getRegInfo().invalidateLiveness();

lib/Target/Mips/MipsDelaySlotFiller.cpp

  231         F.getRegInfo().invalidateLiveness();

lib/Target/Mips/MipsISelLowering.cpp

 1258   Register VReg = MF.getRegInfo().createVirtualRegister(RC);
 1259   MF.getRegInfo().addLiveIn(PReg, VReg);
 1426   MachineRegisterInfo &RegInfo = MF->getRegInfo();
 1555   MachineRegisterInfo &RegInfo = MF->getRegInfo();
 1574   MachineRegisterInfo &RegInfo = MF->getRegInfo();
 1731   MachineRegisterInfo &MRI = MF->getRegInfo();
 1783   MachineRegisterInfo &RegInfo = MF->getRegInfo();
 3591         Reg = MF.getRegInfo().createVirtualRegister(

lib/Target/Mips/MipsInstructionSelector.cpp

  233   MachineRegisterInfo &MRI = MF.getRegInfo();

lib/Target/Mips/MipsMachineFunction.cpp

   50         MF.getRegInfo().createVirtualRegister(&getGlobalBaseRegClass(MF));
   68   MachineRegisterInfo &RegInfo = MF.getRegInfo();
   81     MF.getRegInfo().addLiveIn(Mips::T9_64);
  109   MF.getRegInfo().addLiveIn(Mips::T9);
  144   MF.getRegInfo().addLiveIn(Mips::V0);

lib/Target/Mips/MipsOptimizePICCall.cpp

  139   const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(Reg);
  280   MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();

lib/Target/Mips/MipsRegisterBankInfo.cpp

  672   LegalizationArtifactCombiner ArtCombiner(B, MF->getRegInfo(), LegInfo);

lib/Target/Mips/MipsSEFrameLowering.cpp

   99     : MF(MF_), MRI(MF.getRegInfo()),
  541       Register VR = MF.getRegInfo().createVirtualRegister(RC);

lib/Target/Mips/MipsSEISelDAGToDAG.cpp

  157   MachineRegisterInfo *MRI = &MF.getRegInfo();

lib/Target/Mips/MipsSEISelLowering.cpp

 3036   MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
 3105   MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
 3172   MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
 3218   MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
 3247   MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
 3283   MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
 3329   MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
 3443   MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
 3478   MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
 3512   MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
 3567   MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
 3666   MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
 3771   MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
 3820   MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
 3849   MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();

lib/Target/Mips/MipsSEInstrInfo.cpp

  614   MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo();

lib/Target/Mips/MipsSERegisterInfo.cpp

  224       MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo();

lib/Target/NVPTX/NVPTXAsmPrinter.cpp

  453   MRI = &MF->getRegInfo();

lib/Target/NVPTX/NVPTXFrameLowering.cpp

   37     MachineRegisterInfo &MR = MF.getRegInfo();

lib/Target/NVPTX/NVPTXInstrInfo.cpp

   36   const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();

lib/Target/NVPTX/NVPTXPeephole.cpp

   82   const auto &MRI = MF.getRegInfo();
  107   const auto &MRI = MF.getRegInfo();
  146   const auto &MRI = MF.getRegInfo();

lib/Target/NVPTX/NVPTXReplaceImageHandles.cpp

  134   const MachineRegisterInfo &MRI = MF.getRegInfo();

lib/Target/PowerPC/PPCAsmPrinter.cpp

 1392         && !MF->getRegInfo().use_empty(PPC::X2)) {
 1502       && !MF->getRegInfo().use_empty(PPC::X2)) {

lib/Target/PowerPC/PPCBranchCoalescing.cpp

  220   MRI = &MF.getRegInfo();

lib/Target/PowerPC/PPCBranchSelector.cpp

  109       !Fn.getRegInfo().use_empty(PPC::X2))

lib/Target/PowerPC/PPCFrameLowering.cpp

  344   const MachineRegisterInfo &MRI = MF->getRegInfo();
  352   for (std::pair<unsigned, unsigned> LI : MF->getRegInfo().liveins()) {
 2157         (MF.getRegInfo().isPhysRegUsed(Reg)))
 2219     const MachineRegisterInfo &MRI = MF->getRegInfo();

lib/Target/PowerPC/PPCISelLowering.cpp

 3634       unsigned VReg = MF.getRegInfo().getLiveInVirtReg(GPArgRegs[GPRIndex]);
 3653       unsigned VReg = MF.getRegInfo().getLiveInVirtReg(FPArgRegs[FPRIndex]);
10353   MachineRegisterInfo &RegInfo = F->getRegInfo();
10457   MachineRegisterInfo &RegInfo = F->getRegInfo();
10617   MachineRegisterInfo &MRI = MF->getRegInfo();
10758   MachineRegisterInfo &MRI = MF->getRegInfo();
11023     MachineRegisterInfo &RegInfo = F->getRegInfo();
11272     MachineRegisterInfo &RegInfo = F->getRegInfo();
11439     MachineRegisterInfo &RegInfo = F->getRegInfo();
11465     MachineRegisterInfo &RegInfo = F->getRegInfo();
11478     MachineRegisterInfo &RegInfo = F->getRegInfo();
11528         MachineRegisterInfo &RegInfo = F->getRegInfo();
11588     MachineRegisterInfo &RegInfo = F->getRegInfo();
15032   MachineRegisterInfo *MRI = &Entry->getParent()->getRegInfo();

lib/Target/PowerPC/PPCInstrInfo.cpp

  801   MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
 2325   assert(!MI.getParent()->getParent()->getRegInfo().isSSA() &&
 2346   MachineRegisterInfo *MRI = &MI.getParent()->getParent()->getRegInfo();
 2456       StartMI.getParent()->getParent()->getRegInfo();
 2556   MachineRegisterInfo *MRI = &MF->getRegInfo();
 2755   MachineRegisterInfo *MRI = &MF->getRegInfo();
 3453   MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
 3635   MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
 3717   MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
 4240       MachineRegisterInfo &MRI = MF->getRegInfo();

lib/Target/PowerPC/PPCMIPeephole.cpp

  135   MRI = &MF->getRegInfo();
  655               MF->getRegInfo().createVirtualRegister(&PPC::G8RCRegClass);

lib/Target/PowerPC/PPCReduceCRLogicals.cpp

  145   MachineRegisterInfo *MRI = &MF->getRegInfo();
  569   MRI = &MF->getRegInfo();

lib/Target/PowerPC/PPCRegisterInfo.cpp

  529   Register Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
  558       NegSizeReg = MF.getRegInfo().createVirtualRegister(G8RC);
  566       NegSizeReg = MF.getRegInfo().createVirtualRegister(G8RC);
  583       NegSizeReg = MF.getRegInfo().createVirtualRegister(GPRC);
  591       NegSizeReg = MF.getRegInfo().createVirtualRegister(GPRC);
  657   Register Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
  669     Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
  702   Register Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
  714     Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
  746   Register Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
  794     Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
  825   Register Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
  835   Register RegO = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
  872   Register Reg = MF.getRegInfo().createVirtualRegister(GPRC);
  898   Register Reg = MF.getRegInfo().createVirtualRegister(GPRC);
 1096   unsigned SRegHi = MF.getRegInfo().createVirtualRegister(RC),
 1097            SReg = MF.getRegInfo().createVirtualRegister(RC);
 1234   MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
 1260   MachineRegisterInfo &MRI = MF.getRegInfo();

lib/Target/PowerPC/PPCVSXCopy.cpp

   86       MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();

lib/Target/PowerPC/PPCVSXFMAMutate.cpp

   73       MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();

lib/Target/PowerPC/PPCVSXSwapRemoval.cpp

  221   MRI = &MF->getRegInfo();

lib/Target/RISCV/RISCVFrameLowering.cpp

   67   MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
  219             MF.getRegInfo().createVirtualRegister(&RISCV::GPRRegClass);
  403       const MCPhysReg * Regs = MF.getRegInfo().getCalleeSavedRegs();

lib/Target/RISCV/RISCVISelLowering.cpp

 1121   MachineRegisterInfo &RegInfo = MF.getRegInfo();
 1690   MachineRegisterInfo &RegInfo = MF.getRegInfo();
 1776   MachineRegisterInfo &RegInfo = MF.getRegInfo();
 1948     MachineRegisterInfo &RegInfo = MF.getRegInfo();

lib/Target/RISCV/RISCVInstrInfo.cpp

  166   MachineRegisterInfo &MRI = MF->getRegInfo();
  383   MachineRegisterInfo &MRI = MF->getRegInfo();

lib/Target/RISCV/RISCVMergeBaseOffset.cpp

  263   MRI = &Fn.getRegInfo();

lib/Target/RISCV/RISCVRegisterInfo.cpp

  109   MachineRegisterInfo &MRI = MF.getRegInfo();

lib/Target/Sparc/DelaySlotFiller.cpp

   54       F.getRegInfo().invalidateLiveness();

lib/Target/Sparc/SparcAsmPrinter.cpp

  277   const MachineRegisterInfo &MRI = MF->getRegInfo();

lib/Target/Sparc/SparcFrameLowering.cpp

  323   MachineRegisterInfo &MRI = MF.getRegInfo();
  333   MachineRegisterInfo &MRI = MF.getRegInfo();

lib/Target/Sparc/SparcISelDAGToDAG.cpp

  227     MachineRegisterInfo &MRI = MF->getRegInfo();

lib/Target/Sparc/SparcISelLowering.cpp

  388   MachineRegisterInfo &RegInfo = MF.getRegInfo();
  421         MF.getRegInfo().addLiveIn(VA.getLocReg(), VRegHi);
  449       MF.getRegInfo().addLiveIn(VA.getLocReg(), VReg);
  527       Reg = MF.getRegInfo().createVirtualRegister(&SP::IntRegsRegClass);
  556       MF.getRegInfo().addLiveIn(*CurArgReg, VReg);

lib/Target/Sparc/SparcInstrInfo.cpp

  481   MachineRegisterInfo &RegInfo = MF->getRegInfo();

lib/Target/SystemZ/SystemZISelLowering.cpp

 1299   MachineRegisterInfo &MRI = MF.getRegInfo();
 6509   MachineRegisterInfo &MRI = MF.getRegInfo();
 6811   MachineRegisterInfo &MRI = MF.getRegInfo();
 6930   MachineRegisterInfo &MRI = MF.getRegInfo();
 7045   MachineRegisterInfo &MRI = MF.getRegInfo();
 7169   MachineRegisterInfo &MRI = MF.getRegInfo();
 7197   MachineRegisterInfo &MRI = MF.getRegInfo();
 7227   MachineRegisterInfo &MRI = MF.getRegInfo();
 7407   MachineRegisterInfo &MRI = MF.getRegInfo();
 7512   MachineRegisterInfo *MRI = &MF.getRegInfo();

lib/Target/SystemZ/SystemZInstrInfo.cpp

  572   MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
 1039            TRI->getRegSizeInBits(*MF.getRegInfo()

lib/Target/SystemZ/SystemZLDCleanup.cpp

  134   MachineRegisterInfo &RegInfo = MF->getRegInfo();

lib/Target/SystemZ/SystemZRegisterInfo.cpp

  302         MF.getRegInfo().createVirtualRegister(&SystemZ::ADDR64BitRegClass);

lib/Target/WebAssembly/WebAssemblyAsmPrinter.h

   51     MRI = &MF.getRegInfo();

lib/Target/WebAssembly/WebAssemblyCFGSort.cpp

  415   MF.getRegInfo().invalidateLiveness();

lib/Target/WebAssembly/WebAssemblyCFGStackify.cpp

  728   MachineRegisterInfo &MRI = MF.getRegInfo();
 1363   MF.getRegInfo().invalidateLiveness();

lib/Target/WebAssembly/WebAssemblyExplicitLocals.cpp

  196   MachineRegisterInfo &MRI = MF.getRegInfo();

lib/Target/WebAssembly/WebAssemblyFixIrreducibleControlFlow.cpp

  361   MachineRegisterInfo &MRI = MF.getRegInfo();
  496     MF.getRegInfo().invalidateLiveness();

lib/Target/WebAssembly/WebAssemblyFrameLowering.cpp

  164   auto &MRI = MF.getRegInfo();
  231   auto &MRI = MF.getRegInfo();

lib/Target/WebAssembly/WebAssemblyISelLowering.cpp

  336   MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
  901   MF.getRegInfo().addLiveIn(WebAssembly::ARGUMENTS);
  928         MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrVT));

lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp

   61   auto &MRI = MBB.getParent()->getRegInfo();
  195   auto &MRI = MF.getRegInfo();
  225   auto &MRI = MF.getRegInfo();

lib/Target/WebAssembly/WebAssemblyLateEHPrepare.cpp

  128   MachineRegisterInfo &MRI = MF.getRegInfo();
  237   MachineRegisterInfo &MRI = MF.getRegInfo();

lib/Target/WebAssembly/WebAssemblyLowerBrUnless.cpp

   63   auto &MRI = MF.getRegInfo();

lib/Target/WebAssembly/WebAssemblyMachineFunctionInfo.cpp

   26   WARegs.resize(MF.getRegInfo().getNumVirtRegs(), Reg);

lib/Target/WebAssembly/WebAssemblyMachineFunctionInfo.h

   98     assert(MF.getRegInfo().getUniqueVRegDef(VReg));

lib/Target/WebAssembly/WebAssemblyMemIntrinsicResults.cpp

  183   MachineRegisterInfo &MRI = MF.getRegInfo();

lib/Target/WebAssembly/WebAssemblyOptimizeLiveIntervals.cpp

   73   MachineRegisterInfo &MRI = MF.getRegInfo();

lib/Target/WebAssembly/WebAssemblyPeephole.cpp

  138   MachineRegisterInfo &MRI = MF.getRegInfo();

lib/Target/WebAssembly/WebAssemblyPrepareForLiveIntervals.cpp

   80   MachineRegisterInfo &MRI = MF.getRegInfo();

lib/Target/WebAssembly/WebAssemblyRegColoring.cpp

   88   MachineRegisterInfo *MRI = &MF.getRegInfo();

lib/Target/WebAssembly/WebAssemblyRegNumbering.cpp

   67   MachineRegisterInfo &MRI = MF.getRegInfo();
   87   unsigned NumVRegs = MF.getRegInfo().getNumVirtRegs();

lib/Target/WebAssembly/WebAssemblyRegStackify.cpp

  774   MachineRegisterInfo &MRI = MF.getRegInfo();
  903     MF.getRegInfo().addLiveIn(WebAssembly::VALUE_STACK);

lib/Target/WebAssembly/WebAssemblyRegisterInfo.cpp

   61   MachineRegisterInfo &MRI = MF.getRegInfo();
   96         MachineInstr *Def = MF.getRegInfo().getUniqueVRegDef(OtherMOReg);

lib/Target/WebAssembly/WebAssemblyReplacePhysRegs.cpp

   69   MachineRegisterInfo &MRI = MF.getRegInfo();

lib/Target/X86/X86AvoidStoreForwardingBlocks.cpp

  677   MRI = &MF.getRegInfo();

lib/Target/X86/X86CallFrameOptimization.cpp

  240   MRI = &MF.getRegInfo();

lib/Target/X86/X86CallLowering.cpp

  197     MachineRegisterInfo &MRI = MF.getRegInfo();
  338   MachineRegisterInfo &MRI = MF.getRegInfo();
  382   MachineRegisterInfo &MRI = MF.getRegInfo();

lib/Target/X86/X86CmovConversion.cpp

  169   MRI = &MF.getRegInfo();

lib/Target/X86/X86DomainReassignment.cpp

  739   MRI = &MF.getRegInfo();

lib/Target/X86/X86FixupSetCC.cpp

   97   MRI = &MF.getRegInfo();

lib/Target/X86/X86FlagsCopyLowering.cpp

  342   MRI = &MF.getRegInfo();

lib/Target/X86/X86FloatingPoint.cpp

  330   const MachineRegisterInfo &MRI = MF.getRegInfo();

lib/Target/X86/X86FrameLowering.cpp

  585   MachineRegisterInfo &MRI = MF.getRegInfo();
 1095     assert(MF.getRegInfo().isReserved(MachineFramePtr) && "FP reserved");
 2300   assert(!MF.getRegInfo().isLiveIn(ScratchReg) &&
 2427         SaveScratch2 = MF.getRegInfo().isLiveIn(ScratchReg2);
 2431       assert((!MF.getRegInfo().isLiveIn(ScratchReg2) || SaveScratch2) &&
 2686     assert(!MF.getRegInfo().isLiveIn(ScratchReg) &&
 2743   auto &MRI = MBB.getParent()->getRegInfo();

lib/Target/X86/X86ISelLowering.cpp

 2501       MF.getRegInfo().disableCalleeSavedRegister(VA.getLocReg());
 2582         MF.getRegInfo().disableCalleeSavedRegister(RVLocs[I].getLocReg());
 2642       MF.getRegInfo().disableCalleeSavedRegister(RetValReg);
 3328         Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
 3477       FR.VReg = MF.getRegInfo().createVirtualRegister(getRegClassFor(FR.VT));
 3529     MachineRegisterInfo &MRI = MF.getRegInfo();
 4426       const MachineRegisterInfo *MRI = &MF.getRegInfo();
 4471     const MachineRegisterInfo &MRI = MF.getRegInfo();
22231     MachineRegisterInfo &MRI = MF.getRegInfo();
29211   MachineRegisterInfo &MRI = MF->getRegInfo();
29294   MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
30048   MachineRegisterInfo &MRI = MF->getRegInfo();
30427   MachineRegisterInfo &MRI = MF->getRegInfo();
30471   MachineRegisterInfo &MRI = MF->getRegInfo();
30630   MachineRegisterInfo &MRI = MF->getRegInfo();
30806   MachineRegisterInfo &MRI = MF->getRegInfo();
30889   MachineRegisterInfo *MRI = &MF->getRegInfo();
30938   MachineRegisterInfo *MRI = &MF->getRegInfo();
31110   const MCPhysReg *SavedRegs = MF->getRegInfo().getCalleeSavedRegs();
31264     Register OldCW = MF->getRegInfo().createVirtualRegister(&X86::GR32RegClass);
31269     Register NewCW = MF->getRegInfo().createVirtualRegister(&X86::GR32RegClass);
31275         MF->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
31376     MachineRegisterInfo &MRI = MF->getRegInfo();
46183   MachineRegisterInfo *MRI = &Entry->getParent()->getRegInfo();

lib/Target/X86/X86InstrInfo.cpp

  725         !MF.getRegInfo().constrainRegClass(NewSrc, RC))
  743     NewSrc = MF.getRegInfo().createVirtualRegister(RC);
  764   MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo();
  929         !MF.getRegInfo().constrainRegClass(Src.getReg(),
 2870   MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
 4635   MachineRegisterInfo &MRI = MF.getRegInfo();
 4816   MachineRegisterInfo &RegInfo = MF.getRegInfo();
 6028   MachineRegisterInfo &RegInfo = MF->getRegInfo();
 7763       MachineRegisterInfo &RegInfo = MF.getRegInfo();
 7926       MachineRegisterInfo &RegInfo = MF->getRegInfo();

lib/Target/X86/X86InstructionSelector.cpp

  313   MachineRegisterInfo &MRI = MF.getRegInfo();

lib/Target/X86/X86OptimizeLEAs.cpp

  681   MRI = &MF.getRegInfo();

lib/Target/X86/X86SpeculativeLoadHardening.cpp

  409   MRI = &MF.getRegInfo();

lib/Target/X86/X86VZeroUpper.cpp

  285   MachineRegisterInfo &MRI = MF.getRegInfo();

lib/Target/X86/X86WinAllocaExpander.cpp

  277   MRI = &MF.getRegInfo();

lib/Target/XCore/XCoreFrameLowering.cpp

  541   const MachineRegisterInfo &MRI = MF.getRegInfo();

lib/Target/XCore/XCoreISelLowering.cpp

 1265   MachineRegisterInfo &RegInfo = MF.getRegInfo();

tools/llvm-exegesis/lib/Assembler.cpp

  191     MF.getRegInfo().addLiveIn(Reg);
  214   MF.getRegInfo().freezeReservedRegs(MF);

unittests/CodeGen/GlobalISel/GISelMITest.h

  148     MRI = &MF->getRegInfo();