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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/ARM/ARMGenAsmMatcher.inc15303 MII.get(Inst.getOpcode()).getDeprecatedInfo(Inst, getSTI(), Info)) {
gen/lib/Target/PowerPC/PPCGenAsmMatcher.inc 7185 MII.get(Inst.getOpcode()).getDeprecatedInfo(Inst, getSTI(), Info)) {
gen/lib/Target/X86/X86GenFastISel.inc 6952 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TargetOpcode::COPY), X86::AL).addReg(Op0);
7435 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TargetOpcode::COPY), X86::CL).addReg(Op1);
7537 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TargetOpcode::COPY), X86::CL).addReg(Op1);
7699 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TargetOpcode::COPY), X86::CL).addReg(Op1);
8025 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TargetOpcode::COPY), X86::CL).addReg(Op1);
8041 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TargetOpcode::COPY), X86::CL).addReg(Op1);
include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h 752 OutMIs[NewInsnID]->setDesc(TII.get(NewOpcode));
767 State.MIs[0]->getDebugLoc(), TII.get(Opcode));
include/llvm/CodeGen/TargetInstrInfo.h 1706 return BuildMI(MBB, InsPt, DL, get(TargetOpcode::COPY), Dst)
1718 return BuildMI(MBB, InsPt, DL, get(TargetOpcode::COPY), Dst)
include/llvm/MC/MCInstrAnalysis.h 38 return Info->get(Inst.getOpcode()).isBranch();
42 return Info->get(Inst.getOpcode()).isConditionalBranch();
46 return Info->get(Inst.getOpcode()).isUnconditionalBranch();
50 return Info->get(Inst.getOpcode()).isIndirectBranch();
54 return Info->get(Inst.getOpcode()).isCall();
58 return Info->get(Inst.getOpcode()).isReturn();
62 return Info->get(Inst.getOpcode()).isTerminator();
lib/CodeGen/BranchFolding.cpp 442 BuildMI(OldMBB, OldInst, DL, TII->get(TargetOpcode::IMPLICIT_DEF), Reg);
941 BuildMI(*Pred, InsertBefore, DL, TII->get(TargetOpcode::IMPLICIT_DEF),
lib/CodeGen/CFIInstrInserter.cpp 265 BuildMI(*MBBInfo.MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
274 BuildMI(*MBBInfo.MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
286 BuildMI(*MBBInfo.MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
lib/CodeGen/ExpandPostRAPseudos.cpp 98 MI->setDesc(TII->get(TargetOpcode::KILL));
111 MI->setDesc(TII->get(TargetOpcode::KILL));
138 MI->setDesc(TII->get(TargetOpcode::KILL));
155 MI->setDesc(TII->get(TargetOpcode::KILL));
lib/CodeGen/FEntryInserter.cpp 45 TII->get(TargetOpcode::FENTRY_CALL));
lib/CodeGen/GCRootLowering.cpp 260 BuildMI(MBB, MI, DL, TII->get(TargetOpcode::GC_LABEL)).addSym(Label);
lib/CodeGen/GlobalISel/CombinerHelper.cpp 451 Builder.getTII().get(Preferred.ExtendOpcode == TargetOpcode::G_SEXT
lib/CodeGen/GlobalISel/LegalizerHelper.cpp 1888 MI.setDesc(TII.get(TargetOpcode::G_BUILD_VECTOR_TRUNC));
3688 MI.setDesc(TII.get(TargetOpcode::G_CTLZ));
3738 MI.setDesc(TII.get(TargetOpcode::G_CTTZ));
3780 MI.setDesc(TII.get(TargetOpcode::G_CTPOP));
lib/CodeGen/GlobalISel/LegalizerInfo.cpp 693 const MCInstrDesc &MCID = MII.get(Opcode);
lib/CodeGen/GlobalISel/MachineIRBuilder.cpp 79 MachineInstrBuilder MIB = BuildMI(getMF(), getDL(), getTII().get(Opcode));
98 getTII().get(TargetOpcode::DBG_VALUE),
115 getTII().get(TargetOpcode::DBG_VALUE),
lib/CodeGen/GlobalISel/Utils.cpp 58 TII.get(TargetOpcode::COPY), ConstrainedReg)
63 TII.get(TargetOpcode::COPY), Reg)
lib/CodeGen/ImplicitNullChecks.cpp 637 auto MIB = BuildMI(MBB, DL, TII->get(TargetOpcode::FAULTING_OP), DefReg)
lib/CodeGen/InlineSpiller.cpp 474 MI.setDesc(TII.get(TargetOpcode::KILL));
945 BuildMI(MBB, std::next(MI), MI->getDebugLoc(), TII.get(TargetOpcode::KILL))
1520 RMEnt->setDesc(TII.get(TargetOpcode::KILL));
lib/CodeGen/LiveDebugVariables.cpp 1319 BuildMI(*MBB, I, getDebugLoc(), TII.get(TargetOpcode::DBG_VALUE),
1333 BuildMI(*MBB, I, getDebugLoc(), TII.get(TargetOpcode::DBG_LABEL))
lib/CodeGen/LiveRangeEdit.cpp 348 MI->setDesc(TII.get(TargetOpcode::KILL));
lib/CodeGen/MIRParser/MIParser.cpp 970 const auto &MCID = MF.getSubtarget().getInstrInfo()->get(OpCode);
lib/CodeGen/MachineBasicBlock.cpp 517 BuildMI(*this, I, DebugLoc(), TII.get(TargetOpcode::COPY), VirtReg)
lib/CodeGen/MachineCombiner.cpp 362 unsigned Idx = TII->get(Opc).getSchedClass();
lib/CodeGen/MachineInstrBundle.cpp 135 BuildMI(MF, getDebugLoc(FirstMI, LastMI), TII->get(TargetOpcode::BUNDLE));
lib/CodeGen/MachineLICM.cpp 1302 const MCInstrDesc &MID = TII->get(NewOpc);
lib/CodeGen/MachinePipeliner.cpp 368 auto Copy = BuildMI(PredB, At, DL, TII->get(TargetOpcode::COPY), NewReg)
lib/CodeGen/MachineRegisterInfo.cpp 487 TII.get(TargetOpcode::COPY), LiveIns[i].second)
lib/CodeGen/MachineSSAUpdater.cpp 122 return BuildMI(*BB, I, DebugLoc(), TII->get(Opcode), NewVR);
lib/CodeGen/ModuloSchedule.cpp 552 TII->get(TargetOpcode::PHI), NewReg);
668 TII->get(TargetOpcode::PHI), NewReg);
813 TII->get(TargetOpcode::COPY), SplitReg)
1437 BuildMI(*BB, MI, DebugLoc(), TII->get(TargetOpcode::PHI), R)
1486 BuildMI(*BB, BB->getFirstNonPHI(), DebugLoc(), TII->get(TargetOpcode::PHI), R)
1507 TII->get(TargetOpcode::IMPLICIT_DEF), R);
1689 MachineInstr *NI = BuildMI(NewBB, DebugLoc(), TII->get(TargetOpcode::PHI), R)
lib/CodeGen/PHIElimination.cpp 268 TII->get(TargetOpcode::IMPLICIT_DEF), DestReg);
406 TII->get(TargetOpcode::IMPLICIT_DEF),
lib/CodeGen/PatchableFunction.cpp 73 TII->get(TargetOpcode::PATCHABLE_OP))
lib/CodeGen/PeepholeOptimizer.cpp 586 TII->get(TargetOpcode::COPY), NewVR)
767 TII.get(TargetOpcode::PHI), NewVR);
1006 CopyLike.setDesc(TII.get(TargetOpcode::COPY));
1236 TII->get(TargetOpcode::COPY), NewVReg)
lib/CodeGen/ProcessImplicitDefs.cpp 87 UserMI->setDesc(TII->get(TargetOpcode::IMPLICIT_DEF));
lib/CodeGen/PrologEpilogInserter.cpp 548 TII.get(TargetOpcode::COPY), CS.getDstReg())
575 BuildMI(RestoreBlock, I, DebugLoc(), TII.get(TargetOpcode::COPY), Reg)
lib/CodeGen/RegisterCoalescer.cpp 1124 TII->get(TargetOpcode::COPY), IntB.reg)
1552 CopyMI->setDesc(TII->get(TargetOpcode::IMPLICIT_DEF));
lib/CodeGen/RenameIndependentSubregs.cpp 331 const MCInstrDesc &MCDesc = TII->get(TargetOpcode::IMPLICIT_DEF);
lib/CodeGen/ScheduleDAG.cpp 72 return &TII->get(Node->getMachineOpcode());
lib/CodeGen/SelectionDAG/FastISel.cpp 447 TII.get(TargetOpcode::IMPLICIT_DEF), Reg);
839 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AdjStackDown));
846 TII.get(TargetOpcode::STACKMAP));
852 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AdjStackUp))
1023 TII.get(TargetOpcode::PATCHPOINT));
1052 TII.get(TargetOpcode::PATCHABLE_EVENT_CALL));
1073 TII.get(TargetOpcode::PATCHABLE_TYPED_EVENT_CALL));
1309 TII.get(TargetOpcode::INLINEASM))
1395 TII.get(TargetOpcode::DBG_VALUE), /*IsIndirect*/ false,
1407 const MCInstrDesc &II = TII.get(TargetOpcode::DBG_VALUE);
1456 TII.get(TargetOpcode::DBG_LABEL)).addMetadata(DI->getLabel());
1556 TII.get(TargetOpcode::COPY), ResultReg).addReg(Op0);
2030 TII.get(TargetOpcode::COPY), NewOp).addReg(Op);
2040 const MCInstrDesc &II = TII.get(MachineInstOpcode);
2049 const MCInstrDesc &II = TII.get(MachineInstOpcode);
2061 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
2071 const MCInstrDesc &II = TII.get(MachineInstOpcode);
2086 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
2096 const MCInstrDesc &II = TII.get(MachineInstOpcode);
2114 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
2122 const MCInstrDesc &II = TII.get(MachineInstOpcode);
2136 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
2145 const MCInstrDesc &II = TII.get(MachineInstOpcode);
2161 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
2169 const MCInstrDesc &II = TII.get(MachineInstOpcode);
2180 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
2189 const MCInstrDesc &II = TII.get(MachineInstOpcode);
2206 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
2214 const MCInstrDesc &II = TII.get(MachineInstOpcode);
2222 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
2234 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TargetOpcode::COPY),
lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp 287 BuildMI(MBB, DL, TII->get(TargetOpcode::PHI), PHIReg + i);
lib/CodeGen/SelectionDAG/InstrEmitter.cpp 132 const MCInstrDesc &II = TII->get(User->getMachineOpcode());
177 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
277 TII->get(TargetOpcode::IMPLICIT_DEF), VReg);
324 TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg);
391 TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg);
468 BuildMI(*MBB, InsertPos, DL, TII->get(TargetOpcode::COPY), NewReg)
525 TII->get(TargetOpcode::COPY), VRBase).addReg(SrcReg);
542 TII->get(TargetOpcode::COPY), VRBase);
579 BuildMI(*MF, Node->getDebugLoc(), TII->get(Opc), VRBase);
617 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
634 const MCInstrDesc &II = TII->get(TargetOpcode::REG_SEQUENCE);
691 auto MIB = BuildMI(*MF, DL, TII->get(TargetOpcode::DBG_VALUE));
702 auto FrameMI = BuildMI(*MF, DL, TII->get(TargetOpcode::DBG_VALUE))
712 const MCInstrDesc &II = TII->get(TargetOpcode::DBG_VALUE);
771 const MCInstrDesc &II = TII->get(TargetOpcode::DBG_LABEL);
810 const MCInstrDesc &II = TII->get(Opc);
954 const MCInstrDesc &MCID = TII->get(F->getMachineOpcode());
1001 TII->get(TargetOpcode::IMPLICIT_DEF), DestReg);
1013 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
1029 TII->get(Opc)).addSym(S);
1039 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TarOp))
1055 BuildMI(*MF, Node->getDebugLoc(), TII->get(TgtOpc));
lib/CodeGen/SelectionDAG/ResourcePriorityQueue.cpp 253 if (!ResourcesModel->canReserveResources(&TII->get(
293 ResourcesModel->reserveResources(&TII->get(
436 const MCInstrDesc &TID = TII->get(N->getMachineOpcode());
538 const MCInstrDesc &TID = TII->get(N->getMachineOpcode());
lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp 254 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());
432 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());
511 const MCInstrDesc &MCID = TII->get(Node->getMachineOpcode());
lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp 341 const MCInstrDesc Desc = TII->get(Opcode);
1034 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());
1283 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());
1412 const MCInstrDesc &MCID = TII->get(Node->getMachineOpcode());
2114 unsigned NumDefs = TII->get(N->getMachineOpcode()).getNumDefs();
2160 unsigned NumDefs = TII->get(N->getMachineOpcode()).getNumDefs();
2289 unsigned NumDefs = TII->get(PN->getMachineOpcode()).getNumDefs();
2306 unsigned NumDefs = TII->get(N->getMachineOpcode()).getNumDefs();
2819 const MCInstrDesc &MCID = TII->get(Opc);
2842 = TII->get(SU->getNode()->getMachineOpcode()).getImplicitDefs();
2877 unsigned NumDefs = TII->get(N->getMachineOpcode()).getNumDefs();
2878 const MCPhysReg *ImpDefs = TII->get(N->getMachineOpcode()).getImplicitDefs();
2885 TII->get(SUNode->getMachineOpcode()).getImplicitDefs();
3064 const MCInstrDesc &MCID = TII->get(Opc);
lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp 126 const MCInstrDesc &II = TII->get(Def->getMachineOpcode());
212 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());
315 const MCInstrDesc &MCID = TII->get(Opc);
373 if (N->isMachineOpcode() && TII->get(N->getMachineOpcode()).isCall())
391 if (N->isMachineOpcode() && TII->get(N->getMachineOpcode()).isCall())
449 const MCInstrDesc &MCID = TII->get(Opc);
463 TII->get(N->getMachineOpcode()).getImplicitDefs()) {
468 if (NumUsed > TII->get(N->getMachineOpcode()).getNumDefs())
567 unsigned NRegDefs = SchedDAG->TII->get(Node->getMachineOpcode()).getNumDefs();
654 OpIdx += TII->get(Use->getMachineOpcode()).getNumDefs();
806 BuildMI(*BB, InsertPos, DebugLoc(), TII->get(TargetOpcode::COPY), Reg)
815 BuildMI(*BB, InsertPos, DebugLoc(), TII->get(TargetOpcode::COPY), VRBase)
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp 5543 BuildMI(MF, DL, TII->get(TargetOpcode::DBG_VALUE), false,
5580 BuildMI(MF, DL, TII->get(TargetOpcode::DBG_VALUE), false,
6657 TII->get(TargetOpcode::LOCAL_ESCAPE))
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp 605 BuildMI(*EntryMBB, ++InsertPos, DL, TII->get(TargetOpcode::DBG_VALUE),
627 BuildMI(*MF, DL, TII->get(TargetOpcode::DBG_VALUE), IsIndirect,
642 const MCInstrDesc &MCID = TII->get(MI.getOpcode());
1247 TII->get(TargetOpcode::COPY), VReg)
1258 const MCInstrDesc &II = TII->get(TargetOpcode::EH_LABEL);
3485 const MCInstrDesc &MCID = TII->get(TargetOpc);
lib/CodeGen/SplitKit.cpp 515 const MCInstrDesc &Desc = TII.get(TargetOpcode::COPY);
541 const MCInstrDesc &Desc = TII.get(TargetOpcode::COPY);
lib/CodeGen/SwiftErrorValueTracking.cpp 137 TII->get(TargetOpcode::IMPLICIT_DEF), VReg);
232 BuildMI(*MBB, MBB->getFirstNonPHI(), DLoc, TII->get(TargetOpcode::COPY),
246 TII->get(TargetOpcode::PHI), PHIVReg);
lib/CodeGen/TailDuplicator.cpp 377 TII->get(TargetOpcode::CFI_INSTRUCTION)).addCFIIndex(
438 TII->get(TargetOpcode::COPY), NewReg)
982 const MCInstrDesc &CopyD = TII->get(TargetOpcode::COPY);
lib/CodeGen/TargetInstrInfo.cpp 501 MF.CreateMachineInstr(TII.get(MI.getOpcode()), MI.getDebugLoc(), true);
838 BuildMI(*MF, Prev.getDebugLoc(), TII->get(Opcode), NewVR)
842 BuildMI(*MF, Root.getDebugLoc(), TII->get(Opcode), RegC)
1047 unsigned DefClass = get(DefNode->getMachineOpcode()).getSchedClass();
1050 unsigned UseClass = get(UseNode->getMachineOpcode()).getSchedClass();
1062 return ItinData->getStageLatency(get(N->getMachineOpcode()).getSchedClass());
lib/CodeGen/TargetSchedule.cpp 262 unsigned SCIdx = TII->get(Opcode).getSchedClass();
340 unsigned SchedClass = TII->get(Opcode).getSchedClass();
lib/CodeGen/TwoAddressInstructionPass.cpp 1357 const MCInstrDesc &UnfoldMCID = TII->get(NewOpc);
1553 TII->get(TargetOpcode::COPY), RegA);
1771 mi->setDesc(TII->get(TargetOpcode::COPY));
1838 TII->get(TargetOpcode::COPY))
1863 MI.setDesc(TII->get(TargetOpcode::IMPLICIT_DEF));
lib/CodeGen/UnreachableBlockElim.cpp 196 TII->get(TargetOpcode::COPY), OutputReg)
lib/CodeGen/VirtRegMap.cpp 387 MI.setDesc(TII->get(TargetOpcode::KILL));
lib/CodeGen/XRayInstrumentation.cpp 108 auto MIB = BuildMI(MBB, T, T.getDebugLoc(), TII->get(Opc))
139 BuildMI(MBB, T, T.getDebugLoc(), TII->get(Opc));
206 TII->get(TargetOpcode::PATCHABLE_FUNCTION_ENTER));
lib/MC/MCDisassembler/Disassembler.cpp 180 const MCInstrDesc& Desc = DC->getInstrInfo()->get(Inst.getOpcode());
207 const MCInstrDesc& Desc = DC->getInstrInfo()->get(Inst.getOpcode());
lib/MC/MCInstrAnalysis.cpp 29 Info->get(Inst.getOpcode()).OpInfo[0].OperandType != MCOI::OPERAND_PCREL)
lib/MC/MCParser/AsmParser.cpp 5809 const MCInstrDesc &Desc = MII->get(Info.Opcode);
lib/MC/MCSchedule.cpp 70 unsigned SchedClass = MCII.get(Inst.getOpcode()).getSchedClass();
113 unsigned SchedClass = MCII.get(Inst.getOpcode()).getSchedClass();
lib/MCA/InstrBuilder.cpp 249 const MCInstrDesc &MCDesc = MCII.get(MCI.getOpcode());
419 const MCInstrDesc &MCDesc = MCII.get(MCI.getOpcode());
515 const MCInstrDesc &MCDesc = MCII.get(Opcode);
lib/Target/AArch64/AArch64A53Fix835769.cpp 179 BuildMI(I->getParent(), DL, TII->get(AArch64::HINT)).addImm(0);
183 BuildMI(MBB, MI, DL, TII->get(AArch64::HINT)).addImm(0);
lib/Target/AArch64/AArch64AdvSIMDScalarPass.cpp 277 TII->get(AArch64::COPY), Dst)
362 BuildMI(*MBB, MI, MI.getDebugLoc(), TII->get(NewOpc), Dst)
lib/Target/AArch64/AArch64BranchTargets.cpp 127 TII->get(AArch64::HINT))
lib/Target/AArch64/AArch64CleanupLocalDynamicTLSPass.cpp 105 TII->get(TargetOpcode::COPY), AArch64::X0)
127 TII->get(TargetOpcode::COPY), *TLSBaseAddrReg)
lib/Target/AArch64/AArch64CompressJumpTables.cpp 123 MI.setDesc(TII->get(AArch64::JumpTableDest8));
128 MI.setDesc(TII->get(AArch64::JumpTableDest16));
lib/Target/AArch64/AArch64CondBrTuning.cpp 106 TII->get(NewOpc), NewDestReg);
137 return BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), TII->get(AArch64::Bcc))
lib/Target/AArch64/AArch64ConditionOptimizer.cpp 279 BuildMI(*MBB, CmpMI, CmpMI->getDebugLoc(), TII->get(Opc))
291 BuildMI(*MBB, BrMI, BrMI.getDebugLoc(), TII->get(AArch64::Bcc))
lib/Target/AArch64/AArch64ConditionalCompares.cpp 632 const MCInstrDesc &MCID = TII->get(Opc);
689 const MCInstrDesc &MCID = TII->get(Opc);
708 BuildMI(*Head, CmpMI, CmpMI->getDebugLoc(), TII->get(AArch64::Bcc))
lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp 135 MIBS.push_back(BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(I->Opcode))
145 MIBS.push_back(BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(I->Opcode))
155 MIBS.push_back(BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(I->Opcode))
201 BuildMI(LoadCmpBB, DL, TII->get(AArch64::MOVZWi), StatusReg)
203 BuildMI(LoadCmpBB, DL, TII->get(LdarOp), Dest.getReg())
205 BuildMI(LoadCmpBB, DL, TII->get(CmpOp), ZeroReg)
209 BuildMI(LoadCmpBB, DL, TII->get(AArch64::Bcc))
219 BuildMI(StoreBB, DL, TII->get(StlrOp), StatusReg)
222 BuildMI(StoreBB, DL, TII->get(AArch64::CBNZW))
282 BuildMI(LoadCmpBB, DL, TII->get(AArch64::LDAXPX))
286 BuildMI(LoadCmpBB, DL, TII->get(AArch64::SUBSXrs), AArch64::XZR)
290 BuildMI(LoadCmpBB, DL, TII->get(AArch64::CSINCWr), StatusReg)
294 BuildMI(LoadCmpBB, DL, TII->get(AArch64::SUBSXrs), AArch64::XZR)
298 BuildMI(LoadCmpBB, DL, TII->get(AArch64::CSINCWr), StatusReg)
302 BuildMI(LoadCmpBB, DL, TII->get(AArch64::CBNZW))
311 BuildMI(StoreBB, DL, TII->get(AArch64::STLXPX), StatusReg)
315 BuildMI(StoreBB, DL, TII->get(AArch64::CBNZW))
363 BuildMI(LoopBB, DL, TII->get(OpCode))
370 BuildMI(LoopBB, DL, TII->get(AArch64::SUBXri))
375 BuildMI(LoopBB, DL, TII->get(AArch64::CBNZX)).addUse(SizeReg).addMBB(LoopBB);
466 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opcode),
485 TII->get(AArch64::LDRXl), DstReg);
501 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::ADRP), DstReg);
508 MIB2 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::LDRWui))
514 MIB2 = BuildMI(MBB, MBBI, DL, TII->get(AArch64::LDRXui))
553 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::ADRP), DstReg)
567 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::MOVKXi), DstReg)
574 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::ADDXri))
586 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::ADDXri))
607 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::MRS), DstReg)
624 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::RET))
657 TII->get(Opcode == AArch64::AESMCrrTied ? AArch64::AESMCrr :
687 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::IRG))
695 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::ADDG))
lib/Target/AArch64/AArch64FalkorHWPFFix.cpp 770 BuildMI(*MBB, &MI, DL, TII->get(AArch64::ORRXrs), ScratchReg)
785 TII->get(AArch64::ORRXrs), LdI.BaseReg)
lib/Target/AArch64/AArch64FastISel.cpp 369 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADDXri),
392 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TargetOpcode::COPY),
424 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc1), TmpReg)
429 TII.get(TargetOpcode::COPY), ResultReg)
443 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADRP),
448 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
475 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADRP),
487 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(LdrOpc),
499 TII.get(TargetOpcode::SUBREG_TO_REG))
507 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADRP),
512 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADDXri),
1057 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADDXri),
1343 const MCInstrDesc &II = TII.get(Opc);
1388 const MCInstrDesc &II = TII.get(Opc);
1430 const MCInstrDesc &II = TII.get(Opc);
1475 const MCInstrDesc &II = TII.get(Opc);
1537 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc))
1548 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc))
1898 TII.get(Opc), ResultReg);
1913 TII.get(AArch64::SUBREG_TO_REG), Reg64)
2101 const MCInstrDesc &II = TII.get(Opc);
2170 const MCInstrDesc &II = TII.get(Opc);
2393 const MCInstrDesc &II = TII.get(Opc);
2410 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc))
2480 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::Bcc))
2486 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::Bcc))
2496 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::B))
2517 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::Bcc))
2538 const MCInstrDesc &II = TII.get(Opcode);
2557 const MCInstrDesc &II = TII.get(AArch64::BR);
2584 TII.get(TargetOpcode::COPY), ResultReg)
2623 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::CSINCWr),
2628 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::CSINCWr),
2642 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::CSINCWr),
2809 const MCInstrDesc &II = TII.get(AArch64::ANDSWri);
2849 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::FCVTDSr),
2865 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::FCVTSDr),
2899 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
3055 TII.get(TargetOpcode::COPY), ResultReg)
3075 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AdjStackDown))
3116 TII.get(TargetOpcode::COPY), VA.getLocReg()).addReg(ArgReg);
3158 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AdjStackUp))
3180 TII.get(TargetOpcode::COPY), ResultReg)
3268 const MCInstrDesc &II = TII.get(Addr.getReg() ? AArch64::BLR : AArch64::BL);
3283 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADRP),
3289 TII.get(AArch64::LDRXui), CallReg)
3301 const MCInstrDesc &II = TII.get(AArch64::BLR);
3482 TII.get(TargetOpcode::COPY), SrcReg).addReg(FramePtr);
3507 TII.get(AArch64::ADDXri), ResultReg)
3640 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
3646 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::BRK))
3651 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::BRK))
3815 TII.get(TargetOpcode::COPY), ResultReg1).addReg(MulReg);
3927 TII.get(TargetOpcode::COPY), DestReg).addReg(SrcReg);
3934 TII.get(AArch64::RET_ReallyLR));
3998 TII.get(TargetOpcode::COPY), ResultReg)
4022 TII.get(AArch64::SUBREG_TO_REG), Reg64)
4128 TII.get(TargetOpcode::COPY), ResultReg)
4175 TII.get(AArch64::SUBREG_TO_REG), TmpReg)
4235 TII.get(TargetOpcode::COPY), ResultReg)
4296 TII.get(AArch64::SUBREG_TO_REG), TmpReg)
4356 TII.get(TargetOpcode::COPY), ResultReg)
4405 TII.get(AArch64::SUBREG_TO_REG), TmpReg)
4464 TII.get(AArch64::SUBREG_TO_REG), Src64)
4561 TII.get(AArch64::SUBREG_TO_REG), Reg64)
4605 TII.get(AArch64::SUBREG_TO_REG), ResultReg)
5111 const MCInstrDesc &II = TII.get(Opc);
5132 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(CmpOpc))
5138 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::CSINCWr))
lib/Target/AArch64/AArch64FrameLowering.cpp 365 BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
505 MIB = BuildMI(MF, DL, TII.get(AArch64::SEH_SaveFRegP_X))
519 MIB = BuildMI(MF, DL, TII.get(AArch64::SEH_SaveFPLR_X))
523 MIB = BuildMI(MF, DL, TII.get(AArch64::SEH_SaveRegP_X))
535 MIB = BuildMI(MF, DL, TII.get(AArch64::SEH_SaveFReg_X))
546 MIB = BuildMI(MF, DL, TII.get(AArch64::SEH_SaveReg_X))
556 MIB = BuildMI(MF, DL, TII.get(AArch64::SEH_SaveFRegP))
568 MIB = BuildMI(MF, DL, TII.get(AArch64::SEH_SaveFPLR))
572 MIB = BuildMI(MF, DL, TII.get(AArch64::SEH_SaveRegP))
582 MIB = BuildMI(MF, DL, TII.get(AArch64::SEH_SaveReg))
591 MIB = BuildMI(MF, DL, TII.get(AArch64::SEH_SaveFReg))
693 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(NewOpc));
867 BuildMI(MBB, MBBI, DL, TII->get(AArch64::PACIASP))
870 BuildMI(MBB, MBBI, DL, TII->get(AArch64::EMITBKEY))
872 BuildMI(MBB, MBBI, DL, TII->get(AArch64::PACIBSP))
878 BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
925 BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
933 BuildMI(MBB, MBBI, DL, TII->get(AArch64::SEH_PrologEnd))
981 BuildMI(MBB, MBBI, DL, TII->get(AArch64::SEH_PrologEnd))
991 BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::COPY), AArch64::FP)
1030 BuildMI(MBB, MBBI, DL, TII->get(AArch64::MOVZXi), AArch64::X15)
1034 BuildMI(MBB, MBBI, DL, TII->get(AArch64::SEH_Nop))
1037 BuildMI(MBB, MBBI, DL, TII->get(AArch64::MOVKXi), AArch64::X15)
1042 BuildMI(MBB, MBBI, DL, TII->get(AArch64::SEH_Nop))
1046 BuildMI(MBB, MBBI, DL, TII->get(AArch64::MOVi64imm), AArch64::X15)
1056 BuildMI(MBB, MBBI, DL, TII->get(AArch64::BL))
1065 BuildMI(MBB, MBBI, DL, TII->get(AArch64::SEH_Nop))
1070 BuildMI(MBB, MBBI, DL, TII->get(AArch64::MOVaddrEXT))
1077 BuildMI(MBB, MBBI, DL, TII->get(AArch64::SEH_Nop))
1081 BuildMI(MBB, MBBI, DL, TII->get(AArch64::BLR))
1090 BuildMI(MBB, MBBI, DL, TII->get(AArch64::SEH_Nop))
1096 BuildMI(MBB, MBBI, DL, TII->get(AArch64::SUBXrx64), AArch64::SP)
1103 BuildMI(MBB, MBBI, DL, TII->get(AArch64::SEH_StackAlloc))
1149 BuildMI(MBB, MBBI, DL, TII->get(AArch64::ANDXri), AArch64::SP)
1155 BuildMI(MBB, MBBI, DL, TII->get(AArch64::SEH_StackAlloc))
1174 BuildMI(MBB, MBBI, DL, TII->get(AArch64::SEH_Nop))
1182 BuildMI(MBB, MBBI, DL, TII->get(AArch64::SEH_PrologEnd))
1263 BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
1270 BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
1300 TII->get(ShouldSignWithAKey(MF) ? AArch64::RETAA : AArch64::RETAB))
1306 TII->get(ShouldSignWithAKey(MF) ? AArch64::AUTIASP : AArch64::AUTIBSP))
1457 BuildMI(MBB, LastPopI, DL, TII->get(AArch64::SEH_EpilogStart))
1471 TII->get(AArch64::SEH_EpilogEnd))
1512 TII->get(AArch64::SEH_EpilogEnd))
1559 BuildMI(MBB, MBB.getFirstTerminator(), DL, TII->get(AArch64::SEH_EpilogEnd))
1962 BuildMI(MBB, MI, DL, TII.get(AArch64::STRXpost))
1970 BuildMI(MBB, MI, DL, TII.get(AArch64::SEH_Nop))
1985 BuildMI(MBB, MI, DL, TII.get(AArch64::CFI_INSTRUCTION))
2046 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(StrOpc));
2135 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(LdrOpc));
2162 BuildMI(MBB, MI, DL, TII.get(AArch64::LDRXpre))
2378 BuildMI(MBB, MBBI, DL, TII.get(AArch64::MOVi64imm), DstReg).addImm(-2);
2379 BuildMI(MBB, MBBI, DL, TII.get(AArch64::STURXi))
lib/Target/AArch64/AArch64ISelLowering.cpp 1358 BuildMI(MBB, DL, TII->get(AArch64::Bcc)).addImm(CondCode).addMBB(TrueBB);
1359 BuildMI(MBB, DL, TII->get(AArch64::B)).addMBB(EndBB);
1371 BuildMI(*EndBB, EndBB->begin(), DL, TII->get(AArch64::PHI), DestReg)
12404 BuildMI(*Entry, MBBI, DebugLoc(), TII->get(TargetOpcode::COPY), NewVR)
12410 TII->get(TargetOpcode::COPY), *I)
lib/Target/AArch64/AArch64InstrInfo.cpp 376 BuildMI(&MBB, DL, get(AArch64::Bcc)).addImm(Cond[0].getImm()).addMBB(TBB);
381 BuildMI(&MBB, DL, get(Cond[1].getImm())).add(Cond[2]);
396 BuildMI(&MBB, DL, get(AArch64::B)).addMBB(TBB);
408 BuildMI(&MBB, DL, get(AArch64::B)).addMBB(FBB);
580 BuildMI(MBB, I, DL, get(AArch64::SUBSXri), AArch64::XZR)
586 BuildMI(MBB, I, DL, get(AArch64::SUBSWri), AArch64::WZR)
609 BuildMI(MBB, I, DL, get(AArch64::ANDSWri), AArch64::WZR)
614 BuildMI(MBB, I, DL, get(AArch64::ANDSXri), AArch64::XZR)
668 BuildMI(MBB, I, DL, get(Opc), DstReg)
1199 const MCInstrDesc &MCID = get(NewOpc);
1459 MI->setDesc(get(NewOpc));
1490 BuildMI(MBB, FirstEpilogSEH, DL, TII->get(AArch64::ADRP))
1493 BuildMI(MBB, FirstEpilogSEH, DL, TII->get(AArch64::ADDXri))
1509 BuildMI(MBB, MI, DL, get(AArch64::LOADgot), Reg)
1513 BuildMI(MBB, MI, DL, get(AArch64::LDRWui))
1520 BuildMI(MBB, MI, DL, get(AArch64::LDRXui), Reg)
1527 BuildMI(MBB, MI, DL, get(AArch64::MOVZXi), Reg)
1530 BuildMI(MBB, MI, DL, get(AArch64::MOVKXi), Reg)
1534 BuildMI(MBB, MI, DL, get(AArch64::MOVKXi), Reg)
1538 BuildMI(MBB, MI, DL, get(AArch64::MOVKXi), Reg)
1542 BuildMI(MBB, MI, DL, get(AArch64::LDRXui), Reg)
1547 BuildMI(MBB, MI, DL, get(AArch64::ADR), Reg)
1550 BuildMI(MBB, MI, DL, get(AArch64::ADRP), Reg)
1555 BuildMI(MBB, MI, DL, get(AArch64::LDRWui))
1562 BuildMI(MBB, MI, DL, get(AArch64::LDRXui), Reg)
2430 const MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opcode));
2454 const MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opcode));
2482 BuildMI(MBB, I, DL, get(AArch64::ADDXri), DestRegX)
2488 BuildMI(MBB, I, DL, get(AArch64::ADDWri), DestReg)
2494 BuildMI(MBB, I, DL, get(AArch64::MOVZWi), DestReg)
2508 BuildMI(MBB, I, DL, get(AArch64::ORRXrr), DestRegX)
2514 BuildMI(MBB, I, DL, get(AArch64::ORRWrr), DestReg)
2526 BuildMI(MBB, I, DL, get(AArch64::ORR_PPzPP), DestReg)
2537 BuildMI(MBB, I, DL, get(AArch64::ORR_ZZZ), DestReg)
2547 BuildMI(MBB, I, DL, get(AArch64::ADDXri), DestReg)
2552 BuildMI(MBB, I, DL, get(AArch64::MOVZXi), DestReg)
2557 BuildMI(MBB, I, DL, get(AArch64::ORRXrr), DestReg)
2641 BuildMI(MBB, I, DL, get(AArch64::ORRv16i8), DestReg)
2645 BuildMI(MBB, I, DL, get(AArch64::STRQpre))
2650 BuildMI(MBB, I, DL, get(AArch64::LDRQpre))
2666 BuildMI(MBB, I, DL, get(AArch64::ORRv16i8), DestReg)
2670 BuildMI(MBB, I, DL, get(AArch64::FMOVDr), DestReg)
2683 BuildMI(MBB, I, DL, get(AArch64::ORRv16i8), DestReg)
2687 BuildMI(MBB, I, DL, get(AArch64::FMOVSr), DestReg)
2700 BuildMI(MBB, I, DL, get(AArch64::ORRv16i8), DestReg)
2708 BuildMI(MBB, I, DL, get(AArch64::FMOVSr), DestReg)
2721 BuildMI(MBB, I, DL, get(AArch64::ORRv16i8), DestReg)
2729 BuildMI(MBB, I, DL, get(AArch64::FMOVSr), DestReg)
2738 BuildMI(MBB, I, DL, get(AArch64::FMOVXDr), DestReg)
2744 BuildMI(MBB, I, DL, get(AArch64::FMOVDXr), DestReg)
2751 BuildMI(MBB, I, DL, get(AArch64::FMOVWSr), DestReg)
2757 BuildMI(MBB, I, DL, get(AArch64::FMOVSWr), DestReg)
2764 BuildMI(MBB, I, DL, get(AArch64::MSR))
2773 BuildMI(MBB, I, DL, get(AArch64::MRS), DestReg)
2848 get(AArch64::STPWi), SrcReg, isKill,
2862 get(AArch64::STPXi), SrcReg, isKill,
2902 const MachineInstrBuilder MI = BuildMI(MBB, MBBI, DebugLoc(), get(Opc))
2979 get(AArch64::LDPWi), DestReg, AArch64::sube32,
2993 get(AArch64::LDPXi), DestReg, AArch64::sube64,
3033 const MachineInstrBuilder MI = BuildMI(MBB, MBBI, DebugLoc(), get(Opc))
3096 auto MBI = BuildMI(MBB, MBBI, DL, TII->get(Opc), DestReg)
3112 BuildMI(MBB, MBBI, DL, TII->get(AArch64::SEH_SetFP)).setMIFlag(Flag);
3114 BuildMI(MBB, MBBI, DL, TII->get(AArch64::SEH_AddFP))
3123 BuildMI(MBB, MBBI, DL, TII->get(AArch64::SEH_StackAlloc))
3484 MI.setDesc(TII->get(UnscaledOp));
4021 MIB = BuildMI(MF, Root.getDebugLoc(), TII->get(MaddOpc), ResultReg)
4026 MIB = BuildMI(MF, Root.getDebugLoc(), TII->get(MaddOpc), ResultReg)
4032 MIB = BuildMI(MF, Root.getDebugLoc(), TII->get(MaddOpc), ResultReg)
4086 BuildMI(MF, Root.getDebugLoc(), TII->get(MaddOpc), ResultReg)
4182 BuildMI(MF, Root.getDebugLoc(), TII->get(OrrOpc), NewVR)
4216 BuildMI(MF, Root.getDebugLoc(), TII->get(SubOpc), NewVR)
4273 BuildMI(MF, Root.getDebugLoc(), TII->get(OrrOpc), NewVR)
4540 BuildMI(MF, Root.getDebugLoc(), TII->get(AArch64::FNEGv4f16), NewVR)
4587 BuildMI(MF, Root.getDebugLoc(), TII->get(AArch64::FNEGv8f16), NewVR)
4647 BuildMI(MF, Root.getDebugLoc(), TII->get(AArch64::FNEGv2f32), NewVR)
4667 BuildMI(MF, Root.getDebugLoc(), TII->get(AArch64::FNEGv4f32), NewVR)
4687 BuildMI(MF, Root.getDebugLoc(), TII->get(AArch64::FNEGv2f64), NewVR)
4835 MachineInstr *NewMI = BuildMI(RefToMBB, MI, DL, get(Opc))
4875 BuildMI(RefToMBB, MI, DL, get(AArch64::Bcc)).addImm(CC).addMBB(TBB);
5545 MachineInstr *TC = BuildMI(MF, DebugLoc(), get(TailOpcode))
5574 MachineInstr *STRXpre = BuildMI(MF, DebugLoc(), get(AArch64::STRXpre))
5588 BuildMI(MBB, It, DebugLoc(), get(AArch64::CFI_INSTRUCTION))
5596 BuildMI(MBB, It, DebugLoc(), get(AArch64::CFI_INSTRUCTION))
5601 MachineInstr *LDRXpost = BuildMI(MF, DebugLoc(), get(AArch64::LDRXpost))
5615 MachineInstr *ret = BuildMI(MF, DebugLoc(), get(AArch64::RET))
5635 It = MBB.insert(It, BuildMI(MF, DebugLoc(), get(AArch64::TCRETURNdi))
5645 It = MBB.insert(It, BuildMI(MF, DebugLoc(), get(AArch64::BL))
5665 Save = BuildMI(MF, DebugLoc(), get(AArch64::ORRXrs), Reg)
5669 Restore = BuildMI(MF, DebugLoc(), get(AArch64::ORRXrs), AArch64::LR)
5675 Save = BuildMI(MF, DebugLoc(), get(AArch64::STRXpre))
5680 Restore = BuildMI(MF, DebugLoc(), get(AArch64::LDRXpost))
5691 It = MBB.insert(It, BuildMI(MF, DebugLoc(), get(AArch64::BL))
lib/Target/AArch64/AArch64InstructionSelector.cpp 726 TII.get(AArch64::SUBREG_TO_REG), PromoteReg)
751 I.setDesc(TII.get(AArch64::COPY));
1000 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(CBOpc))
1096 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(AArch64::ADDXri))
1104 MIB = BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(AArch64::STRXui))
1308 I.setDesc(TII.get(TargetOpcode::COPY));
1354 I.setDesc(TII.get(TargetOpcode::PHI));
1416 auto MIB = BuildMI(MBB, I, I.getDebugLoc(), TII.get(AArch64::TBNZW))
1424 auto CMP = BuildMI(MBB, I, I.getDebugLoc(), TII.get(AArch64::ANDSWri))
1430 BuildMI(MBB, I, I.getDebugLoc(), TII.get(AArch64::Bcc))
1440 I.setDesc(TII.get(AArch64::BR));
1480 I.setDesc(TII.get(Opc));
1575 I.setDesc(TII.get(MovOpc));
1618 I.setDesc(TII.get(SrcSize == 64 ? AArch64::UBFMXri : AArch64::UBFMWri));
1648 I.setDesc(TII.get(DstSize == 64 ? AArch64::BFMXri : AArch64::BFMWri));
1662 TII.get(AArch64::SUBREG_TO_REG))
1680 I.setDesc(TII.get(AArch64::ADDXri));
1696 I.setDesc(TII.get(AArch64::LOADgot));
1704 I.setDesc(TII.get(AArch64::ADR));
1707 I.setDesc(TII.get(AArch64::MOVaddr));
1736 I.setDesc(TII.get(AArch64::LDARB));
1762 I.setDesc(TII.get(NewOpc));
1843 I.setDesc(TII.get(NewOpc));
1878 I.setDesc(TII.get(NewOpc));
1936 I.setDesc(TII.get(AArch64::ANDXri));
1990 I.setDesc(TII.get(TargetOpcode::COPY));
1994 I.setDesc(TII.get(AArch64::XTNv4i16));
2047 BuildMI(MBB, I, I.getDebugLoc(), TII.get(AArch64::SUBREG_TO_REG))
2137 I.setDesc(TII.get(NewOpc));
2173 *BuildMI(MBB, I, I.getDebugLoc(), TII.get(AArch64::ANDSWri))
2178 MachineInstr &CSelMI = *BuildMI(MBB, I, I.getDebugLoc(), TII.get(CSelOpc))
2229 auto CmpMI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(CmpOpc))
2244 *BuildMI(MBB, I, I.getDebugLoc(), TII.get(AArch64::CSINCWr))
2253 *BuildMI(MBB, I, I.getDebugLoc(), TII.get(AArch64::CSINCWr))
2259 *BuildMI(MBB, I, I.getDebugLoc(), TII.get(AArch64::ORRWrr))
2280 I.setDesc(TII.get(TargetOpcode::IMPLICIT_DEF));
2295 I.setDesc(TII.get(AArch64::MOVaddrBA));
2296 auto MovMI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(AArch64::MOVaddrBA),
2451 I.setDesc(TII.get(Opc));
2506 I.setDesc(TII.get(Opc));
2752 TII.get(TargetOpcode::SUBREG_TO_REG))
2760 TII.get(TargetOpcode::SUBREG_TO_REG))
2766 *BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(AArch64::BFMXri))
2993 *BuildMI(MBB, I, I.getDebugLoc(), TII.get(TargetOpcode::IMPLICIT_DEF),
3000 TII.get(TargetOpcode::INSERT_SUBREG), InsertReg)
3027 *BuildMI(MBB, I, I.getDebugLoc(), TII.get(CopyOpc), CopyTo)
3359 I.setDesc(TII.get(MovOpc));
lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp 764 MIB = BuildMI(*MBB, InsertionPoint, DL, TII->get(getMatchingWideOpcode(Opc)))
880 MIB = BuildMI(*MBB, InsertionPoint, DL, TII->get(getMatchingPairOpcode(Opc)))
916 BuildMI(*MBB, InsertionPoint, DL, TII->get(TargetOpcode::KILL), DstRegW)
922 BuildMI(*MBB, InsertionPoint, DL, TII->get(AArch64::SBFMXri), DstRegX)
979 TII->get(IsStoreXReg ? AArch64::ORRXrs : AArch64::ORRWrs), LdRt)
1019 TII->get(IsStoreXReg ? AArch64::ANDXri : AArch64::ANDWri),
1027 TII->get(IsStoreXReg ? AArch64::UBFMXri : AArch64::UBFMWri),
1399 MIB = BuildMI(*I->getParent(), I, I->getDebugLoc(), TII->get(NewOpc))
1408 MIB = BuildMI(*I->getParent(), I, I->getDebugLoc(), TII->get(NewOpc))
lib/Target/AArch64/AArch64RegisterInfo.cpp 416 const MCInstrDesc &MCID = TII->get(AArch64::ADDXri);
506 BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(AArch64::LDG), ScratchReg)
lib/Target/AArch64/AArch64SIMDInstrOpt.cpp 282 OriginalMCID = &TII->get(AArch64::FMLAv4i32_indexed);
283 ReplInstrMCID.push_back(&TII->get(AArch64::DUPv4i32lane));
284 ReplInstrMCID.push_back(&TII->get(AArch64::FMLAv4f32));
296 OriginalMCID = &TII->get(I.OrigOpc);
298 ReplInstrMCID.push_back(&TII->get(Repl));
360 DupMCID = &TII->get(AArch64::DUPv4i32lane);
361 MulMCID = &TII->get(AArch64::FMLAv4f32);
364 DupMCID = &TII->get(AArch64::DUPv4i32lane);
365 MulMCID = &TII->get(AArch64::FMLSv4f32);
368 DupMCID = &TII->get(AArch64::DUPv4i32lane);
369 MulMCID = &TII->get(AArch64::FMULXv4f32);
372 DupMCID = &TII->get(AArch64::DUPv4i32lane);
373 MulMCID = &TII->get(AArch64::FMULv4f32);
378 DupMCID = &TII->get(AArch64::DUPv2i64lane);
379 MulMCID = &TII->get(AArch64::FMLAv2f64);
382 DupMCID = &TII->get(AArch64::DUPv2i64lane);
383 MulMCID = &TII->get(AArch64::FMLSv2f64);
386 DupMCID = &TII->get(AArch64::DUPv2i64lane);
387 MulMCID = &TII->get(AArch64::FMULXv2f64);
390 DupMCID = &TII->get(AArch64::DUPv2i64lane);
391 MulMCID = &TII->get(AArch64::FMULv2f64);
397 DupMCID = &TII->get(AArch64::DUPv2i32lane);
398 MulMCID = &TII->get(AArch64::FMLAv2f32);
402 DupMCID = &TII->get(AArch64::DUPv2i32lane);
403 MulMCID = &TII->get(AArch64::FMLSv2f32);
407 DupMCID = &TII->get(AArch64::DUPv2i32lane);
408 MulMCID = &TII->get(AArch64::FMULXv2f32);
412 DupMCID = &TII->get(AArch64::DUPv2i32lane);
413 MulMCID = &TII->get(AArch64::FMULv2f32);
420 if (!shouldReplaceInst(MI.getParent()->getParent(), &TII->get(MI.getOpcode()),
525 ReplInstrMCID.push_back(&TII->get(Repl));
540 if (!shouldReplaceInst(MI.getParent()->getParent(), &TII->get(MI.getOpcode()),
lib/Target/AArch64/AArch64SpeculationHardening.cpp 221 BuildMI(MBB, MBBI, DL, TII->get(AArch64::DSB)).addImm(0xf);
222 BuildMI(MBB, MBBI, DL, TII->get(AArch64::ISB)).addImm(0xf);
231 BuildMI(SplitEdgeBB, SplitEdgeBB.begin(), DL, TII->get(AArch64::CSELXr))
369 BuildMI(MBB, MBBI, DebugLoc(), TII->get(AArch64::SUBSXri))
375 BuildMI(MBB, MBBI, DebugLoc(), TII->get(AArch64::CSINVXr))
392 BuildMI(MBB, MBBI, DebugLoc(), TII->get(AArch64::ADDXri))
398 BuildMI(MBB, MBBI, DebugLoc(), TII->get(AArch64::ANDXrs))
404 BuildMI(MBB, MBBI, DebugLoc(), TII->get(AArch64::ADDXri))
451 TII->get(Is64Bit ? AArch64::SpeculationSafeValueX
576 Is64Bit ? TII->get(AArch64::ANDXrs) : TII->get(AArch64::ANDWrs))
576 Is64Bit ? TII->get(AArch64::ANDXrs) : TII->get(AArch64::ANDWrs))
596 BuildMI(MBB, MBBI, DL, TII->get(AArch64::HINT)).addImm(0x14);
lib/Target/AArch64/AArch64StorePairSuppress.cpp 85 unsigned SCIdx = TII->get(AArch64::STPDi).getSchedClass();
lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp 3891 const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp 317 const auto &Desc = Info->get(Inst.getOpcode());
lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp 566 Subtarget->getInstrInfo()->get(N->getMachineOpcode());
2658 MCInstrDesc Desc = SII->get(Opc);
lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp 115 I.setDesc(TII.get(TargetOpcode::COPY));
136 BuildMI(*BB, &I, DL, TII.get(AMDGPU::V_CMP_NE_U32_e64), DstReg)
210 I.setDesc(TII.get(TargetOpcode::PHI));
226 BuildMI(*BB, MI, MI->getDebugLoc(), TII.get(AMDGPU::COPY), DstReg)
274 I.setDesc(TII.get(InstOpc));
292 I.setDesc(TII.get(InstOpc));
313 BuildMI(*BB, &I, DL, TII.get(Opc), DstReg)
322 I.setDesc(TII.get(Opc));
332 = BuildMI(*BB, &I, DL, TII.get(Opc), DstReg)
357 BuildMI(*BB, &I, DL, TII.get(AMDGPU::S_ADD_U32), DstLo)
360 BuildMI(*BB, &I, DL, TII.get(AMDGPU::S_ADDC_U32), DstHi)
366 BuildMI(*BB, &I, DL, TII.get(AMDGPU::V_ADD_I32_e64), DstLo)
371 MachineInstr *Addc = BuildMI(*BB, &I, DL, TII.get(AMDGPU::V_ADDC_U32_e64), DstHi)
382 BuildMI(*BB, &I, DL, TII.get(AMDGPU::REG_SEQUENCE), DstReg)
410 I.setDesc(TII.get(NewOpc));
419 BuildMI(*BB, &I, DL, TII.get(NewOpc), Dst0Reg)
422 BuildMI(*BB, &I, DL, TII.get(AMDGPU::COPY), Dst1Reg)
445 MachineInstr *Copy = BuildMI(*BB, &I, DL, TII.get(TargetOpcode::COPY),
480 BuildMI(*BB, &MI, DL, TII.get(TargetOpcode::REG_SEQUENCE), DstReg);
528 BuildMI(*BB, &MI, DL, TII.get(TargetOpcode::COPY), Dst.getReg())
553 I.setDesc(TII.get(TargetOpcode::IMPLICIT_DEF));
604 BuildMI(*BB, &I, DL, TII.get(TargetOpcode::INSERT_SUBREG), DstReg)
621 BuildMI(*BB, &I, I.getDebugLoc(), TII.get(AMDGPU::SI_IF_BREAK))
730 MachineInstr *ICmp = BuildMI(*BB, &I, DL, TII.get(Opcode))
733 BuildMI(*BB, &I, DL, TII.get(AMDGPU::COPY), CCReg)
746 MachineInstr *ICmp = BuildMI(*BB, &I, DL, TII.get(Opcode),
764 return BuildMI(BB, Insert, DL, TII.get(Opcode))
1062 BuildMI(*BB, &I, DL, TII.get(AMDGPU::IMPLICIT_DEF), Undef);
1073 TII.get(AMDGPU::SI_END_CF))
1104 MachineInstr *CopySCC = BuildMI(*BB, &I, DL, TII.get(AMDGPU::COPY), AMDGPU::SCC)
1112 MachineInstr *Select = BuildMI(*BB, &I, DL, TII.get(SelectOpcode), DstReg)
1127 BuildMI(*BB, &I, DL, TII.get(AMDGPU::V_CNDMASK_B32_e64), DstReg)
1206 I.setDesc(TII.get(TargetOpcode::COPY));
1246 BuildMI(MBB, I, DL, TII.get(AMDGPU::COPY), TmpReg)
1248 BuildMI(MBB, I, DL, TII.get(AMDGPU::COPY), AMDGPU::SCC)
1252 BuildMI(MBB, I, DL, TII.get(Opcode), DstReg)
1264 BuildMI(MBB, I, DL, TII.get(AMDGPU::V_CNDMASK_B32_e64), DstReg)
1284 BuildMI(MBB, I, DL, TII.get(AMDGPU::V_AND_B32_e32), DstReg)
1293 BuildMI(MBB, I, DL, TII.get(BFE), DstReg)
1308 BuildMI(MBB, I, DL, TII.get(SextOpc), DstReg)
1322 BuildMI(MBB, I, DL, TII.get(AMDGPU::IMPLICIT_DEF), UndefReg);
1323 BuildMI(MBB, I, DL, TII.get(AMDGPU::REG_SEQUENCE), ExtReg)
1329 BuildMI(MBB, I, DL, TII.get(BFE64), DstReg)
1339 BuildMI(MBB, I, DL, TII.get(AMDGPU::S_AND_B32), DstReg)
1343 BuildMI(MBB, I, DL, TII.get(BFE32), DstReg)
1382 BuildMI(*MBB, I, DL, TII.get(AMDGPU::COPY), AMDGPU::SCC)
1387 auto MIB = BuildMI(*MBB, I, DL, TII.get(NewOpc), DstReg)
1428 I.setDesc(TII.get(Opcode));
1439 ResInst = BuildMI(*BB, &I, DL, TII.get(AMDGPU::S_MOV_B64), DstReg)
1447 BuildMI(*BB, &I, DL, TII.get(Opcode), LoReg)
1450 BuildMI(*BB, &I, DL, TII.get(Opcode), HiReg)
1453 ResInst = BuildMI(*BB, &I, DL, TII.get(AMDGPU::REG_SEQUENCE), DstReg)
1546 BuildMI(*BB, &I, I.getDebugLoc(), TII.get(AMDGPU::S_MOV_B32), AMDGPU::M0)
1591 BuildMI(*BB, &I, DL, TII.get(AMDGPU::COPY), CondPhysReg)
1593 BuildMI(*BB, &I, DL, TII.get(BrOpcode))
1604 I.setDesc(TII.get(IsVGPR ? AMDGPU::V_MOV_B32_e32 : AMDGPU::S_MOV_B32));
1641 BuildMI(*BB, &I, DL, TII.get(MovOpc), ImmReg)
1645 BuildMI(*BB, &I, DL, TII.get(NewOpc), DstReg)
1656 BuildMI(*BB, &I, DL, TII.get(AMDGPU::COPY), LoReg)
1658 BuildMI(*BB, &I, DL, TII.get(AMDGPU::COPY), HiReg)
1661 BuildMI(*BB, &I, DL, TII.get(NewOpc), MaskLo)
1664 BuildMI(*BB, &I, DL, TII.get(AMDGPU::REG_SEQUENCE), DstReg)
1761 I.setDesc(TII.get(AMDGPU::ATOMIC_FENCE));
1941 BuildMI(*MBB, MI, MI->getDebugLoc(), TII.get(AMDGPU::S_MOV_B32), OffsetReg)
2013 BuildMI(*MBB, MI, MI->getDebugLoc(), TII.get(AMDGPU::V_MOV_B32_e32),
lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp 1235 MI.setDesc(B.getTII().get(TargetOpcode::G_BITCAST));
lib/Target/AMDGPU/AMDGPUMCInstLower.cpp 113 ST.getInstrInfo()->get(AMDGPU::S_GETPC_B64).Size == 4);
lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp 1485 BuildMI(*MBB, PHI, PHI.getDebugLoc(), TII->get(TargetOpcode::PHI),
1530 BuildMI(*MBB, PHI, PHI.getDebugLoc(), TII->get(TargetOpcode::PHI),
1579 BuildMI(*MBB, PHI, PHI.getDebugLoc(), TII->get(TargetOpcode::PHI),
1770 TII->get(TargetOpcode::PHI), DestRegister);
2161 TII->get(TargetOpcode::PHI), DestReg);
2180 TII->get(TargetOpcode::PHI), NewBackedgeReg);
2455 TII->get(TargetOpcode::PHI), NewDestReg);
lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp 782 BuildMI(*LoopBB, I, DL, TII->get(AMDGPU::V_READFIRSTLANE_B32),
844 BuildMI(*LoopBB, I, DL, TII->get(AMDGPU::V_READFIRSTLANE_B32),
849 BuildMI(*LoopBB, I, DL, TII->get(AMDGPU::V_READFIRSTLANE_B32),
875 BuildMI(*LoopBB, I, DL, TII->get(AMDGPU::V_READFIRSTLANE_B32),
942 BuildMI(MBB, MBB.end(), DL, TII->get(MovTermOpc), SaveExecReg)
lib/Target/AMDGPU/AMDILCFGStructurizer.cpp 458 MBB->getParent()->CreateMachineInstr(TII->get(NewOpcode), DL);
468 MBB->getParent()->CreateMachineInstr(TII->get(NewOpcode), DL);
482 MBB->getParent()->CreateMachineInstr(TII->get(NewOpcode), DebugLoc());
494 MachineInstr *NewMI = MF->CreateMachineInstr(TII->get(NewOpcode), DL);
506 MachineInstr *NewInstr = MF->CreateMachineInstr(TII->get(NewOpcode), DL);
lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp 1688 if (AMDGPU::isSISrcOperand(AsmParser->getMII()->get(Inst.getOpcode()),
1700 const auto& InstDesc = AsmParser->getMII()->get(Inst.getOpcode());
2659 uint64_t TSFlags = MII.get(Inst.getOpcode()).TSFlags;
2718 const MCInstrDesc &Desc = MII.get(Inst.getOpcode());
2742 const MCInstrDesc &Desc = MII.get(Inst.getOpcode());
2812 const MCInstrDesc &Desc = MII.get(Opcode);
2891 const MCInstrDesc &Desc = MII.get(Opcode);
2929 const MCInstrDesc &Desc = MII.get(Opc);
2943 const MCInstrDesc &Desc = MII.get(Opc);
2975 const MCInstrDesc &Desc = MII.get(Opc);
3016 const MCInstrDesc &Desc = MII.get(Opc);
3036 const MCInstrDesc &Desc = MII.get(Opc);
3055 const MCInstrDesc &Desc = MII.get(Opc);
3071 const MCInstrDesc &Desc = MII.get(Opc);
3220 const MCInstrDesc &Desc = MII.get(Opcode);
3264 uint64_t TSFlags = MII.get(Inst.getOpcode()).TSFlags;
3304 const MCInstrDesc &Desc = MII.get(Opcode);
3361 const MCInstrDesc &Desc = MII.get(Opcode);
5913 const MCInstrDesc &Desc = MII.get(Inst.getOpcode());
6200 const MCInstrDesc &Desc = MII.get(Inst.getOpcode());
6238 const MCInstrDesc &Desc = MII.get(Inst.getOpcode());
6305 const MCInstrDesc &Desc = MII.get(Opc);
6682 const MCInstrDesc &Desc = MII.get(Inst.getOpcode());
6841 const MCInstrDesc &Desc = MII.get(Inst.getOpcode());
lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp 365 !(MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOP3))) {
383 if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::MIMG)) {
412 int Tied = MCII->get(MI.getOpcode()).getOperandConstraint(VDstIn_Idx,
454 unsigned DescNumOps = MCII->get(Opc).getNumOperands();
496 bool IsGather4 = MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::Gather4;
551 auto DataRCID = MCII->get(NewOpcode).OpInfo[VDataIdx].RegClass;
574 auto AddrRCID = MCII->get(NewOpcode).OpInfo[VAddr0Idx].RegClass;
lib/Target/AMDGPU/GCNDPPCombine.cpp 168 OrigMI.getDebugLoc(), TII->get(DPPOp));
438 TII->get(AMDGPU::IMPLICIT_DEF), CombOldVGPR.Reg);
lib/Target/AMDGPU/GCNHazardRecognizer.cpp 201 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), TII.get(AMDGPU::S_NOP))
897 TII->get(AMDGPU::V_MOV_B32_e32))
941 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), TII->get(AMDGPU::V_NOP_e32));
1028 TII->get(AMDGPU::S_MOV_B32), AMDGPU::SGPR_NULL)
1069 TII->get(AMDGPU::S_WAITCNT_DEPCTR))
1129 TII->get(AMDGPU::S_WAITCNT_VSCNT))
lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp 127 const MCInstrDesc &Desc = MII.get(MI->getOpcode());
305 if (MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::VOP3)
307 else if (MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::DPP)
309 else if (MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::SDWA)
505 const MCInstrDesc &Desc = MII.get(MI->getOpcode());
577 const MCInstrDesc &Desc = MII.get(MI->getOpcode());
974 MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::VOP3_OPSEL;
977 MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::IsPacked;
lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp 118 Info->get(Inst.getOpcode()).OpInfo[0].OperandType !=
lib/Target/AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp 105 const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
176 if (HAS_NATIVE_OPERANDS(MCII.get(MI.getOpcode()).TSFlags))
lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp 286 const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
381 const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
475 const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
490 const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
lib/Target/AMDGPU/R600ClauseMergePass.cpp 178 RootCFAlu.setDesc(TII->get(LatrCFAlu.getOpcode()));
lib/Target/AMDGPU/R600ControlFlowFinalizer.cpp 293 return TII->get(Opcode);
402 TII->get(R600::LITERALS))
444 TII->get(R600::LITERALS));
473 BuildMI(BB, DL, TII->get(R600::FETCH_CLAUSE)).addImm(CfCount);
485 BuildMI(BB, DL, TII->get(R600::ALU_CLAUSE)).addImm(CfCount);
554 BuildMI(MBB, MI, MBB.findDebugLoc(MI), TII->get(R600::CF_PUSH_EG))
557 MI->setDesc(TII->get(R600::CF_ALU));
665 BuildMI(MBB, I, DL, TII->get(R600::PAD));
686 TII->get(R600::CF_ALU_POP_AFTER))
lib/Target/AMDGPU/R600EmitClauseMarkers.cpp 292 BuildMI(MBB, ClauseHead, MBB.findDebugLoc(ClauseHead), TII->get(Opcode))
lib/Target/AMDGPU/R600ISelLowering.cpp 312 TII->get(R600::getLDSNoRetOp(MI.getOpcode())));
379 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(MI.getOpcode()))
386 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(MI.getOpcode()))
394 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(R600::JUMP))
400 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(R600::PRED_X),
406 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(R600::JUMP_COND))
414 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(R600::PRED_X),
420 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(R600::JUMP_COND))
448 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(MI.getOpcode()))
lib/Target/AMDGPU/R600InstrInfo.cpp 58 return get(MI.getOpcode()).TSFlags & R600_InstFlag::VECTOR;
134 unsigned TargetFlags = get(Opcode).TSFlags;
140 unsigned TargetFlags = get(Opcode).TSFlags;
148 unsigned TargetFlags = get(Opcode).TSFlags;
180 return (get(Opcode).getSchedClass() == R600::Sched::TransALU);
188 return (get(Opcode).getSchedClass() == R600::Sched::VecALU);
196 return (get(Opcode).TSFlags & R600_InstFlag::IS_EXPORT);
200 return ST.hasVertexCache() && IS_VTX(get(Opcode));
210 return (!ST.hasVertexCache() && IS_VTX(get(Opcode))) || IS_TEX(get(Opcode));
210 return (!ST.hasVertexCache() && IS_VTX(get(Opcode))) || IS_TEX(get(Opcode));
767 BuildMI(&MBB, DL, get(R600::JUMP)).addMBB(TBB);
775 BuildMI(&MBB, DL, get(R600::JUMP_COND))
782 CfAlu->setDesc(get(R600::CF_ALU_PUSH_BEFORE));
790 BuildMI(&MBB, DL, get(R600::JUMP_COND))
793 BuildMI(&MBB, DL, get(R600::JUMP)).addMBB(FBB);
798 CfAlu->setDesc(get(R600::CF_ALU_PUSH_BEFORE));
827 CfAlu->setDesc(get(R600::CF_ALU));
852 CfAlu->setDesc(get(R600::CF_ALU));
1243 MachineInstrBuilder MIB = BuildMI(MBB, I, MBB.findDebugLoc(I), get(Opcode),
1402 unsigned TargetFlags = get(MI.getOpcode()).TSFlags;
1467 unsigned TargetFlags = get(MI.getOpcode()).TSFlags;
1488 unsigned TargetFlags = get(MI.getOpcode()).TSFlags;
lib/Target/AMDGPU/R600InstrInfo.h 318 return get(MI.getOpcode()).TSFlags & R600InstrFlags::REGISTER_STORE;
322 return get(MI.getOpcode()).TSFlags & R600InstrFlags::REGISTER_LOAD;
lib/Target/AMDGPU/R600OptimizeVectorRegisters.cpp 153 if (TII->get(MI.getOpcode()).TSFlags & R600_InstFlag::TEX_INST)
215 MachineInstr *Tmp = BuildMI(MBB, Pos, DL, TII->get(R600::INSERT_SUBREG),
231 BuildMI(MBB, Pos, DL, TII->get(R600::COPY), Reg).addReg(SrcVec);
267 if (TII->get(MI.getOpcode()).TSFlags & R600_InstFlag::TEX_INST)
352 if (TII->get(MI.getOpcode()).TSFlags & R600_InstFlag::TEX_INST) {
lib/Target/AMDGPU/SIAddIMGInit.cpp 144 BuildMI(MBB, MI, DL, TII->get(AMDGPU::V_MOV_B32_e32), PrevDst)
148 BuildMI(MBB, MI, DL, TII->get(AMDGPU::IMPLICIT_DEF), PrevDst);
155 BuildMI(MBB, MI, DL, TII->get(AMDGPU::V_MOV_B32_e32), SubReg)
158 BuildMI(MBB, I, DL, TII->get(TargetOpcode::INSERT_SUBREG), NewDst)
lib/Target/AMDGPU/SIFixSGPRCopies.cpp 300 BuildMI(*MI.getParent(), &MI, MI.getDebugLoc(), TII->get(AMDGPU::COPY),
309 BuildMI(*MI.getParent(), &MI, MI.getDebugLoc(), TII->get(Opc),
626 TII->get(AMDGPU::V_READFIRSTLANE_B32), TmpReg)
649 MI.setDesc(TII->get(SMovOp));
741 TII->get(AMDGPU::COPY), AMDGPU::M0)
lib/Target/AMDGPU/SIFixupVectorISel.cpp 186 NewGlob = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcd));
lib/Target/AMDGPU/SIFoldOperands.cpp 160 const MCInstrDesc &MadDesc = TII->get(Opc);
217 switch (TII.get(Opcode).OpInfo[OpNo].OperandType) {
263 BuildMI(*MBB, MI, MI->getDebugLoc(), TII.get(AMDGPU::COPY), Dst1.getReg())
276 MI->setDesc(TII.get(AMDGPU::IMPLICIT_DEF));
349 MI->setDesc(TII->get(NewOpc));
355 MI->setDesc(TII->get(Opc));
360 MI->setDesc(TII->get(AMDGPU::S_SETREG_IMM32_B32));
646 UseMI->setDesc(TII->get(AMDGPU::V_ACCVGPR_WRITE_B32));
659 UseMI->setDesc(TII->get(MovOp));
693 UseMI->setDesc(TII->get(AMDGPU::REG_SEQUENCE));
709 TII->get(AMDGPU::V_ACCVGPR_WRITE_B32), Tmp).addImm(Imm);
735 BuildMI(MBB, UseMI, DL, TII->get(AMDGPU::COPY), Tmp).add(*Def);
746 BuildMI(MBB, UseMI, DL, TII->get(AMDGPU::COPY), Vgpr).add(*Def);
751 TII->get(AMDGPU::V_ACCVGPR_WRITE_B32), Tmp).addReg(Vgpr);
765 UseMI->setDesc(TII->get(AMDGPU::V_ACCVGPR_WRITE_B32));
768 UseMI->setDesc(TII->get(AMDGPU::V_ACCVGPR_READ_B32));
788 UseMI->setDesc(TII->get(AMDGPU::S_MOV_B32));
811 UseMI->setDesc(TII->get(AMDGPU::COPY));
973 mutateCopyOp(*MI, TII->get(getMovOpc(Opc == AMDGPU::S_NOT_B32)));
996 MI->setDesc(TII->get(UseCopy ? AMDGPU::COPY : AMDGPU::V_MOV_B32_e32));
1016 mutateCopyOp(*MI, TII->get(getMovOpc(IsSGPR)));
1035 mutateCopyOp(*MI, TII->get(AMDGPU::COPY));
1039 mutateCopyOp(*MI, TII->get(getMovOpc(Opc == AMDGPU::S_OR_B32)));
1052 mutateCopyOp(*MI, TII->get(getMovOpc(Opc == AMDGPU::S_AND_B32)));
1056 mutateCopyOp(*MI, TII->get(AMDGPU::COPY));
1070 mutateCopyOp(*MI, TII->get(AMDGPU::COPY));
1095 TII->get(Src0->isReg() ? (unsigned)AMDGPU::COPY : getMovOpc(false));
lib/Target/AMDGPU/SIFormMemoryClauses.cpp 362 auto B = BuildMI(MBB, I, DebugLoc(), TII->get(TargetOpcode::BUNDLE));
lib/Target/AMDGPU/SIFrameLowering.cpp 106 BuildMI(MBB, I, DebugLoc(), TII->get(AMDGPU::BUFFER_STORE_DWORD_OFFSET))
123 BuildMI(MBB, I, DebugLoc(), TII->get(AMDGPU::V_MOV_B32_e32), OffsetReg)
126 BuildMI(MBB, I, DebugLoc(), TII->get(AMDGPU::BUFFER_STORE_DWORD_OFFEN))
154 TII->get(AMDGPU::BUFFER_LOAD_DWORD_OFFSET), SpillReg)
170 BuildMI(MBB, I, DebugLoc(), TII->get(AMDGPU::V_MOV_B32_e32), OffsetReg)
174 TII->get(AMDGPU::BUFFER_LOAD_DWORD_OFFEN), SpillReg)
224 BuildMI(MBB, I, DL, TII->get(AMDGPU::S_ADD_U32), FlatScrInitLo)
227 BuildMI(MBB, I, DL, TII->get(AMDGPU::S_ADDC_U32), FlatScrInitHi)
230 BuildMI(MBB, I, DL, TII->get(AMDGPU::S_SETREG_B32)).
234 BuildMI(MBB, I, DL, TII->get(AMDGPU::S_SETREG_B32)).
241 BuildMI(MBB, I, DL, TII->get(AMDGPU::S_ADD_U32), AMDGPU::FLAT_SCR_LO)
244 BuildMI(MBB, I, DL, TII->get(AMDGPU::S_ADDC_U32), AMDGPU::FLAT_SCR_HI)
254 BuildMI(MBB, I, DL, TII->get(AMDGPU::COPY), AMDGPU::FLAT_SCR_LO)
259 BuildMI(MBB, I, DL, TII->get(AMDGPU::S_ADD_U32), FlatScrInitLo)
264 BuildMI(MBB, I, DL, TII->get(AMDGPU::S_LSHR_B32), AMDGPU::FLAT_SCR_HI)
489 BuildMI(MBB, I, DL, TII->get(AMDGPU::COPY), ScratchRsrcReg)
501 BuildMI(MBB, I, DL, TII->get(AMDGPU::COPY), ScratchWaveOffsetReg)
506 BuildMI(MBB, I, DL, TII->get(AMDGPU::COPY), ScratchRsrcReg)
522 BuildMI(MBB, I, DL, TII->get(AMDGPU::COPY), SPReg)
525 BuildMI(MBB, I, DL, TII->get(AMDGPU::S_ADD_U32), SPReg)
550 const MCInstrDesc &SMovB32 = TII->get(AMDGPU::S_MOV_B32);
557 const MCInstrDesc &GetPC64 = TII->get(AMDGPU::S_GETPC_B64);
585 const MCInstrDesc &LoadDwordX4 = TII->get(AMDGPU::S_LOAD_DWORDX4_IMM);
606 const MCInstrDesc &SMovB32 = TII->get(AMDGPU::S_MOV_B32);
618 const MCInstrDesc &Mov64 = TII->get(AMDGPU::S_MOV_B64);
624 const MCInstrDesc &LoadDwordX2 = TII->get(AMDGPU::S_LOAD_DWORDX2_IMM);
712 BuildMI(MBB, MBBI, DL, TII->get(AMDGPU::COPY), FuncInfo->SGPRForFPSaveRestoreCopy)
737 BuildMI(MBB, MBBI, DL, TII->get(OrSaveExec),
752 BuildMI(MBB, MBBI, DL, TII->get(ExecMov), Exec)
793 BuildMI(MBB, MBBI, DL, TII->get(AMDGPU::S_ADD_U32), ScratchSPReg)
797 BuildMI(MBB, MBBI, DL, TII->get(AMDGPU::S_AND_B32), FramePtrReg)
807 BuildMI(MBB, MBBI, DL, TII->get(AMDGPU::COPY), FramePtrReg)
813 BuildMI(MBB, MBBI, DL, TII->get(AMDGPU::S_ADD_U32), StackPtrReg)
848 BuildMI(MBB, MBBI, DL, TII->get(AMDGPU::S_SUB_U32), StackPtrReg)
855 BuildMI(MBB, MBBI, DL, TII->get(AMDGPU::COPY), FuncInfo->getFrameOffsetReg())
897 BuildMI(MBB, MBBI, DL, TII->get(OrSaveExec), ScratchExecCopy)
910 BuildMI(MBB, MBBI, DL, TII->get(ExecMov), Exec)
1121 BuildMI(MBB, I, DL, TII->get(Op), SPReg)
lib/Target/AMDGPU/SIISelLowering.cpp 2006 BuildMI(*Entry, MBBI, DebugLoc(), TII->get(TargetOpcode::COPY), NewVR)
2012 TII->get(TargetOpcode::COPY), *I)
3107 BuildMI(*MBB, E, MI.getDebugLoc(), TII->get(AMDGPU::S_WAITCNT))
3137 BuildMI(*LoopBB, LoopBB->begin(), DL, TII->get(AMDGPU::S_SETREG_IMM32_B32))
3146 BuildMI(*LoopBB, I, DL, TII->get(AMDGPU::S_GETREG_B32), Reg)
3150 BuildMI(*LoopBB, I, DL, TII->get(AMDGPU::S_CMP_LG_U32))
3153 BuildMI(*LoopBB, I, DL, TII->get(AMDGPU::S_CBRANCH_SCC1))
3189 BuildMI(LoopBB, I, DL, TII->get(TargetOpcode::PHI), PhiReg)
3195 BuildMI(LoopBB, I, DL, TII->get(TargetOpcode::PHI), PhiExec)
3202 BuildMI(LoopBB, I, DL, TII->get(AMDGPU::V_READFIRSTLANE_B32), CurrentIdxReg)
3206 BuildMI(LoopBB, I, DL, TII->get(AMDGPU::V_CMP_EQ_U32_e64), CondReg)
3211 BuildMI(LoopBB, I, DL, TII->get(ST.isWave32() ? AMDGPU::S_AND_SAVEEXEC_B32
3224 BuildMI(LoopBB, I, DL, TII->get(AMDGPU::S_ADD_I32), IdxReg)
3231 BuildMI(LoopBB, I, DL, TII->get(AMDGPU::S_SET_GPR_IDX_ON))
3238 BuildMI(LoopBB, I, DL, TII->get(AMDGPU::S_MOV_B32), AMDGPU::M0)
3241 BuildMI(LoopBB, I, DL, TII->get(AMDGPU::S_ADD_I32), AMDGPU::M0)
3250 BuildMI(LoopBB, I, DL, TII->get(ST.isWave32() ? AMDGPU::S_XOR_B32_term
3259 BuildMI(LoopBB, I, DL, TII->get(AMDGPU::S_CBRANCH_EXECNZ))
3292 BuildMI(MBB, I, DL, TII->get(TargetOpcode::IMPLICIT_DEF), TmpExec);
3295 BuildMI(MBB, I, DL, TII->get(MovExecOpc), SaveExec)
3309 BuildMI(*RemainderBB, First, DL, TII->get(MovExecOpc), Exec)
3355 BuildMI(*MBB, I, DL, TII->get(AMDGPU::S_SET_GPR_IDX_ON))
3362 BuildMI(*MBB, I, DL, TII->get(AMDGPU::S_ADD_I32), Tmp)
3366 BuildMI(*MBB, I, DL, TII->get(AMDGPU::S_SET_GPR_IDX_ON))
3377 BuildMI(*MBB, I, DL, TII->get(AMDGPU::S_MOV_B32), AMDGPU::M0)
3380 BuildMI(*MBB, I, DL, TII->get(AMDGPU::S_ADD_I32), AMDGPU::M0)
3417 BuildMI(MBB, I, DL, TII->get(AMDGPU::V_MOV_B32_e32), Dst)
3421 BuildMI(MBB, I, DL, TII->get(AMDGPU::S_SET_GPR_IDX_OFF));
3423 BuildMI(MBB, I, DL, TII->get(AMDGPU::V_MOVRELS_B32_e32), Dst)
3439 BuildMI(MBB, I, DL, TII->get(TargetOpcode::IMPLICIT_DEF), InitReg);
3446 BuildMI(*LoopBB, InsPt, DL, TII->get(AMDGPU::V_MOV_B32_e32), Dst)
3450 BuildMI(*LoopBB, InsPt, DL, TII->get(AMDGPU::S_SET_GPR_IDX_OFF));
3452 BuildMI(*LoopBB, InsPt, DL, TII->get(AMDGPU::V_MOVRELS_B32_e32), Dst)
3510 BuildMI(MBB, I, DL, TII->get(TargetOpcode::INSERT_SUBREG), Dst)
3524 BuildMI(MBB, I, DL, TII->get(AMDGPU::V_MOV_B32_indirect))
3531 BuildMI(MBB, I, DL, TII->get(AMDGPU::S_SET_GPR_IDX_OFF));
3533 const MCInstrDesc &MovRelDesc = TII->get(getMOVRELDPseudo(TRI, VecRC));
3558 BuildMI(*LoopBB, InsPt, DL, TII->get(AMDGPU::V_MOV_B32_indirect))
3564 BuildMI(*LoopBB, InsPt, DL, TII->get(AMDGPU::S_SET_GPR_IDX_OFF));
3566 const MCInstrDesc &MovRelDesc = TII->get(getMOVRELDPseudo(TRI, VecRC));
3631 BuildMI(*BB, MI, DL, TII->get(LoOpc), DestSub0)
3634 BuildMI(*BB, MI, DL, TII->get(HiOpc), DestSub1)
3637 BuildMI(*BB, MI, DL, TII->get(TargetOpcode::REG_SEQUENCE), Dest.getReg())
3647 TII->get(AMDGPU::S_MOV_B32), AMDGPU::M0)
3654 BuildMI(*BB, &*BB->begin(), MI.getDebugLoc(), TII->get(AMDGPU::S_MOV_B64),
3662 BuildMI(*BB, &*BB->begin(), MI.getDebugLoc(), TII->get(AMDGPU::S_MOV_B32),
3704 BuildMI(*BB, FirstMI, DebugLoc(), TII->get(AMDGPU::S_BFE_U32), CountReg)
3708 TII->get(isWave32 ? AMDGPU::S_BFM_B32 : AMDGPU::S_BFM_B64),
3712 BuildMI(*BB, FirstMI, DebugLoc(), TII->get(AMDGPU::S_CMP_EQ_U32))
3716 TII->get(isWave32 ? AMDGPU::S_CMOV_B32 : AMDGPU::S_CMOV_B64),
3727 BuildMI(*BB, MI, DL, TII->get(AMDGPU::S_MOV_B32))
3764 BuildMI(*BB, MI, DL, TII->get(AMDGPU::COPY), SrcCondCopy)
3766 BuildMI(*BB, MI, DL, TII->get(AMDGPU::V_CNDMASK_B32_e64), DstLo)
3772 BuildMI(*BB, MI, DL, TII->get(AMDGPU::V_CNDMASK_B32_e64), DstHi)
3779 BuildMI(*BB, MI, DL, TII->get(AMDGPU::REG_SEQUENCE), Dst)
3790 MachineInstr *Br = BuildMI(*BB, MI, DL, TII->get(AMDGPU::S_CBRANCH_SCC1))
3816 MIB = BuildMI(*BB, MI, DL, TII->get(AMDGPU::SI_CALL), ReturnAddrReg);
3838 auto I = BuildMI(*BB, MI, DL, TII->get(Opc), MI.getOperand(0).getReg());
10298 if (TII->isMIMG(Opcode) && !TII->get(Opcode).mayStore() &&
10432 MI.setDesc(TII->get(NoRetAtomicOp));
10450 MI.setDesc(TII->get(NoRetAtomicOp));
10458 TII->get(AMDGPU::IMPLICIT_DEF), Def);
10715 BuildMI(MBB, I, DL, TII->get(TargetOpcode::IMPLICIT_DEF), AMDGPU::VCC_HI);
10801 TII->get(AMDGPU::S_INST_PREFETCH))
10805 TII->get(AMDGPU::S_INST_PREFETCH))
lib/Target/AMDGPU/SIInsertSkips.cpp 162 BuildMI(&MBB, DL, TII->get(AMDGPU::S_CBRANCH_EXECNZ))
168 BuildMI(*SkipBB, Insert, DL, TII->get(AMDGPU::EXP_DONE))
179 BuildMI(*SkipBB, Insert, DL, TII->get(AMDGPU::S_ENDPGM)).addImm(0);
256 BuildMI(MBB, &MI, DL, TII->get(Opcode))
260 auto I = BuildMI(MBB, &MI, DL, TII->get(Opcode));
287 BuildMI(MBB, &MI, DL, TII->get(ST.isWave32() ? AMDGPU::S_MOV_B32
296 BuildMI(MBB, &MI, DL, TII->get(Opcode), Exec)
331 BuildMI(SrcMBB, InsPt, DL, TII->get(AMDGPU::S_CBRANCH_EXECZ))
417 MI.setDesc(TII->get(AMDGPU::S_BRANCH));
419 MI.setDesc(TII->get(IsVCCZ ? AMDGPU::S_CBRANCH_EXECZ
520 BuildMI(*BI, I, MI.getDebugLoc(), TII->get(AMDGPU::S_BRANCH))
lib/Target/AMDGPU/SIInsertWaitcnts.cpp 1153 MI.getDebugLoc(), TII->get(AMDGPU::S_WAITCNT))
1168 TII->get(AMDGPU::S_WAITCNT_VSCNT))
1431 TII->get(ST->isWave32() ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64),
1581 BuildMI(*MBB, I, I->getDebugLoc(), TII->get(AMDGPU::S_DCACHE_WB));
1597 TII->get(AMDGPU::S_WAITCNT_VSCNT))
1600 BuildMI(EntryBB, EntryBB.getFirstNonPHI(), DebugLoc(), TII->get(AMDGPU::S_WAITCNT))
lib/Target/AMDGPU/SIInstrInfo.cpp 154 if (!get(Opc0).mayLoad() || !get(Opc1).mayLoad())
154 if (!get(Opc0).mayLoad() || !get(Opc1).mayLoad())
179 Offset0Idx -= get(Opc0).NumDefs;
180 Offset1Idx -= get(Opc1).NumDefs;
229 OffIdx0 -= get(Opc0).NumDefs;
230 OffIdx1 -= get(Opc1).NumDefs;
520 BuildMI(MBB, MI, DL, TII->get(AMDGPU::SI_ILLEGAL_COPY), DestReg)
536 BuildMI(MBB, MI, DL, get(Opc), DestReg)
544 BuildMI(MBB, MI, DL, get(AMDGPU::S_CSELECT_B32), DestReg)
552 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B32), AMDGPU::VCC_LO)
557 BuildMI(MBB, MI, DL, get(AMDGPU::V_CMP_NE_U32_e32))
570 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B32), DestReg)
578 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), AMDGPU::VCC)
583 BuildMI(MBB, MI, DL, get(AMDGPU::V_CMP_NE_U32_e32))
596 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), DestReg)
603 BuildMI(MBB, MI, DL, get(AMDGPU::S_CMP_LG_U32))
639 BuildMI(MBB, MI, DL, get(AMDGPU::V_ACCVGPR_WRITE_B32), DestReg)
671 BuildMI(MBB, MI, DL, get(AMDGPU::V_ACCVGPR_WRITE_B32), DestReg)
676 BuildMI(MBB, MI, DL, get(AMDGPU::V_ACCVGPR_WRITE_B32), DestReg)
721 get(Opcode), RI.getSubReg(DestReg, SubIdx));
761 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B32), DestReg)
769 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), DestReg)
775 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DestReg)
780 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B64_PSEUDO), DestReg)
802 get(Opcode), RI.getSubReg(DestReg, Idx));
828 BuildMI(MBB, I, DL, get(AMDGPU::COPY), SReg)
830 BuildMI(MBB, I, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstReg)
841 BuildMI(MBB, I, DL, get(ST.isWave32() ? AMDGPU::S_CSELECT_B32
845 BuildMI(MBB, I, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstReg)
855 BuildMI(MBB, I, DL, get(ST.isWave32() ? AMDGPU::S_CSELECT_B32
859 BuildMI(MBB, I, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstReg)
871 BuildMI(MBB, I, DL, get(AMDGPU::COPY), SReg)
873 BuildMI(MBB, I, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstReg)
885 BuildMI(MBB, I, DL, get(AMDGPU::COPY), SReg)
887 BuildMI(MBB, I, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstReg)
898 BuildMI(MBB, I, DL, get(ST.isWave32() ? AMDGPU::S_OR_SAVEEXEC_B32
901 BuildMI(MBB, I, DL, get(ST.isWave32() ? AMDGPU::S_CSELECT_B32
905 BuildMI(MBB, I, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstReg)
916 BuildMI(MBB, I, DL, get(ST.isWave32() ? AMDGPU::S_OR_SAVEEXEC_B32
919 BuildMI(MBB, I, DL, get(ST.isWave32() ? AMDGPU::S_CSELECT_B32
923 BuildMI(MBB, I, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstReg)
946 BuildMI(*MBB, I, DL, get(AMDGPU::V_CMP_EQ_I32_e64), Reg)
959 BuildMI(*MBB, I, DL, get(AMDGPU::V_CMP_NE_I32_e64), Reg)
1068 const MCInstrDesc &OpDesc = get(getSGPRSpillSaveOpcode(SpillSize));
1095 auto MIB = BuildMI(MBB, MI, DL, get(Opcode));
1196 const MCInstrDesc &OpDesc = get(getSGPRSpillRestoreOpcode(SpillSize));
1214 auto MIB = BuildMI(MBB, MI, DL, get(Opcode), DestReg);
1268 BuildMI(Entry, Insert, DL, get(AMDGPU::S_LOAD_DWORD_IMM), STmp0)
1271 BuildMI(Entry, Insert, DL, get(AMDGPU::S_LOAD_DWORD_IMM), STmp1)
1276 BuildMI(Entry, Insert, DL, get(AMDGPU::S_MUL_I32), STmp1)
1280 BuildMI(Entry, Insert, DL, get(AMDGPU::V_MUL_U32_U24_e32), TIDReg)
1284 BuildMI(Entry, Insert, DL, get(AMDGPU::V_MAD_U32_U24), TIDReg)
1295 BuildMI(Entry, Insert, DL, get(AMDGPU::V_MBCNT_LO_U32_B32_e64),
1300 BuildMI(Entry, Insert, DL, get(AMDGPU::V_MBCNT_HI_U32_B32_e64),
1306 BuildMI(Entry, Insert, DL, get(AMDGPU::V_LSHLREV_B32_e32),
1334 BuildMI(MBB, MI, DL, get(AMDGPU::S_NOP))
1354 BuildMI(MBB, MBB.end(), DebugLoc(), get(AMDGPU::S_ENDPGM)).addImm(0);
1356 BuildMI(MBB, MBB.end(), DebugLoc(), get(AMDGPU::SI_RETURN_TO_EPILOG));
1379 MI.setDesc(get(AMDGPU::S_MOV_B64));
1385 MI.setDesc(get(AMDGPU::S_MOV_B32));
1391 MI.setDesc(get(AMDGPU::S_XOR_B64));
1397 MI.setDesc(get(AMDGPU::S_XOR_B32));
1403 MI.setDesc(get(AMDGPU::S_OR_B32));
1409 MI.setDesc(get(AMDGPU::S_ANDN2_B64));
1415 MI.setDesc(get(AMDGPU::S_ANDN2_B32));
1428 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstLo)
1431 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstHi)
1436 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstLo)
1439 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstHi)
1453 BuildMI(MBB, MI, DL, get(NotOpc), Exec)
1455 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), MI.getOperand(0).getReg())
1457 BuildMI(MBB, MI, DL, get(NotOpc), Exec)
1465 BuildMI(MBB, MI, DL, get(NotOpc), Exec)
1467 MachineInstr *Copy = BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B64_PSEUDO),
1471 BuildMI(MBB, MI, DL, get(NotOpc), Exec)
1481 const MCInstrDesc &MovRelDesc = get(AMDGPU::V_MOVRELD_B32_e32);
1512 Bundler.append(BuildMI(MF, DL, get(AMDGPU::S_GETPC_B64), Reg));
1516 Bundler.append(BuildMI(MF, DL, get(AMDGPU::S_ADD_U32), RegLo)
1520 MachineInstrBuilder MIB = BuildMI(MF, DL, get(AMDGPU::S_ADDC_U32), RegHi)
1533 MI.setDesc(get(ST.isWave32() ? AMDGPU::S_OR_SAVEEXEC_B32
1540 MI.setDesc(get(ST.isWave32() ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64));
1577 auto MovDPP = BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_dpp));
1611 BuildMI(MBB, MI, DL, get(AMDGPU::REG_SEQUENCE), Dst)
1708 CommutedMI->setDesc(get(CommutedOpcode));
1788 MachineInstr *GetPC = BuildMI(MBB, I, DL, get(AMDGPU::S_GETPC_B64), PCReg);
1792 BuildMI(MBB, I, DL, get(AMDGPU::S_ADD_U32))
1796 BuildMI(MBB, I, DL, get(AMDGPU::S_ADDC_U32))
1802 BuildMI(MBB, I, DL, get(AMDGPU::S_SUB_U32))
1806 BuildMI(MBB, I, DL, get(AMDGPU::S_SUBB_U32))
1813 BuildMI(&MBB, DL, get(AMDGPU::S_SETPC_B64))
2052 BuildMI(&MBB, DL, get(AMDGPU::S_BRANCH))
2060 BuildMI(&MBB, DL, get(AMDGPU::SI_NON_UNIFORM_BRCOND_PSEUDO))
2074 BuildMI(&MBB, DL, get(Opcode))
2088 BuildMI(&MBB, DL, get(Opcode))
2090 BuildMI(&MBB, DL, get(AMDGPU::S_BRANCH))
2177 BuildMI(MBB, I, DL, get(SelOp), DstReg)
2187 BuildMI(MBB, I, DL, get(AMDGPU::S_CSELECT_B64), DstReg)
2229 MBB, I, DL, get(AMDGPU::REG_SEQUENCE), DstReg);
2241 BuildMI(MBB, I, DL, get(SelOp), DstElt)
2340 UseMI.setDesc(get(NewOpc));
2415 UseMI.setDesc(get(NewOpc));
2494 UseMI.setDesc(get(NewOpc));
2663 return BuildMI(*MBB, MI, MI.getDebugLoc(), get(NewOpc))
2674 return BuildMI(*MBB, MI, MI.getDebugLoc(), get(NewOpc))
2684 return BuildMI(*MBB, MI, MI.getDebugLoc(), get(NewOpc))
2697 return BuildMI(*MBB, MI, MI.getDebugLoc(), get(NewOpc))
3062 BuildMI(*MBB, MI, MI.getDebugLoc(), get(Op32));
3204 const MCInstrDesc &Desc = get(Opcode);
3810 const MCInstrDesc &Desc = get(MI.getOpcode());
3831 unsigned RCID = get(MI.getOpcode()).OpInfo[OpIdx].RegClass;
3848 BuildMI(*MI.getParent(), I, DL, get(Opcode), Reg).add(MO);
3864 BuildMI(*MBB, MI, DL, get(TargetOpcode::COPY), SubReg)
3875 BuildMI(*MBB, MI, DL, get(TargetOpcode::COPY), NewSuperReg)
3878 BuildMI(*MBB, MI, DL, get(TargetOpcode::COPY), SubReg)
4015 const MCInstrDesc &InstrDesc = get(Opc);
4038 BuildMI(*MI.getParent(), MI, DL, get(AMDGPU::V_READFIRSTLANE_B32), Reg)
4045 BuildMI(*MI.getParent(), MI, DL, get(AMDGPU::V_READFIRSTLANE_B32), Reg)
4071 BuildMI(*MI.getParent(), MI, DL, get(AMDGPU::V_READFIRSTLANE_B32), Reg)
4103 MI.setDesc(get(CommutedOpc));
4142 BuildMI(*MI.getParent(), MI, DL, get(AMDGPU::V_READFIRSTLANE_B32), Reg)
4148 BuildMI(*MI.getParent(), MI, DL, get(AMDGPU::V_READFIRSTLANE_B32), Reg)
4171 if (!isLiteralConstantLike(MO, get(Opc).OpInfo[Idx]))
4222 get(TargetOpcode::COPY), NewSrcReg)
4229 get(AMDGPU::V_READFIRSTLANE_B32), DstReg)
4238 get(AMDGPU::V_READFIRSTLANE_B32), SGPR)
4245 get(AMDGPU::REG_SEQUENCE), DstReg);
4290 BuildMI(InsertMBB, I, DL, get(AMDGPU::COPY), DstReg).add(Op);
4350 BuildMI(LoopBB, I, DL, TII.get(AMDGPU::V_READFIRSTLANE_B32), SRsrcSub0)
4352 BuildMI(LoopBB, I, DL, TII.get(AMDGPU::V_READFIRSTLANE_B32), SRsrcSub1)
4354 BuildMI(LoopBB, I, DL, TII.get(AMDGPU::V_READFIRSTLANE_B32), SRsrcSub2)
4356 BuildMI(LoopBB, I, DL, TII.get(AMDGPU::V_READFIRSTLANE_B32), SRsrcSub3)
4359 BuildMI(LoopBB, I, DL, TII.get(AMDGPU::REG_SEQUENCE), SRsrc)
4374 BuildMI(LoopBB, I, DL, TII.get(AMDGPU::V_CMP_EQ_U64_e64), CondReg0)
4377 BuildMI(LoopBB, I, DL, TII.get(AMDGPU::V_CMP_EQ_U64_e64), CondReg1)
4380 BuildMI(LoopBB, I, DL, TII.get(AndOpc), AndCond)
4387 BuildMI(LoopBB, I, DL, TII.get(SaveExecOpc), SaveExec)
4394 BuildMI(LoopBB, I, DL, TII.get(XorTermOpc), Exec)
4397 BuildMI(LoopBB, I, DL, TII.get(AMDGPU::S_CBRANCH_EXECNZ)).addMBB(&LoopBB);
4418 BuildMI(MBB, I, DL, TII.get(MovExecOpc), SaveExec).addReg(Exec);
4467 BuildMI(*RemainderBB, First, DL, TII.get(MovExecOpc), Exec).addReg(SaveExec);
4490 BuildMI(MBB, MI, MI.getDebugLoc(), TII.get(AMDGPU::S_MOV_B64), Zero64)
4494 BuildMI(MBB, MI, MI.getDebugLoc(), TII.get(AMDGPU::S_MOV_B32), SRsrcFormatLo)
4498 BuildMI(MBB, MI, MI.getDebugLoc(), TII.get(AMDGPU::S_MOV_B32), SRsrcFormatHi)
4502 BuildMI(MBB, MI, MI.getDebugLoc(), TII.get(AMDGPU::REG_SEQUENCE), NewSRsrc)
4671 unsigned RsrcRC = get(MI.getOpcode()).OpInfo[RsrcIdx].RegClass;
4711 BuildMI(MBB, MI, DL, get(AMDGPU::V_ADD_I32_e64), NewVAddrLo)
4718 BuildMI(MBB, MI, DL, get(AMDGPU::V_ADDC_U32_e64), NewVAddrHi)
4726 BuildMI(MBB, MI, MI.getDebugLoc(), get(AMDGPU::REG_SEQUENCE), NewVAddr)
4758 BuildMI(MBB, MI, MI.getDebugLoc(), get(Addr64Opcode))
4788 Addr64 = BuildMI(MBB, MI, MI.getDebugLoc(), get(Addr64Opcode))
4802 BuildMI(MBB, Addr64, Addr64->getDebugLoc(), get(AMDGPU::REG_SEQUENCE),
4950 BuildMI(*MBB, Inst, Inst.getDebugLoc(), get(AMDGPU::S_AND_B32),
4955 BuildMI(*MBB, Inst, Inst.getDebugLoc(), get(AMDGPU::S_AND_B64),
5006 const MCInstrDesc &NewDesc = get(NewOpcode);
5084 Inst.setDesc(get(AMDGPU::IMPLICIT_DEF));
5123 Inst.setDesc(get(NewOpc));
5151 BuildMI(MBB, MII, DL, get(SubOp), TmpReg)
5155 BuildMI(MBB, MII, DL, get(AMDGPU::V_MAX_I32_e64), ResultReg)
5179 BuildMI(MBB, MII, DL, get(AMDGPU::V_XNOR_B32_e64), NewDest)
5202 BuildMI(MBB, MII, DL, get(AMDGPU::S_NOT_B32), Temp).add(Src0);
5203 Xor = BuildMI(MBB, MII, DL, get(AMDGPU::S_XOR_B32), NewDest)
5207 BuildMI(MBB, MII, DL, get(AMDGPU::S_NOT_B32), Temp).add(Src1);
5208 Xor = BuildMI(MBB, MII, DL, get(AMDGPU::S_XOR_B32), NewDest)
5212 Xor = BuildMI(MBB, MII, DL, get(AMDGPU::S_XOR_B32), Temp)
5216 BuildMI(MBB, MII, DL, get(AMDGPU::S_NOT_B32), NewDest).addReg(Temp);
5243 MachineInstr &Op = *BuildMI(MBB, MII, DL, get(Opcode), Interm)
5247 MachineInstr &Not = *BuildMI(MBB, MII, DL, get(AMDGPU::S_NOT_B32), NewDest)
5272 MachineInstr &Not = *BuildMI(MBB, MII, DL, get(AMDGPU::S_NOT_B32), Interm)
5275 MachineInstr &Op = *BuildMI(MBB, MII, DL, get(Opcode), NewDest)
5298 const MCInstrDesc &InstDesc = get(Opcode);
5322 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), FullDestReg)
5380 BuildMI(MBB, MII, DL, get(LoOpc), DestSub0)
5388 BuildMI(MBB, MII, DL, get(HiOpc), DestSub1)
5395 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), FullDestReg)
5425 const MCInstrDesc &InstDesc = get(Opcode);
5461 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), FullDestReg)
5504 BuildMI(MBB, MII, DL, get(AMDGPU::S_NOT_B64), Interm)
5509 MachineInstr &Xor = *BuildMI(MBB, MII, DL, get(AMDGPU::S_XOR_B64), NewDest)
5529 const MCInstrDesc &InstDesc = get(AMDGPU::V_BCNT_U32_B32_e64);
5578 BuildMI(MBB, MII, DL, get(AMDGPU::V_BFE_I32), MidRegLo)
5583 BuildMI(MBB, MII, DL, get(AMDGPU::V_ASHRREV_I32_e32), MidRegHi)
5587 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), ResultReg)
5602 BuildMI(MBB, MII, DL, get(AMDGPU::V_ASHRREV_I32_e64), TmpReg)
5606 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), ResultReg)
5668 BuildMI(*MBB, Inst, DL, get(AMDGPU::V_MOV_B32_e32), ImmReg)
5671 BuildMI(*MBB, Inst, DL, get(AMDGPU::V_AND_B32_e64), TmpReg)
5675 BuildMI(*MBB, Inst, DL, get(AMDGPU::V_LSHL_OR_B32), ResultReg)
5683 BuildMI(*MBB, Inst, DL, get(AMDGPU::V_MOV_B32_e32), ImmReg)
5685 BuildMI(*MBB, Inst, DL, get(AMDGPU::V_BFI_B32), ResultReg)
5694 BuildMI(*MBB, Inst, DL, get(AMDGPU::V_LSHRREV_B32_e64), TmpReg)
5697 BuildMI(*MBB, Inst, DL, get(AMDGPU::V_MOV_B32_e32), ImmReg)
5699 BuildMI(*MBB, Inst, DL, get(AMDGPU::V_AND_OR_B32), ResultReg)
6077 BuildMI(*MF, Branch->getDebugLoc(), get(AMDGPU::SI_IF), DstReg)
6081 BuildMI(*MF, Branch->getDebugLoc(), get(AMDGPU::SI_END_CF))
6105 BuildMI(*(MF), Branch->getDebugLoc(), get(TargetOpcode::PHI), DstReg);
6122 get(AMDGPU::SI_IF_BREAK), BackEdgeReg)
6126 BuildMI(*(MF), Branch->getDebugLoc(), get(AMDGPU::SI_LOOP))
6194 return BuildMI(MBB, I, DL, get(AMDGPU::V_ADD_U32_e64), DestReg);
6200 return BuildMI(MBB, I, DL, get(AMDGPU::V_ADD_I32_e64), DestReg)
6210 return BuildMI(MBB, I, DL, get(AMDGPU::V_ADD_U32_e32), DestReg);
6217 return BuildMI(MBB, I, DL, get(AMDGPU::V_ADD_I32_e64), DestReg)
6234 return get(AMDGPU::SI_KILL_F32_COND_IMM_TERMINATOR);
6236 return get(AMDGPU::SI_KILL_I1_TERMINATOR);
6333 if ((get(Opcode).TSFlags & SIInstrFlags::renamedInGFX9) != 0 &&
6340 if (ST.hasUnpackedD16VMem() && (get(Opcode).TSFlags & SIInstrFlags::D16Buf))
6343 if (get(Opcode).TSFlags & SIInstrFlags::SDWA) {
6532 return BuildMI(MBB, Cur, DL, get(TargetOpcode::COPY), Dst).addReg(Src);
6550 get(ST.isWave32() ? AMDGPU::S_MOV_B32_term
lib/Target/AMDGPU/SIInstrInfo.h 336 return get(Opcode).TSFlags & SIInstrFlags::SALU;
344 return get(Opcode).TSFlags & SIInstrFlags::VALU;
360 return get(Opcode).TSFlags & SIInstrFlags::SOP1;
368 return get(Opcode).TSFlags & SIInstrFlags::SOP2;
376 return get(Opcode).TSFlags & SIInstrFlags::SOPC;
384 return get(Opcode).TSFlags & SIInstrFlags::SOPK;
392 return get(Opcode).TSFlags & SIInstrFlags::SOPP;
400 return get(Opcode).TSFlags & SIInstrFlags::IsPacked;
408 return get(Opcode).TSFlags & SIInstrFlags::VOP1;
416 return get(Opcode).TSFlags & SIInstrFlags::VOP2;
424 return get(Opcode).TSFlags & SIInstrFlags::VOP3;
432 return get(Opcode).TSFlags & SIInstrFlags::SDWA;
440 return get(Opcode).TSFlags & SIInstrFlags::VOPC;
448 return get(Opcode).TSFlags & SIInstrFlags::MUBUF;
456 return get(Opcode).TSFlags & SIInstrFlags::MTBUF;
464 return get(Opcode).TSFlags & SIInstrFlags::SMRD;
474 return get(Opcode).TSFlags & SIInstrFlags::DS;
484 return get(Opcode).TSFlags & SIInstrFlags::MIMG;
492 return get(Opcode).TSFlags & SIInstrFlags::Gather4;
513 return get(Opcode).TSFlags & SIInstrFlags::FLAT;
521 return get(Opcode).TSFlags & SIInstrFlags::EXP;
529 return get(Opcode).TSFlags & SIInstrFlags::WQM;
537 return get(Opcode).TSFlags & SIInstrFlags::DisableWQM;
545 return get(Opcode).TSFlags & SIInstrFlags::VGPRSpill;
553 return get(Opcode).TSFlags & SIInstrFlags::SGPRSpill;
561 return get(Opcode).TSFlags & SIInstrFlags::DPP;
569 return get(Opcode).TSFlags & SIInstrFlags::VOP3P;
577 return get(Opcode).TSFlags & SIInstrFlags::VINTRP;
585 return get(Opcode).TSFlags & SIInstrFlags::IsMAI;
593 return get(Opcode).TSFlags & SIInstrFlags::IsDOT;
613 return get(Opcode).TSFlags & SIInstrFlags::SOPK_ZEXT;
623 return get(Opcode).TSFlags & SIInstrFlags::SCALAR_STORE;
631 return get(Opcode).TSFlags & SIInstrFlags::FIXED_SIZE;
639 return get(Opcode).TSFlags & SIInstrFlags::FPClamp;
659 return get(Opcode).TSFlags & SIInstrFlags::FPDPRounding;
667 return get(Opcode).TSFlags & SIInstrFlags::FPAtomic;
804 const MCOperandInfo &OpInfo = get(Opcode).OpInfo[OpNo];
930 return get(pseudoToMCOpcode(Opcode));
lib/Target/AMDGPU/SILoadStoreOptimizer.cpp 325 if (TII.get(Opc).mayStore() || !TII.get(Opc).mayLoad() || TII.isGather4(Opc))
325 if (TII.get(Opc).mayStore() || !TII.get(Opc).mayLoad() || TII.isGather4(Opc))
899 const MCInstrDesc &Read2Desc = TII->get(Opc);
912 BuildMI(*MBB, CI.Paired, DL, TII->get(AMDGPU::S_MOV_B32), ImmReg)
935 const MCInstrDesc &CopyDesc = TII->get(TargetOpcode::COPY);
997 const MCInstrDesc &Write2Desc = TII->get(Opc);
1005 BuildMI(*MBB, CI.Paired, DL, TII->get(AMDGPU::S_MOV_B32), ImmReg)
1050 auto MIB = BuildMI(*MBB, CI.Paired, DL, TII->get(Opcode), DestReg);
1073 const MCInstrDesc &CopyDesc = TII->get(TargetOpcode::COPY);
1111 BuildMI(*MBB, CI.Paired, DL, TII->get(Opcode), DestReg)
1123 const MCInstrDesc &CopyDesc = TII->get(TargetOpcode::COPY);
1154 auto MIB = BuildMI(*MBB, CI.Paired, DL, TII->get(Opcode), DestReg);
1185 const MCInstrDesc &CopyDesc = TII->get(TargetOpcode::COPY);
1313 BuildMI(*MBB, CI.Paired, DL, TII->get(AMDGPU::REG_SEQUENCE), SrcReg)
1319 auto MIB = BuildMI(*MBB, CI.Paired, DL, TII->get(Opcode))
1363 TII->get(AMDGPU::S_MOV_B32), Reg)
1397 BuildMI(*MBB, MBBI, DL, TII->get(AMDGPU::V_ADD_I32_e64), DestSub0)
1406 BuildMI(*MBB, MBBI, DL, TII->get(AMDGPU::V_ADDC_U32_e64), DestSub1)
1417 BuildMI(*MBB, MBBI, DL, TII->get(TargetOpcode::REG_SEQUENCE), FullDestReg)
lib/Target/AMDGPU/SILowerControlFlow.cpp 219 BuildMI(MBB, I, DL, TII->get(AMDGPU::COPY), CopyReg)
226 BuildMI(MBB, I, DL, TII->get(AndOpc), Tmp)
235 BuildMI(MBB, I, DL, TII->get(XorOpc), SaveExecReg)
244 BuildMI(MBB, I, DL, TII->get(MovTermOpc), Exec)
249 MachineInstr *NewBr = BuildMI(MBB, I, DL, TII->get(AMDGPU::SI_MASK_BRANCH))
295 BuildMI(MBB, Start, DL, TII->get(AMDGPU::COPY), CopyReg)
303 BuildMI(MBB, Start, DL, TII->get(OrSaveExecOpc), SaveReg)
312 BuildMI(MBB, ElsePt, DL, TII->get(AndOpc), DstReg)
321 BuildMI(MBB, ElsePt, DL, TII->get(XorTermrOpc), Exec)
326 BuildMI(MBB, ElsePt, DL, TII->get(AMDGPU::SI_MASK_BRANCH))
375 And = BuildMI(MBB, &MI, DL, TII->get(AndOpc), Dst)
378 Or = BuildMI(MBB, &MI, DL, TII->get(OrOpc), Dst)
382 Or = BuildMI(MBB, &MI, DL, TII->get(OrOpc), Dst)
400 BuildMI(MBB, &MI, DL, TII->get(Andn2TermOpc), Exec)
405 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_CBRANCH_EXECNZ))
426 MachineInstr *NewMI = BuildMI(MBB, InsPt, DL, TII->get(OrOpc), Exec)
lib/Target/AMDGPU/SILowerI1Copies.cpp 439 BuildMI(MBB, MBB.getFirstTerminator(), {}, TII->get(AMDGPU::IMPLICIT_DEF),
525 BuildMI(MBB, MI, DL, TII->get(AMDGPU::V_CNDMASK_B32_e64), DstReg)
704 BuildMI(MBB, MI, DL, TII->get(AMDGPU::V_CMP_NE_U32_e64), TmpReg)
824 BuildMI(MBB, I, DL, TII->get(AMDGPU::COPY), DstReg).addReg(CurReg);
826 BuildMI(MBB, I, DL, TII->get(AMDGPU::COPY), DstReg).addReg(ExecReg);
828 BuildMI(MBB, I, DL, TII->get(XorOp), DstReg)
842 BuildMI(MBB, I, DL, TII->get(AndN2Op), PrevMaskedReg)
853 BuildMI(MBB, I, DL, TII->get(AndOp), CurMaskedReg)
860 BuildMI(MBB, I, DL, TII->get(AMDGPU::COPY), DstReg)
863 BuildMI(MBB, I, DL, TII->get(AMDGPU::COPY), DstReg)
866 BuildMI(MBB, I, DL, TII->get(OrN2Op), DstReg)
870 BuildMI(MBB, I, DL, TII->get(OrOp), DstReg)
lib/Target/AMDGPU/SIMemoryLegalizer.cpp 729 BuildMI(MBB, MI, DL, TII->get(AMDGPU::BUFFER_WBINVL1));
841 BuildMI(MBB, MI, DL, TII->get(AMDGPU::S_WAITCNT)).addImm(WaitCntImmediate);
873 BuildMI(MBB, MI, DL, TII->get(Flush));
969 BuildMI(MBB, MI, DL, TII->get(AMDGPU::BUFFER_GL0_INV));
970 BuildMI(MBB, MI, DL, TII->get(AMDGPU::BUFFER_GL1_INV));
979 BuildMI(MBB, MI, DL, TII->get(AMDGPU::BUFFER_GL0_INV));
1107 BuildMI(MBB, MI, DL, TII->get(AMDGPU::S_WAITCNT)).addImm(WaitCntImmediate);
1112 BuildMI(MBB, MI, DL, TII->get(AMDGPU::S_WAITCNT_VSCNT))
lib/Target/AMDGPU/SIModeRegister.cpp 198 BuildMI(MBB, MI, 0, TII->get(AMDGPU::S_SETREG_IMM32_B32))
lib/Target/AMDGPU/SIOptimizeExecMasking.cpp 184 MI.setDesc(TII.get(AMDGPU::COPY));
190 MI.setDesc(TII.get(AMDGPU::S_XOR_B64));
196 MI.setDesc(TII.get(AMDGPU::S_XOR_B32));
202 MI.setDesc(TII.get(AMDGPU::S_OR_B32));
208 MI.setDesc(TII.get(AMDGPU::S_ANDN2_B64));
214 MI.setDesc(TII.get(AMDGPU::S_ANDN2_B32));
408 BuildMI(MBB, InsPt, DL, TII->get(getSaveExecOp(SaveExecInst->getOpcode())),
lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp 259 BuildMI(MBB, *And, And->getDebugLoc(), TII->get(Andn2Opc),
lib/Target/AMDGPU/SIPeepholeSDWA.cpp 924 auto NewMI = BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(Opc));
930 auto NewInst = BuildMI(MBB, MISucc, MISucc.getDebugLoc(), TII->get(SuccOpc));
1006 const MCInstrDesc &SDWADesc = TII->get(SDWAOpcode);
1175 const MCInstrDesc &Desc = TII->get(MI.getOpcode());
1194 TII->get(AMDGPU::V_MOV_B32_e32), VGPR);
lib/Target/AMDGPU/SIRegisterInfo.cpp 356 BuildMI(*MBB, Ins, DL, TII->get(AMDGPU::V_MOV_B32_e32), BaseReg)
366 BuildMI(*MBB, Ins, DL, TII->get(AMDGPU::S_MOV_B32), OffsetReg)
368 BuildMI(*MBB, Ins, DL, TII->get(AMDGPU::V_MOV_B32_e32), FIReg)
568 return BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(Opc), Dst)
595 BuildMI(*MBB, MI, DL, TII->get(LoadStoreOp))
629 const MCInstrDesc &Desc = TII->get(LoadStoreOp);
679 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::S_ADD_U32), SOffset)
705 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::V_ACCVGPR_READ_B32), TmpReg)
728 MIB = BuildMI(*MBB, MI, DL, TII->get(AMDGPU::V_ACCVGPR_WRITE_B32),
739 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::S_SUB_U32), ScratchOffsetReg)
824 = BuildMI(*MBB, MI, DL, TII->get(AMDGPU::V_MOV_B32_e32), TmpVGPR)
843 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::SI_SPILL_V32_SAVE))
854 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::COPY), AMDGPU::M0)
927 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::SI_SPILL_V32_RESTORE), TmpVGPR)
935 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::V_READFIRSTLANE_B32), SubReg)
944 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::COPY), AMDGPU::M0)
1110 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::S_SUB_U32), DiffReg)
1117 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::V_LSHRREV_B32_e64), ResultReg)
1125 BuildMI(*MBB, *MIB, DL, TII->get(AMDGPU::V_LSHRREV_B32_e64),
1146 BuildMI(*MBB, *MIB, DL, TII->get(AMDGPU::S_MOV_B32), ConstOffsetReg)
1164 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::S_LSHR_B32), ScaledReg)
1167 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::S_ADD_U32), ScaledReg)
1170 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::COPY), ResultReg)
1175 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::S_SUB_U32), ScaledReg)
1178 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::S_LSHL_B32), ScaledReg)
1187 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::S_ADD_U32), FrameReg)
1230 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::V_MOV_B32_e32), TmpReg)
lib/Target/AMDGPU/SIShrinkInstructions.cpp 206 MI.setDesc(TII->get(SOPKOpc));
212 const MCInstrDesc &NewDesc = TII->get(SOPKOpc);
295 MI.setDesc(TII->get(NewOpcode));
370 MI.setDesc(TII->get(Opc));
529 TII->get(AMDGPU::V_SWAP_B32))
583 MI.setDesc(TII->get(AMDGPU::V_BFREV_B32_e32));
655 MI.setDesc(TII->get(Opc));
675 MI.setDesc(TII->get(AMDGPU::S_MOVK_I32));
677 MI.setDesc(TII->get(AMDGPU::S_BREV_B32));
lib/Target/AMDGPU/SIWholeQuadMode.cpp 562 BuildMI(MBB, Before, DebugLoc(), TII->get(AMDGPU::COPY), SaveReg)
565 BuildMI(MBB, Before, DebugLoc(), TII->get(AMDGPU::COPY), AMDGPU::SCC)
632 MI = BuildMI(MBB, Before, DebugLoc(), TII->get(ST->isWave32() ?
638 MI = BuildMI(MBB, Before, DebugLoc(), TII->get(ST->isWave32() ?
655 MI = BuildMI(MBB, Before, DebugLoc(), TII->get(AMDGPU::COPY), Exec)
658 MI = BuildMI(MBB, Before, DebugLoc(), TII->get(ST->isWave32() ?
673 MI = BuildMI(MBB, Before, DebugLoc(), TII->get(AMDGPU::ENTER_WWM), SaveOrig)
684 MI = BuildMI(MBB, Before, DebugLoc(), TII->get(AMDGPU::EXIT_WWM),
845 BuildMI(*MI->getParent(), MI, DL, TII->get(AMDGPU::COPY), Dest)
866 MI->setDesc(TII->get(MovOp));
871 MI->setDesc(TII->get(AMDGPU::COPY));
905 TII->get(AMDGPU::COPY), LiveMaskReg)
914 BuildMI(Entry, EntryMI, DebugLoc(), TII->get(ST->isWave32() ?
lib/Target/ARC/ARCBranchFinalize.cpp 118 TII->get(getBRccForPseudo(MI)))
133 TII->get(getCmpForPseudo(MI)))
136 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), TII->get(ARC::Bcc))
lib/Target/ARC/ARCExpandPseudos.cpp 65 BuildMI(*SI.getParent(), SI, SI.getDebugLoc(), TII->get(AddOpc), AddrReg)
69 TII->get(getMappedOp(SI.getOpcode())))
lib/Target/ARC/ARCFrameLowering.cpp 72 BuildMI(MBB, MBBI, dl, TII.get(AdjOp), StackPtr)
143 BuildMI(MBB, MBBI, dl, TII->get(Opc), ARC::SP)
149 BuildMI(MBB, MBBI, dl, TII->get(ARC::ST_AW_rs9))
160 BuildMI(MBB, MBBI, dl, TII->get(ARC::PUSH_S_BLINK));
161 BuildMI(MBB, MBBI, dl, TII->get(ARC::SUB_rru6))
165 BuildMI(MBB, MBBI, dl, TII->get(ARC::BL))
174 BuildMI(MBB, MBBI, dl, TII->get(ARC::PUSH_S_BLINK));
188 TII->get(isUInt<6>(MFI.getStackSize()) ? ARC::ADD_rru6
201 BuildMI(MBB, MBBI, dl, TII->get(TargetOpcode::CFI_INSTRUCTION))
209 BuildMI(MBB, MBBI, dl, TII->get(TargetOpcode::CFI_INSTRUCTION))
218 BuildMI(MBB, MBBI, dl, TII->get(TargetOpcode::CFI_INSTRUCTION))
231 BuildMI(MBB, MBBI, dl, TII->get(TargetOpcode::CFI_INSTRUCTION))
258 BuildMI(MBB, MBBI, DebugLoc(), TII->get(Opc), ARC::SP)
288 BuildMI(MBB, MBBI, MBB.findDebugLoc(MBBI), TII->get(Opc), ARC::SP)
295 BuildMI(MBB, MBBI, MBB.findDebugLoc(MBBI), TII->get(ARC::BL))
303 BuildMI(MBB, MBBI, MBB.findDebugLoc(MBBI), TII->get(Opc), ARC::SP)
309 BuildMI(MBB, MBBI, MBB.findDebugLoc(MBBI), TII->get(ARC::POP_S_BLINK));
313 BuildMI(MBB, MBBI, MBB.findDebugLoc(MBBI), TII->get(ARC::LD_AB_rs9))
330 BuildMI(MBB, MBBI, MBB.findDebugLoc(MBBI), TII->get(Opc))
464 BuildMI(MBB, MBBI, dl, TII->get(Opc), Reg)
lib/Target/ARC/ARCInstrInfo.cpp 289 BuildMI(MBB, I, dl, get(ARC::MOV_rr), DestReg)
315 BuildMI(MBB, I, dl, get(ARC::ST_rs9))
342 BuildMI(MBB, I, dl, get(ARC::LD_rs9))
363 return BuildMI(MBB, MI, dl, get(ARC::MOV_rs12), Reg)
383 BuildMI(&MBB, dl, get(ARC::BR)).addMBB(TBB);
387 MachineInstrBuilder MIB = BuildMI(&MBB, dl, get(BccOpc));
399 BuildMI(&MBB, dl, get(ARC::BR)).addMBB(FBB);
lib/Target/ARC/ARCOptAddrMode.cpp 458 Ldst.setDesc(AST->getInstrInfo()->get(NewOpcode));
lib/Target/ARC/ARCRegisterInfo.cpp 50 BuildMI(MBB, II, dl, TII.get(ARC::LD_rlimm), Reg)
75 BuildMI(MBB, II, dl, TII.get(AddOpc))
93 BuildMI(MBB, II, dl, TII.get(MI.getOpcode()), Reg)
106 BuildMI(MBB, II, dl, TII.get(MI.getOpcode()))
115 TII.get(isUInt<6>(Offset) ? ARC::ADD_rru6 : ARC::ADD_rrlimm))
lib/Target/ARM/A15SDOptimizer.cpp 424 TII->get(QPR ? ARM::VDUPLN32q : ARM::VDUPLN32d), Out)
441 TII->get(TargetOpcode::COPY), Out)
455 TII->get(TargetOpcode::REG_SEQUENCE), Out)
470 BuildMI(MBB, InsertBefore, DL, TII->get(ARM::VEXTd32), Out)
485 TII->get(TargetOpcode::INSERT_SUBREG), Out)
501 TII->get(TargetOpcode::IMPLICIT_DEF), Out);
lib/Target/ARM/ARMBaseInstrInfo.cpp 191 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
200 get(isSub ? ARM::SUBrsi : ARM::ADDrsi), WBReg)
209 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
222 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
229 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
242 BuildMI(MF, MI.getDebugLoc(), get(MemOpc), MI.getOperand(0).getReg())
247 MemMI = BuildMI(MF, MI.getDebugLoc(), get(MemOpc))
258 BuildMI(MF, MI.getDebugLoc(), get(MemOpc), MI.getOperand(0).getReg())
263 MemMI = BuildMI(MF, MI.getDebugLoc(), get(MemOpc))
452 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB).add(predOps(ARMCC::AL));
454 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
456 BuildMI(&MBB, DL, get(BccOpc))
464 BuildMI(&MBB, DL, get(BccOpc))
469 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB).add(predOps(ARMCC::AL));
471 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
502 MI.setDesc(get(getMatchingCondBranchOpcode(Opc)));
777 BuildMI(MBB, I, I->getDebugLoc(), get(Opc), DestReg);
796 MachineInstrBuilder MIB = BuildMI(MBB, I, I->getDebugLoc(), get(Opc));
838 BuildMI(MBB, I, DL, get(ARM::MOVr), DestReg)
861 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg);
931 BuildMI(MBB, I, I->getDebugLoc(), get(ARM::VMSR_P0), DestReg)
937 BuildMI(MBB, I, I->getDebugLoc(), get(ARM::VMRS_P0), DestReg)
943 BuildMI(MBB, I, I->getDebugLoc(), get(ARM::VMSR_FPSCR_NZCVQC), DestReg)
949 BuildMI(MBB, I, I->getDebugLoc(), get(ARM::VMRS_FPSCR_NZCVQC), DestReg)
976 Mov = BuildMI(MBB, I, I->getDebugLoc(), get(Opc), Dst).addReg(Src);
1043 BuildMI(MBB, I, DebugLoc(), get(ARM::VSTRH))
1054 BuildMI(MBB, I, DebugLoc(), get(ARM::STRi12))
1061 BuildMI(MBB, I, DebugLoc(), get(ARM::VSTRS))
1068 BuildMI(MBB, I, DebugLoc(), get(ARM::VSTR_P0_off))
1079 BuildMI(MBB, I, DebugLoc(), get(ARM::VSTRD))
1087 MachineInstrBuilder MIB = BuildMI(MBB, I, DebugLoc(), get(ARM::STRD));
1095 MachineInstrBuilder MIB = BuildMI(MBB, I, DebugLoc(), get(ARM::STMIA))
1109 BuildMI(MBB, I, DebugLoc(), get(ARM::VST1q64))
1116 BuildMI(MBB, I, DebugLoc(), get(ARM::VSTMQIA))
1124 auto MIB = BuildMI(MBB, I, DebugLoc(), get(ARM::MVE_VSTRWU32));
1138 BuildMI(MBB, I, DebugLoc(), get(ARM::VST1d64TPseudo))
1146 get(ARM::VSTMDIA))
1163 BuildMI(MBB, I, DebugLoc(), get(ARM::VST1d64QPseudo))
1171 get(ARM::VSTMDIA))
1185 MachineInstrBuilder MIB = BuildMI(MBB, I, DebugLoc(), get(ARM::VSTMDIA))
1285 BuildMI(MBB, I, DL, get(ARM::VLDRH), DestReg)
1295 BuildMI(MBB, I, DL, get(ARM::LDRi12), DestReg)
1301 BuildMI(MBB, I, DL, get(ARM::VLDRS), DestReg)
1307 BuildMI(MBB, I, DL, get(ARM::VLDR_P0_off), DestReg)
1317 BuildMI(MBB, I, DL, get(ARM::VLDRD), DestReg)
1326 MIB = BuildMI(MBB, I, DL, get(ARM::LDRD));
1334 MIB = BuildMI(MBB, I, DL, get(ARM::LDMIA))
1350 BuildMI(MBB, I, DL, get(ARM::VLD1q64), DestReg)
1356 BuildMI(MBB, I, DL, get(ARM::VLDMQIA), DestReg)
1363 auto MIB = BuildMI(MBB, I, DL, get(ARM::MVE_VLDRWU32), DestReg);
1375 BuildMI(MBB, I, DL, get(ARM::VLD1d64TPseudo), DestReg)
1381 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
1398 BuildMI(MBB, I, DL, get(ARM::VLD1d64QPseudo), DestReg)
1404 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
1420 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
1524 LDM = BuildMI(*BB, MI, dl, TII->get(isThumb2 ? ARM::t2LDMIA_UPD
1529 LDM = BuildMI(*BB, MI, dl, TII->get(isThumb2 ? ARM::t2LDMIA : ARM::LDMIA));
1534 STM = BuildMI(*BB, MI, dl, TII->get(isThumb2 ? ARM::t2STMIA_UPD
1539 STM = BuildMI(*BB, MI, dl, TII->get(isThumb2 ? ARM::t2STMIA : ARM::STMIA));
1624 MI.setDesc(get(ARM::VMOVD));
1710 BuildMI(MBB, I, Orig.getDebugLoc(), get(Opcode), DestReg)
2365 BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), DestReg)
2388 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
2536 MI.setDesc(TII.get(ARM::MOVr));
2544 MI.setDesc(TII.get(ARM::SUBri));
3318 BuildMI(*UseMI.getParent(), UseMI, UseMI.getDebugLoc(), get(NewUseOpc),
3324 UseMI.setDesc(get(NewUseOpc));
4356 const MCInstrDesc &DefMCID = get(DefNode->getMachineOpcode());
4371 const MCInstrDesc &UseMCID = get(UseNode->getMachineOpcode());
4687 return ItinData->getStageLatency(get(Opcode).getSchedClass());
4780 BuildMI(MBB, MI, DL, get(LoadImmOpc), Reg)
4784 MIB = BuildMI(MBB, MI, DL, get(LoadOpc), Reg);
4794 MIB = BuildMI(MBB, MI, DL, get(LoadOpc), Reg);
4956 MI.setDesc(get(ARM::VORRd));
4979 MI.setDesc(get(ARM::VGETLNi32));
5009 MI.setDesc(get(ARM::VSETLNi32));
5045 MI.setDesc(get(ARM::VDUPLN32d));
5073 NewMIB = BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(ARM::VEXTd32),
5092 MI.setDesc(get(ARM::VEXTd32));
5225 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(ARM::FCONSTD), DReg)
lib/Target/ARM/ARMBaseRegisterInfo.cpp 469 BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp))
645 const MCInstrDesc &MCID = TII.get(ADDriOpc);
lib/Target/ARM/ARMConstantIslandPass.cpp 531 BuildMI(*BB, InsAt, DebugLoc(), TII->get(ARM::CONSTPOOL_ENTRY))
599 DebugLoc(), TII->get(JTOpcode))
911 BuildMI(OrigBB, DebugLoc(), TII->get(Opc)).addMBB(NewBB);
913 BuildMI(OrigBB, DebugLoc(), TII->get(Opc))
1297 BuildMI(UserMBB, DebugLoc(), TII->get(UncondBr)).addMBB(NewMBB);
1299 BuildMI(UserMBB, DebugLoc(), TII->get(UncondBr))
1632 MI->setDesc(TII->get(ARM::tBfar));
1717 BuildMI(MBB, DebugLoc(), TII->get(MI->getOpcode()))
1722 BuildMI(MBB, DebugLoc(), TII->get(Br.UncondBr))
1726 BuildMI(MBB, DebugLoc(), TII->get(Br.UncondBr)).addMBB(DestBB);
1750 BuildMI(MI->getParent(), MI->getDebugLoc(), TII->get(ARM::tBX_RET))
1807 U.MI->setDesc(TII->get(NewOpc));
1845 Br.MI->setDesc(TII->get(NewOpc));
1919 TII->get(ARM::t2LE));
1973 BuildMI(*MBB, Br.MI, Br.MI->getDebugLoc(), TII->get(Cmp.NewOpc))
2296 BuildMI(*MBB, MI_JT, MI->getDebugLoc(), TII->get(Opc))
2305 CPEMI->setDesc(TII->get(JTOpc));
2437 BuildMI(NewBB, DebugLoc(), TII->get(ARM::t2B))
2441 BuildMI(NewBB, DebugLoc(), TII->get(ARM::tB))
lib/Target/ARM/ARMExpandPseudoInsts.cpp 480 TII->get(TableEntry->RealOpc));
591 TII->get(TableEntry->RealOpc));
668 TII->get(TableEntry->RealOpc));
752 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc));
846 LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVi), DstReg);
847 HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::ORRri))
878 LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(LO16Opc), DstReg);
879 HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(HI16Opc))
955 BuildMI(MBB, MBBI, DL, TII->get(UxtOp), DesiredReg)
968 MIB = BuildMI(LoadCmpBB, DL, TII->get(LdrexOp), Dest.getReg());
975 BuildMI(LoadCmpBB, DL, TII->get(CMPrr))
980 BuildMI(LoadCmpBB, DL, TII->get(Bcc))
991 MIB = BuildMI(StoreBB, DL, TII->get(StrexOp), TempReg)
999 BuildMI(StoreBB, DL, TII->get(CMPri))
1003 BuildMI(StoreBB, DL, TII->get(Bcc))
1085 MIB = BuildMI(LoadCmpBB, DL, TII->get(LDREXD));
1090 BuildMI(LoadCmpBB, DL, TII->get(CMPrr))
1095 BuildMI(LoadCmpBB, DL, TII->get(CMPrr))
1101 BuildMI(LoadCmpBB, DL, TII->get(Bcc))
1113 MIB = BuildMI(StoreBB, DL, TII->get(STREXD), TempReg);
1119 BuildMI(StoreBB, DL, TII->get(CMPri))
1123 BuildMI(StoreBB, DL, TII->get(Bcc))
1182 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(TCOpcode));
1200 TII.get(Opcode))
1219 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(newOpc),
1232 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc),
1244 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsi),
1257 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsr),
1273 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc),
1285 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc),
1299 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc),
1322 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc),
1369 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(bicOpc), ARM::R6)
1384 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsi),
1397 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsi),
1421 TII->get(Thumb ? ARM::tLDRpci : ARM::LDRi12), Reg)
1428 TII->get(Thumb ? ARM::tBLXr : ARM::BLX));
1434 TII->get(Thumb ? ARM::tBL : ARM::BL));
1453 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewLdOpc), DstReg)
1458 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::tPICADD))
1505 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(LDRLITOpc), DstReg)
1513 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(PICAddOpc))
1544 TII->get(LO16Opc), DstReg)
1548 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(HI16Opc), DstReg)
1554 TII->get(PICAddOpc))
1576 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::SUBri), ARM::PC)
1589 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc));
1620 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc));
1932 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::tPUSH))
1937 MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::tBL));
1940 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::STMDB_UPD))
1947 MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::BL));
lib/Target/ARM/ARMFastISel.cpp 305 const MCInstrDesc &II = TII.get(MachineInstOpcode);
317 TII.get(TargetOpcode::COPY), ResultReg)
328 const MCInstrDesc &II = TII.get(MachineInstOpcode);
345 TII.get(TargetOpcode::COPY), ResultReg)
356 const MCInstrDesc &II = TII.get(MachineInstOpcode);
371 TII.get(TargetOpcode::COPY), ResultReg)
381 const MCInstrDesc &II = TII.get(MachineInstOpcode);
390 TII.get(TargetOpcode::COPY), ResultReg)
403 TII.get(ARM::VMOVSR), MoveReg)
413 TII.get(ARM::VMOVRS), MoveReg)
439 TII.get(Opc), DestReg).addImm(Imm));
458 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg)
477 TII.get(Opc), ImmReg)
493 TII.get(Opc), ImmReg)
520 TII.get(ARM::t2LDRpci), ResultReg)
524 ResultReg = constrainOperandRegClass(TII.get(ARM::LDRcp), ResultReg, 0);
526 TII.get(ARM::LDRcp), ResultReg)
570 TII.get(Opc), DestReg).addGlobalAddress(GV, 0, TF));
594 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc),
601 DestReg = constrainOperandRegClass(TII.get(ARM::LDRcp), DestReg, 0);
603 TII.get(ARM::LDRcp), DestReg)
613 DbgLoc, TII.get(Opc), NewDestReg)
627 TII.get(ARM::t2LDRi12), NewDestReg)
632 TII.get(ARM::LDRi12), NewDestReg)
677 ResultReg = constrainOperandRegClass(TII.get(Opc), ResultReg, 0);
680 TII.get(Opc), ResultReg)
854 TII.get(Opc), ResultReg)
1004 TII.get(Opc), ResultReg);
1012 TII.get(ARM::VMOVSR), MoveReg)
1066 SrcReg = constrainOperandRegClass(TII.get(Opc), SrcReg, 1);
1068 TII.get(Opc), Res)
1116 TII.get(ARM::VMOVRS), MoveReg)
1140 SrcReg = constrainOperandRegClass(TII.get(StrOpc), SrcReg, 0);
1142 TII.get(StrOpc))
1266 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(BrOpc))
1277 OpReg = constrainOperandRegClass(TII.get(TstOpc), OpReg, 0);
1279 TII.get(TstOpc))
1289 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(BrOpc))
1314 CmpReg = constrainOperandRegClass(TII.get(TstOpc), CmpReg, 0);
1316 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TstOpc))
1327 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(BrOpc))
1341 TII.get(Opc)).addReg(AddrReg));
1444 const MCInstrDesc &II = TII.get(CmpOpc);
1465 TII.get(ARM::FMSTAT)));
1491 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(MovCCOpc), DestReg)
1512 TII.get(ARM::VCVTDS), Result)
1531 TII.get(ARM::VCVTSD), Result)
1577 TII.get(Opc), ResultReg).addReg(FP));
1604 TII.get(Opc), ResultReg).addReg(Op));
1650 CondReg = constrainOperandRegClass(TII.get(TstOpc), CondReg, 0);
1652 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TstOpc))
1670 Op2Reg = constrainOperandRegClass(TII.get(MovCCOpc), Op2Reg, 1);
1671 Op1Reg = constrainOperandRegClass(TII.get(MovCCOpc), Op1Reg, 2);
1672 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(MovCCOpc),
1679 Op1Reg = constrainOperandRegClass(TII.get(MovCCOpc), Op1Reg, 1);
1680 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(MovCCOpc),
1780 SrcReg1 = constrainOperandRegClass(TII.get(Opc), SrcReg1, 1);
1781 SrcReg2 = constrainOperandRegClass(TII.get(Opc), SrcReg2, 2);
1783 TII.get(Opc), ResultReg)
1830 TII.get(Opc), ResultReg)
1948 TII.get(AdjStackDown))
1994 TII.get(TargetOpcode::COPY), VA.getLocReg()).addReg(Arg);
2008 TII.get(ARM::VMOVRRD), VA.getLocReg())
2040 TII.get(AdjStackUp))
2057 TII.get(ARM::VMOVDRR), ResultReg)
2078 TII.get(TargetOpcode::COPY),
2163 TII.get(TargetOpcode::COPY), DstReg).addReg(SrcReg);
2170 TII.get(Subtarget->getReturnOpcode()));
2266 DbgLoc, TII.get(CallOpc));
2407 DbgLoc, TII.get(CallOpc));
2512 TII.get(LdrOpc), DestReg)
2569 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(
2722 *FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opcode), ResultReg);
2725 SrcReg = constrainOperandRegClass(TII.get(Opcode), SrcReg, 1 + setsCPSR);
2803 TII.get(Opc), ResultReg)
2970 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), TempReg)
2981 DestReg = constrainOperandRegClass(TII.get(Opc), DestReg, 0);
2982 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg)
2992 TII.get(ARM::t2LDRi12), NewDestReg)
3065 TII.get(TargetOpcode::COPY),
lib/Target/ARM/ARMFrameLowering.cpp 263 TII.get(TargetOpcode::CFI_INSTRUCTION))
303 BuildMI(MBB, MBBI, DL, TII.get(ARM::BFC), Reg)
308 BuildMI(MBB, MBBI, DL, TII.get(ARM::BICri), Reg)
318 BuildMI(MBB, MBBI, DL, TII.get(ARM::MOVsi), Reg)
323 BuildMI(MBB, MBBI, DL, TII.get(ARM::MOVsi), Reg)
333 BuildMI(MBB, MBBI, DL, TII.get(ARM::t2BFC), Reg)
522 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi16), ARM::R4)
527 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi32imm), ARM::R4)
537 BuildMI(MBB, MBBI, dl, TII.get(ARM::tBL))
544 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi32imm), ARM::R12)
548 BuildMI(MBB, MBBI, dl, TII.get(ARM::tBLXr))
556 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2SUBrr), ARM::SP)
605 BuildMI(MBB, AfterPush, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
612 BuildMI(MBB, AfterPush, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
647 BuildMI(MBB, Pos, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
671 BuildMI(MBB, Pos, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
693 BuildMI(MBB, Pos, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
733 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::R4)
738 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP)
753 BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), RegInfo->getBaseRegister())
758 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), RegInfo->getBaseRegister())
835 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP)
842 BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), ARM::SP)
847 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP)
1024 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(StmOpc), ARM::SP)
1031 BuildMI(MBB, MI, DL, TII.get(StrOpc), ARM::SP)
1120 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(LdmOpc), ARM::SP)
1138 BuildMI(MBB, MI, DL, TII.get(LdrOpc), Regs[0])
1209 BuildMI(MBB, MI, DL, TII.get(Opc), ARM::R4)
1228 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(Opc), ARM::SP)
1244 BuildMI(MBB, MI, DL, TII.get(ARM::VST1d64Qwb_fixed), ARM::R4)
1263 BuildMI(MBB, MI, DL, TII.get(ARM::VST1d64Q))
1278 BuildMI(MBB, MI, DL, TII.get(ARM::VST1q64))
1291 BuildMI(MBB, MI, DL, TII.get(ARM::VSTRD))
1362 BuildMI(MBB, MI, DL, TII.get(Opc), ARM::R4)
1375 BuildMI(MBB, MI, DL, TII.get(ARM::VLD1d64Qwb_fixed), NextReg)
1393 BuildMI(MBB, MI, DL, TII.get(ARM::VLD1d64Q), NextReg)
1406 BuildMI(MBB, MI, DL, TII.get(ARM::VLD1q64), SupReg)
1416 BuildMI(MBB, MI, DL, TII.get(ARM::VLDRD), NextReg)
2352 BuildMI(PrevStackMBB, DL, TII.get(ARM::tPUSH))
2357 BuildMI(PrevStackMBB, DL, TII.get(ARM::STMDB_UPD))
2369 BuildMI(PrevStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
2373 BuildMI(PrevStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
2377 BuildMI(PrevStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
2382 BuildMI(McrMBB, DL, TII.get(ARM::tMOVr), ScratchReg1)
2386 BuildMI(McrMBB, DL, TII.get(ARM::MOVr), ScratchReg1)
2394 BuildMI(McrMBB, DL, TII.get(ARM::tSUBi8), ScratchReg1)
2400 BuildMI(McrMBB, DL, TII.get(ARM::SUBri), ScratchReg1)
2415 BuildMI(GetMBB, DL, TII.get(ARM::tLDRpci), ScratchReg0)
2420 BuildMI(GetMBB, DL, TII.get(ARM::tLDRi), ScratchReg0)
2427 BuildMI(McrMBB, DL, TII.get(ARM::MRC), ScratchReg0)
2441 BuildMI(GetMBB, DL, TII.get(ARM::LDRi12), ScratchReg0)
2450 BuildMI(GetMBB, DL, TII.get(Opcode))
2457 BuildMI(GetMBB, DL, TII.get(Opcode)).addMBB(PostStackMBB)
2469 BuildMI(AllocMBB, DL, TII.get(ARM::tMOVi8), ScratchReg0)
2474 BuildMI(AllocMBB, DL, TII.get(ARM::MOVi), ScratchReg0)
2482 BuildMI(AllocMBB, DL, TII.get(ARM::tMOVi8), ScratchReg1)
2487 BuildMI(AllocMBB, DL, TII.get(ARM::MOVi), ScratchReg1)
2495 BuildMI(AllocMBB, DL, TII.get(ARM::tPUSH))
2499 BuildMI(AllocMBB, DL, TII.get(ARM::STMDB_UPD))
2510 BuildMI(AllocMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
2514 BuildMI(AllocMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
2519 BuildMI(AllocMBB, DL, TII.get(ARM::tBL))
2523 BuildMI(AllocMBB, DL, TII.get(ARM::BL))
2530 BuildMI(AllocMBB, DL, TII.get(ARM::tPOP))
2533 BuildMI(AllocMBB, DL, TII.get(ARM::tMOVr), ARM::LR)
2537 BuildMI(AllocMBB, DL, TII.get(ARM::t2LDR_POST))
2545 BuildMI(AllocMBB, DL, TII.get(ARM::LDMIA_UPD))
2557 BuildMI(AllocMBB, DL, TII.get(ARM::tPOP))
2562 BuildMI(AllocMBB, DL, TII.get(ARM::LDMIA_UPD))
2572 BuildMI(AllocMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
2576 BuildMI(AllocMBB, DL, TII.get(ST->getReturnOpcode())).add(predOps(ARMCC::AL));
2581 BuildMI(PostStackMBB, DL, TII.get(ARM::tPOP))
2586 BuildMI(PostStackMBB, DL, TII.get(ARM::LDMIA_UPD))
2596 BuildMI(PostStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
2603 BuildMI(PostStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
2607 BuildMI(PostStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
lib/Target/ARM/ARMISelDAGToDAG.cpp 449 const MCInstrDesc &MCID = TII->get(Use->getMachineOpcode());
lib/Target/ARM/ARMISelLowering.cpp 1747 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());
9379 BuildMI(*MBB, MI, dl, TII->get(ARM::t2LDRpci), NewVReg1)
9385 BuildMI(*MBB, MI, dl, TII->get(ARM::t2ORRri), NewVReg2)
9391 BuildMI(*MBB, MI, dl, TII->get(ARM::tPICADD), NewVReg3)
9394 BuildMI(*MBB, MI, dl, TII->get(ARM::t2STRi12))
9409 BuildMI(*MBB, MI, dl, TII->get(ARM::tLDRpci), NewVReg1)
9414 BuildMI(*MBB, MI, dl, TII->get(ARM::tPICADD), NewVReg2)
9419 BuildMI(*MBB, MI, dl, TII->get(ARM::tMOVi8), NewVReg3)
9424 BuildMI(*MBB, MI, dl, TII->get(ARM::tORR), NewVReg4)
9430 BuildMI(*MBB, MI, dl, TII->get(ARM::tADDframe), NewVReg5)
9433 BuildMI(*MBB, MI, dl, TII->get(ARM::tSTRi))
9445 BuildMI(*MBB, MI, dl, TII->get(ARM::LDRi12), NewVReg1)
9451 BuildMI(*MBB, MI, dl, TII->get(ARM::PICADD), NewVReg2)
9455 BuildMI(*MBB, MI, dl, TII->get(ARM::STRi12))
9538 BuildMI(TrapBB, dl, TII->get(trap_opcode));
9558 MIB = BuildMI(DispatchBB, dl, TII->get(ARM::Int_eh_sjlj_dispatchsetup));
9573 BuildMI(DispatchBB, dl, TII->get(ARM::t2LDRi12), NewVReg1)
9580 BuildMI(DispatchBB, dl, TII->get(ARM::t2CMPri))
9586 BuildMI(DispatchBB, dl, TII->get(ARM::t2MOVi16), VReg1)
9593 BuildMI(DispatchBB, dl, TII->get(ARM::t2MOVTi16), VReg2)
9599 BuildMI(DispatchBB, dl, TII->get(ARM::t2CMPrr))
9605 BuildMI(DispatchBB, dl, TII->get(ARM::t2Bcc))
9611 BuildMI(DispContBB, dl, TII->get(ARM::t2LEApcrelJT), NewVReg3)
9616 BuildMI(DispContBB, dl, TII->get(ARM::t2ADDrs), NewVReg4)
9623 BuildMI(DispContBB, dl, TII->get(ARM::t2BR_JT))
9629 BuildMI(DispatchBB, dl, TII->get(ARM::tLDRspi), NewVReg1)
9636 BuildMI(DispatchBB, dl, TII->get(ARM::tCMPi8))
9652 BuildMI(DispatchBB, dl, TII->get(ARM::tLDRpci))
9656 BuildMI(DispatchBB, dl, TII->get(ARM::tCMPr))
9662 BuildMI(DispatchBB, dl, TII->get(ARM::tBcc))
9668 BuildMI(DispContBB, dl, TII->get(ARM::tLSLri), NewVReg2)
9675 BuildMI(DispContBB, dl, TII->get(ARM::tLEApcrelJT), NewVReg3)
9680 BuildMI(DispContBB, dl, TII->get(ARM::tADDrr), NewVReg4)
9690 BuildMI(DispContBB, dl, TII->get(ARM::tLDRi), NewVReg5)
9699 BuildMI(DispContBB, dl, TII->get(ARM::tADDrr), NewVReg6)
9706 BuildMI(DispContBB, dl, TII->get(ARM::tBR_JTr))
9711 BuildMI(DispatchBB, dl, TII->get(ARM::LDRi12), NewVReg1)
9718 BuildMI(DispatchBB, dl, TII->get(ARM::CMPri))
9724 BuildMI(DispatchBB, dl, TII->get(ARM::MOVi16), VReg1)
9731 BuildMI(DispatchBB, dl, TII->get(ARM::MOVTi16), VReg2)
9737 BuildMI(DispatchBB, dl, TII->get(ARM::CMPrr))
9753 BuildMI(DispatchBB, dl, TII->get(ARM::LDRcp))
9758 BuildMI(DispatchBB, dl, TII->get(ARM::CMPrr))
9764 BuildMI(DispatchBB, dl, TII->get(ARM::Bcc))
9770 BuildMI(DispContBB, dl, TII->get(ARM::MOVsi), NewVReg3)
9776 BuildMI(DispContBB, dl, TII->get(ARM::LEApcrelJT), NewVReg4)
9783 BuildMI(DispContBB, dl, TII->get(ARM::LDRrs), NewVReg5)
9791 BuildMI(DispContBB, dl, TII->get(ARM::BR_JTadd))
9796 BuildMI(DispContBB, dl, TII->get(ARM::BR_JTr))
9933 BuildMI(*BB, Pos, dl, TII->get(LdOpc), Data)
9940 BuildMI(*BB, Pos, dl, TII->get(LdOpc), Data)
9944 BuildMI(*BB, Pos, dl, TII->get(ARM::tADDi8), AddrOut)
9950 BuildMI(*BB, Pos, dl, TII->get(LdOpc), Data)
9956 BuildMI(*BB, Pos, dl, TII->get(LdOpc), Data)
9974 BuildMI(*BB, Pos, dl, TII->get(StOpc), AddrOut)
9981 BuildMI(*BB, Pos, dl, TII->get(StOpc))
9986 BuildMI(*BB, Pos, dl, TII->get(ARM::tADDi8), AddrOut)
9992 BuildMI(*BB, Pos, dl, TII->get(StOpc), AddrOut)
9998 BuildMI(*BB, Pos, dl, TII->get(StOpc), AddrOut)
10134 BuildMI(BB, dl, TII->get(IsThumb ? ARM::t2MOVi16 : ARM::MOVi16), Vtmp)
10139 BuildMI(BB, dl, TII->get(IsThumb ? ARM::t2MOVTi16 : ARM::MOVTi16), varEnd)
10158 BuildMI(*BB, MI, dl, TII->get(ARM::tLDRpci))
10164 BuildMI(*BB, MI, dl, TII->get(ARM::LDRcp))
10186 BuildMI(*BB, BB->begin(), dl, TII->get(ARM::PHI), varPhi)
10189 BuildMI(BB, dl, TII->get(ARM::PHI), srcPhi)
10192 BuildMI(BB, dl, TII->get(ARM::PHI), destPhi)
10206 BuildMI(*BB, BB->end(), dl, TII->get(ARM::tSUBi8), varLoop)
10214 TII->get(IsThumb2 ? ARM::t2SUBri : ARM::SUBri), varLoop);
10223 TII->get(IsThumb1 ? ARM::tBcc : IsThumb2 ? ARM::t2Bcc : ARM::Bcc))
10289 BuildMI(*MBB, MI, DL, TII.get(ARM::tBL))
10303 BuildMI(*MBB, MI, DL, TII.get(ARM::t2MOVi32imm), Reg)
10305 BuildMI(*MBB, MI, DL, TII.get(ARM::tBLXr))
10318 BuildMI(*MBB, MI, DL, TII.get(ARM::t2SUBrr), ARM::SP)
10344 BuildMI(TrapBB, DL, TII->get(ARM::t__brkdiv0));
10348 BuildMI(*MBB, MI, DL, TII->get(ARM::tCMPi8))
10352 BuildMI(*MBB, MI, DL, TII->get(ARM::t2Bcc))
10412 BuildMI(*BB, MI, dl, TII->get(ARM::tLDMIA_UPD))
10427 MI.setDesc(TII->get(ARM::t2STR_PRE));
10430 MI.setDesc(TII->get(ARM::t2STRB_PRE));
10433 MI.setDesc(TII->get(ARM::t2STRH_PRE));
10448 BuildMI(*BB, MI, dl, TII->get(NewOpc))
10469 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(NewOpc));
10513 BuildMI(BB, dl, TII->get(ARM::tBcc))
10530 BuildMI(*BB, BB->begin(), dl, TII->get(ARM::PHI), MI.getOperand(0).getReg())
10552 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
10556 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
10562 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
10566 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
10576 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
10579 BuildMI(BB, dl, TII->get(ARM::t2B))
10583 BuildMI(BB, dl, TII->get(ARM::B)) .addMBB(exitMBB);
10644 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
10651 TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc)).addMBB(SinkBB)
10658 TII->get(isThumb2 ? ARM::t2RSBri : ARM::RSBri), NewRsbDstReg)
10667 TII->get(ARM::PHI), ABSDstReg)
10735 MCID = &TII->get(NewOpc);
17125 BuildMI(*Entry, MBBI, DebugLoc(), TII->get(TargetOpcode::COPY), NewVR)
17131 TII->get(TargetOpcode::COPY), *I)
lib/Target/ARM/ARMInstrInfo.cpp 123 MIB = BuildMI(MBB, MI, DL, get(ARM::MOV_ga_pcrel_ldr), Reg)
131 BuildMI(MBB, MI, DL, get(ARM::LDRi12), Reg)
lib/Target/ARM/ARMInstructionSelector.cpp 255 MIB->setDesc(TII.get(ARM::VMOVDRR));
287 MIB->setDesc(TII.get(ARM::VMOVRRD));
493 (void)BuildMI(I.MBB, I.InsertBefore, I.DbgLoc, TII.get(Opcodes.MOVi))
579 BuildMI(I.MBB, I.InsertBefore, I.DbgLoc, TII.get(Helper.ComparisonOpcode))
589 TII.get(Helper.ReadFlagsOpcode))
597 TII.get(Helper.SelectResultOpcode))
676 MIB->setDesc(TII.get(Opc));
694 TII.get(Opcodes.LOAD32))
714 MIB->setDesc(TII.get(Opc));
722 TII.get(Opcodes.MOVi32imm), Offset);
727 TII.get(Opcodes.ConstPoolLoad), Offset);
734 MIB->setDesc(TII.get(Opcodes.ADDrr));
746 MIB->setDesc(TII.get(Opcodes.MOVi32imm));
749 MIB->setDesc(TII.get(Opcodes.ConstPoolLoad));
755 MIB->setDesc(TII.get(Opcodes.MOVi32imm));
757 MIB->setDesc(TII.get(Opcodes.LDRLIT_ga_abs));
776 auto CmpI = BuildMI(MBB, InsertBefore, DbgLoc, TII.get(Opcodes.TSTri))
791 auto Mov1I = BuildMI(MBB, InsertBefore, DbgLoc, TII.get(Opcodes.MOVCCr))
806 MIB->setDesc(TII.get(ARM::MOVsr));
872 I.setDesc(TII.get(Opcodes.AND));
884 BuildMI(MBB, InsertBefore, I.getDebugLoc(), TII.get(Opcodes.RSB))
900 I.setDesc(TII.get(NewOpc));
933 BuildMI(MBB, InsertBefore, I.getDebugLoc(), TII.get(ARM::VMOVRRD))
956 I.setDesc(TII.get(COPY));
982 I.setDesc(TII.get(ARM::MOVi));
997 MIB->setDesc(TII.get(LoadOpcode));
1028 I.setDesc(TII.get(COPY));
1065 I.setDesc(TII.get(Opcodes.ADDrr));
1071 I.setDesc(TII.get(Opcodes.ADDri));
1105 auto AndI = BuildMI(MBB, InsertBefore, I.getDebugLoc(), TII.get(Opcodes.AND))
1115 I.setDesc(TII.get(NewOpc));
1141 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Opcodes.TSTri))
1150 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Opcodes.Bcc))
1159 I.setDesc(TII.get(PHI));
lib/Target/ARM/ARMLoadStoreOptimizer.cpp 550 BuildMI(MBB, MBBI, DL, TII->get(ARM::tSUBi8), Base)
571 BuildMI(MBB, MBBI, DL, TII->get(ARM::tSUBi8), Base)
736 BuildMI(MBB, InsertBefore, DL, TII->get(ARM::tMOVSr), NewBase)
739 BuildMI(MBB, InsertBefore, DL, TII->get(ARM::tMOVr), NewBase)
749 BuildMI(MBB, InsertBefore, DL, TII->get(BaseOpc), NewBase)
754 BuildMI(MBB, InsertBefore, DL, TII->get(BaseOpc), NewBase)
760 BuildMI(MBB, InsertBefore, DL, TII->get(BaseOpc), NewBase)
799 MIB = BuildMI(MBB, InsertBefore, DL, TII->get(Opcode));
811 MIB = BuildMI(MBB, InsertBefore, DL, TII->get(Opcode));
837 TII->get(LoadStoreOpcode));
1317 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(NewOpc))
1441 BuildMI(MBB, MBBI, DL, TII->get(NewOpc))
1452 BuildMI(MBB, MBBI, DL, TII->get(NewOpc), MI->getOperand(0).getReg())
1458 BuildMI(MBB, MBBI, DL, TII->get(NewOpc), MI->getOperand(0).getReg())
1468 BuildMI(MBB, MBBI, DL, TII->get(NewOpc), MI->getOperand(0).getReg())
1483 BuildMI(MBB, MBBI, DL, TII->get(NewOpc), Base)
1492 BuildMI(MBB, MBBI, DL, TII->get(NewOpc), Base)
1541 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(NewOpc));
1550 assert(TII->get(Opcode).getNumOperands() == 6 &&
1551 TII->get(NewOpc).getNumOperands() == 7 &&
1629 TII->get(NewOpc))
1638 TII->get(NewOpc))
1698 BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII->get(NewOpc))
1706 BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII->get(NewOpc))
1949 PrevMI.setDesc(TII->get(NewOpc));
1984 BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII->get(ARM::tBX))
2322 const MCInstrDesc &MCID = TII->get(NewOpc);
lib/Target/ARM/ARMLowOverheadLoops.cpp 363 TII->get(ARM::t2CMPri));
373 MIB = BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(BrOpc));
396 TII->get(ARM::t2SUBri));
421 TII->get(ARM::t2CMPri));
434 BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(BrOpc));
452 BuildMI(*MBB, InsertPt, InsertPt->getDebugLoc(), TII->get(Opc));
471 TII->get(ARM::t2LEUpdate));
lib/Target/ARM/AsmParser/ARMAsmParser.cpp 7298 const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
10187 const MCInstrDesc &MCID = MII.get(Opc);
10304 const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
10337 const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
10361 const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
10388 const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp 1871 const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp 268 if (Info->get(Inst.getOpcode()).OpInfo[0].OperandType!=MCOI::OPERAND_PCREL)
298 if (Info->get(Inst.getOpcode()).OpInfo[OpId].OperandType !=
lib/Target/ARM/MLxExpansionPass.cpp 284 const MCInstrDesc &MCID1 = TII->get(MulOpc);
285 const MCInstrDesc &MCID2 = TII->get(AddSubOpc);
lib/Target/ARM/MVEVPTBlockPass.cpp 236 MIBuilder = BuildMI(Block, MI, dl, TII->get(NewOpcode));
243 MIBuilder = BuildMI(Block, MI, dl, TII->get(ARM::MVE_VPST));
lib/Target/ARM/Thumb1FrameLowering.cpp 84 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi32imm), ScratchReg)
90 BuildMI(MBB, MBBI, dl, TII.get(ARM::tADDhirr), ARM::SP)
186 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
199 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
263 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
291 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
302 BuildMI(MBB, MBBI, dl, TII.get(ARM::tADDrSPi), FramePtr)
311 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
318 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
360 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
390 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
412 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::R4)
416 BuildMI(MBB, MBBI, dl, TII.get(ARM::tLSRri), ARM::R4)
422 BuildMI(MBB, MBBI, dl, TII.get(ARM::tLSLri), ARM::R4)
428 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP)
440 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), BasePtr)
519 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP)
523 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP)
638 BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII.get(ARM::tPOP_RET))
721 BuildMI(MBB, MBBI, dl, TII.get(ARM::tLDRspi))
727 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr))
743 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr))
753 BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII.get(ARM::tPOP))
768 MBBI = BuildMI(MBB, MBB.end(), dl, TII.get(ARM::tBX_RET))
773 BuildMI(MBB, MBBI, dl, TII.get(ARM::tPOP))
780 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr))
786 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr))
852 BuildMI(MBB, MI, DL, TII.get(ARM::tPUSH)).add(predOps(ARMCC::AL));
892 MachineInstrBuilder PushMIB = BuildMI(MF, DL, TII.get(ARM::tPUSH))
904 BuildMI(MBB, MI, DL, TII.get(ARM::tMOVr))
1003 BuildMI(MBB, MI, DL, TII.get(ARM::tPOP)).add(predOps(ARMCC::AL));
1010 BuildMI(MBB, MI, DL, TII.get(ARM::tMOVr))
1022 BuildMI(MF, DL, TII.get(ARM::tPOP)).add(predOps(ARMCC::AL));
1054 (*MIB).setDesc(TII.get(ARM::tPOP_RET));
lib/Target/ARM/Thumb1InstrInfo.cpp 51 BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg)
61 BuildMI(MBB, I, DL, get(ARM::tMOVSr), DestReg)
68 BuildMI(MBB, I, DL, get(ARM::tPUSH))
71 BuildMI(MBB, I, DL, get(ARM::tPOP))
96 BuildMI(MBB, I, DL, get(ARM::tSTRspi))
125 BuildMI(MBB, I, DL, get(ARM::tLDRspi), DestReg)
lib/Target/ARM/Thumb2ITBlockPass.cpp 214 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII->get(ARM::t2IT))
lib/Target/ARM/Thumb2InstrInfo.cpp 129 BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg)
149 BuildMI(MBB, I, DL, get(ARM::t2STRi12))
167 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::t2STRDi8));
191 BuildMI(MBB, I, DL, get(ARM::t2LDRi12), DestReg)
208 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::t2LDRDi8));
238 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), DestReg)
255 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi16), DestReg)
261 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVTi16), DestReg)
270 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2SUBrr), DestReg)
282 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2ADDrr), DestReg)
298 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), DestReg)
312 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
353 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
488 MI.setDesc(TII.get(ARM::tMOVr));
503 MI.setDesc(TII.get(ARM::t2SUBri));
505 MI.setDesc(TII.get(ARM::t2ADDri));
522 MI.setDesc(TII.get(NewOpc));
641 MI.setDesc(TII.get(NewOpc));
685 MI.setDesc(TII.get(positiveOffsetOpcode(NewOpc)));
lib/Target/ARM/Thumb2SizeReduction.cpp 480 auto MIB = BuildMI(MBB, MI, dl, TII->get(Entry.NarrowOpc1))
582 MachineInstrBuilder MIB = BuildMI(MBB, MI, dl, TII->get(Opc));
652 TII->get(ARM::tADDrSPi))
791 const MCInstrDesc &NewMCID = TII->get(Entry.NarrowOpc2);
884 const MCInstrDesc &NewMCID = TII->get(Entry.NarrowOpc1);
lib/Target/ARM/ThumbRegisterInfo.cpp 75 BuildMI(MBB, MBBI, dl, TII.get(ARM::tLDRpci))
94 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2LDRpci))
149 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg)
154 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg)
158 BuildMI(MBB, MBBI, dl, TII.get(ARM::tRSB), LdReg)
163 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi32imm), LdReg)
172 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg);
312 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(CopyOpc), DestReg);
329 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(ExtraOpc), DestReg);
407 MI.setDesc(TII.get(NewOpc));
528 MI.setDesc(TII.get(UseRR ? ARM::tLDRr : ARM::tLDRi));
550 MI.setDesc(TII.get(UseRR ? ARM::tSTRr : ARM::tSTRi));
lib/Target/AVR/AVRExpandPseudoInsts.cpp 63 return BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII->get(Opcode));
68 return BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII->get(Opcode), DstReg);
lib/Target/AVR/AVRFrameLowering.cpp 64 BuildMI(MBB, MBBI, DL, TII.get(AVR::BSETs))
71 BuildMI(MBB, MBBI, DL, TII.get(AVR::PUSHWRr))
80 BuildMI(MBB, MBBI, DL, TII.get(AVR::PUSHWRr))
84 BuildMI(MBB, MBBI, DL, TII.get(AVR::INRdA), AVR::R0)
87 BuildMI(MBB, MBBI, DL, TII.get(AVR::PUSHRr))
90 BuildMI(MBB, MBBI, DL, TII.get(AVR::EORRdRr))
114 BuildMI(MBB, MBBI, DL, TII.get(AVR::SPREAD), AVR::R29R28)
131 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opcode), AVR::R29R28)
139 BuildMI(MBB, MBBI, DL, TII.get(AVR::SPWRITE), AVR::SP)
170 BuildMI(MBB, MBBI, DL, TII.get(AVR::POPRd), AVR::R0);
171 BuildMI(MBB, MBBI, DL, TII.get(AVR::OUTARr))
174 BuildMI(MBB, MBBI, DL, TII.get(AVR::POPWRd), AVR::R1R0);
178 BuildMI(MBB, MBBI, DL, TII.get(AVR::POPWRd), AVR::R29R28);
208 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opcode), AVR::R29R28)
215 BuildMI(MBB, MBBI, DL, TII.get(AVR::SPWRITE), AVR::SP)
265 BuildMI(MBB, MI, DL, TII.get(AVR::PUSHRr))
295 BuildMI(MBB, MI, DL, TII.get(AVR::POPRd), Reg);
333 BuildMI(MBB, I, MI.getDebugLoc(), TII.get(AVR::PUSHRr))
336 BuildMI(MBB, I, MI.getDebugLoc(), TII.get(AVR::PUSHRr))
340 BuildMI(MBB, I, MI.getDebugLoc(), TII.get(AVR::PUSHRr))
354 MI.setDesc(TII.get(STOpc));
401 BuildMI(MBB, MI, DL, TII.get(AVR::SPREAD), AVR::R31R30).addReg(AVR::SP);
403 MachineInstr *New = BuildMI(MBB, MI, DL, TII.get(addOpcode), AVR::R31R30)
408 BuildMI(MBB, MI, DL, TII.get(AVR::SPWRITE), AVR::SP)
518 BuildMI(EntryMBB, MBBI, DL, TII.get(AVR::COPY), SPCopy).addReg(AVR::SP);
526 BuildMI(MBB, MBBI, DL, TII.get(AVR::COPY), AVR::SP)
lib/Target/AVR/AVRISelLowering.cpp 1529 BuildMI(BB, dl, TII.get(AVR::CPIRdK)).addReg(ShiftAmtSrcReg).addImm(0);
1530 BuildMI(BB, dl, TII.get(AVR::BREQk)).addMBB(RemBB);
1537 BuildMI(LoopBB, dl, TII.get(AVR::PHI), ShiftReg)
1542 BuildMI(LoopBB, dl, TII.get(AVR::PHI), ShiftAmtReg)
1548 auto ShiftMI = BuildMI(LoopBB, dl, TII.get(Opc), ShiftReg2).addReg(ShiftReg);
1552 BuildMI(LoopBB, dl, TII.get(AVR::SUBIRdK), ShiftAmtReg2)
1555 BuildMI(LoopBB, dl, TII.get(AVR::BRNEk)).addMBB(LoopBB);
1559 BuildMI(*RemBB, RemBB->begin(), dl, TII.get(AVR::PHI), DstReg)
1590 BuildMI(*BB, I, MI.getDebugLoc(), TII.get(AVR::EORRdRr), AVR::R1)
1643 BuildMI(MBB, dl, TII.get(AVR::RJMPk)).addMBB(FallThrough);
1664 BuildMI(MBB, dl, TII.get(AVR::RJMPk)).addMBB(falseMBB);
1669 BuildMI(falseMBB, dl, TII.get(AVR::RJMPk)).addMBB(trueMBB);
1673 BuildMI(*trueMBB, trueMBB->begin(), dl, TII.get(AVR::PHI), MI.getOperand(0).getReg())
lib/Target/AVR/AVRInstrInfo.cpp 52 BuildMI(MBB, MI, DL, get(AVR::MOVWRdRr), DestReg)
61 BuildMI(MBB, MI, DL, get(AVR::MOVRdRr), DestLo)
63 BuildMI(MBB, MI, DL, get(AVR::MOVRdRr), DestHi)
77 BuildMI(MBB, MI, DL, get(Opc), DestReg)
152 BuildMI(MBB, MI, DL, get(Opcode))
188 BuildMI(MBB, MI, DL, get(Opcode), DestReg)
199 return get(AVR::BREQk);
201 return get(AVR::BRNEk);
203 return get(AVR::BRGEk);
205 return get(AVR::BRLTk);
207 return get(AVR::BRSHk);
209 return get(AVR::BRLOk);
211 return get(AVR::BRMIk);
213 return get(AVR::BRPLk);
355 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(JNCC))
357 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(AVR::RJMPk))
413 auto &MI = *BuildMI(&MBB, DL, get(AVR::RJMPk)).addMBB(TBB);
429 auto &MI = *BuildMI(&MBB, DL, get(AVR::RJMPk)).addMBB(FBB);
482 const MCInstrDesc &Desc = get(Opcode);
568 auto &MI = *BuildMI(&MBB, DL, get(AVR::JMPk)).addMBB(&NewDestBB);
lib/Target/AVR/AVRRegisterInfo.cpp 153 MI.setDesc(TII.get(AVR::MOVWRdRr));
196 MachineInstr *New = BuildMI(MBB, II, dl, TII.get(Opcode), DstReg)
222 BuildMI(MBB, II, dl, TII.get(AVR::INRdA), AVR::R0).addImm(0x3f);
224 MachineInstr *New = BuildMI(MBB, II, dl, TII.get(AddOpc), AVR::R29R28)
230 BuildMI(MBB, std::next(II), dl, TII.get(AVR::OUTARr))
236 BuildMI(MBB, std::next(II), dl, TII.get(SubOpc), AVR::R29R28)
lib/Target/AVR/AVRRelaxMemOperations.cpp 54 return BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII->get(Opcode));
lib/Target/AVR/MCTargetDesc/AVRInstPrinter.cpp 103 const MCOperandInfo &MOI = this->MII.get(MI->getOpcode()).OpInfo[OpNo];
lib/Target/AVR/MCTargetDesc/AVRMCCodeEmitter.cpp 285 const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
lib/Target/BPF/BPFISelLowering.cpp 576 BuildMI(BB, DL, TII.get(BPF::MOV_32_64), PromotedReg0).addReg(Reg);
577 BuildMI(BB, DL, TII.get(BPF::SLL_ri), PromotedReg1)
579 BuildMI(BB, DL, TII.get(RShiftOp), PromotedReg2)
723 BuildMI(BB, DL, TII.get(NewCC)).addReg(LHS).addReg(RHS).addMBB(Copy1MBB);
728 BuildMI(BB, DL, TII.get(NewCC))
744 BuildMI(*BB, BB->begin(), DL, TII.get(BPF::PHI), MI.getOperand(0).getReg())
lib/Target/BPF/BPFInstrInfo.cpp 36 BuildMI(MBB, I, DL, get(BPF::MOV_rr), DestReg)
39 BuildMI(MBB, I, DL, get(BPF::MOV_rr_32), DestReg)
78 BuildMI(*BB, MI, dl, get(LdOpc))
81 BuildMI(*BB, MI, dl, get(StOpc))
92 BuildMI(*BB, MI, dl, get(BPF::LDW))
94 BuildMI(*BB, MI, dl, get(BPF::STW))
99 BuildMI(*BB, MI, dl, get(BPF::LDH))
101 BuildMI(*BB, MI, dl, get(BPF::STH))
106 BuildMI(*BB, MI, dl, get(BPF::LDB))
108 BuildMI(*BB, MI, dl, get(BPF::STB))
134 BuildMI(MBB, I, DL, get(BPF::STD))
139 BuildMI(MBB, I, DL, get(BPF::STW32))
157 BuildMI(MBB, I, DL, get(BPF::LDD), DestReg).addFrameIndex(FI).addImm(0);
159 BuildMI(MBB, I, DL, get(BPF::LDW32), DestReg).addFrameIndex(FI).addImm(0);
233 BuildMI(&MBB, DL, get(BPF::JMP)).addMBB(TBB);
lib/Target/BPF/BPFMIPeephole.cpp 170 BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(BPF::SUBREG_TO_REG), DstReg)
437 BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(BPF::MOV_rr), DstReg)
lib/Target/BPF/BPFMISimplifyPatchable.cpp 128 BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(BPF::COPY), DstReg)
lib/Target/BPF/BPFRegisterInfo.cpp 90 BuildMI(MBB, ++II, DL, TII.get(BPF::ADD_ri), reg)
110 BuildMI(MBB, ++II, DL, TII.get(BPF::MOV_rr), reg)
112 BuildMI(MBB, II, DL, TII.get(BPF::ADD_ri), reg)
lib/Target/Hexagon/HexagonBitSimplify.cpp 624 const MCInstrDesc &D = HII.get(Opc);
1347 BuildMI(B, At, DL, HII.get(TargetOpcode::COPY), NewR)
1414 BuildMI(B, At, DL, HII.get(Hexagon::A2_tfrsi), Reg)
1421 BuildMI(B, At, DL, HII.get(Hexagon::A2_tfrpi), Reg)
1430 BuildMI(B, At, DL, HII.get(Opc), Reg)
1436 BuildMI(B, At, DL, HII.get(Hexagon::CONST64), Reg)
1449 BuildMI(B, At, DL, HII.get(Opc), Reg);
1610 BuildMI(B, At, DL, HII.get(TargetOpcode::COPY), NewR)
1629 BuildMI(B, At, DL, HII.get(TargetOpcode::REG_SEQUENCE), NewR)
1875 auto *OpRC = HII.getRegClass(HII.get(Opc), OpNum, &HRI, MF);
1928 MI->setDesc(HII.get(Hexagon::S2_storerf_io));
1995 MI->setDesc(HII.get(Hexagon::S4_storeirb_io));
1998 MI->setDesc(HII.get(Hexagon::S4_storeirh_io));
2001 MI->setDesc(HII.get(Hexagon::S4_storeiri_io));
2029 BuildMI(B, At, DL, HII.get(Hexagon::S2_packhl), NewR)
2058 BuildMI(B, At, DL, HII.get(Hexagon::A2_zxth), NewR)
2064 BuildMI(B, MI, DL, HII.get(Hexagon::S2_lsr_i_r), NewR)
2100 BuildMI(B, At, DL, HII.get(COpc), NewR)
2157 auto MIB = BuildMI(B, At, DL, HII.get(NewOpc), NewR)
2299 auto NewBS = BuildMI(B, At, DL, HII.get(Hexagon::A4_bitspliti), NewR)
2360 BuildMI(B, At, DL, HII.get(Hexagon::S2_tstbit_i), NewR)
2370 BuildMI(B, At, DL, HII.get(NewOpc), NewR);
2544 auto MIB = BuildMI(B, At, DL, HII.get(ExtOpc), NewR)
2614 BuildMI(B, At, DL, HII.get(Hexagon::A2_tfrsi), NewR)
2679 BuildMI(B, At, DL, HII.get(Hexagon::C2_muxii), NewR)
3072 BuildMI(LB, At, At->getDebugLoc(), HII->get(TargetOpcode::PHI), PhiR)
3086 auto MIB = BuildMI(LB, At, DL, HII->get(SI->getOpcode()), NewDR);
3289 BuildMI(*C.PB, T, DL, HII->get(TfrI), PrehR)
lib/Target/Hexagon/HexagonCFGOptimizer.cpp 102 MI.setDesc(TII->get(NewOpcode));
lib/Target/Hexagon/HexagonConstExtenders.cpp 873 const MCInstrDesc &D = HII->get(ExtOpc);
1066 const MCInstrDesc &D = HII->get(Opc);
1114 const MCInstrDesc &D = HII->get(IdxOpc);
1542 InitI = BuildMI(MBB, At, dl, HII->get(Hexagon::PS_fi), DefR)
1549 InitI = BuildMI(MBB, At, dl, HII->get(Hexagon::A2_tfrsi), DefR)
1554 InitI = BuildMI(MBB, At, dl, HII->get(Hexagon::A2_subri), DefR)
1559 InitI = BuildMI(MBB, At, dl, HII->get(Hexagon::A2_addi), DefR)
1567 InitI = BuildMI(MBB, At, dl, HII->get(NewOpc), DefR)
1597 BuildMI(MBB, At, dl, HII->get(RegOpc))
1604 BuildMI(MBB, At, dl, HII->get(RegOpc))
1618 BuildMI(MBB, At, dl, HII->get(NewOpc))
1627 MachineInstrBuilder MIB = BuildMI(MBB, At, dl, HII->get(RegOpc));
1673 MachineInstrBuilder MIB = BuildMI(MBB, At, dl, HII->get(RegOpc));
1731 BuildMI(MBB, At, dl, HII->get(IdxOpc))
1764 BuildMI(MBB, At, dl, HII->get(TargetOpcode::COPY))
1788 BuildMI(MBB, At, dl, HII->get(NewOpc))
1799 MachineInstrBuilder MIB = BuildMI(MBB, At, dl, HII->get(IdxOpc));
lib/Target/Hexagon/HexagonConstPropagation.cpp 2502 MI.setDesc(HII.get(Hexagon::A2_nop));
2872 &HII.get(Hexagon::PS_false) :
2873 &HII.get(Hexagon::PS_true);
2900 NewD = &HII.get(Hexagon::A2_tfrsi);
2905 NewD = &HII.get(Hexagon::A2_tfrpi);
2912 NewD = &HII.get(Hexagon::A2_combineii);
2917 NewD = &HII.get(Hexagon::CONST64);
2984 NewMI = BuildMI(B, At, DL, HII.get(TargetOpcode::COPY), NewR)
3007 const MCInstrDesc &D = (V >= 0) ? HII.get(Hexagon::M2_macsip)
3008 : HII.get(Hexagon::M2_macsin);
3050 NewMI = BuildMI(B, At, DL, HII.get(TargetOpcode::COPY), NewR)
3082 NewMI = BuildMI(B, At, DL, HII.get(TargetOpcode::COPY), NewR)
3151 const MCInstrDesc &JD = HII.get(Hexagon::J2_jump);
lib/Target/Hexagon/HexagonCopyToCombine.cpp 659 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::CONST64), DoubleDestReg)
672 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A2_combineii), DoubleDestReg)
679 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineii), DoubleDestReg)
688 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A2_combineii), DoubleDestReg)
695 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineii), DoubleDestReg)
704 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A2_combineii), DoubleDestReg)
710 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineii), DoubleDestReg)
718 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A2_combineii), DoubleDestReg)
725 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineii), DoubleDestReg)
736 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A2_combineii), DoubleDestReg)
744 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineii), DoubleDestReg)
752 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A2_combineii), DoubleDestReg)
769 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineir), DoubleDestReg)
777 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineir), DoubleDestReg)
785 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineir), DoubleDestReg)
792 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineir), DoubleDestReg)
800 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineir), DoubleDestReg)
817 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineri), DoubleDestReg)
825 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineri), DoubleDestReg)
833 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineri), DoubleDestReg)
840 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineri), DoubleDestReg)
849 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineri), DoubleDestReg)
877 BuildMI(*BB, InsertPt, DL, TII->get(NewOpc), DoubleDestReg)
lib/Target/Hexagon/HexagonEarlyIfConv.cpp 722 MachineInstrBuilder MIB = BuildMI(*ToB, At, DL, HII->get(COpc));
741 const MCInstrDesc &D = HII->get(IfTrue ? Hexagon::J2_jumpt
798 const MCInstrDesc &D = HII->get(Opc);
908 BuildMI(*FP.SplitB, FP.SplitB->end(), DL, HII->get(Hexagon::J2_jump))
914 BuildMI(*FP.SplitB, FP.SplitB->end(), DL, HII->get(Hexagon::J2_jumpt))
921 const MCInstrDesc &D = HasBranch ? HII->get(Hexagon::J2_jump)
922 : HII->get(Hexagon::J2_jumpf);
934 BuildMI(*FP.SplitB, FP.SplitB->end(), DL, HII->get(Hexagon::J2_jump))
1001 NonPHI = BuildMI(*B, NonPHI, DL, HII->get(TargetOpcode::COPY), NewR)
lib/Target/Hexagon/HexagonExpandCondsets.cpp 645 MIB = BuildMI(B, At, DL, HII->get(Opc))
650 MIB = BuildMI(B, At, DL, HII->get(Opc))
694 MI.setDesc(HII->get(TargetOpcode::COPY));
873 MachineInstrBuilder MB = BuildMI(B, Where, DL, HII->get(PredOpc));
lib/Target/Hexagon/HexagonFixupHwLoops.cpp 191 MIB = BuildMI(*MBB, MII, DL, TII->get(newOp));
lib/Target/Hexagon/HexagonFrameLowering.cpp 628 BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::A2_andir), SP)
636 BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::PS_call_stk))
640 BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::A2_addi), SP)
659 BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::A2_addi), SP)
671 BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::L2_deallocframe))
674 BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::A2_add), SP)
719 BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::L2_deallocframe))
725 MachineInstr *NewI = BuildMI(MBB, RetI, dl, HII.get(NewOpc))
754 BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::S2_allocframe))
762 BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::A2_addi), SP)
766 BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::S2_allocframe))
892 const MCInstrDesc &CFID = HII.get(TargetOpcode::CFI_INSTRUCTION);
1252 BuildMI(MBB, MI, DL, HII.get(SpillOpc))
1310 DeallocCall = BuildMI(MBB, MI, DL, HII.get(RetOpc))
1323 DeallocCall = BuildMI(MBB, It, DL, HII.get(RetOpc))
1580 BuildMI(B, It, DL, HII.get(TargetOpcode::COPY), TmpR).add(MI->getOperand(1));
1581 BuildMI(B, It, DL, HII.get(TargetOpcode::COPY), DstR)
1607 BuildMI(B, It, DL, HII.get(TfrOpc), TmpR)
1611 BuildMI(B, It, DL, HII.get(Hexagon::S2_storeri_io))
1636 BuildMI(B, It, DL, HII.get(Hexagon::L2_loadri_io), TmpR)
1645 BuildMI(B, It, DL, HII.get(TfrOpc), DstR)
1673 BuildMI(B, It, DL, HII.get(Hexagon::A2_tfrsi), TmpR0)
1676 BuildMI(B, It, DL, HII.get(Hexagon::V6_vandqrt), TmpR1)
1708 BuildMI(B, It, DL, HII.get(Hexagon::A2_tfrsi), TmpR0)
1715 BuildMI(B, It, DL, HII.get(Hexagon::V6_vandvrt), DstR)
1763 BuildMI(B, It, DL, HII.get(StoreOpc))
1774 BuildMI(B, It, DL, HII.get(StoreOpc))
1809 BuildMI(B, It, DL, HII.get(LoadOpc), DstLo)
1817 BuildMI(B, It, DL, HII.get(LoadOpc), DstHi)
1845 BuildMI(B, It, DL, HII.get(StoreOpc))
1873 BuildMI(B, It, DL, HII.get(LoadOpc), DstR)
2275 CopyIn = BuildMI(B, StartIt, DL, HII.get(TargetOpcode::COPY), FoundR)
2314 CopyOut = BuildMI(B, It, DL, HII.get(CopyOpc), DstR)
2356 BuildMI(MB, AI, DL, HII.get(Hexagon::A2_sub), Rd)
2361 BuildMI(MB, AI, DL, HII.get(Hexagon::A2_sub), SP)
2367 BuildMI(MB, AI, DL, HII.get(Hexagon::A2_andir), Rd)
2371 BuildMI(MB, AI, DL, HII.get(Hexagon::A2_andir), SP)
2377 BuildMI(MB, AI, DL, HII.get(TargetOpcode::COPY), SP)
2382 BuildMI(MB, AI, DL, HII.get(Hexagon::A2_addi), Rd)
lib/Target/Hexagon/HexagonGenInsert.cpp 1415 const MCInstrDesc &D = R32 ? HII->get(Hexagon::S2_insert)
1416 : HII->get(Hexagon::S2_insertp);
lib/Target/Hexagon/HexagonGenMux.cpp 162 const MCInstrDesc &D = HII->get(Opc);
337 auto NewMux = BuildMI(B, MX.At, DL, HII->get(MxOpc), MX.DefR)
lib/Target/Hexagon/HexagonGenPredicate.cpp 274 BuildMI(B, std::next(DefIt), DL, TII->get(TargetOpcode::COPY), NewPR)
422 MachineInstrBuilder MIB = BuildMI(B, MI, DL, TII->get(NewOpc), NewPR.R);
436 BuildMI(B, MI, DL, TII->get(TargetOpcode::COPY), NewOutR)
lib/Target/Hexagon/HexagonHardwareLoops.cpp 909 const MCInstrDesc &SubD = RegToReg ? TII->get(Hexagon::A2_sub) :
910 (RegToImm ? TII->get(Hexagon::A2_subri) :
911 TII->get(Hexagon::A2_addi));
954 MCInstrDesc const &AddD = TII->get(Hexagon::A2_addi);
975 const MCInstrDesc &LsrD = TII->get(Hexagon::S2_lsr_i_r);
1248 BuildMI(*Preheader, InsertPos, DL, TII->get(TargetOpcode::COPY), CountReg)
1251 BuildMI(*Preheader, InsertPos, DL, TII->get(LOOP_r)).addMBB(LoopStart)
1261 BuildMI(*Preheader, InsertPos, DL, TII->get(Hexagon::A2_tfrsi), CountReg)
1263 BuildMI(*Preheader, InsertPos, DL, TII->get(LOOP_r))
1266 BuildMI(*Preheader, InsertPos, DL, TII->get(LOOP_i))
1280 BuildMI(*LastMBB, LastI, LastIDL, TII->get(ENDLOOP)).addMBB(LoopStart);
1592 BuildMI(B, DI, DL, TII->get(DI->getOpcode()), NewR).addImm(Val);
1902 const MCInstrDesc &PD = TII->get(TargetOpcode::PHI);
lib/Target/Hexagon/HexagonHazardRecognizer.cpp 57 MF->CreateMachineInstr(TII->get(TII->getDotNewOp(*MI)),
128 MF->CreateMachineInstr(TII->get(TII->getDotNewOp(*MI)),
lib/Target/Hexagon/HexagonISelDAGToDAG.cpp 221 uint64_t F = HII->get(LoadN->getMachineOpcode()).TSFlags;
1273 BuildMI(EntryBB, DebugLoc(), HII->get(Hexagon::PS_aligna), AR)
lib/Target/Hexagon/HexagonInstrInfo.cpp 612 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
624 BuildMI(&MBB, DL, get(EndLoopOp)).addMBB(TBB);
635 BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[1].getReg(), Flags1).
638 BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[1].getReg(), Flags1).
646 BuildMI(&MBB, DL, get(BccOpc)).addReg(RO.getReg(), Flags).addMBB(TBB);
666 BuildMI(&MBB, DL, get(EndLoopOp)).addMBB(TBB);
670 BuildMI(&MBB, DL, get(BccOpc)).addReg(RO.getReg(), Flags).addMBB(TBB);
672 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
712 TII->get(Hexagon::C2_cmpgtui), Done)
744 TII->get(Hexagon::A2_addi), NewLoopCount)
795 BuildMI(MBB, I, DL, get(Hexagon::A2_tfr), DestReg)
800 BuildMI(MBB, I, DL, get(Hexagon::A2_tfrp), DestReg)
806 BuildMI(MBB, I, DL, get(Hexagon::C2_or), DestReg)
812 BuildMI(MBB, I, DL, get(Hexagon::A2_tfrrcr), DestReg)
818 BuildMI(MBB, I, DL, get(Hexagon::A2_tfrcrr), DestReg)
824 BuildMI(MBB, I, DL, get(Hexagon::A2_tfrrcr), DestReg)
830 BuildMI(MBB, I, DL, get(Hexagon::C2_tfrpr), DestReg)
836 BuildMI(MBB, I, DL, get(Hexagon::C2_tfrrp), DestReg)
842 BuildMI(MBB, I, DL, get(Hexagon::C2_tfrpr), DestReg)
847 BuildMI(MBB, I, DL, get(Hexagon::V6_vassign), DestReg).
854 BuildMI(MBB, I, DL, get(Hexagon::V6_vcombine), DestReg)
860 BuildMI(MBB, I, DL, get(Hexagon::V6_pred_and), DestReg)
901 BuildMI(MBB, I, DL, get(Hexagon::S2_storeri_io))
905 BuildMI(MBB, I, DL, get(Hexagon::S2_storerd_io))
909 BuildMI(MBB, I, DL, get(Hexagon::STriw_pred))
913 BuildMI(MBB, I, DL, get(Hexagon::STriw_ctr))
917 BuildMI(MBB, I, DL, get(Hexagon::PS_vstorerq_ai))
929 BuildMI(MBB, I, DL, get(Opc))
941 BuildMI(MBB, I, DL, get(Opc))
966 BuildMI(MBB, I, DL, get(Hexagon::L2_loadri_io), DestReg)
969 BuildMI(MBB, I, DL, get(Hexagon::L2_loadrd_io), DestReg)
972 BuildMI(MBB, I, DL, get(Hexagon::LDriw_pred), DestReg)
975 BuildMI(MBB, I, DL, get(Hexagon::LDriw_ctr), DestReg)
978 BuildMI(MBB, I, DL, get(Hexagon::PS_vloadrq_ai), DestReg)
989 BuildMI(MBB, I, DL, get(Opc), DestReg)
1000 BuildMI(MBB, I, DL, get(Opc), DestReg)
1032 BuildMI(MBB, MI, DL, get(Hexagon::A2_tfrrcr), CSx)
1034 auto MIB = BuildMI(MBB, MI, DL, get(Opc)).add(MI.getOperand(0))
1056 BuildMI(MBB, MI, DL, get(Hexagon::A2_andir), MI.getOperand(0).getReg())
1065 BuildMI(MBB, MI, DL, get(Hexagon::V6_vcombine), DstReg)
1098 MachineInstr *MI1New = BuildMI(MBB, MI, DL, get(NewOpc))
1104 BuildMI(MBB, MI, DL, get(NewOpc))
1120 MachineInstr *MI1New = BuildMI(MBB, MI, DL, get(NewOpc),
1126 BuildMI(MBB, MI, DL, get(NewOpc), HRI.getSubReg(DstReg, Hexagon::vsub_hi))
1136 BuildMI(MBB, MI, DL, get(Hexagon::C2_orn), Reg)
1144 BuildMI(MBB, MI, DL, get(Hexagon::C2_andn), Reg)
1151 BuildMI(MBB, MI, DL, get(Hexagon::V6_veqw), MI.getOperand(0).getReg())
1158 BuildMI(MBB, MI, DL, get(Hexagon::V6_vgtw), MI.getOperand(0).getReg())
1166 BuildMI(MBB, MI, DL, get(Hexagon::V6_vsubw_dv), Vd)
1181 BuildMI(MBB, MI, MI.getDebugLoc(), get(Hexagon::M2_mpyi),
1185 BuildMI(MBB, MI, MI.getDebugLoc(), get(Hexagon::M2_mpyi),
1208 BuildMI(MBB, MI, MI.getDebugLoc(), get(Hexagon::M2_maci),
1213 BuildMI(MBB, MI, MI.getDebugLoc(), get(Hexagon::M2_maci),
1241 BuildMI(MBB, MI, DL, get(Hexagon::A2_tfrpt), Rd)
1245 BuildMI(MBB, MI, DL, get(Hexagon::A2_tfrpf), Rd)
1266 auto T = BuildMI(MBB, MI, DL, get(Hexagon::V6_vcmov))
1275 auto T = BuildMI(MBB, MI, DL, get(Hexagon::V6_vncmov))
1302 auto T = BuildMI(MBB, MI, DL, get(Hexagon::V6_vccombine))
1314 auto T = BuildMI(MBB, MI, DL, get(Hexagon::V6_vnccombine))
1351 BuildMI(MBB, MI, DL, get(Hexagon::PS_loadrdabs), Hexagon::D13)
1359 MI.setDesc(get(Hexagon::J2_jump));
1363 MI.setDesc(get(Hexagon::J2_jumpr));
1366 MI.setDesc(get(Hexagon::J2_jumprt));
1369 MI.setDesc(get(Hexagon::J2_jumprf));
1372 MI.setDesc(get(Hexagon::J2_jumprtnewpt));
1375 MI.setDesc(get(Hexagon::J2_jumprfnewpt));
1378 MI.setDesc(get(Hexagon::J2_jumprtnew));
1381 MI.setDesc(get(Hexagon::J2_jumprfnew));
1442 First = BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermh))
1446 BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai))
1454 First = BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermw))
1458 BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai))
1466 First = BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermhw))
1470 BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai))
1478 First = BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermhq))
1483 BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai))
1491 First = BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermwq))
1496 BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai))
1504 First = BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermhwq))
1509 BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai))
1529 assert(get(opcode).isBranch() && "Should be a branching condition.");
1540 BuildMI(MBB, MI, DL, get(Hexagon::A2_nop));
1579 MachineInstrBuilder T = BuildMI(B, MI, DL, get(PredOpc));
1597 MI.setDesc(get(PredOpc));
2212 const uint64_t F = get(Opcode).TSFlags;
2404 const uint64_t F = get(Opcode).TSFlags;
2417 return isNewValue(Opcode) && get(Opcode).isBranch() && isPredicated(Opcode);
2426 const uint64_t F = get(Opcode).TSFlags;
2445 const uint64_t F = get(Opcode).TSFlags;
2457 const uint64_t F = get(Opcode).TSFlags;
2465 const uint64_t F = get(Opcode).TSFlags;
2470 const uint64_t F = get(Opcode).TSFlags;
2475 const uint64_t F = get(Opcode).TSFlags;
2476 assert(get(Opcode).isBranch() &&
2830 const uint64_t F = get(MI.getOpcode()).TSFlags;
4382 MI.setDesc(get(NewOpcode));
4396 NewMI = BuildMI(B, I, DL, get(insn));
4410 MI.setDesc(get(getInvertedPredicatedOpcode(MI.getOpcode())));
lib/Target/Hexagon/HexagonNewValueJump.cpp 692 NewMI = BuildMI(*MBB, jmpPos, dl, QII->get(opc))
698 NewMI = BuildMI(*MBB, jmpPos, dl, QII->get(opc))
lib/Target/Hexagon/HexagonOptAddrMode.cpp 497 MIB = BuildMI(*BB, InsertPt, OldMI->getDebugLoc(), HII->get(NewOpCode));
508 MIB = BuildMI(*BB, InsertPt, OldMI->getDebugLoc(), HII->get(NewOpCode))
525 MIB = BuildMI(*BB, InsertPt, OldMI->getDebugLoc(), HII->get(NewOpCode));
557 MIB = BuildMI(*BB, InsertPt, OldMI->getDebugLoc(), HII->get(NewOpCode));
566 MIB = BuildMI(*BB, InsertPt, OldMI->getDebugLoc(), HII->get(NewOpCode));
579 MIB = BuildMI(*BB, InsertPt, OldMI->getDebugLoc(), HII->get(NewOpCode));
637 BuildMI(*BB, InsertPt, UseMI->getDebugLoc(), HII->get(NewOpCode));
lib/Target/Hexagon/HexagonPeephole.cpp 252 MI.setDesc(QII->get(NewOp));
281 QII->get(NewOp), MI.getOperand(0).getReg())
lib/Target/Hexagon/HexagonRDFOpt.cpp 272 MI.setDesc(HII.get(NewOpc));
lib/Target/Hexagon/HexagonRegisterInfo.cpp 206 MI.setDesc(HII.get(Hexagon::A2_addi));
212 MI.setDesc(HII.get(Hexagon::A2_addi));
222 BuildMI(MB, II, DL, HII.get(Hexagon::A2_addi), TmpR)
lib/Target/Hexagon/HexagonSplitConst32AndConst64.cpp 82 BuildMI(B, MI, DL, TII->get(Hexagon::A2_tfrsi), DestReg)
95 BuildMI(B, MI, DL, TII->get(Hexagon::A2_tfrsi), DestLo)
97 BuildMI(B, MI, DL, TII->get(Hexagon::A2_tfrsi), DestHi)
lib/Target/Hexagon/HexagonSplitDouble.cpp 598 MachineInstr *NewI = BuildMI(B, MI, DL, TII->get(Opc));
652 LowI = BuildMI(B, MI, DL, TII->get(Hexagon::L2_loadri_io), P.first)
655 HighI = BuildMI(B, MI, DL, TII->get(Hexagon::L2_loadri_io), P.second)
661 LowI = BuildMI(B, MI, DL, TII->get(Hexagon::S2_storeri_io))
665 HighI = BuildMI(B, MI, DL, TII->get(Hexagon::S2_storeri_io))
679 BuildMI(B, MI, DL, TII->get(Hexagon::A2_addi), NewR)
721 BuildMI(B, MI, DL, TII->get(Hexagon::A2_tfrsi), P.first)
723 BuildMI(B, MI, DL, TII->get(Hexagon::A2_tfrsi), P.second)
741 BuildMI(B, MI, DL, TII->get(Hexagon::A2_tfrsi), P.second)
744 BuildMI(B, MI, DL, TII->get(TargetOpcode::COPY), P.second)
749 BuildMI(B, MI, DL, TII->get(Hexagon::A2_tfrsi), P.first)
752 BuildMI(B, MI, DL, TII->get(TargetOpcode::COPY), P.first)
770 BuildMI(B, MI, DL, TII->get(TargetOpcode::COPY), P.first)
772 BuildMI(B, MI, DL, TII->get(Hexagon::S2_asr_i_r), P.second)
810 BuildMI(B, MI, DL, TII->get(TargetOpcode::COPY), LoR)
812 BuildMI(B, MI, DL, TII->get(TargetOpcode::COPY), HiR)
835 BuildMI(B, MI, DL, TII->get(A2_aslh), LoR)
838 BuildMI(B, MI, DL, TII->get(A2_asrh), TmpR)
841 BuildMI(B, MI, DL, TII->get(ShiftOpc), (Left ? LoR : TmpR))
847 BuildMI(B, MI, DL, TII->get(S2_extractu), TmpR)
852 BuildMI(B, MI, DL, TII->get(S2_asl_i_r_or), HiR)
858 BuildMI(B, MI, DL, TII->get(ShiftOpc), HiR)
862 BuildMI(B, MI, DL, TII->get(S2_insert), LoR)
869 BuildMI(B, MI, DL, TII->get(TargetOpcode::COPY), (Left ? HiR : LoR))
872 BuildMI(B, MI, DL, TII->get(A2_tfrsi), (Left ? LoR : HiR))
875 BuildMI(B, MI, DL, TII->get(S2_asr_i_r), HiR)
881 BuildMI(B, MI, DL, TII->get(A2_aslh), HiR)
884 BuildMI(B, MI, DL, TII->get(A2_asrh), LoR)
887 BuildMI(B, MI, DL, TII->get(ShiftOpc), (Left ? HiR : LoR))
892 BuildMI(B, MI, DL, TII->get(S2_asr_i_r), HiR)
896 BuildMI(B, MI, DL, TII->get(A2_tfrsi), (Left ? LoR : HiR))
945 BuildMI(B, MI, DL, TII->get(A2_or), LoR)
948 BuildMI(B, MI, DL, TII->get(A2_or), HiR)
952 BuildMI(B, MI, DL, TII->get(S2_asl_i_r_or), LoR)
957 BuildMI(B, MI, DL, TII->get(S2_extractu), TmpR1)
962 BuildMI(B, MI, DL, TII->get(A2_or), TmpR2)
965 BuildMI(B, MI, DL, TII->get(S2_asl_i_r_or), HiR)
974 BuildMI(B, MI, DL, TII->get(TargetOpcode::COPY), LoR)
976 BuildMI(B, MI, DL, TII->get(A2_or), HiR)
985 BuildMI(B, MI, DL, TII->get(TargetOpcode::COPY), LoR)
987 BuildMI(B, MI, DL, TII->get(S2_asl_i_r_or), HiR)
1117 BuildMI(B, MI, DL, TII->get(TargetOpcode::REG_SEQUENCE), NewDR)
lib/Target/Hexagon/HexagonStoreWidening.cpp 430 const MCInstrDesc &StD = TII->get(WOpc);
442 const MCInstrDesc &TfrD = TII->get(Hexagon::A2_tfrsi);
453 const MCInstrDesc &StD = TII->get(WOpc);
lib/Target/Hexagon/HexagonVExtract.cpp 82 BuildMI(ExtB, ExtI, DL, HII->get(Hexagon::L2_loadri_io), ElemR)
90 BuildMI(ExtB, ExtI, DL, HII->get(Hexagon::A2_andir), IdxR)
93 BuildMI(ExtB, ExtI, DL, HII->get(Hexagon::L4_loadri_rr), ElemR)
133 BuildMI(DefB, At, DefI->getDebugLoc(), HII->get(StoreOpc))
148 BuildMI(ExtB, ExtI, DL, HII->get(Hexagon::PS_fi), BaseR)
lib/Target/Hexagon/HexagonVLIWPacketizer.cpp 287 auto *ExtMI = MF.CreateMachineInstr(HII->get(Hexagon::A4_ext), DebugLoc());
373 MI.setDesc(HII->get(CurOpcode));
394 MI->setDesc(HII->get(HII->getNonDotCurOp(*MI)));
459 MI.setDesc(HII->get(NewOpcode));
465 MI.setDesc(HII->get(NewOpcode));
884 const MCInstrDesc &D = HII->get(NewOpcode);
lib/Target/Hexagon/HexagonVectorPrint.cpp 102 BuildMI(*MBB, I, DL, QII->get(TargetOpcode::INLINEASM))
lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp 225 return MCII.get(MCI.getOpcode());
393 const uint64_t F = MCII.get(MCI.getOpcode()).TSFlags;
685 const uint64_t F = MCII.get(MCI.getOpcode()).TSFlags;
lib/Target/Lanai/LanaiDelaySlotFiller.cpp 126 BuildMI(MBB, std::next(I), DebugLoc(), TII->get(Lanai::NOP));
lib/Target/Lanai/LanaiFrameLowering.cpp 78 BuildMI(*MBB, MI, DL, LII.get(Lanai::ADD_I_LO), Dst)
113 BuildMI(MBB, MBBI, DL, LII.get(Lanai::SW_RI))
122 BuildMI(MBB, MBBI, DL, LII.get(Lanai::ADD_I_LO), Lanai::FP)
130 BuildMI(MBB, MBBI, DL, LII.get(Lanai::SUB_I_LO), Lanai::SP)
186 BuildMI(MBB, MBBI, DL, LII.get(Lanai::ADD_I_LO), Lanai::SP)
191 BuildMI(MBB, MBBI, DL, LII.get(Lanai::LDW_RI), Lanai::FP)
lib/Target/Lanai/LanaiInstrInfo.cpp 44 BuildMI(MBB, Position, DL, get(Lanai::OR_I_LO), DestinationRegister)
62 BuildMI(MBB, Position, DL, get(Lanai::SW_RI))
82 BuildMI(MBB, Position, DL, get(Lanai::LDW_RI), DestinationRegister)
429 MI->setDesc(get(flagSettingOpcodeVariant(MI->getOpcode())));
673 BuildMI(&MBB, DL, get(Lanai::BT)).addMBB(TrueBlock);
681 BuildMI(&MBB, DL, get(Lanai::BRCC)).addMBB(TrueBlock).addImm(ConditionalCode);
688 BuildMI(&MBB, DL, get(Lanai::BT)).addMBB(FalseBlock);
lib/Target/Lanai/LanaiMemAluCombiner.cpp 259 BuildMI(*BB, MemInstr, MemInstr->getDebugLoc(), TII->get(NewOpc));
lib/Target/Lanai/LanaiRegisterInfo.cpp 188 BuildMI(*MI.getParent(), II, DL, TII->get(Lanai::MOVHI), Reg)
190 BuildMI(*MI.getParent(), II, DL, TII->get(Lanai::OR_I_LO), Reg)
195 BuildMI(*MI.getParent(), II, DL, TII->get(Lanai::ADD_I_LO), Reg)
202 HasNegOffset ? TII->get(Lanai::SUB_R) : TII->get(Lanai::ADD_R),
202 HasNegOffset ? TII->get(Lanai::SUB_R) : TII->get(Lanai::ADD_R),
211 MI.setDesc(TII->get(getRRMOpcodeVariant(MI.getOpcode())));
238 BuildMI(*MI.getParent(), II, DL, TII->get(NewOpcode),
lib/Target/Lanai/MCTargetDesc/LanaiMCTargetDesc.cpp 101 if (Info->get(Inst.getOpcode()).OpInfo[0].OperandType ==
lib/Target/MSP430/MCTargetDesc/MSP430MCCodeEmitter.cpp 85 const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
lib/Target/MSP430/MSP430BranchSelector.cpp 196 MI = BuildMI(*MBB, MI, dl, TII->get(MSP430::JCC))
204 MI = BuildMI(*MBB, MI, dl, TII->get(MSP430::Bi)).addMBB(DestBB);
lib/Target/MSP430/MSP430FrameLowering.cpp 66 BuildMI(MBB, MBBI, DL, TII.get(MSP430::PUSH16r))
70 BuildMI(MBB, MBBI, DL, TII.get(MSP430::MOV16rr), MSP430::FP)
98 BuildMI(MBB, MBBI, DL, TII.get(MSP430::SUB16ri), MSP430::SP)
135 BuildMI(MBB, MBBI, DL, TII.get(MSP430::POP16r), MSP430::FP);
157 TII.get(MSP430::MOV16rr), MSP430::SP).addReg(MSP430::FP);
161 TII.get(MSP430::SUB16ri), MSP430::SP)
170 BuildMI(MBB, MBBI, DL, TII.get(MSP430::ADD16ri), MSP430::SP)
199 BuildMI(MBB, MI, DL, TII.get(MSP430::PUSH16r))
220 BuildMI(MBB, MI, DL, TII.get(MSP430::POP16r), CSI[i].getReg());
248 BuildMI(MF, Old.getDebugLoc(), TII.get(MSP430::SUB16ri), MSP430::SP)
256 New = BuildMI(MF, Old.getDebugLoc(), TII.get(MSP430::ADD16ri),
276 BuildMI(MF, Old.getDebugLoc(), TII.get(MSP430::SUB16ri), MSP430::SP)
lib/Target/MSP430/MSP430ISelLowering.cpp 1450 BuildMI(*BB, MI, dl, TII.get(MSP430::BIC16rc), MSP430::SR)
1456 BuildMI(*BB, MI, dl, TII.get(RrcOpc), DstReg)
1496 BuildMI(BB, dl, TII.get(MSP430::CMP8ri))
1498 BuildMI(BB, dl, TII.get(MSP430::JCC))
1507 BuildMI(LoopBB, dl, TII.get(MSP430::PHI), ShiftReg)
1510 BuildMI(LoopBB, dl, TII.get(MSP430::PHI), ShiftAmtReg)
1514 BuildMI(LoopBB, dl, TII.get(MSP430::BIC16rc), MSP430::SR)
1517 BuildMI(LoopBB, dl, TII.get(Opc), ShiftReg2)
1521 BuildMI(LoopBB, dl, TII.get(Opc), ShiftReg2)
1523 BuildMI(LoopBB, dl, TII.get(MSP430::SUB8ri), ShiftAmtReg2)
1525 BuildMI(LoopBB, dl, TII.get(MSP430::JCC))
1531 BuildMI(*RemBB, RemBB->begin(), dl, TII.get(MSP430::PHI), DstReg)
1584 BuildMI(BB, dl, TII.get(MSP430::JCC))
1600 BuildMI(*BB, BB->begin(), dl, TII.get(MSP430::PHI), MI.getOperand(0).getReg())
lib/Target/MSP430/MSP430InstrInfo.cpp 52 BuildMI(MBB, MI, DL, get(MSP430::MOV16mr))
56 BuildMI(MBB, MI, DL, get(MSP430::MOV8mr))
79 BuildMI(MBB, MI, DL, get(MSP430::MOV16rm))
83 BuildMI(MBB, MI, DL, get(MSP430::MOV8rm))
102 BuildMI(MBB, I, DL, get(Opc), DestReg)
280 BuildMI(&MBB, DL, get(MSP430::JMP)).addMBB(TBB);
286 BuildMI(&MBB, DL, get(MSP430::JCC)).addMBB(TBB).addImm(Cond[0].getImm());
291 BuildMI(&MBB, DL, get(MSP430::JMP)).addMBB(FBB);
lib/Target/MSP430/MSP430RegisterInfo.cpp 135 MI.setDesc(TII.get(MSP430::MOV16rr));
144 BuildMI(MBB, std::next(II), dl, TII.get(MSP430::SUB16ri), DstReg)
147 BuildMI(MBB, std::next(II), dl, TII.get(MSP430::ADD16ri), DstReg)
lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp 222 const MCInstrDesc &Desc = MCII.get(TmpInst.getOpcode());
lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp 145 switch (Info->get(Inst.getOpcode()).OpInfo[NumOps - 1].OperandType) {
lib/Target/Mips/MicroMipsSizeReduction.cpp 704 MI->setDesc(MipsII->get(Entry.NarrowOpc()));
709 const MCInstrDesc &NewMCID = MipsII->get(Entry.NarrowOpc());
lib/Target/Mips/Mips16FrameLowering.cpp 67 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
82 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
87 BuildMI(MBB, MBBI, dl, TII.get(Mips::MoveR3216), Mips::S0)
104 BuildMI(MBB, MBBI, dl, TII.get(Mips::Move32R16), Mips::SP)
lib/Target/Mips/Mips16ISelDAGToDAG.cpp 83 BuildMI(MBB, I, DL, TII.get(Mips::LiRxImmX16), V0)
85 BuildMI(MBB, I, DL, TII.get(Mips::AddiuRxPcImmX16), V1)
88 BuildMI(MBB, I, DL, TII.get(Mips::SllX16), V2).addReg(V0).addImm(16);
89 BuildMI(MBB, I, DL, TII.get(Mips::AdduRxRyRz16), GlobalBaseReg)
lib/Target/Mips/Mips16ISelLowering.cpp 546 BuildMI(BB, DL, TII->get(Opc))
563 BuildMI(*BB, BB->begin(), DL, TII->get(Mips::PHI), MI.getOperand(0).getReg())
609 BuildMI(BB, DL, TII->get(Opc2))
612 BuildMI(BB, DL, TII->get(Opc1)).addMBB(sinkMBB);
627 BuildMI(*BB, BB->begin(), DL, TII->get(Mips::PHI), MI.getOperand(0).getReg())
675 BuildMI(BB, DL, TII->get(Opc2))
678 BuildMI(BB, DL, TII->get(Opc1)).addMBB(sinkMBB);
693 BuildMI(*BB, BB->begin(), DL, TII->get(Mips::PHI), MI.getOperand(0).getReg())
714 BuildMI(*BB, MI, MI.getDebugLoc(), TII->get(CmpOpc))
717 BuildMI(*BB, MI, MI.getDebugLoc(), TII->get(BtOpc)).addMBB(target);
739 BuildMI(*BB, MI, MI.getDebugLoc(), TII->get(CmpOpc)).addReg(regX).addImm(imm);
740 BuildMI(*BB, MI, MI.getDebugLoc(), TII->get(BtOpc)).addMBB(target);
764 BuildMI(*BB, MI, MI.getDebugLoc(), TII->get(SltOpc))
767 BuildMI(*BB, MI, MI.getDebugLoc(), TII->get(Mips::MoveR3216), CC)
784 BuildMI(*BB, MI, MI.getDebugLoc(), TII->get(SltOpc)).addReg(regX).addImm(Imm);
785 BuildMI(*BB, MI, MI.getDebugLoc(), TII->get(Mips::MoveR3216), CC)
lib/Target/Mips/Mips16InstrInfo.cpp 90 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc));
123 BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill)).
142 BuildMI(MBB, I, DL, get(Opc), DestReg).addFrameIndex(FI).addImm(Offset)
224 MIB = BuildMI(MBB, I, DL, get(Opc));
267 MIB = BuildMI(MBB, I, DL, get(Opc));
291 MachineInstrBuilder MIB1 = BuildMI(MBB, I, DL, get(Mips::LwConstant32), Reg1);
293 MachineInstrBuilder MIB2 = BuildMI(MBB, I, DL, get(Mips::MoveR3216), Reg2);
295 MachineInstrBuilder MIB3 = BuildMI(MBB, I, DL, get(Mips::AdduRxRyRz16), Reg1);
298 MachineInstrBuilder MIB4 = BuildMI(MBB, I, DL, get(Mips::Move32R16),
404 BuildMI(MBB, II, DL, get(Mips::LwConstant32), Reg).addImm(Imm).addImm(-1);
421 BuildMI(MBB, II, DL, get(Mips:: AdduRxRyRz16), Reg).addReg(SpReg, RegState::Kill)
425 BuildMI(MBB, II, DL, get(Mips:: AdduRxRyRz16), Reg).addReg(FrameReg)
455 BuildMI(MBB, I, I->getDebugLoc(), get(Opc));
460 return get(Mips::AddiuSpImm16);
462 return get(Mips::AddiuSpImmX16);
lib/Target/Mips/MipsBranchExpansion.cpp 338 const MCInstrDesc &NewDesc = TII->get(NewOpc);
387 BuildMI(*MBB, Pos, DL, TII->get(JumpOp)).addReg(ATReg);
456 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::SP)
459 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::SW))
480 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::LONG_BRANCH_LUi), Mips::AT)
485 BuildMI(*MFp, DL, TII->get(BalOp)).addMBB(BalTgtMBB);
487 BuildMI(*MFp, DL, TII->get(Mips::LONG_BRANCH_ADDiu), Mips::AT)
502 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::ADDu), Mips::AT)
505 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::LW), Mips::RA)
517 BuildMI(*BalTgtMBB, std::prev(Pos), DL, TII->get(Mips::ADDiu), Mips::SP)
523 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::NOP));
525 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::SP)
579 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::DADDiu), Mips::SP_64)
582 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::SD))
586 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::LONG_BRANCH_DADDiu),
591 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::DSLL), Mips::AT_64)
596 BuildMI(*MFp, DL, TII->get(BalOp)).addMBB(BalTgtMBB);
598 BuildMI(*MFp, DL, TII->get(Mips::LONG_BRANCH_DADDiu), Mips::AT_64)
613 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::DADDu), Mips::AT_64)
616 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::LD), Mips::RA_64)
623 BuildMI(*BalTgtMBB, std::prev(Pos), DL, TII->get(Mips::DADDiu),
628 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::DADDiu), Mips::SP_64)
657 TII->get(STI->inMicroMipsMode() ? Mips::BC_MMR6 : Mips::BC))
667 .append(BuildMI(*MFp, DL, TII->get(Mips::J)).addMBB(TgtMBB))
668 .append(BuildMI(*MFp, DL, TII->get(Mips::NOP)));
676 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::LONG_BRANCH_LUi2Op_64),
679 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::LONG_BRANCH_DADDiu2Op),
683 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::DSLL), Mips::AT_64)
686 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::LONG_BRANCH_DADDiu2Op),
690 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::DSLL), Mips::AT_64)
693 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::LONG_BRANCH_DADDiu2Op),
698 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::LONG_BRANCH_LUi2Op),
701 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::LONG_BRANCH_ADDiu2Op),
724 BuildMI(MBB, I, DL, TII->get(Mips::LUi), Mips::V0)
726 BuildMI(MBB, I, DL, TII->get(Mips::ADDiu), Mips::V0)
762 BuildMI(*MFp, I->getDebugLoc(), TII->get(Mips::NOP)));
lib/Target/Mips/MipsConstantIslandPass.cpp 568 BuildMI(*BB, InsAt, DebugLoc(), TII->get(Mips::CONSTPOOL_ENTRY))
866 BuildMI(OrigBB, DebugLoc(), TII->get(Mips::Bimm16)).addMBB(NewBB);
1109 UserMI->setDesc(TII->get(U.getLongFormOpcode()));
1239 BuildMI(UserMBB, DebugLoc(), TII->get(UncondBr)).addMBB(NewMBB);
1388 U.CPEMI = BuildMI(NewIsland, DebugLoc(), TII->get(Mips::CONSTPOOL_ENTRY))
1511 MI->setDesc(TII->get(Mips::BimmX16));
1527 MI->setDesc(TII->get(Mips::JalB16));
1554 MI->setDesc(TII->get(LongFormOpcode));
1592 MI->setDesc(TII->get(OppositeBranchOpcode));
1618 BuildMI(MBB, DebugLoc(), TII->get(OppositeBranchOpcode))
1622 BuildMI(MBB, DebugLoc(), TII->get(OppositeBranchOpcode))
1627 BuildMI(MBB, DebugLoc(), TII->get(Br.UncondBr)).addMBB(DestBB);
1662 I->setDesc(TII->get(Mips::LwRxPcTcp16));
lib/Target/Mips/MipsDelaySlotFiller.cpp 640 DSI->setDesc(TII->get(getEquivalentCallShort(DSI->getOpcode())));
666 BuildMI(MBB, std::next(I), I->getDebugLoc(), TII->get(Mips::NOP));
lib/Target/Mips/MipsExpandPseudo.cpp 145 BuildMI(loop1MBB, DL, TII->get(LL), Scratch).addReg(Ptr).addImm(0);
146 BuildMI(loop1MBB, DL, TII->get(Mips::AND), Scratch2)
149 BuildMI(loop1MBB, DL, TII->get(BNE))
157 BuildMI(loop2MBB, DL, TII->get(Mips::AND), Scratch)
160 BuildMI(loop2MBB, DL, TII->get(Mips::OR), Scratch)
163 BuildMI(loop2MBB, DL, TII->get(SC), Scratch)
167 BuildMI(loop2MBB, DL, TII->get(BEQ))
175 BuildMI(sinkMBB, DL, TII->get(Mips::SRLV), Dest)
179 BuildMI(sinkMBB, DL, TII->get(SEOp), Dest).addReg(Dest);
183 BuildMI(sinkMBB, DL, TII->get(Mips::SLL), Dest)
186 BuildMI(sinkMBB, DL, TII->get(Mips::SRA), Dest)
278 BuildMI(loop1MBB, DL, TII->get(LL), Dest).addReg(Ptr).addImm(0);
279 BuildMI(loop1MBB, DL, TII->get(BNE))
286 BuildMI(loop2MBB, DL, TII->get(MOVE), Scratch).addReg(NewVal).addReg(ZERO);
287 BuildMI(loop2MBB, DL, TII->get(SC), Scratch)
289 BuildMI(loop2MBB, DL, TII->get(BEQ))
404 BuildMI(loopMBB, DL, TII->get(LL), OldVal).addReg(Ptr).addImm(0);
409 BuildMI(loopMBB, DL, TII->get(Mips::AND), BinOpRes)
412 BuildMI(loopMBB, DL, TII->get(Mips::NOR), BinOpRes)
415 BuildMI(loopMBB, DL, TII->get(Mips::AND), BinOpRes)
421 BuildMI(loopMBB, DL, TII->get(Opcode), BinOpRes)
424 BuildMI(loopMBB, DL, TII->get(Mips::AND), BinOpRes)
429 BuildMI(loopMBB, DL, TII->get(Mips::AND), BinOpRes)
438 BuildMI(loopMBB, DL, TII->get(Mips::AND), StoreVal)
440 BuildMI(loopMBB, DL, TII->get(Mips::OR), StoreVal)
442 BuildMI(loopMBB, DL, TII->get(SC), StoreVal)
444 BuildMI(loopMBB, DL, TII->get(BEQ))
454 BuildMI(sinkMBB, DL, TII->get(Mips::AND), Dest)
456 BuildMI(sinkMBB, DL, TII->get(Mips::SRLV), Dest)
460 BuildMI(sinkMBB, DL, TII->get(SEOp), Dest).addReg(Dest);
463 BuildMI(sinkMBB, DL, TII->get(Mips::SLL), Dest)
466 BuildMI(sinkMBB, DL, TII->get(Mips::SRA), Dest)
592 BuildMI(loopMBB, DL, TII->get(LL), OldVal).addReg(Ptr).addImm(0);
596 BuildMI(loopMBB, DL, TII->get(Opcode), Scratch).addReg(OldVal).addReg(Incr);
600 BuildMI(loopMBB, DL, TII->get(AND), Scratch).addReg(OldVal).addReg(Incr);
601 BuildMI(loopMBB, DL, TII->get(NOR), Scratch).addReg(ZERO).addReg(Scratch);
604 BuildMI(loopMBB, DL, TII->get(OR), Scratch).addReg(Incr).addReg(ZERO);
607 BuildMI(loopMBB, DL, TII->get(SC), Scratch).addReg(Scratch).addReg(Ptr).addImm(0);
608 BuildMI(loopMBB, DL, TII->get(BEQ)).addReg(Scratch).addReg(ZERO).addMBB(loopMBB);
lib/Target/Mips/MipsFastISel.cpp 211 return BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc));
215 return BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc),
346 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::LEA_ADDiu),
804 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
855 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc))
979 BuildMI(*BrBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::BGTZ))
1234 TII.get(TargetOpcode::COPY), VA.getLocReg()).addReg(ArgReg);
1304 TII.get(TargetOpcode::COPY),
1474 TII.get(TargetOpcode::COPY), ResultReg)
1562 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::JALR),
1769 TII.get(TargetOpcode::COPY), DestReg).addReg(SrcReg);
2137 const MCInstrDesc &II = TII.get(MachineInstOpcode);
lib/Target/Mips/MipsISelLowering.cpp 1275 TII.get(IsMicroMips ? Mips::TEQ_MM : Mips::TEQ))
1523 BuildMI(*BB, II, DL, TII->get(Mips::COPY), IncrCopy).addReg(Incr);
1524 BuildMI(*BB, II, DL, TII->get(Mips::COPY), PtrCopy).addReg(Ptr);
1526 BuildMI(*BB, II, DL, TII->get(AtomicOp))
1545 BuildMI(BB, DL, TII->get(Mips::SEB), DstReg).addReg(SrcReg);
1550 BuildMI(BB, DL, TII->get(Mips::SEH), DstReg).addReg(SrcReg);
1562 BuildMI(BB, DL, TII->get(Mips::SLL), ScrReg).addReg(SrcReg).addImm(ShiftImm);
1563 BuildMI(BB, DL, TII->get(Mips::SRA), DstReg).addReg(ScrReg).addImm(ShiftImm);
1670 BuildMI(BB, DL, TII->get(ABI.GetPtrAddiuOp()), MaskLSB2)
1672 BuildMI(BB, DL, TII->get(ABI.GetPtrAndOp()), AlignedAddr)
1674 BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2)
1677 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
1680 BuildMI(BB, DL, TII->get(Mips::XORi), Off)
1682 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3);
1684 BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper)
1686 BuildMI(BB, DL, TII->get(Mips::SLLV), Mask)
1688 BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
1689 BuildMI(BB, DL, TII->get(Mips::SLLV), Incr2).addReg(Incr).addReg(ShiftAmt);
1696 BuildMI(BB, DL, TII->get(AtomicOp))
1756 BuildMI(*BB, II, DL, TII->get(Mips::COPY), PtrCopy).addReg(Ptr);
1757 BuildMI(*BB, II, DL, TII->get(Mips::COPY), OldValCopy).addReg(OldVal);
1758 BuildMI(*BB, II, DL, TII->get(Mips::COPY), NewValCopy).addReg(NewVal);
1764 BuildMI(*BB, II, DL, TII->get(AtomicOp))
1851 BuildMI(BB, DL, TII->get(ArePtrs64bit ? Mips::DADDiu : Mips::ADDiu), MaskLSB2)
1853 BuildMI(BB, DL, TII->get(ArePtrs64bit ? Mips::AND64 : Mips::AND), AlignedAddr)
1855 BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2)
1858 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
1861 BuildMI(BB, DL, TII->get(Mips::XORi), Off)
1863 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3);
1865 BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper)
1867 BuildMI(BB, DL, TII->get(Mips::SLLV), Mask)
1869 BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
1870 BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedCmpVal)
1872 BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedCmpVal)
1874 BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedNewVal)
1876 BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedNewVal)
1883 BuildMI(BB, DL, TII->get(AtomicOp))
4457 BuildMI(BB, DL, TII->get(Opc))
4462 BuildMI(BB, DL, TII->get(Opc))
4481 BuildMI(*BB, BB->begin(), DL, TII->get(Mips::PHI), MI.getOperand(0).getReg())
4532 BuildMI(BB, DL, TII->get(Mips::BNE))
4551 BuildMI(*BB, BB->begin(), DL, TII->get(Mips::PHI), MI.getOperand(0).getReg())
4556 BuildMI(*BB, BB->begin(), DL, TII->get(Mips::PHI), MI.getOperand(1).getReg())
lib/Target/Mips/MipsInstrInfo.cpp 61 BuildMI(MBB, MI, DL, get(Mips::NOP));
109 const MCInstrDesc &MCID = get(Opc);
141 BuildMI(&MBB, DL, get(UncondBrOpc)).addMBB(FBB);
148 BuildMI(&MBB, DL, get(UncondBrOpc)).addMBB(TBB);
638 MIB = BuildMI(*I->getParent(), I, I->getDebugLoc(), get(NewOpc));
lib/Target/Mips/MipsInstructionSelector.cpp 245 MachineInstr *Mul = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::MUL))
269 PseudoMULTu = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::PseudoMULTu))
276 PseudoMove = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::PseudoMFHI))
286 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDu))
294 I.setDesc(TII.get(COPY));
298 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDiu))
305 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::BNE))
318 MachineInstr *SLL = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::SLL))
326 MachineInstr *ADDu = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDu))
335 BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LW))
347 MachineInstr *ADDu = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDu))
357 BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::PseudoIndirectBranch))
366 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::PseudoIndirectBranch))
381 I.setDesc(TII.get(TargetOpcode::PHI));
413 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(NewOpc))
430 TII.get(IsSigned ? Mips::PseudoSDIV : Mips::PseudoUDIV))
438 TII.get(IsDiv ? Mips::PseudoMFLO : Mips::PseudoMFHI))
449 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::MOVN_I_I))
457 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::IMPLICIT_DEF))
517 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(FABSOpcode))
536 MachineInstr *Trunc = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Opcode))
542 MachineInstr *Move = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::MFC1))
554 MachineInstr *LWGOT = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LW))
578 BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDiu))
589 MachineInstr *LUi = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LUi))
597 BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDiu))
610 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LW))
620 BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LUi))
757 BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDiu))
766 MachineInstr *FCMP = BuildMI(MBB, I, I.getDebugLoc(), TII.get(FCMPOpcode))
773 MachineInstr *Move = BuildMI(MBB, I, I.getDebugLoc(), TII.get(MoveOpcode))
785 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::SYNC)).addImm(0);
794 BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LEA_ADDiu))
801 MachineInstr *Store = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::SW))
lib/Target/Mips/MipsMachineFunction.cpp 88 BuildMI(MBB, I, DL, TII.get(Mips::LUi64), V0)
90 BuildMI(MBB, I, DL, TII.get(Mips::DADDu), V1).addReg(V0)
92 BuildMI(MBB, I, DL, TII.get(Mips::DADDiu), GlobalBaseReg).addReg(V1)
102 BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0)
104 BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V0)
117 BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0)
119 BuildMI(MBB, I, DL, TII.get(Mips::ADDu), V1).addReg(V0).addReg(Mips::T9);
120 BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V1)
146 BuildMI(MBB, I, DL, TII.get(Mips::ADDu), GlobalBaseReg)
lib/Target/Mips/MipsOptimizePICCall.cpp 156 BuildMI(*MBB, I, I->getDebugLoc(), TII.get(TargetOpcode::COPY), DstReg)
lib/Target/Mips/MipsSEFrameLowering.cpp 178 BuildMI(MBB, I, I->getDebugLoc(), TII.get(TargetOpcode::COPY), Dst)
192 BuildMI(MBB, I, I->getDebugLoc(), TII.get(TargetOpcode::COPY), VR)
213 const MCInstrDesc &Desc = TII.get(TargetOpcode::COPY);
238 BuildMI(MBB, I, DL, TII.get(MFLoOpc), VR0).addReg(Src);
240 BuildMI(MBB, I, DL, TII.get(MFHiOpc), VR1).addReg(Src, SrcKill);
272 BuildMI(MBB, I, DL, TII.get(MFLoOpc), VR0).addReg(Src);
273 BuildMI(MBB, I, DL, TII.get(TargetOpcode::COPY), DstLo)
275 BuildMI(MBB, I, DL, TII.get(MFHiOpc), VR1).addReg(Src, SrcKill);
276 BuildMI(MBB, I, DL, TII.get(TargetOpcode::COPY), DstHi)
350 BuildMI(MBB, I, I->getDebugLoc(), TII.get(Mips::IMPLICIT_DEF), DstReg);
439 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
473 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
478 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
489 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
494 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
500 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
521 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
529 BuildMI(MBB, MBBI, dl, TII.get(MOVE), FP).addReg(SP).addReg(ZERO)
535 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
546 BuildMI(MBB, MBBI, dl, TII.get(ADDiu), VR).addReg(ZERO) .addImm(MaxAlign);
547 BuildMI(MBB, MBBI, dl, TII.get(AND), SP).addReg(SP).addReg(VR);
552 BuildMI(MBB, MBBI, dl, TII.get(MOVE), BP)
598 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::MFC0), Mips::K0)
603 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::EXT), Mips::K0)
612 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::MFC0), Mips::K1)
623 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::MFC0), Mips::K1)
657 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::INS), Mips::K1)
665 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::INS), Mips::K1)
674 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::INS), Mips::K1)
682 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::MTC0), Mips::COP012)
715 BuildMI(MBB, I, DL, TII.get(MOVE), SP).addReg(FP).addReg(ZERO);
757 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::DI), Mips::ZERO);
758 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::EHB));
764 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::MTC0), Mips::COP014)
772 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::MTC0), Mips::COP012)
828 BuildMI(MBB, MI, DL, TII.get(Op), Mips::K0)
lib/Target/Mips/MipsSEISelDAGToDAG.cpp 132 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(Mips::OR64))
140 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(Mips::OR))
145 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(Mips::ADDiu))
lib/Target/Mips/MipsSEISelLowering.cpp 3062 BuildMI(BB, DL, TII->get(Mips::BPOSGE32)).addMBB(TBB);
3064 BuildMI(BB, DL, TII->get(Mips::BPOSGE32C_MMR3)).addMBB(TBB);
3068 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), VR2)
3070 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink);
3074 BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), VR1)
3078 BuildMI(*Sink, Sink->begin(), DL, TII->get(Mips::PHI),
3131 BuildMI(BB, DL, TII->get(BranchOp))
3137 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), RD1)
3139 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink);
3143 BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), RD2)
3147 BuildMI(*Sink, Sink->begin(), DL, TII->get(Mips::PHI),
3185 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Wt).addReg(Ws);
3188 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Wt, 0, Mips::sub_lo);
3194 BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_W), Wt).addReg(Ws).addImm(Lane);
3195 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Wt, 0, Mips::sub_lo);
3225 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Ws, 0, Mips::sub_64);
3229 BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_D), Wt).addReg(Ws).addImm(1);
3230 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Wt, 0, Mips::sub_64);
3257 BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Wt)
3261 BuildMI(*BB, MI, DL, TII->get(Mips::INSVE_W), Wd)
3291 BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Wt)
3295 BuildMI(*BB, MI, DL, TII->get(Mips::INSVE_D), Wd)
3376 BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Wt)
3386 BuildMI(*BB, MI, DL, TII->get(ShiftOp), LaneTmp1)
3394 BuildMI(*BB, MI, DL, TII->get(Mips::SLD_B), WdTmp1)
3402 BuildMI(*BB, MI, DL, TII->get(InsveOp), WdTmp2)
3409 BuildMI(*BB, MI, DL, TII->get(InsertOp), WdTmp2)
3419 BuildMI(*BB, MI, DL, TII->get(Subtarget.isABI_N64() ? Mips::DSUB : Mips::SUB),
3423 BuildMI(*BB, MI, DL, TII->get(Mips::SLD_B), Wd)
3454 BuildMI(*BB, MI, DL, TII->get(Mips::IMPLICIT_DEF), Wt1);
3455 BuildMI(*BB, MI, DL, TII->get(Mips::INSERT_SUBREG), Wt2)
3459 BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_W), Wd).addReg(Wt2).addImm(0);
3485 BuildMI(*BB, MI, DL, TII->get(Mips::IMPLICIT_DEF), Wt1);
3486 BuildMI(*BB, MI, DL, TII->get(Mips::INSERT_SUBREG), Wt2)
3490 BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_D), Wd).addReg(Wt2).addImm(0);
3529 BuildMI(*BB, MI, DL, TII->get(Mips::COPY_U_H), Rs).addReg(Ws).addImm(0);
3532 BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Tmp)
3538 BuildMI(*BB, MI, DL, TII->get(UsingMips32 ? Mips::SH : Mips::SH64))
3583 BuildMI(*BB, MI, DL, TII->get(UsingMips32 ? Mips::LH : Mips::LH64), Rt);
3589 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Tmp).addReg(Rt, 0, Mips::sub_32);
3593 BuildMI(*BB, MI, DL, TII->get(Mips::FILL_H), Wd).addReg(Rt);
3677 BuildMI(*BB, MI, DL, TII->get(MFC1Opc), Rtemp).addReg(Fs);
3678 BuildMI(*BB, MI, DL, TII->get(FILLOpc), Wtemp).addReg(Rtemp);
3683 BuildMI(*BB, MI, DL, TII->get(Mips::MFHC1_D64), Rtemp2).addReg(Fs);
3686 BuildMI(*BB, MI, DL, TII->get(Mips::INSERT_W), Wtemp2)
3690 BuildMI(*BB, MI, DL, TII->get(Mips::INSERT_W), Wtemp3)
3699 BuildMI(*BB, MI, DL, TII->get(Mips::FEXDO_W), Wtemp2)
3705 BuildMI(*BB, MI, DL, TII->get(Mips::FEXDO_H), Wd).addReg(WPHI).addReg(WPHI);
3782 BuildMI(*BB, MI, DL, TII->get(Mips::FEXUPR_W), Wtemp).addReg(Ws);
3785 BuildMI(*BB, MI, DL, TII->get(Mips::FEXUPR_D), WPHI).addReg(Wtemp);
3793 BuildMI(*BB, MI, DL, TII->get(COPYOpc), Rtemp).addReg(WPHI).addImm(0);
3794 BuildMI(*BB, MI, DL, TII->get(MTC1Opc), FPRPHI).addReg(Rtemp);
3798 BuildMI(*BB, MI, DL, TII->get(Mips::COPY_S_W), Rtemp2)
3801 BuildMI(*BB, MI, DL, TII->get(Mips::MTHC1_D64), Fd)
3827 BuildMI(*BB, MI, DL, TII->get(Mips::LDI_W), Ws1).addImm(1);
3828 BuildMI(*BB, MI, DL, TII->get(Mips::FFINT_U_W), Ws2).addReg(Ws1);
3831 BuildMI(*BB, MI, DL, TII->get(Mips::FEXP2_W), MI.getOperand(0).getReg())
3856 BuildMI(*BB, MI, DL, TII->get(Mips::LDI_D), Ws1).addImm(1);
3857 BuildMI(*BB, MI, DL, TII->get(Mips::FFINT_U_D), Ws2).addReg(Ws1);
3860 BuildMI(*BB, MI, DL, TII->get(Mips::FEXP2_D), MI.getOperand(0).getReg())
lib/Target/Mips/MipsSEInstrInfo.cpp 111 BuildMI(MBB, I, DL, get(Mips::RDDSP), DestReg).addImm(1 << 4)
132 BuildMI(MBB, I, DL, get(Mips::WRDSP))
137 BuildMI(MBB, I, DL, get(Mips::CTCMSA))
174 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc));
304 BuildMI(MBB, I, DL, get(Mips::MFHI), Mips::K0);
307 BuildMI(MBB, I, DL, get(Mips::MFHI64), Mips::K0_64);
310 BuildMI(MBB, I, DL, get(Mips::MFLO), Mips::K0);
313 BuildMI(MBB, I, DL, get(Mips::MFLO64), Mips::K0_64);
319 BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill))
380 BuildMI(MBB, I, DL, get(Opc), DestReg)
400 BuildMI(MBB, I, DL, get(Opc), Reg)
404 BuildMI(MBB, I, DL, get(LdOp)).addReg(Reg);
592 BuildMI(MBB, I, DL, get(ADDiu), SP).addReg(SP).addImm(Amount);
602 BuildMI(MBB, I, DL, get(Opc), SP).addReg(SP).addReg(Reg, RegState::Kill);
634 BuildMI(MBB, II, DL, get(LUi), Reg).addImm(SignExtend64<16>(Inst->ImmOpnd));
636 BuildMI(MBB, II, DL, get(Inst->Opc), Reg).addReg(ZEROReg)
641 BuildMI(MBB, II, DL, get(Inst->Opc), Reg).addReg(Reg, RegState::Kill)
682 MIB = BuildMI(MBB, I, I->getDebugLoc(), get(Mips::PseudoReturn64))
685 MIB = BuildMI(MBB, I, I->getDebugLoc(), get(Mips::PseudoReturn))
697 BuildMI(MBB, I, I->getDebugLoc(), get(Mips::ERET));
703 const MCInstrDesc &Desc = get(Opc);
715 BuildMI(MBB, I, I->getDebugLoc(), get(NewOpc), I->getOperand(0).getReg());
731 MachineInstrBuilder LoInst = BuildMI(MBB, I, DL, get(LoOpc));
732 MachineInstrBuilder HiInst = BuildMI(MBB, I, DL, get(HiOpc));
752 const MCInstrDesc &CvtDesc = get(CvtOpc), &MovDesc = get(MovOpc);
752 const MCInstrDesc &CvtDesc = get(CvtOpc), &MovDesc = get(MovOpc);
807 get(isMicroMips ? (FP64 ? Mips::MFHC1_D64_MM : Mips::MFHC1_D32_MM)
812 BuildMI(MBB, I, dl, get(Mips::MFC1), DstReg).addReg(SubReg);
820 const MCInstrDesc& Mtc1Tdd = get(Mips::MTC1);
863 get(isMicroMips ? (FP64 ? Mips::MTHC1_D64_MM : Mips::MTHC1_D32_MM)
894 BuildMI(MBB, I, I->getDebugLoc(), get(ADDU), T9)
897 BuildMI(MBB, I, I->getDebugLoc(), get(ADDU), RA)
900 BuildMI(MBB, I, I->getDebugLoc(), get(ADDU), SP).addReg(SP).addReg(OffsetReg);
lib/Target/Mips/MipsSERegisterInfo.cpp 229 BuildMI(MBB, II, DL, TII.get(ABI.GetPtrAddiuOp()), Reg)
247 BuildMI(MBB, II, DL, TII.get(ABI.GetPtrAdduOp()), Reg).addReg(FrameReg)
lib/Target/NVPTX/NVPTXFrameLowering.cpp 56 MF.getSubtarget().getInstrInfo()->get(CvtaLocalOpcode),
60 BuildMI(MBB, MI, dl, MF.getSubtarget().getInstrInfo()->get(MovDepotOpcode),
lib/Target/NVPTX/NVPTXInstrInfo.cpp 68 BuildMI(MBB, I, DL, get(Op), DestReg)
196 BuildMI(&MBB, DL, get(NVPTX::GOTO)).addMBB(TBB);
198 BuildMI(&MBB, DL, get(NVPTX::CBranch)).addReg(Cond[0].getReg())
204 BuildMI(&MBB, DL, get(NVPTX::CBranch)).addReg(Cond[0].getReg()).addMBB(TBB);
205 BuildMI(&MBB, DL, get(NVPTX::GOTO)).addMBB(FBB);
lib/Target/NVPTX/NVPTXPeephole.cpp 112 BuildMI(MF, Root.getDebugLoc(), TII->get(Prev.getOpcode()),
lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp 544 Reg = PPCInstrInfo::getRegNumForOperand(MII.get(MI->getOpcode()),
lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp 272 PPCInstrInfo::getRegNumForOperand(MCII.get(MI.getOpcode()),
315 const MCInstrDesc &Desc = MCII.get(Opcode);
lib/Target/PowerPC/PPCBranchSelector.cpp 342 BuildMI(MBB, I, dl, TII->get(PPC::BCC))
346 BuildMI(MBB, I, dl, TII->get(PPC::BCn)).addReg(CRBit).addImm(2);
349 BuildMI(MBB, I, dl, TII->get(PPC::BC)).addReg(CRBit).addImm(2);
351 BuildMI(MBB, I, dl, TII->get(PPC::BDZ)).addImm(2);
353 BuildMI(MBB, I, dl, TII->get(PPC::BDZ8)).addImm(2);
355 BuildMI(MBB, I, dl, TII->get(PPC::BDNZ)).addImm(2);
357 BuildMI(MBB, I, dl, TII->get(PPC::BDNZ8)).addImm(2);
363 I = BuildMI(MBB, I, dl, TII->get(PPC::B)).addMBB(Dest);
lib/Target/PowerPC/PPCEarlyReturn.cpp 80 BuildMI(**PI, J, J->getDebugLoc(), TII->get(I->getOpcode()))
92 BuildMI(**PI, J, J->getDebugLoc(), TII->get(PPC::BCCLR))
108 TII->get(J->getOpcode() == PPC::BC ? PPC::BCLR : PPC::BCLRn))
lib/Target/PowerPC/PPCExpandISEL.cpp 234 BuildMI(*MBB, (*I), dl, TII->get(isISEL8(**I) ? PPC::OR8 : PPC::OR))
311 BuildMI(*MBB, (*MI), dl, TII->get(isISEL8(**MI) ? PPC::OR8 : PPC::OR))
421 BuildMI(*MBB, BIL.back(), dl, TII->get(PPC::BC))
428 TII->get(PPC::B))
459 TII->get(isISEL8(*MI) ? PPC::ADDI8 : PPC::ADDI))
484 TII->get(isISEL8(*MI) ? PPC::ORI8 : PPC::ORI))
lib/Target/PowerPC/PPCFastISel.cpp 159 TII.get(TargetOpcode::COPY), TmpReg).addReg(SrcReg, Flag, SubReg);
436 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::ADDI8),
541 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
549 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
576 auto MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc),
687 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc))
699 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc))
722 auto MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc))
796 BuildMI(*BrBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::BCC))
948 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(CmpOpc), DestReg)
951 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(CmpOpc), DestReg)
994 TII.get(PPC::EFSCFD), DestReg)
999 TII.get(PPC::XSRSP), DestReg)
1004 TII.get(PPC::FRSP), DestReg)
1098 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg)
1142 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg)
1253 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg)
1348 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc),
1366 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
1420 TII.get(TII.getCallFrameSetupOpcode()))
1481 TII.get(TargetOpcode::COPY), ArgReg).addReg(Arg);
1495 TII.get(TII.getCallFrameDestroyOpcode()))
1527 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::FRSP),
1654 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::NOP));
1661 TII.get(PPC::BL8_NOP));
1729 TII.get(TargetOpcode::COPY), RetReg).addReg(SrcReg);
1786 TII.get(TargetOpcode::COPY), RetRegs[i])
1793 TII.get(PPC::BLR8));
1822 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg)
1834 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::RLWINM),
1848 TII.get(PPC::RLDICL_32_64), DestReg)
1861 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::MTCTR8))
1863 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::BCTR8));
2028 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::LDtocCPT),
2031 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg)
2035 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::ADDIStocHA8),
2041 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::LDtocL),
2043 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg)
2047 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg)
2079 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::LDtoc),
2093 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::ADDIStocHA8),
2097 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::LDtocL),
2101 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::ADDItocL),
2121 TII.get(IsGPRC ? PPC::LI : PPC::LI8), ResultReg)
2127 TII.get(IsGPRC ? PPC::LIS : PPC::LIS8), TmpReg)
2130 TII.get(IsGPRC ? PPC::ORI : PPC::ORI8), ResultReg)
2135 TII.get(IsGPRC ? PPC::LIS : PPC::LIS8), ResultReg)
2174 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::RLDICR),
2182 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::ORIS8),
2189 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::ORI8),
2206 TII.get(CI->isZero() ? PPC::CRUNSET : PPC::CRSET), ImmReg);
2225 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ImmReg)
2277 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::ADDI8),
2388 TII.get(Imm == 0 ? PPC::CRUNSET : PPC::CRSET), ImmReg);
lib/Target/PowerPC/PPCFrameLowering.cpp 386 BuildMI(*MI.getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
390 BuildMI(*MI.getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
395 BuildMI(*MI.getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
399 BuildMI(*MI.getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
404 BuildMI(*MI.getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
408 BuildMI(*MI.getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
412 BuildMI(*MI.getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
840 const MCInstrDesc& MFLRInst = TII.get(isPPC64 ? PPC::MFLR8
842 const MCInstrDesc& StoreInst = TII.get(isPPC64 ? PPC::STD
844 const MCInstrDesc& StoreUpdtInst = TII.get(isPPC64 ? PPC::STDU
846 const MCInstrDesc& StoreUpdtIdxInst = TII.get(isPPC64 ? PPC::STDUX
848 const MCInstrDesc& LoadImmShiftedInst = TII.get(isPPC64 ? PPC::LIS8
850 const MCInstrDesc& OrImmInst = TII.get(isPPC64 ? PPC::ORI8
852 const MCInstrDesc& OrInst = TII.get(isPPC64 ? PPC::OR8
854 const MCInstrDesc& SubtractCarryingInst = TII.get(isPPC64 ? PPC::SUBFC8
856 const MCInstrDesc& SubtractImmCarryingInst = TII.get(isPPC64 ? PPC::SUBFIC8
978 BuildMI(MBB, MBBI, dl, TII.get(MfcrOpcode), TempReg);
981 BuildMI(MBB, MBBI, dl, TII.get(PPC::STW8))
1003 BuildMI(MBB, MBBI, dl, TII.get(MfcrOpcode), TempReg);
1035 BuildMI(MBB, MBBI, dl, TII.get(PPC::STW8))
1062 BuildMI(MBB, MBBI, dl, TII.get(PPC::RLDICL), ScratchReg)
1067 BuildMI(MBB, MBBI, dl, TII.get(PPC::RLWINM), ScratchReg)
1117 BuildMI(MBB, StackUpdateLoc, dl, TII.get(PPC::STD))
1136 BuildMI(MBB, MBBI, dl, TII.get(PPC::SUBF), ScratchReg)
1147 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDIC), ScratchReg)
1152 BuildMI(MBB, MBBI, dl, TII.get(PPC::STWX))
1159 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDIC), ScratchReg)
1163 BuildMI(MBB, MBBI, dl, TII.get(PPC::STWX))
1170 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDIC), ScratchReg)
1174 BuildMI(MBB, MBBI, dl, TII.get(PPC::STWX))
1179 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDIC), BPReg)
1229 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI), BPReg)
1253 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
1261 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
1270 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
1279 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
1288 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
1306 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
1342 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
1352 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
1364 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
1408 const MCInstrDesc& MTLRInst = TII.get( isPPC64 ? PPC::MTLR8
1410 const MCInstrDesc& LoadInst = TII.get( isPPC64 ? PPC::LD
1412 const MCInstrDesc& LoadImmShiftedInst = TII.get( isPPC64 ? PPC::LIS8
1414 const MCInstrDesc& OrInst = TII.get(isPPC64 ? PPC::OR8
1416 const MCInstrDesc& OrImmInst = TII.get( isPPC64 ? PPC::ORI8
1418 const MCInstrDesc& AddImmInst = TII.get( isPPC64 ? PPC::ADDI8
1420 const MCInstrDesc& AddInst = TII.get( isPPC64 ? PPC::ADD8
1606 BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ8), TempReg)
1610 BuildMI(MBB, MBBI, dl, TII.get(PPC::MTOCRF8), MustSaveCRs[i])
1630 BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ8), TempReg)
1688 BuildMI(MBB, MBBI, dl, TII.get(PPC::MTOCRF8), MustSaveCRs[i])
1738 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB)).
1743 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR));
1747 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA)).addImm(JumpTarget.getImm());
1751 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB8)).
1756 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR8));
1760 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA8)).addImm(JumpTarget.getImm());
2245 CRMIB = BuildMI(*MF, DL, TII.get(PPC::MFCR), PPC::R12)
2249 MBB.insert(MI, addFrameReference(BuildMI(*MF, DL, TII.get(PPC::STW))
2257 BuildMI(MBB, MI, DL, TII.get(PPC::MTVSRD), CSI[i].getDstReg())
2288 MBB.insert(MI, addFrameReference(BuildMI(*MF, DL, TII.get(PPC::LWZ),
2296 MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR2)
2300 MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR3)
2304 MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR4)
2327 BuildMI(MBB, I, dl, TII.get(ADDIInstr), StackReg)
2332 BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg)
2334 BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg)
2337 BuildMI(MBB, MBBI, dl, TII.get(ADDInstr), StackReg)
2414 BuildMI(MBB, I, DL, TII.get(PPC::MFVSRD), Reg)
lib/Target/PowerPC/PPCHazardRecognizers.cpp 282 const MCInstrDesc &MCID = DAG.TII->get(Opcode);
lib/Target/PowerPC/PPCISelDAGToDAG.cpp 405 BuildMI(EntryBB, IP, dl, TII.get(PPC::MFVRSAVE), InVRSAVE);
406 BuildMI(EntryBB, IP, dl, TII.get(PPC::UPDATE_VRSAVE),
408 BuildMI(EntryBB, IP, dl, TII.get(PPC::MTVRSAVE)).addReg(UpdatedVRSAVE);
422 BuildMI(*BB, IP, dl, TII.get(PPC::MTVRSAVE)).addReg(InVRSAVE);
444 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MoveGOTtoLR));
445 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR), GlobalBaseReg);
448 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR));
449 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR), GlobalBaseReg);
452 TII.get(PPC::UpdateGBR), GlobalBaseReg)
459 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR));
460 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR), GlobalBaseReg);
474 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR8));
475 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR8), GlobalBaseReg);
lib/Target/PowerPC/PPCISelLowering.cpp10381 BuildMI(BB, dl, TII->get(LoadMnemonic), dest)
10384 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest);
10389 BuildMI(BB, dl, TII->get(AtomicSize == 1 ? PPC::EXTSB : PPC::EXTSH),
10391 BuildMI(BB, dl, TII->get(CmpOpcode), PPC::CR0)
10394 BuildMI(BB, dl, TII->get(CmpOpcode), PPC::CR0)
10397 BuildMI(BB, dl, TII->get(PPC::BCC))
10403 BuildMI(BB, dl, TII->get(StoreMnemonic))
10405 BuildMI(BB, dl, TII->get(PPC::BCC))
10504 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
10512 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg)
10518 BuildMI(BB, dl, TII->get(PPC::XORI), ShiftReg)
10522 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
10527 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
10532 BuildMI(BB, dl, TII->get(PPC::SLW), Incr2Reg).addReg(incr).addReg(ShiftReg);
10534 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
10536 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
10537 BuildMI(BB, dl, TII->get(PPC::ORI), Mask2Reg)
10541 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
10546 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
10550 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg)
10553 BuildMI(BB, dl, TII->get(PPC::ANDC), Tmp2Reg)
10556 BuildMI(BB, dl, TII->get(PPC::AND), Tmp3Reg).addReg(TmpReg).addReg(MaskReg);
10561 BuildMI(BB, dl, TII->get(PPC::AND), SReg)
10568 BuildMI(BB, dl, TII->get(PPC::SRW), ValueReg)
10572 BuildMI(BB, dl, TII->get(is8bit ? PPC::EXTSB : PPC::EXTSH), ValueSReg)
10577 BuildMI(BB, dl, TII->get(CmpOpcode), PPC::CR0)
10580 BuildMI(BB, dl, TII->get(PPC::BCC))
10588 BuildMI(BB, dl, TII->get(PPC::OR), Tmp4Reg).addReg(Tmp3Reg).addReg(Tmp2Reg);
10589 BuildMI(BB, dl, TII->get(PPC::STWCX))
10593 BuildMI(BB, dl, TII->get(PPC::BCC))
10603 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW), dest)
10683 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::STD))
10699 TII->get(Subtarget.isPPC64() ? PPC::STD : PPC::STW))
10706 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::BCLalways)).addMBB(mainMBB);
10709 BuildMI(*thisMBB, MI, DL, TII->get(PPC::LI), restoreDstReg).addImm(1);
10711 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::EH_SjLj_Setup))
10713 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::B)).addMBB(sinkMBB);
10722 TII->get(Subtarget.isPPC64() ? PPC::MFLR8 : PPC::MFLR), LabelReg);
10726 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STD))
10731 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STW))
10738 BuildMI(mainMBB, DL, TII->get(PPC::LI), mainDstReg).addImm(0);
10743 TII->get(PPC::PHI), DstReg)
10789 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), FP)
10793 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), FP)
10801 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), Tmp)
10805 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), Tmp)
10813 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), SP)
10817 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), SP)
10825 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), BP)
10829 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), BP)
10838 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), PPC::X2)
10846 TII->get(PVT == MVT::i64 ? PPC::MTCTR8 : PPC::MTCTR)).addReg(Tmp);
10847 BuildMI(*MBB, MI, DL, TII->get(PVT == MVT::i64 ? PPC::BCTR8 : PPC::BCTR));
10968 BuildMI(BB, dl, TII->get(PPC::BC))
10973 BuildMI(BB, dl, TII->get(PPC::BCC))
10991 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::PHI), MI.getOperand(0).getReg())
11028 BuildMI(BB, dl, TII->get(PPC::MFSPR), HiReg).addImm(269);
11029 BuildMI(BB, dl, TII->get(PPC::MFSPR), LoReg).addImm(268);
11030 BuildMI(BB, dl, TII->get(PPC::MFSPR), ReadAgainReg).addImm(269);
11034 BuildMI(BB, dl, TII->get(PPC::CMPW), CmpReg)
11037 BuildMI(BB, dl, TII->get(PPC::BCC))
11210 BuildMI(BB, dl, TII->get(LoadMnemonic), dest).addReg(ptrA).addReg(ptrB);
11211 BuildMI(BB, dl, TII->get(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR0)
11214 BuildMI(BB, dl, TII->get(PPC::BCC))
11222 BuildMI(BB, dl, TII->get(StoreMnemonic))
11226 BuildMI(BB, dl, TII->get(PPC::BCC))
11230 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
11235 BuildMI(BB, dl, TII->get(StoreMnemonic))
11328 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
11337 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg)
11343 BuildMI(BB, dl, TII->get(PPC::XORI), ShiftReg)
11347 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
11352 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
11357 BuildMI(BB, dl, TII->get(PPC::SLW), NewVal2Reg)
11360 BuildMI(BB, dl, TII->get(PPC::SLW), OldVal2Reg)
11364 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
11366 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
11367 BuildMI(BB, dl, TII->get(PPC::ORI), Mask2Reg)
11371 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
11374 BuildMI(BB, dl, TII->get(PPC::AND), NewVal3Reg)
11377 BuildMI(BB, dl, TII->get(PPC::AND), OldVal3Reg)
11382 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
11385 BuildMI(BB, dl, TII->get(PPC::AND), TmpReg)
11388 BuildMI(BB, dl, TII->get(PPC::CMPW), PPC::CR0)
11391 BuildMI(BB, dl, TII->get(PPC::BCC))
11399 BuildMI(BB, dl, TII->get(PPC::ANDC), Tmp2Reg)
11402 BuildMI(BB, dl, TII->get(PPC::OR), Tmp4Reg)
11405 BuildMI(BB, dl, TII->get(PPC::STWCX))
11409 BuildMI(BB, dl, TII->get(PPC::BCC))
11413 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
11418 BuildMI(BB, dl, TII->get(PPC::STWCX))
11427 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW), dest)
11443 BuildMI(*BB, MI, dl, TII->get(PPC::MFFS), MFFSReg);
11446 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB1)).addImm(31);
11447 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB0)).addImm(30);
11450 BuildMI(*BB, MI, dl, TII->get(PPC::FADD), Dest).addReg(Src1).addReg(Src2);
11453 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSFb)).addImm(1).addReg(MFFSReg);
11470 BuildMI(*BB, MI, dl, TII->get(Opcode), Dest)
11473 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY),
11480 BuildMI(*BB, MI, Dl, TII->get(PPC::TCHECK), CRReg);
11481 BuildMI(*BB, MI, Dl, TII->get(TargetOpcode::COPY),
11487 BuildMI(*BB, MI, Dl, TII->get(PPC::TBEGIN)).addImm(Imm);
11488 BuildMI(*BB, MI, Dl, TII->get(TargetOpcode::COPY),
11496 BuildMI(*BB, MI, dl, TII->get(PPC::MFFS), OldFPSCRReg);
11508 BuildMI(*BB, MI, dl, TII->get((Mode & 1) ? PPC::MTFSB1 : PPC::MTFSB0))
11511 BuildMI(*BB, MI, dl, TII->get((Mode & 2) ? PPC::MTFSB1 : PPC::MTFSB0))
11523 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), DestReg)
11553 BuildMI(*BB, MI, dl, TII->get(StoreOp))
11567 BuildMI(*BB, MI, dl, TII->get(LoadOp), DestReg)
11577 BuildMI(*BB, MI, dl, TII->get(PPC::MFFS), OldFPSCRReg);
11599 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::IMPLICIT_DEF), ImDefReg);
11600 BuildMI(*BB, MI, dl, TII->get(PPC::INSERT_SUBREG), ExtSrcReg)
11606 BuildMI(*BB, MI, dl, TII->get(PPC::RLDIMI), NewFPSCRTmpReg)
11617 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSF))
15057 BuildMI(*Entry, MBBI, DebugLoc(), TII->get(TargetOpcode::COPY), NewVR)
15063 TII->get(TargetOpcode::COPY), *I)
lib/Target/PowerPC/PPCInstrInfo.cpp 484 BuildMI(MBB, MI, DL, get(Opcode));
719 BuildMI(&MBB, DL, get(PPC::B)).addMBB(TBB);
721 BuildMI(&MBB, DL, get(Cond[0].getImm() ?
725 BuildMI(&MBB, DL, get(PPC::BC)).add(Cond[1]).addMBB(TBB);
727 BuildMI(&MBB, DL, get(PPC::BCn)).add(Cond[1]).addMBB(TBB);
729 BuildMI(&MBB, DL, get(PPC::BCC))
738 BuildMI(&MBB, DL, get(Cond[0].getImm() ?
742 BuildMI(&MBB, DL, get(PPC::BC)).add(Cond[1]).addMBB(TBB);
744 BuildMI(&MBB, DL, get(PPC::BCn)).add(Cond[1]).addMBB(TBB);
746 BuildMI(&MBB, DL, get(PPC::BCC))
750 BuildMI(&MBB, DL, get(PPC::B)).addMBB(FBB);
868 BuildMI(MBB, MI, dl, get(TargetOpcode::COPY), FirstReg)
872 BuildMI(MBB, MI, dl, get(OpCode), DestReg)
935 BuildMI(MBB, I, DL, get(PPC::MFOCRF), DestReg).addReg(CRReg);
939 BuildMI(MBB, I, DL, get(PPC::RLWINM), DestReg)
947 BuildMI(MBB, I, DL, get(PPC::MFOCRF8), DestReg).addReg(SrcReg);
952 BuildMI(MBB, I, DL, get(PPC::MFOCRF), DestReg).addReg(SrcReg);
959 BuildMI(MBB, I, DL, get(PPC::MTVSRD), DestReg).addReg(SrcReg);
967 BuildMI(MBB, I, DL, get(PPC::MFVSRD), DestReg).addReg(SrcReg);
972 BuildMI(MBB, I, DL, get(PPC::EFSCFD), DestReg).addReg(SrcReg);
977 BuildMI(MBB, I, DL, get(PPC::EFDCFS), DestReg).addReg(SrcReg);
1019 const MCInstrDesc &MCID = get(Opc);
1210 BuildMI(MF, DL, get(Opcode)).addReg(SrcReg, getKillRegState(isKill)),
1261 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(Opcode), DestReg),
1443 MI.setDesc(get(Pred[0].getImm() ? (isPPC64 ? PPC::BDNZLR8 : PPC::BDNZLR)
1446 MI.setDesc(get(PPC::BCLR));
1449 MI.setDesc(get(PPC::BCLRn));
1452 MI.setDesc(get(PPC::BCCLR));
1462 MI.setDesc(get(Pred[0].getImm() ? (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ)
1468 MI.setDesc(get(PPC::BC));
1476 MI.setDesc(get(PPC::BCn));
1484 MI.setDesc(get(PPC::BCC));
1501 MI.setDesc(get(isPPC64 ? (setLR ? PPC::BCCTRL8 : PPC::BCCTR8)
1506 MI.setDesc(get(isPPC64 ? (setLR ? PPC::BCCTRL8n : PPC::BCCTR8n)
1512 MI.setDesc(get(isPPC64 ? (setLR ? PPC::BCCCTRL8 : PPC::BCCCTR8)
1914 get(TargetOpcode::COPY), CRReg)
1976 const MCInstrDesc &NewDesc = get(NewOpC);
2024 return get(Opcode).getSize();
2124 MI.setDesc(get(Opcode));
2142 MI.setDesc(get(Subtarget.isPPC64() ? PPC::LD : PPC::LWZ));
2181 MI.setDesc(get(PPC::DFLOADf64));
2185 MI.setDesc(get(PPC::LD));
2192 MI.setDesc(get(PPC::DFSTOREf64));
2196 MI.setDesc(get(PPC::STD));
2203 MI.setDesc(get(PPC::LXSDX));
2205 MI.setDesc(get(PPC::LDX));
2212 MI.setDesc(get(PPC::STXSDX));
2215 MI.setDesc(get(PPC::STDX));
2222 BuildMI(MBB, MI, DL, get(PPC::CMPD), PPC::CR7).addReg(Val).addReg(Val);
2223 BuildMI(MBB, MI, DL, get(PPC::CTRL_DEP))
2227 MI.setDesc(get(PPC::ISYNC));
2309 MI.setDesc(get(LII.Is64Bit ? PPC::ANDIo8 : PPC::ANDIo));
2316 MI.setDesc(get(LII.Is64Bit ? PPC::LI8 : PPC::LI));
2627 MI.setDesc(get(XFormOpcode));
2841 CompareUseMI.setDesc(get(UseOpc == PPC::ISEL8 ? PPC::LI8 : PPC::LI));
2852 CompareUseMI.setDesc(get(PPC::COPY));
3688 MI.setDesc(get(III.ImmOpcode));
3769 MI.setDesc(get(III.ImmOpcode));
3790 MI.setDesc(get(PPC::COPY));
lib/Target/PowerPC/PPCInstrInfo.h 188 return get(Opcode).TSFlags & PPCII::XFormMemOp;
lib/Target/PowerPC/PPCMIPeephole.cpp 372 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY),
393 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY),
418 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY),
474 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY),
600 SrcMI->setDesc(TII->get(Opc));
644 SrcMI->setDesc(TII->get(Opc));
656 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::IMPLICIT_DEF),
658 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::INSERT_SUBREG),
705 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY),
784 LiMI->setDesc(TII->get(LiMI->getOpcode() == PPC::LI ? PPC::ADDI
795 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY),
1256 CMPI1->setDesc(TII->get(NewOpCode));
1298 TII->get(PPC::PHI), NewVReg)
1373 MI.setDesc(TII->get(PPC::RLDIC));
1441 SrcMI->getOpcode() == PPC::EXTSW ? TII->get(PPC::EXTSWSLI)
1442 : TII->get(PPC::EXTSWSLI_32_64),
lib/Target/PowerPC/PPCPreEmitPeephole.cpp 178 const MCInstrDesc &MCID = TII->get(Opc);
lib/Target/PowerPC/PPCReduceCRLogicals.cpp 220 TII->get(NewBROpcode))
224 TII->get(PPC::B))
237 FirstTerminator->setDesc(TII->get(InvertedOpcode));
lib/Target/PowerPC/PPCRegisterInfo.cpp 533 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), Reg)
537 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), Reg)
541 BuildMI(MBB, II, dl, TII.get(PPC::LD), Reg)
545 BuildMI(MBB, II, dl, TII.get(PPC::LWZ), Reg)
562 BuildMI(MBB, II, dl, TII.get(PPC::LI8), NegSizeReg)
567 BuildMI(MBB, II, dl, TII.get(PPC::AND8), NegSizeReg)
573 BuildMI(MBB, II, dl, TII.get(PPC::STDUX), PPC::X1)
577 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg())
587 BuildMI(MBB, II, dl, TII.get(PPC::LI), NegSizeReg)
592 BuildMI(MBB, II, dl, TII.get(PPC::AND), NegSizeReg)
598 BuildMI(MBB, II, dl, TII.get(PPC::STWUX), PPC::R1)
602 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg())
628 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::LI8 : PPC::LI),
662 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), Reg)
672 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg)
679 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::STW8 : PPC::STW))
707 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LWZ8 : PPC::LWZ),
718 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg)
723 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MTOCRF8 : PPC::MTOCRF), DestReg)
773 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LI8 : PPC::LI), Reg)
777 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LIS8 : PPC::LIS), Reg)
786 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), Reg)
797 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg)
802 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::STW8 : PPC::STW))
830 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LWZ8 : PPC::LWZ),
833 BuildMI(MBB, II, dl, TII.get(TargetOpcode::IMPLICIT_DEF), DestReg);
836 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), RegO)
841 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWIMI8 : PPC::RLWIMI), RegO)
848 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MTOCRF8 : PPC::MTOCRF),
875 BuildMI(MBB, II, dl, TII.get(PPC::MFVRSAVEv), Reg)
879 BuildMI(MBB, II, dl, TII.get(PPC::STW)).addReg(Reg, RegState::Kill),
903 addFrameReference(BuildMI(MBB, II, dl, TII.get(PPC::LWZ),
906 BuildMI(MBB, II, dl, TII.get(PPC::MTVRSAVEv), DestReg)
1101 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::LI8 : PPC::LI), SReg)
1104 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::LIS8 : PPC::LIS), SRegHi)
1106 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::ORI8 : PPC::ORI), SReg)
1124 MI.setDesc(TII.get(NewOpcode));
1233 const MCInstrDesc &MCID = TII.get(ADDriOpc);
lib/Target/PowerPC/PPCTLSDynamicCall.cpp 112 BuildMI(MBB, I, DL, TII->get(PPC::ADJCALLSTACKDOWN)).addImm(0)
116 MachineInstr *Addi = BuildMI(MBB, I, DL, TII->get(Opc1), GPR3)
125 MachineInstr *Call = (BuildMI(MBB, I, DL, TII->get(Opc2), GPR3)
130 BuildMI(MBB, I, DL, TII->get(PPC::ADJCALLSTACKUP)).addImm(0).addImm(0);
132 BuildMI(MBB, I, DL, TII->get(TargetOpcode::COPY), OutReg)
lib/Target/PowerPC/PPCVSXCopy.cpp 107 TII->get(TargetOpcode::SUBREG_TO_REG), NewVReg)
128 BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(TargetOpcode::COPY),
lib/Target/PowerPC/PPCVSXFMAMutate.cpp 259 MI.setDesc(TII->get(AltOpc));
lib/Target/PowerPC/PPCVSXSwapRemoval.cpp 803 TII->get(PPC::XXPERMDI), DstReg)
917 TII->get(PPC::COPY), VSRCTmp1)
925 TII->get(PPC::COPY), DstReg)
951 BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(TargetOpcode::COPY),
lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp 179 const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
251 MCInstrDesc const &Desc = MCII.get(MI.getOpcode());
lib/Target/RISCV/RISCVExpandPseudoInsts.cpp 250 BuildMI(LoopMBB, DL, TII->get(getLRForRMW(Ordering, Width)), DestReg)
256 BuildMI(LoopMBB, DL, TII->get(RISCV::AND), ScratchReg)
259 BuildMI(LoopMBB, DL, TII->get(RISCV::XORI), ScratchReg)
264 BuildMI(LoopMBB, DL, TII->get(getSCForRMW(Ordering, Width)), ScratchReg)
267 BuildMI(LoopMBB, DL, TII->get(RISCV::BNE))
284 BuildMI(MBB, DL, TII->get(RISCV::XOR), ScratchReg)
287 BuildMI(MBB, DL, TII->get(RISCV::AND), ScratchReg)
290 BuildMI(MBB, DL, TII->get(RISCV::XOR), DestReg)
316 BuildMI(LoopMBB, DL, TII->get(getLRForRMW32(Ordering)), DestReg)
322 BuildMI(LoopMBB, DL, TII->get(RISCV::ADD), ScratchReg)
327 BuildMI(LoopMBB, DL, TII->get(RISCV::ADD), ScratchReg)
332 BuildMI(LoopMBB, DL, TII->get(RISCV::SUB), ScratchReg)
337 BuildMI(LoopMBB, DL, TII->get(RISCV::AND), ScratchReg)
340 BuildMI(LoopMBB, DL, TII->get(RISCV::XORI), ScratchReg)
349 BuildMI(LoopMBB, DL, TII->get(getSCForRMW32(Ordering)), ScratchReg)
352 BuildMI(LoopMBB, DL, TII->get(RISCV::BNE))
399 BuildMI(MBB, DL, TII->get(RISCV::SLL), ValReg)
402 BuildMI(MBB, DL, TII->get(RISCV::SRA), ValReg)
456 BuildMI(LoopHeadMBB, DL, TII->get(getLRForRMW32(Ordering)), DestReg)
458 BuildMI(LoopHeadMBB, DL, TII->get(RISCV::AND), Scratch2Reg)
461 BuildMI(LoopHeadMBB, DL, TII->get(RISCV::ADDI), Scratch1Reg)
470 BuildMI(LoopHeadMBB, DL, TII->get(RISCV::BGE))
478 BuildMI(LoopHeadMBB, DL, TII->get(RISCV::BGE))
485 BuildMI(LoopHeadMBB, DL, TII->get(RISCV::BGEU))
491 BuildMI(LoopHeadMBB, DL, TII->get(RISCV::BGEU))
508 BuildMI(LoopTailMBB, DL, TII->get(getSCForRMW32(Ordering)), Scratch1Reg)
511 BuildMI(LoopTailMBB, DL, TII->get(RISCV::BNE))
564 BuildMI(LoopHeadMBB, DL, TII->get(getLRForRMW(Ordering, Width)), DestReg)
566 BuildMI(LoopHeadMBB, DL, TII->get(RISCV::BNE))
573 BuildMI(LoopTailMBB, DL, TII->get(getSCForRMW(Ordering, Width)), ScratchReg)
576 BuildMI(LoopTailMBB, DL, TII->get(RISCV::BNE))
586 BuildMI(LoopHeadMBB, DL, TII->get(getLRForRMW(Ordering, Width)), DestReg)
588 BuildMI(LoopHeadMBB, DL, TII->get(RISCV::AND), ScratchReg)
591 BuildMI(LoopHeadMBB, DL, TII->get(RISCV::BNE))
604 BuildMI(LoopTailMBB, DL, TII->get(getSCForRMW(Ordering, Width)), ScratchReg)
607 BuildMI(LoopTailMBB, DL, TII->get(RISCV::BNE))
643 BuildMI(NewMBB, DL, TII->get(RISCV::AUIPC), DestReg)
645 BuildMI(NewMBB, DL, TII->get(SecondOpcode), DestReg)
lib/Target/RISCV/RISCVFrameLowering.cpp 74 BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADDI), DestReg)
88 BuildMI(MBB, MBBI, DL, TII->get(Opc), DestReg)
152 BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
171 BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
187 BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
201 BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
213 BuildMI(MBB, MBBI, DL, TII->get(RISCV::ANDI), SPReg)
220 BuildMI(MBB, MBBI, DL, TII->get(RISCV::SRLI), VR)
223 BuildMI(MBB, MBBI, DL, TII->get(RISCV::SLLI), SPReg)
273 BuildMI(MBB, LastFrameDestroy, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
289 TII->get(TargetOpcode::CFI_INSTRUCTION))
305 BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
319 BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
lib/Target/RISCV/RISCVISelLowering.cpp 1128 BuildMI(LoopMBB, DL, TII->get(RISCV::CSRRS), HiReg)
1131 BuildMI(LoopMBB, DL, TII->get(RISCV::CSRRS), LoReg)
1134 BuildMI(LoopMBB, DL, TII->get(RISCV::CSRRS), ReadAgainReg)
1138 BuildMI(LoopMBB, DL, TII->get(RISCV::BNE))
1170 BuildMI(*BB, MI, DL, TII.get(RISCV::LW), LoReg)
1174 BuildMI(*BB, MI, DL, TII.get(RISCV::LW), HiReg)
1200 BuildMI(*BB, MI, DL, TII.get(RISCV::SW))
1205 BuildMI(*BB, MI, DL, TII.get(RISCV::SW))
1318 BuildMI(HeadMBB, DL, TII.get(Opcode))
1335 TII.get(RISCV::PHI), SelectMBBI->getOperand(0).getReg())
lib/Target/RISCV/RISCVInstrInfo.cpp 90 BuildMI(MBB, MBBI, DL, get(RISCV::ADDI), DstReg)
105 BuildMI(MBB, MBBI, DL, get(Opc), DstReg)
131 BuildMI(MBB, I, DL, get(Opcode))
158 BuildMI(MBB, I, DL, get(Opcode), DstReg).addFrameIndex(FI).addImm(0);
186 BuildMI(MBB, MBBI, DL, get(RISCV::LUI), Result)
190 BuildMI(MBB, MBBI, DL, get(Inst.Opc), Result)
348 MachineInstr &MI = *BuildMI(&MBB, DL, get(RISCV::PseudoBR)).addMBB(TBB);
357 *BuildMI(&MBB, DL, get(Opc)).add(Cond[1]).add(Cond[2]).addMBB(TBB);
366 MachineInstr &MI = *BuildMI(&MBB, DL, get(RISCV::PseudoBR)).addMBB(FBB);
399 MachineInstr &LuiMI = *BuildMI(MBB, II, DL, get(RISCV::LUI), ScratchReg)
401 BuildMI(MBB, II, DL, get(RISCV::PseudoBRIND))
454 default: { return get(Opcode).getSize(); }
494 MCInstrDesc const &Desc = MCII->get(MI.getOpcode());
lib/Target/RISCV/RISCVRegisterInfo.cpp 133 BuildMI(MBB, II, DL, TII->get(RISCV::ADD), ScratchReg)
lib/Target/Sparc/DelaySlotFiller.cpp 128 BuildMI(MBB, I, MI->getDebugLoc(), TII->get(SP::NOP));
146 BuildMI(MBB, I, MI->getDebugLoc(), TII->get(SP::NOP));
156 TII->get(SP::UNIMP)).addImm(structSize);
188 slot->setDesc(Subtarget->getInstrInfo()->get(SP::RET));
391 AddMI->setDesc(TII->get((AddMI->getOpcode() == SP::ADDrr)
430 OrMI->setDesc(TII->get((OrMI->getOpcode() == SP::ORrr)
467 RestoreMI->setDesc(TII->get(SP::RESTOREri));
lib/Target/Sparc/LeonPasses.cpp 53 BuildMI(MBB, NMBBI, DL, TII.get(SP::NOP));
145 BuildMI(MBB, MBBI, DL, TII.get(SP::NOP));
149 BuildMI(MBB, NMBBI, DL, TII.get(SP::NOP));
lib/Target/Sparc/SparcFrameLowering.cpp 52 BuildMI(MBB, MBBI, dl, TII.get(ADDri), SP::O6)
64 BuildMI(MBB, MBBI, dl, TII.get(SP::SETHIi), SP::G1)
66 BuildMI(MBB, MBBI, dl, TII.get(SP::ORri), SP::G1)
68 BuildMI(MBB, MBBI, dl, TII.get(ADDrr), SP::O6)
77 BuildMI(MBB, MBBI, dl, TII.get(SP::SETHIi), SP::G1)
79 BuildMI(MBB, MBBI, dl, TII.get(SP::XORri), SP::G1)
81 BuildMI(MBB, MBBI, dl, TII.get(ADDrr), SP::O6)
163 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
168 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
176 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
186 BuildMI(MBB, MBBI, dl, TII.get(SP::ADDri), regUnbiased)
193 BuildMI(MBB, MBBI, dl, TII.get(SP::ANDNri), regUnbiased)
198 BuildMI(MBB, MBBI, dl, TII.get(SP::ADDri), SP::O6)
230 BuildMI(MBB, MBBI, dl, TII.get(SP::RESTORErr), SP::G0).addReg(SP::G0)
lib/Target/Sparc/SparcISelLowering.cpp 3153 BuildMI(ThisMBB, dl, TII.get(BROpcode))
3161 BuildMI(*SinkMBB, SinkMBB->begin(), dl, TII.get(SP::PHI),
lib/Target/Sparc/SparcInstrInfo.cpp 255 BuildMI(&MBB, DL, get(SP::BA)).addMBB(TBB);
263 BuildMI(&MBB, DL, get(SP::BCOND)).addMBB(TBB).addImm(CC);
265 BuildMI(&MBB, DL, get(SP::FBCOND)).addMBB(TBB).addImm(CC);
269 BuildMI(&MBB, DL, get(SP::BA)).addMBB(FBB);
322 BuildMI(MBB, I, DL, get(SP::ORrr), DestReg).addReg(SP::G0)
330 BuildMI(MBB, I, DL, get(SP::FMOVS), DestReg)
334 BuildMI(MBB, I, DL, get(SP::FMOVD), DestReg)
345 BuildMI(MBB, I, DL, get(SP::FMOVQ), DestReg)
361 BuildMI(MBB, I, DL, get(SP::WRASRrr), DestReg)
366 BuildMI(MBB, I, DL, get(SP::RDASR), DestReg)
382 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(movOpc), Dst);
410 BuildMI(MBB, I, DL, get(SP::STXri)).addFrameIndex(FI).addImm(0)
413 BuildMI(MBB, I, DL, get(SP::STri)).addFrameIndex(FI).addImm(0)
416 BuildMI(MBB, I, DL, get(SP::STDri)).addFrameIndex(FI).addImm(0)
419 BuildMI(MBB, I, DL, get(SP::STFri)).addFrameIndex(FI).addImm(0)
422 BuildMI(MBB, I, DL, get(SP::STDFri)).addFrameIndex(FI).addImm(0)
427 BuildMI(MBB, I, DL, get(SP::STQFri)).addFrameIndex(FI).addImm(0)
448 BuildMI(MBB, I, DL, get(SP::LDXri), DestReg).addFrameIndex(FI).addImm(0)
451 BuildMI(MBB, I, DL, get(SP::LDri), DestReg).addFrameIndex(FI).addImm(0)
454 BuildMI(MBB, I, DL, get(SP::LDDri), DestReg).addFrameIndex(FI).addImm(0)
457 BuildMI(MBB, I, DL, get(SP::LDFri), DestReg).addFrameIndex(FI).addImm(0)
460 BuildMI(MBB, I, DL, get(SP::LDDFri), DestReg).addFrameIndex(FI).addImm(0)
465 BuildMI(MBB, I, DL, get(SP::LDQFri), DestReg).addFrameIndex(FI).addImm(0)
489 BuildMI(FirstMBB, MBBI, dl, get(SP::GETPCX), GlobalBaseReg);
501 MI.setDesc(get(Subtarget.is64Bit() ? SP::LDXri : SP::LDri));
lib/Target/Sparc/SparcRegisterInfo.cpp 132 BuildMI(*MI.getParent(), II, dl, TII.get(SP::SETHIi), SP::G1)
137 BuildMI(*MI.getParent(), II, dl, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1)
150 BuildMI(*MI.getParent(), II, dl, TII.get(SP::SETHIi), SP::G1)
152 BuildMI(*MI.getParent(), II, dl, TII.get(SP::XORri), SP::G1)
155 BuildMI(*MI.getParent(), II, dl, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1)
189 BuildMI(*MI.getParent(), II, dl, TII.get(SP::STDFri))
192 MI.setDesc(TII.get(SP::STDFri));
201 BuildMI(*MI.getParent(), II, dl, TII.get(SP::LDDFri), DestEvenReg)
205 MI.setDesc(TII.get(SP::LDDFri));
lib/Target/SystemZ/MCTargetDesc/SystemZMCCodeEmitter.cpp 162 unsigned Size = MCII.get(MI.getOpcode()).getSize();
lib/Target/SystemZ/SystemZElimCompare.cpp 234 Branch->setDesc(TII->get(BRCT));
277 Branch->setDesc(TII->get(LATOpcode));
299 auto MIB = BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), TII->get(Opcode));
319 const MCInstrDesc &Desc = TII->get(Opcode);
562 Branch->setDesc(TII->get(FusedOpcode));
lib/Target/SystemZ/SystemZFrameLowering.cpp 183 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(SystemZ::STMG));
261 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(SystemZ::LMG));
333 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII->get(Opcode), Reg)
375 BuildMI(MBB, MBBI, DL, ZII->get(TargetOpcode::CFI_INSTRUCTION))
397 BuildMI(MBB, MBBI, DL, ZII->get(SystemZ::LGR))
407 BuildMI(MBB, MBBI, DL, ZII->get(TargetOpcode::CFI_INSTRUCTION))
412 BuildMI(MBB, MBBI, DL, ZII->get(SystemZ::STG))
418 BuildMI(MBB, MBBI, DL, ZII->get(SystemZ::LGR), SystemZ::R11D)
425 BuildMI(MBB, MBBI, DL, ZII->get(TargetOpcode::CFI_INSTRUCTION))
468 BuildMI(MBB, MBBI, DL, ZII->get(TargetOpcode::CFI_INSTRUCTION))
507 MBBI->setDesc(ZII->get(NewOpcode));
lib/Target/SystemZ/SystemZISelLowering.cpp 6512 BuildMI(*MBB, MI, MI.getDebugLoc(), TII->get(SystemZ::LA), Reg)
6606 BuildMI(*SinkMBB, SinkInsertionPoint, DL, TII->get(SystemZ::PHI), DestReg)
6684 BuildMI(MBB, MI.getDebugLoc(), TII->get(SystemZ::BRC))
6747 BuildMI(*MBB, MI, DL, TII->get(STOCOpcode))
6778 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
6787 BuildMI(MBB, DL, TII->get(StoreOpcode))
6856 BuildMI(MBB, DL, TII->get(LOpcode), OrigVal).add(Base).addImm(Disp).addReg(0);
6868 BuildMI(MBB, DL, TII->get(SystemZ::PHI), OldVal)
6872 BuildMI(MBB, DL, TII->get(SystemZ::RLL), RotatedOldVal)
6877 BuildMI(MBB, DL, TII->get(BinOpcode), Tmp).addReg(RotatedOldVal).add(Src2);
6880 BuildMI(MBB, DL, TII->get(SystemZ::XILF), RotatedNewVal)
6886 BuildMI(MBB, DL, TII->get(SystemZ::LCGR), Tmp2).addReg(Tmp);
6887 BuildMI(MBB, DL, TII->get(SystemZ::AGHI), RotatedNewVal)
6892 BuildMI(MBB, DL, TII->get(BinOpcode), RotatedNewVal)
6898 BuildMI(MBB, DL, TII->get(SystemZ::RISBG32), RotatedNewVal)
6902 BuildMI(MBB, DL, TII->get(SystemZ::RLL), NewVal)
6904 BuildMI(MBB, DL, TII->get(CSOpcode), Dest)
6909 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
6976 BuildMI(MBB, DL, TII->get(LOpcode), OrigVal).add(Base).addImm(Disp).addReg(0);
6985 BuildMI(MBB, DL, TII->get(SystemZ::PHI), OldVal)
6989 BuildMI(MBB, DL, TII->get(SystemZ::RLL), RotatedOldVal)
6991 BuildMI(MBB, DL, TII->get(CompareOpcode))
6993 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
7003 BuildMI(MBB, DL, TII->get(SystemZ::RISBG32), RotatedAltVal)
7016 BuildMI(MBB, DL, TII->get(SystemZ::PHI), RotatedNewVal)
7020 BuildMI(MBB, DL, TII->get(SystemZ::RLL), NewVal)
7022 BuildMI(MBB, DL, TII->get(CSOpcode), Dest)
7027 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
7086 BuildMI(MBB, DL, TII->get(LOpcode), OrigOldVal)
7107 BuildMI(MBB, DL, TII->get(SystemZ::PHI), OldVal)
7110 BuildMI(MBB, DL, TII->get(SystemZ::PHI), CmpVal)
7113 BuildMI(MBB, DL, TII->get(SystemZ::PHI), SwapVal)
7116 BuildMI(MBB, DL, TII->get(SystemZ::RLL), Dest)
7118 BuildMI(MBB, DL, TII->get(SystemZ::RISBG32), RetryCmpVal)
7120 BuildMI(MBB, DL, TII->get(SystemZ::CR))
7122 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
7138 BuildMI(MBB, DL, TII->get(SystemZ::RISBG32), RetrySwapVal)
7140 BuildMI(MBB, DL, TII->get(SystemZ::RLL), StoreVal)
7142 BuildMI(MBB, DL, TII->get(CSOpcode), RetryOldVal)
7147 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
7178 BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::IMPLICIT_DEF), Tmp1);
7179 BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::INSERT_SUBREG), Tmp2)
7181 BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::INSERT_SUBREG), Dest)
7204 BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::IMPLICIT_DEF), In128);
7209 BuildMI(*MBB, MI, DL, TII->get(SystemZ::LLILL), Zero64)
7211 BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::INSERT_SUBREG), NewIn128)
7215 BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::INSERT_SUBREG), Dest)
7285 BuildMI(MBB, DL, TII->get(SystemZ::PHI), ThisDestReg)
7289 BuildMI(MBB, DL, TII->get(SystemZ::PHI), ThisSrcReg)
7292 BuildMI(MBB, DL, TII->get(SystemZ::PHI), ThisCountReg)
7296 BuildMI(MBB, DL, TII->get(SystemZ::PFD))
7299 BuildMI(MBB, DL, TII->get(Opcode))
7303 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
7321 BuildMI(MBB, DL, TII->get(SystemZ::LA), NextDestReg)
7324 BuildMI(MBB, DL, TII->get(SystemZ::LA), NextSrcReg)
7326 BuildMI(MBB, DL, TII->get(SystemZ::AGHI), NextCountReg)
7328 BuildMI(MBB, DL, TII->get(SystemZ::CGHI))
7330 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
7352 BuildMI(*MBB, MI, MI.getDebugLoc(), TII->get(SystemZ::LAY), Reg)
7361 BuildMI(*MBB, MI, MI.getDebugLoc(), TII->get(SystemZ::LAY), Reg)
7368 BuildMI(*MBB, MI, DL, TII->get(Opcode))
7382 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
7439 BuildMI(MBB, DL, TII->get(SystemZ::PHI), This1Reg)
7442 BuildMI(MBB, DL, TII->get(SystemZ::PHI), This2Reg)
7445 BuildMI(MBB, DL, TII->get(TargetOpcode::COPY), SystemZ::R0L).addReg(CharReg);
7446 BuildMI(MBB, DL, TII->get(Opcode))
7449 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
7469 MI.setDesc(TII->get(Opcode));
7525 BuildMI(*MBB, MI, DL, TII->get(Opcode), DstReg)
lib/Target/SystemZ/SystemZInstrInfo.cpp 111 EarlierMI->setDesc(get(HighOpcode));
112 MI->setDesc(get(LowOpcode));
127 MI->setDesc(get(NewOpcode));
142 MI.setDesc(get(IsHigh ? HighOpcode : LowOpcode));
159 MI.setDesc(get(LowOpcodeK));
167 MI.setDesc(get(DestIsHigh ? HighOpcode : LowOpcode));
181 MI.setDesc(get(Opcode));
191 MI.setDesc(get(Opcode));
221 BuildMI(*MBB, MI, MI->getDebugLoc(), get(SystemZ::EAR), Reg32)
226 BuildMI(*MBB, MI, MI->getDebugLoc(), get(SystemZ::SLLG), Reg64)
232 BuildMI(*MBB, MI, MI->getDebugLoc(), get(SystemZ::EAR), Reg32)
236 MI->setDesc(get(SystemZ::LG));
262 return BuildMI(MBB, MBBI, DL, get(LowLowOpcode), DestReg)
266 return BuildMI(MBB, MBBI, DL, get(Opcode), DestReg)
496 BuildMI(&MBB, DL, get(SystemZ::J)).addMBB(TBB);
504 BuildMI(&MBB, DL, get(SystemZ::BRC))
510 BuildMI(&MBB, DL, get(SystemZ::J)).addMBB(FBB);
590 BuildMI(MBB, I, DL, get(TargetOpcode::COPY), TReg).addReg(TrueReg);
591 BuildMI(MBB, I, DL, get(TargetOpcode::COPY), FReg).addReg(FalseReg);
603 BuildMI(MBB, I, DL, get(Opc), DstReg)
662 UseMI.setDesc(get(NewUseOpc));
726 MI.setDesc(get(SystemZ::CondTrap));
733 MI.setDesc(get(SystemZ::CondReturn));
744 MI.setDesc(get(SystemZ::CallBRCL));
756 MI.setDesc(get(SystemZ::CallBCR));
801 BuildMI(MBB, MBBI, DL, get(SystemZ::VMRHG), DestReg)
817 BuildMI(MBB, MBBI, DL, get(SystemZ::VREPG), DestRegLo)
824 auto MIB = BuildMI(MBB, MBBI, DL, get(SystemZ::IPM), DestReg);
833 BuildMI(MBB, MBBI, DL, get(SystemZ::TMLH))
867 BuildMI(MBB, MBBI, DL, get(Opcode), DestReg)
881 addFrameReference(BuildMI(MBB, MBBI, DL, get(StoreOpcode))
896 addFrameReference(BuildMI(MBB, MBBI, DL, get(LoadOpcode), DestReg),
974 BuildMI(*MBB, MI, MI.getDebugLoc(), get(NewOpcode))
1021 MI.getDebugLoc(), get(SystemZ::AGSI))
1048 BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(), get(Opcode))
1063 BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(), get(Opcode))
1078 BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(), get(Opcode))
1094 get(StoreOpcode))
1105 get(LoadOpcode))
1132 get(SystemZ::MVC))
1143 get(SystemZ::MVC))
1186 const MCInstrDesc &MemDesc = get(MemOpcode);
1192 MI.getDebugLoc(), get(MemOpcode));
1375 MI.setDesc(get(DestIsHigh ? SystemZ::RISBHH : SystemZ::RISBLL));
1377 MI.setDesc(get(DestIsHigh ? SystemZ::RISBHL : SystemZ::RISBLH));
1503 const MCInstrDesc &MCID = get(Opcode);
1748 BuildMI(MBB, MBBI, DL, get(Opcode), Reg).addImm(Value);
lib/Target/SystemZ/SystemZLDCleanup.cpp 120 TII->get(TargetOpcode::COPY), SystemZ::R2D)
140 TII->get(TargetOpcode::COPY), *TLSBaseAddrReg)
lib/Target/SystemZ/SystemZLongBranch.cpp 358 BuildMI(*MBB, MI, DL, TII->get(AddOpcode))
362 MachineInstr *BRCL = BuildMI(*MBB, MI, DL, TII->get(SystemZ::BRCL))
377 BuildMI(*MBB, MI, DL, TII->get(CompareOpcode))
380 MachineInstr *BRCL = BuildMI(*MBB, MI, DL, TII->get(SystemZ::BRCL))
394 Branch->setDesc(TII->get(SystemZ::JG));
397 Branch->setDesc(TII->get(SystemZ::BRCL));
lib/Target/SystemZ/SystemZPostRewrite.cpp 95 MBBI->setDesc(TII->get(LowOpcode));
97 MBBI->setDesc(TII->get(HighOpcode));
123 TII->get(SystemZ::COPY), DestReg)
130 TII->get(SystemZ::COPY), DestReg)
146 MBBI->setDesc(TII->get(LowOpcode));
148 MBBI->setDesc(TII->get(HighOpcode));
193 BuildMI(&MBB, DL, TII->get(SystemZ::BRC))
200 BuildMI(*MoveMBB, MoveMBB->end(), DL, TII->get(SystemZ::COPY), DestReg)
223 MI.setDesc(TII->get(TargetMemOpcode));
228 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(SystemZ::COPY), DstReg)
lib/Target/SystemZ/SystemZRegisterInfo.cpp 317 BuildMI(MBB, MI, DL, TII->get(LAOpcode),ScratchReg)
323 BuildMI(MBB, MI, DL, TII->get(SystemZ::AGR),ScratchReg)
332 MI->setDesc(TII->get(OpcodeForOffset));
lib/Target/SystemZ/SystemZShortenInst.cpp 95 MI.setDesc(TII->get(LLIxL));
100 MI.setDesc(TII->get(LLIxH));
111 MI.setDesc(TII->get(Opcode));
122 MI.setDesc(TII->get(Opcode));
135 MI.setDesc(TII->get(Opcode));
168 MI.setDesc(TII->get(Opcode));
183 MI.setDesc(TII->get(Opcode));
189 MI.setDesc(TII->get(Opcode));
344 MI.setDesc(TII->get(TwoOperandOpcode));
lib/Target/WebAssembly/MCTargetDesc/WebAssemblyInstPrinter.cpp 54 const MCInstrDesc &Desc = MII.get(MI->getOpcode());
215 else if (OpNo >= MII.get(MI->getOpcode()).getNumDefs())
222 if (OpNo < MII.get(MI->getOpcode()).getNumDefs())
227 const MCInstrDesc &Desc = MII.get(MI->getOpcode());
lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCCodeEmitter.cpp 83 const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
lib/Target/WebAssembly/WebAssemblyCFGStackify.cpp 330 TII.get(WebAssembly::BLOCK))
362 TII.get(WebAssembly::END_BLOCK));
409 TII.get(WebAssembly::LOOP))
429 BuildMI(*AfterLoop, InsertPos, EndDL, TII.get(WebAssembly::END_LOOP));
578 TII.get(WebAssembly::TRY))
619 TII.get(WebAssembly::END_TRY));
969 BuildMI(AppendixBB, DebugLoc(), TII.get(WebAssembly::RETHROW))
1077 BuildMI(EHPadLayoutPred, DL, TII.get(WebAssembly::BR)).addMBB(Cont);
1132 TII.get(WebAssembly::TRY))
1140 BuildMI(NestedEHPad, RangeEnd->getDebugLoc(), TII.get(WebAssembly::CATCH),
1142 BuildMI(NestedEHPad, RangeEnd->getDebugLoc(), TII.get(WebAssembly::BR))
1150 TII.get(WebAssembly::END_TRY));
1267 TII.get(WebAssembly::END_FUNCTION));
lib/Target/WebAssembly/WebAssemblyCallIndirectFixup.cpp 116 const MCInstrDesc &Desc = TII->get(getNonPseudoCallIndirectOpcode(MI));
lib/Target/WebAssembly/WebAssemblyExplicitLocals.cpp 249 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(Opc), NewReg)
259 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(Opc),
286 BuildMI(MBB, InsertPt, MI.getDebugLoc(), TII->get(Opc))
293 BuildMI(MBB, InsertPt, MI.getDebugLoc(), TII->get(Opc))
351 BuildMI(MBB, InsertPt, MI.getDebugLoc(), TII->get(Opc), NewReg)
lib/Target/WebAssembly/WebAssemblyFastISel.cpp 388 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), Reg)
464 TII.get(WebAssembly::CONST_I32), Imm)
469 TII.get(WebAssembly::AND_I32), Result)
494 TII.get(WebAssembly::CONST_I32), Imm)
499 TII.get(WebAssembly::SHL_I32), Left)
505 TII.get(WebAssembly::SHR_S_I32), Right)
523 TII.get(WebAssembly::I64_EXTEND_U_I32), Result)
545 TII.get(WebAssembly::I64_EXTEND_S_I32), Result)
584 TII.get(WebAssembly::EQZ_I32), NotReg)
591 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(WebAssembly::COPY),
607 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
626 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
713 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
869 auto MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc));
937 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
956 TII.get(WebAssembly::I32_WRAP_I64), Result)
1053 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
1114 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
1204 auto MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc),
1261 auto MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc));
1289 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc))
1305 TII.get(WebAssembly::RETURN));
1349 TII.get(WebAssembly::RETURN))
1356 TII.get(WebAssembly::UNREACHABLE));
lib/Target/WebAssembly/WebAssemblyFixIrreducibleControlFlow.cpp 357 BuildMI(Dispatch, DebugLoc(), TII.get(WebAssembly::BR_TABLE_I32));
442 BuildMI(Routing, DebugLoc(), TII.get(WebAssembly::CONST_I32), Reg)
444 BuildMI(Routing, DebugLoc(), TII.get(WebAssembly::BR)).addMBB(Dispatch);
lib/Target/WebAssembly/WebAssemblyFrameLowering.cpp 132 BuildMI(MBB, InsertStore, DL, TII->get(WebAssembly::GLOBAL_SET_I32))
180 BuildMI(MBB, InsertPt, DL, TII->get(WebAssembly::GLOBAL_GET_I32), SPReg)
188 BuildMI(MBB, InsertPt, DL, TII->get(WebAssembly::COPY), BasePtr)
194 BuildMI(MBB, InsertPt, DL, TII->get(WebAssembly::CONST_I32), OffsetReg)
196 BuildMI(MBB, InsertPt, DL, TII->get(WebAssembly::SUB_I32),
206 BuildMI(MBB, InsertPt, DL, TII->get(WebAssembly::CONST_I32), BitmaskReg)
208 BuildMI(MBB, InsertPt, DL, TII->get(WebAssembly::AND_I32),
217 BuildMI(MBB, InsertPt, DL, TII->get(WebAssembly::COPY), WebAssembly::FP32)
248 BuildMI(MBB, InsertPt, DL, TII->get(WebAssembly::CONST_I32), OffsetReg)
253 BuildMI(MBB, InsertPt, DL, TII->get(WebAssembly::ADD_I32), SPReg)
lib/Target/WebAssembly/WebAssemblyISelLowering.cpp 388 BuildMI(BB, DL, TII.get(Abs), Tmp0).addReg(InReg);
390 BuildMI(BB, DL, TII.get(FConst), Tmp1)
392 BuildMI(BB, DL, TII.get(LT), CmpReg).addReg(Tmp0).addReg(Tmp1);
400 BuildMI(BB, DL, TII.get(FConst), Tmp1)
402 BuildMI(BB, DL, TII.get(GE), SecondCmpReg).addReg(Tmp0).addReg(Tmp1);
403 BuildMI(BB, DL, TII.get(And), AndReg).addReg(CmpReg).addReg(SecondCmpReg);
407 BuildMI(BB, DL, TII.get(Eqz), EqzReg).addReg(CmpReg);
411 BuildMI(BB, DL, TII.get(WebAssembly::BR_IF)).addMBB(TrueMBB).addReg(EqzReg);
412 BuildMI(FalseMBB, DL, TII.get(LoweredOpcode), FalseReg).addReg(InReg);
413 BuildMI(FalseMBB, DL, TII.get(WebAssembly::BR)).addMBB(DoneMBB);
414 BuildMI(TrueMBB, DL, TII.get(IConst), TrueReg).addImm(Substitute);
415 BuildMI(*DoneMBB, DoneMBB->begin(), DL, TII.get(TargetOpcode::PHI), OutReg)
lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp 83 BuildMI(MBB, I, DL, get(CopyOpcode), DestReg)
188 BuildMI(&MBB, DL, get(WebAssembly::BR)).addMBB(TBB);
202 BuildMI(&MBB, DL, get(WebAssembly::BR_ON_EXN))
207 BuildMI(&MBB, DL, get(WebAssembly::BR_IF)).addMBB(TBB).add(Cond[1]);
210 BuildMI(&MBB, DL, get(WebAssembly::BR_UNLESS)).addMBB(TBB).add(Cond[1]);
215 BuildMI(&MBB, DL, get(WebAssembly::BR)).addMBB(FBB);
lib/Target/WebAssembly/WebAssemblyLateEHPrepare.cpp 137 TII.get(WebAssembly::CATCH), DstReg);
158 BuildMI(MBB, TI, TI->getDebugLoc(), TII.get(WebAssembly::BR))
173 BuildMI(MBB, TI, TI->getDebugLoc(), TII.get(WebAssembly::RETHROW))
309 BuildMI(EHPad, DL, TII.get(WebAssembly::BR_ON_EXN))
313 BuildMI(EHPad, DL, TII.get(WebAssembly::BR)).addMBB(ElseMBB);
345 BuildMI(ElseMBB, DL, TII.get(WebAssembly::CONST_I32), Reg).addImm(0);
346 BuildMI(ElseMBB, DL, TII.get(WebAssembly::CALL_VOID))
349 BuildMI(ElseMBB, DL, TII.get(WebAssembly::UNREACHABLE));
352 BuildMI(ElseMBB, DL, TII.get(WebAssembly::RETHROW)).addReg(ExnReg);
lib/Target/WebAssembly/WebAssemblyLowerBrUnless.cpp 81 Def->setDesc(TII.get(NE_I32));
85 Def->setDesc(TII.get(EQ_I32));
89 Def->setDesc(TII.get(LE_S_I32));
93 Def->setDesc(TII.get(LT_S_I32));
97 Def->setDesc(TII.get(GE_S_I32));
101 Def->setDesc(TII.get(GT_S_I32));
105 Def->setDesc(TII.get(LE_U_I32));
109 Def->setDesc(TII.get(LT_U_I32));
113 Def->setDesc(TII.get(GE_U_I32));
117 Def->setDesc(TII.get(GT_U_I32));
121 Def->setDesc(TII.get(NE_I64));
125 Def->setDesc(TII.get(EQ_I64));
129 Def->setDesc(TII.get(LE_S_I64));
133 Def->setDesc(TII.get(LT_S_I64));
137 Def->setDesc(TII.get(GE_S_I64));
141 Def->setDesc(TII.get(GT_S_I64));
145 Def->setDesc(TII.get(LE_U_I64));
149 Def->setDesc(TII.get(LT_U_I64));
153 Def->setDesc(TII.get(GE_U_I64));
157 Def->setDesc(TII.get(GT_U_I64));
161 Def->setDesc(TII.get(NE_F32));
165 Def->setDesc(TII.get(EQ_F32));
169 Def->setDesc(TII.get(NE_F64));
173 Def->setDesc(TII.get(EQ_F64));
192 BuildMI(MBB, MI, MI->getDebugLoc(), TII.get(WebAssembly::EQZ_I32), Tmp)
202 BuildMI(MBB, MI, MI->getDebugLoc(), TII.get(WebAssembly::BR_IF))
lib/Target/WebAssembly/WebAssemblyPeephole.cpp 121 BuildMI(MBB, MI, MI.getDebugLoc(), TII.get(CopyLocalOpc), NewReg)
128 MI.setDesc(TII.get(WebAssembly::FALLTHROUGH_RETURN));
lib/Target/WebAssembly/WebAssemblyPrepareForLiveIntervals.cpp 109 TII.get(WebAssembly::IMPLICIT_DEF), Reg);
lib/Target/WebAssembly/WebAssemblyRegStackify.cpp 107 MI->setDesc(TII->get(WebAssembly::CONST_I32));
110 MI->setDesc(TII->get(WebAssembly::CONST_I64));
113 MI->setDesc(TII->get(WebAssembly::CONST_F32));
118 MI->setDesc(TII->get(WebAssembly::CONST_F64));
124 MI->setDesc(TII->get(WebAssembly::SPLAT_v4i32));
127 TII->get(WebAssembly::CONST_I32), TempReg)
614 TII->get(getTeeOpcode(RegClass)), TeeReg)
lib/Target/WebAssembly/WebAssemblyRegisterInfo.cpp 121 BuildMI(MBB, *II, II->getDebugLoc(), TII->get(WebAssembly::CONST_I32),
125 BuildMI(MBB, *II, II->getDebugLoc(), TII->get(WebAssembly::ADD_I32),
lib/Target/X86/AsmParser/X86AsmParser.cpp 3108 const MCInstrDesc &MCID = MII.get(Opc);
lib/Target/X86/MCTargetDesc/X86ATTInstPrinter.cpp 86 const MCInstrDesc &Desc = MII.get(MI->getOpcode());
lib/Target/X86/MCTargetDesc/X86InstComments.cpp 228 const MCInstrDesc &Desc = MCII.get(MI->getOpcode());
lib/Target/X86/MCTargetDesc/X86InstPrinterCommon.cpp 323 const MCInstrDesc &Desc = MII.get(MI->getOpcode());
lib/Target/X86/MCTargetDesc/X86IntelInstPrinter.cpp 67 const MCInstrDesc &Desc = MII.get(MI->getOpcode());
lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp 284 const MCInstrDesc &Desc = MCII.get(Opcode);
1216 const MCInstrDesc &Desc = MCII.get(Opcode);
lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp 418 const MCInstrDesc &Desc = Info->get(Inst.getOpcode());
527 const MCInstrDesc &MCID = Info->get(Inst.getOpcode());
lib/Target/X86/X86AvoidStoreForwardingBlocks.cpp 395 TII->getRegClass(TII->get(NLoadOpcode), 0, TRI, *(MBB->getParent())));
397 BuildMI(*MBB, LoadInst, LoadInst->getDebugLoc(), TII->get(NLoadOpcode),
418 BuildMI(*MBB, StInst, StInst->getDebugLoc(), TII->get(NStoreOpcode))
565 auto TRC = TII->getRegClass(TII->get(LoadInst->getOpcode()), 0, TRI,
lib/Target/X86/X86AvoidTrailingCall.cpp 102 TII.get(X86::INT3));
lib/Target/X86/X86CallFrameOptimization.cpp 533 Push = BuildMI(MBB, Context.Call, DL, TII->get(PushOpcode)).add(PushOp);
544 BuildMI(MBB, Context.Call, DL, TII->get(X86::IMPLICIT_DEF), UndefReg);
545 BuildMI(MBB, Context.Call, DL, TII->get(X86::INSERT_SUBREG), Reg)
560 Push = BuildMI(MBB, Context.Call, DL, TII->get(PushOpcode));
569 Push = BuildMI(MBB, Context.Call, DL, TII->get(PushOpcode))
lib/Target/X86/X86CmovConversion.cpp 691 BuildMI(MBB, DL, TII->get(X86::JCC_1)).addMBB(SinkMBB).addImm(CC);
834 MIB = BuildMI(*SinkMBB, SinkInsertionPoint, DL, TII->get(X86::PHI), DestReg)
lib/Target/X86/X86CondBrFolding.cpp 227 BuildMI(*MBB, BrMI, MBB->findDebugLoc(BrMI), TII->get(X86::JCC_1))
233 BuildMI(*MBB, UncondBrI, MBB->findDebugLoc(UncondBrI), TII->get(X86::JMP_1))
254 TII->get(X86::JCC_1))
260 BuildMI(*MBB, UncondBrI, MBB->findDebugLoc(UncondBrI), TII->get(X86::JMP_1))
323 TII->get(X86::JCC_1))
328 TII->get(X86::JMP_1))
lib/Target/X86/X86DomainReassignment.cpp 146 !TII->get(DstOpcode).hasImplicitDefOfPhysReg(MO.getReg()))
155 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), TII->get(DstOpcode));
186 TII->getRegClass(TII->get(DstOpcode), 0, MRI->getTargetRegisterInfo(),
188 MachineInstrBuilder Bld = BuildMI(*MBB, MI, DL, TII->get(DstOpcode), Reg);
192 BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::COPY))
271 TII->get(TargetOpcode::COPY))
531 const MCInstrDesc &Desc = TII->get(MI.getOpcode());
lib/Target/X86/X86EvexToVex.cpp 267 MI.setDesc(TII->get(NewOpc));
lib/Target/X86/X86ExpandPseudo.cpp 92 BuildMI(*MBB, MBBI, DL, TII->get(X86::LEA64r), X86::R11)
99 BuildMI(*MBB, MBBI, DL, TII->get(X86::CMP64rr))
113 BuildMI(*MBB, MBBI, DL, TII->get(X86::JCC_1)).addMBB(ThenMBB).addImm(CC);
128 BuildMI(*MBB, MBBI, DL, TII->get(X86::TAILJMPd64))
170 BuildMI(P.first, DL, TII->get(X86::TAILJMPd64))
245 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(Op));
262 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(Op));
268 TII->get(IsWin64 ? X86::TAILJMPr64_REX : X86::TAILJMPr64))
272 BuildMI(MBB, MBBI, DL, TII->get(X86::TAILJMPr))
293 TII->get(Uses64BitFramePtr ? X86::MOV64rr : X86::MOV32rr), StackPtr)
304 TII->get(STI->is64Bit() ? X86::IRET64 : X86::IRET32));
314 TII->get(STI->is64Bit() ? X86::RETQ : X86::RETL));
317 TII->get(STI->is64Bit() ? X86::RETIQ : X86::RETIL))
324 BuildMI(MBB, MBBI, DL, TII->get(X86::POP32r)).addReg(X86::ECX, RegState::Define);
326 BuildMI(MBB, MBBI, DL, TII->get(X86::PUSH32r)).addReg(X86::ECX);
327 MIB = BuildMI(MBB, MBBI, DL, TII->get(X86::RETL));
362 MachineInstr *NewInstr = BuildMI(MBB, MBBI, DL, TII->get(ActualOpc));
lib/Target/X86/X86FastISel.cpp 471 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg);
502 TII.get(X86::AND8ri), AndResult)
639 const MCInstrDesc &Desc = TII.get(Opc);
684 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc));
792 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), LoadReg);
1252 TII.get(TargetOpcode::COPY), DstReg).addReg(SrcReg);
1271 TII.get(TargetOpcode::COPY), RetReg).addReg(Reg);
1279 TII.get(Subtarget->is64Bit() ? X86::RETIQ : X86::RETIL))
1283 TII.get(Subtarget->is64Bit() ? X86::RETQ : X86::RETL));
1406 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, CurDbgLoc, TII.get(CompareImmOpc))
1418 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, CurDbgLoc, TII.get(CompareOpc))
1439 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::MOV32r0),
1449 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::MOV8ri),
1491 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::SETCCr),
1493 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::SETCCr),
1495 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(SETFOpc[2]),
1513 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::SETCCr),
1551 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(MovInst), Result32)
1555 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TargetOpcode::SUBREG_TO_REG),
1562 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::MOVZX32rr8),
1598 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::NEG8r),
1608 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::MOVSX32rr8),
1694 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::JCC_1))
1700 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::JCC_1))
1725 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TestOpc))
1734 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::JCC_1))
1748 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::JCC_1))
1765 TII.get(TargetOpcode::COPY), OpReg)
1770 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::TEST8ri))
1773 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::JCC_1))
1831 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TargetOpcode::COPY),
1838 TII.get(TargetOpcode::KILL), X86::CL)
1842 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(OpReg), ResultReg)
1944 TII.get(OpEntry.OpCopy), TypeEntry.LowInReg).addReg(Op0Reg);
1949 TII.get(OpEntry.OpSignExtend));
1953 TII.get(X86::MOV32r0), Zero32);
1960 TII.get(Copy), TypeEntry.HighInReg)
1964 TII.get(Copy), TypeEntry.HighInReg)
1968 TII.get(TargetOpcode::SUBREG_TO_REG), TypeEntry.HighInReg)
1975 TII.get(OpEntry.OpDivRem)).addReg(Op1Reg);
1991 TII.get(Copy), SourceSuperReg).addReg(X86::AX);
1994 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::SHR16ri),
2004 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Copy), ResultReg)
2070 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::SETCCr),
2072 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::SETCCr),
2074 auto const &II = TII.get(SETFOpc[2]);
2111 TII.get(TargetOpcode::COPY), CondReg)
2116 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::TEST8ri))
2216 TII.get(TargetOpcode::IMPLICIT_DEF), ImplicitDefReg);
2228 TII.get(TargetOpcode::COPY), ResultReg).addReg(MovReg);
2249 TII.get(TargetOpcode::COPY), ResultReg).addReg(VBlendReg);
2275 TII.get(TargetOpcode::COPY), ResultReg).addReg(OrReg);
2329 TII.get(TargetOpcode::COPY), CondReg)
2334 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::TEST8ri))
2382 TII.get(TargetOpcode::COPY), ResultReg)
2452 TII.get(TargetOpcode::IMPLICIT_DEF), ImplicitDefReg);
2484 TII.get(TargetOpcode::IMPLICIT_DEF), ImplicitDefReg);
2490 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TargetOpc),
2639 TII.get(X86::VMOVPDI2DIrr), ResultReg)
2661 TII.get(TargetOpcode::COPY), ResultReg)
2704 TII.get(TargetOpcode::COPY), SrcReg).addReg(FrameReg);
2716 TII.get(Opc), DestReg), SrcReg);
2788 const MCInstrDesc &II = TII.get(TargetOpcode::DBG_VALUE);
2800 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::TRAP));
2842 TII.get(TargetOpcode::IMPLICIT_DEF), ImplicitDefReg);
2847 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc),
2924 TII.get(Opc[IsDec][VT.SimpleTy-MVT::i8]), ResultReg)
2951 TII.get(TargetOpcode::COPY), Reg[VT.SimpleTy-MVT::i8])
2962 TII.get(TargetOpcode::COPY), X86::AL)
2978 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::SETCCr),
3048 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
3147 TII.get(TargetOpcode::COPY), ResultReg)
3313 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AdjStackDown))
3405 TII.get(TargetOpcode::COPY), VA.getLocReg()).addReg(ArgReg);
3447 TII.get(TargetOpcode::COPY), X86::EBX).addReg(Base);
3467 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::MOV8ri),
3491 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(CallOpc))
3508 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(CallOpc));
3541 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AdjStackUp))
3574 TII.get(TargetOpcode::COPY), CopyReg).addReg(SrcReg);
3586 TII.get(Opc)), FI)
3590 TII.get(Opc), ResultReg + i), FI);
3705 TII.get(TargetOpcode::SUBREG_TO_REG), ResultReg)
3793 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::MOV64ri),
3797 TII.get(Opc), ResultReg);
3807 TII.get(Opc), ResultReg),
3831 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::MOV64ri),
3840 TII.get(Opc), ResultReg), AM);
3887 TII.get(Opc), ResultReg), AM);
3919 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg);
3980 const MCInstrDesc &II = TII.get(MachineInstOpcode);
4001 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
lib/Target/X86/X86FixupBWInsts.cpp 288 BuildMI(*MF, MI->getDebugLoc(), TII->get(New32BitOpcode), NewDestReg);
323 BuildMI(*MF, MI->getDebugLoc(), TII->get(X86::MOV32rr), NewDestReg)
351 BuildMI(*MF, MI->getDebugLoc(), TII->get(New32BitOpcode), NewDestReg);
lib/Target/X86/X86FixupLEAs.cpp 136 TII->get(MI.getOpcode() == X86::MOV32rr ? X86::LEA32r
395 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg)
400 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg)
416 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg)
419 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg)
426 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg)
430 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg)
507 const MCInstrDesc &ADDrr = TII->get(getADDrrFromLEA(Opcode));
516 TII->get(getADDriFromLEA(Opcode, Offset));
583 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpc), DestReg)
589 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpc), DestReg)
598 NewMI = BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(LEAOpcode))
617 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpc), DestReg)
622 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpc), DestReg)
649 NewMI = BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(NewOpc), DestReg)
658 NewMI = BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(LEAOpcode))
668 NewMI = BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(NewOpc), DestReg)
lib/Target/X86/X86FixupSetCC.cpp 143 BuildMI(MBB, FlagsDefMI, MI.getDebugLoc(), TII->get(X86::MOV32r0),
149 TII->get(X86::INSERT_SUBREG), InsertReg)
lib/Target/X86/X86FlagsCopyLowering.cpp 745 TII->get(X86::SETCCr), Reg).addImm(Cond);
770 BuildMI(MBB, Pos, Loc, TII->get(X86::TEST8rr)).addReg(Reg).addReg(Reg);
819 BuildMI(MBB, MI.getIterator(), MI.getDebugLoc(), TII->get(X86::ADD8ri))
935 BuildMI(MBB, SetPos, SetLoc, TII->get(X86::MOVZX32rr8), NewReg)
945 BuildMI(MBB, SetPos, SetLoc, TII->get(TargetOpcode::SUBREG_TO_REG),
956 BuildMI(MBB, SetPos, SetLoc, TII->get(TargetOpcode::COPY),
960 BuildMI(MBB, SetPos, SetLoc, TII->get(TargetOpcode::COPY), NewReg)
979 BuildMI(MBB, SetPos, SetLoc, TII->get(X86::MOV32r0), ZeroReg);
1004 BuildMI(MBB, SetPos, SetLoc, TII->get(Sub), ResultReg)
1036 SetCCI.getDebugLoc(), TII->get(X86::MOV8mr));
lib/Target/X86/X86FloatingPoint.cpp 240 BuildMI(*MBB, I, dl, TII->get(X86::XCH_F)).addReg(STReg);
250 BuildMI(*MBB, I, dl, TII->get(X86::LD_Frr)).addReg(STReg);
843 I->setDesc(TII->get(Opcode));
847 I = BuildMI(*MBB, ++I, dl, TII->get(X86::ST_FPrr)).addReg(X86::ST0);
878 return BuildMI(*MBB, I, DebugLoc(), TII->get(X86::ST_FPrr))
936 BuildMI(*MBB, I, DebugLoc(), TII->get(X86::LD_F0));
1103 MI.setDesc(TII->get(getConcreteOpcode(MI.getOpcode())));
1149 MI.setDesc(TII->get(getConcreteOpcode(MI.getOpcode())));
1201 MI.setDesc(TII->get(getConcreteOpcode(MI.getOpcode())));
1359 I = BuildMI(*MBB, I, dl, TII->get(Opcode)).addReg(getSTReg(NotTOS));
1397 MI.setDesc(TII->get(getConcreteOpcode(MI.getOpcode())));
1423 MI.setDesc(TII->get(getConcreteOpcode(MI.getOpcode())));
1480 BuildMI(*MBB, Inst, MI.getDebugLoc(), TII->get(X86::LD_F0));
1677 Inst = BuildMI(*MBB, Inst, DebugLoc(), TII->get(TargetOpcode::KILL));
lib/Target/X86/X86FrameLowering.cpp 275 BuildMI(MBB, MBBI, DL, TII.get(MovRIOpc), Reg)
278 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(AddSubRROpc), StackPtr)
292 BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH64r))
301 BuildMI(MBB, MBBI, DL, TII.get(MovRIOpc), Rax)
304 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(X86::ADD64rr), Rax)
310 BuildMI(MBB, MBBI, DL, TII.get(X86::XCHG64rm), Rax).addReg(Rax),
313 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64rm), StackPtr),
331 BuildMI(MBB, MBBI, DL, TII.get(Opc))
378 TII.get(getLEArOpcode(Uses64BitFramePtr)),
386 MI = BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
456 BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
635 addRegOffset(BuildMI(&MBB, DL, TII.get(X86::MOV64mr)), X86::RSP, false,
639 addRegOffset(BuildMI(&MBB, DL, TII.get(X86::MOV64mr)), X86::RSP, false,
644 BuildMI(&MBB, DL, TII.get(X86::MOV64rr), SizeReg).addReg(X86::RAX);
649 BuildMI(&MBB, DL, TII.get(X86::XOR64rr), ZeroReg)
652 BuildMI(&MBB, DL, TII.get(X86::MOV64rr), CopyReg).addReg(X86::RSP);
653 BuildMI(&MBB, DL, TII.get(X86::SUB64rr), TestReg)
656 BuildMI(&MBB, DL, TII.get(X86::CMOV64rr), FinalReg)
668 BuildMI(&MBB, DL, TII.get(X86::MOV64rm), LimitReg)
674 BuildMI(&MBB, DL, TII.get(X86::CMP64rr)).addReg(FinalReg).addReg(LimitReg);
676 BuildMI(&MBB, DL, TII.get(X86::JCC_1)).addMBB(ContinueMBB).addImm(X86::COND_AE);
680 BuildMI(RoundMBB, DL, TII.get(X86::AND64ri32), RoundedReg)
683 BuildMI(RoundMBB, DL, TII.get(X86::JMP_1)).addMBB(LoopMBB);
689 BuildMI(LoopMBB, DL, TII.get(X86::PHI), JoinReg)
697 addRegOffset(BuildMI(LoopMBB, DL, TII.get(X86::LEA64r), ProbeReg), JoinReg,
701 BuildMI(LoopMBB, DL, TII.get(X86::MOV8mi))
710 BuildMI(LoopMBB, DL, TII.get(X86::CMP64rr))
713 BuildMI(LoopMBB, DL, TII.get(X86::JCC_1)).addMBB(LoopMBB).addImm(X86::COND_NE);
721 TII.get(X86::MOV64rm), X86::RCX),
725 TII.get(X86::MOV64rm), X86::RDX),
732 BuildMI(*ContinueMBB, ContinueMBBI, DL, TII.get(X86::SUB64rr), X86::RSP)
789 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64ri), X86::R11)
791 CI = BuildMI(MBB, MBBI, DL, TII.get(CallOp)).addReg(X86::R11);
793 CI = BuildMI(MBB, MBBI, DL, TII.get(CallOp))
812 BuildMI(MBB, MBBI, DL, TII.get(getSUBrrOpcode(Uses64BitFramePtr)), SP)
830 BuildMI(MBB, MBBI, DL, TII.get(X86::CALLpcrel32))
866 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(AndOp), Reg)
1088 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(MOVmr)), StackPtr, true, 16)
1110 BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
1129 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_PushReg))
1137 TII.get(Uses64BitFramePtr ? X86::MOV64rr : X86::MOV32rr),
1153 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_SetFrame))
1202 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_PushReg))
1217 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_StackAlign))
1251 BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH64r))
1256 BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH32r))
1267 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
1271 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64ri32), X86::RAX)
1275 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64ri), X86::RAX)
1282 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
1294 MI = addRegOffset(BuildMI(MF, DL, TII.get(X86::MOV64rm), X86::RAX),
1297 MI = addRegOffset(BuildMI(MF, DL, TII.get(X86::MOV32rm), X86::EAX),
1308 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_StackAlloc))
1324 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64rm), Establisher),
1331 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64mr)), StackPtr,
1350 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::LEA64r), FramePtr),
1353 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64rr), FramePtr)
1360 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_SetFrame))
1378 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32mr)), FrameReg,
1402 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_SaveXMM))
1412 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_EndPrologue))
1422 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64mr)), StackPtr, false,
1449 BuildMI(MBB, MBBI, DL, TII.get(Opc), BasePtr)
1456 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opm)),
1472 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opm)), UsedReg, true, Offset)
1500 BuildMI(MBB, MBBI, DL, TII.get(X86::CLD))
1641 BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::POP64r : X86::POP32r),
1702 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr),
1707 BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
1729 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_Epilogue));
2106 BuildMI(MBB, MI, DL, TII.get(Opc)).addReg(Reg, getKillRegState(CanKill))
2149 BuildMI(MBB, MBBI, DL, TII.get(X86::LEA64r), X86::RAX)
2157 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
2215 BuildMI(MBB, MI, DL, TII.get(Opc), Reg)
2378 BuildMI(checkMBB, DL, TII.get(IsLP64 ? X86::LEA64r : X86::LEA64_32r), ScratchReg).addReg(X86::RSP)
2381 BuildMI(checkMBB, DL, TII.get(IsLP64 ? X86::CMP64rm : X86::CMP32rm)).addReg(ScratchReg)
2405 BuildMI(checkMBB, DL, TII.get(X86::LEA32r), ScratchReg).addReg(X86::ESP)
2410 BuildMI(checkMBB, DL, TII.get(X86::CMP32rm)).addReg(ScratchReg)
2435 BuildMI(checkMBB, DL, TII.get(X86::PUSH32r))
2438 BuildMI(checkMBB, DL, TII.get(X86::MOV32ri), ScratchReg2)
2440 BuildMI(checkMBB, DL, TII.get(X86::CMP32rm))
2447 BuildMI(checkMBB, DL, TII.get(X86::POP32r), ScratchReg2);
2453 BuildMI(checkMBB, DL, TII.get(X86::JCC_1)).addMBB(&PrologueMBB).addImm(X86::COND_A);
2468 BuildMI(allocMBB, DL, TII.get(MOVrr), RegAX).addReg(Reg10);
2470 BuildMI(allocMBB, DL, TII.get(MOVri), Reg10)
2472 BuildMI(allocMBB, DL, TII.get(MOVri), Reg11)
2475 BuildMI(allocMBB, DL, TII.get(X86::PUSHi32))
2477 BuildMI(allocMBB, DL, TII.get(X86::PUSHi32))
2501 BuildMI(allocMBB, DL, TII.get(X86::CALL64m))
2510 BuildMI(allocMBB, DL, TII.get(X86::CALL64pcrel32))
2513 BuildMI(allocMBB, DL, TII.get(X86::CALLpcrel32))
2518 BuildMI(allocMBB, DL, TII.get(X86::MORESTACK_RET_RESTORE_R10));
2520 BuildMI(allocMBB, DL, TII.get(X86::MORESTACK_RET));
2690 addRegOffset(BuildMI(stackCheckMBB, DL, TII.get(LEAop), ScratchReg),
2693 addRegOffset(BuildMI(stackCheckMBB, DL, TII.get(CMPop))
2695 BuildMI(stackCheckMBB, DL, TII.get(X86::JCC_1)).addMBB(&PrologueMBB).addImm(X86::COND_AE);
2698 BuildMI(incStackMBB, DL, TII.get(CALLop)).
2700 addRegOffset(BuildMI(incStackMBB, DL, TII.get(LEAop), ScratchReg),
2702 addRegOffset(BuildMI(incStackMBB, DL, TII.get(CMPop))
2704 BuildMI(incStackMBB, DL, TII.get(X86::JCC_1)).addMBB(incStackMBB).addImm(X86::COND_LE);
2787 TII.get(STI.is64Bit() ? X86::POP64r : X86::POP32r), Regs[i]);
2966 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32rm), X86::ESP),
2979 BuildMI(MBB, MBBI, DL, TII.get(ADDri), FramePtr)
2989 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::LEA32r), BasePtr),
2997 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32rm), FramePtr),
3222 addFrameReference(BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64mi32)),
lib/Target/X86/X86ISelDAGToDAG.cpp 1294 uint64_t TSFlags = getInstrInfo()->get(In.getMachineOpcode()).TSFlags;
lib/Target/X86/X86ISelLowering.cpp29221 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(fallMBB);
29227 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), mainDstReg).addImm(-1);
29228 BuildMI(mainMBB, DL, TII->get(X86::JMP_1)).addMBB(sinkMBB);
29235 BuildMI(fallMBB, DL, TII->get(X86::XABORT_DEF));
29236 BuildMI(fallMBB, DL, TII->get(TargetOpcode::COPY), fallDstReg)
29242 BuildMI(*sinkMBB, sinkMBB->begin(), DL, TII->get(X86::PHI), DstReg)
29381 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
29390 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
29396 BuildMI(thisMBB, DL, TII->get(X86::JCC_1))
29406 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
29416 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
29422 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
29428 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
29433 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
29443 BuildMI(offsetMBB, DL, TII->get(X86::JMP_1))
29453 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
29469 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
29473 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
29477 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
29484 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
29489 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
29501 TII->get(X86::PHI), DestReg)
29553 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
29554 BuildMI(MBB, DL, TII->get(X86::JCC_1)).addMBB(EndMBB).addImm(X86::COND_E);
29572 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
29700 MIB = BuildMI(*SinkMBB, SinkInsertionPoint, DL, TII->get(X86::PHI), DestReg)
29836 BuildMI(ThisMBB, DL, TII->get(X86::JCC_1)).addMBB(SinkMBB).addImm(FirstCC);
29840 BuildMI(FirstInsertedMBB, DL, TII->get(X86::JCC_1)).addMBB(SinkMBB).addImm(SecondCC);
29848 BuildMI(*SinkMBB, SinkMBB->begin(), DL, TII->get(X86::PHI), DestReg)
29859 TII->get(TargetOpcode::COPY),
29996 BuildMI(ThisMBB, DL, TII->get(X86::JCC_1)).addMBB(SinkMBB).addImm(CC);
30072 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
30073 BuildMI(BB, DL, TII->get(IsLP64 ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
30075 BuildMI(BB, DL, TII->get(IsLP64 ? X86::CMP64mr:X86::CMP32mr))
30078 BuildMI(BB, DL, TII->get(X86::JCC_1)).addMBB(mallocMBB).addImm(X86::COND_G);
30082 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
30084 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
30086 BuildMI(bumpMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
30092 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
30094 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
30100 BuildMI(mallocMBB, DL, TII->get(X86::MOV32rr), X86::EDI)
30102 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
30108 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
30110 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
30111 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
30118 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
30121 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
30123 BuildMI(mallocMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
30132 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
30173 BuildMI(*RestoreMBB, RestoreMBBI, DL, TII.get(X86::EH_RESTORE));
30174 BuildMI(*RestoreMBB, RestoreMBBI, DL, TII.get(X86::JMP_4)).addMBB(TargetMBB);
30188 BuildMI(*BB, MI, DL, TII.get(X86::EH_RESTORE));
30209 BuildMI(MF, DL, TII.get(AdjStackDown)).addImm(0).addImm(0).addImm(0);
30217 BuildMI(MF, DL, TII.get(AdjStackUp)).addImm(0).addImm(0);
30246 BuildMI(*BB, MI, DL, TII->get(X86::MOV64rm), X86::RDI)
30253 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
30258 BuildMI(*BB, MI, DL, TII->get(X86::MOV32rm), X86::EAX)
30265 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
30270 BuildMI(*BB, MI, DL, TII->get(X86::MOV32rm), X86::EAX)
30277 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
30401 BuildMI(*BB, MI, DL, TII->get(TargetOpcode::COPY), AvailableReg)
30404 MI.setDesc(TII->get(Opc));
30439 BuildMI(*MBB, MI, DL, TII->get(XorRROpc))
30447 BuildMI(*MBB, MI, DL, TII->get(RdsspOpc), SSPCopyReg).addReg(ZReg);
30451 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrStoreOpc));
30543 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
30551 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
30561 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
30579 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
30589 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
30594 TII->get(X86::PHI), DstReg)
30607 addRegOffset(BuildMI(restoreMBB, DL, TII->get(Opm), BasePtr),
30611 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
30612 BuildMI(restoreMBB, DL, TII->get(X86::JMP_1)).addMBB(sinkMBB);
30689 BuildMI(checkSspMBB, DL, TII->get(XorRROpc))
30697 BuildMI(checkSspMBB, DL, TII->get(RdsspOpc), SSPCopyReg).addReg(ZReg);
30702 BuildMI(checkSspMBB, DL, TII->get(TestRROpc))
30705 BuildMI(checkSspMBB, DL, TII->get(X86::JCC_1)).addMBB(sinkMBB).addImm(X86::COND_E);
30714 BuildMI(fallMBB, DL, TII->get(PtrLoadOpc), PrevSSPReg);
30730 BuildMI(fallMBB, DL, TII->get(SubRROpc), SspSubReg)
30735 BuildMI(fallMBB, DL, TII->get(X86::JCC_1)).addMBB(sinkMBB).addImm(X86::COND_BE);
30743 BuildMI(fixShadowMBB, DL, TII->get(ShrRIOpc), SspFirstShrReg)
30749 BuildMI(fixShadowMBB, DL, TII->get(IncsspOpc)).addReg(SspFirstShrReg);
30753 BuildMI(fixShadowMBB, DL, TII->get(ShrRIOpc), SspSecondShrReg)
30758 BuildMI(fixShadowMBB, DL, TII->get(X86::JCC_1)).addMBB(sinkMBB).addImm(X86::COND_E);
30765 BuildMI(fixShadowLoopPrepareMBB, DL, TII->get(ShlR1Opc), SspAfterShlReg)
30771 BuildMI(fixShadowLoopPrepareMBB, DL, TII->get(MovRIOpc), Value128InReg)
30779 BuildMI(fixShadowLoopMBB, DL, TII->get(X86::PHI), CounterReg)
30786 BuildMI(fixShadowLoopMBB, DL, TII->get(IncsspOpc)).addReg(Value128InReg);
30790 BuildMI(fixShadowLoopMBB, DL, TII->get(DecROpc), DecReg).addReg(CounterReg);
30793 BuildMI(fixShadowLoopMBB, DL, TII->get(X86::JCC_1)).addMBB(fixShadowLoopMBB).addImm(X86::COND_NE);
30840 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrLoadOpc), FP);
30852 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
30866 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrLoadOpc), SP);
30877 BuildMI(*thisMBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
30910 BuildMI(*MBB, MI, DL, TII->get(X86::LEA64r), VR)
30917 BuildMI(*MBB, MI, DL, TII->get(X86::LEA32r), VR)
30925 MachineInstrBuilder MIB = BuildMI(*MBB, MI, DL, TII->get(Op));
30991 BuildMI(TrapBB, DL, TII->get(X86::TRAP));
31023 addRegOffset(BuildMI(DispatchBB, DL, TII->get(Op), BP), FP, true,
31027 BuildMI(DispatchBB, DL, TII->get(X86::NOOP))
31033 addFrameReference(BuildMI(DispatchBB, DL, TII->get(X86::MOV32rm), IReg), FI,
31035 BuildMI(DispatchBB, DL, TII->get(X86::CMP32ri))
31038 BuildMI(DispatchBB, DL, TII->get(X86::JCC_1)).addMBB(TrapBB).addImm(X86::COND_AE);
31045 BuildMI(DispContBB, DL, TII->get(X86::LEA64r), BReg)
31052 BuildMI(DispContBB, DL, TII->get(TargetOpcode::SUBREG_TO_REG), IReg64)
31060 BuildMI(DispContBB, DL, TII->get(X86::JMP64m))
31073 BuildMI(DispContBB, DL, TII->get(X86::MOV32rm), OReg)
31080 BuildMI(DispContBB, DL, TII->get(X86::MOVSX64rr32), OReg64).addReg(OReg);
31082 BuildMI(DispContBB, DL, TII->get(X86::ADD64rr), TReg)
31086 BuildMI(DispContBB, DL, TII->get(X86::JMP64r)).addReg(TReg);
31094 BuildMI(DispContBB, DL, TII->get(X86::JMP32m))
31218 MachineInstr *Push = BuildMI(*BB, MI, DL, TII->get(PushF));
31229 BuildMI(*BB, MI, DL, TII->get(Pop), MI.getOperand(0).getReg());
31241 BuildMI(*BB, MI, DL, TII->get(Push)).addReg(MI.getOperand(0).getReg());
31242 BuildMI(*BB, MI, DL, TII->get(PopF));
31261 TII->get(X86::FNSTCW16m)), OrigCWFrameIdx);
31265 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOVZX32rm16), OldCW),
31270 BuildMI(*BB, MI, DL, TII->get(X86::OR32ri), NewCW)
31276 BuildMI(*BB, MI, DL, TII->get(TargetOpcode::COPY), NewCW16)
31281 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)),
31287 TII->get(X86::FLDCW16m)), NewCWFrameIdx);
31305 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
31310 TII->get(X86::FLDCW16m)), OrigCWFrameIdx);
31399 BuildMI(*BB, *MBBI, DL, TII->get(X86::LEA32r), computedAddrVReg), AM);
46202 BuildMI(*Entry, MBBI, DebugLoc(), TII->get(TargetOpcode::COPY), NewVR)
46208 TII->get(TargetOpcode::COPY), *I)
lib/Target/X86/X86IndirectBranchTracking.cpp 80 BuildMI(MBB, I, MBB.findDebugLoc(I), TII->get(EndbrOpcode));
lib/Target/X86/X86InsertPrefetch.cpp 212 const MCInstrDesc &Desc = TII->get(PFetchInstrID);
lib/Target/X86/X86InstrInfo.cpp 659 BuildMI(MBB, I, DL, get(X86::MOV32ri))
745 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(TargetOpcode::COPY))
797 BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(X86::IMPLICIT_DEF), InRegLEA);
799 BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(TargetOpcode::COPY))
804 BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(Opcode), OutRegLEA);
850 BuildMI(*MFI, &*MIB, MI.getDebugLoc(), get(X86::IMPLICIT_DEF), InRegLEA2);
851 InsMI2 = BuildMI(*MFI, &*MIB, MI.getDebugLoc(), get(TargetOpcode::COPY))
864 BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(TargetOpcode::COPY))
933 NewMI = BuildMI(MF, MI.getDebugLoc(), get(X86::LEA64r))
958 BuildMI(MF, MI.getDebugLoc(), get(Opc))
994 BuildMI(MF, MI.getDebugLoc(), get(Opc))
1016 MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc))
1059 MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc)).add(Dest);
1083 BuildMI(MF, MI.getDebugLoc(), get(X86::LEA64r)).add(Dest).add(Src),
1100 MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc))
1141 MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc))
1162 get(X86::LEA64r)).add(Dest).add(Src);
1242 NewMI = BuildMI(MF, MI.getDebugLoc(), get(Opc))
1307 NewMI = BuildMI(MF, MI.getDebugLoc(), get(Opc))
1556 WorkingMI.setDesc(get(Opc));
1568 WorkingMI.setDesc(get(Opc));
1588 WorkingMI.setDesc(get(Opc));
1665 WorkingMI.setDesc(get(Opc));
1676 WorkingMI.setDesc(get(X86::SHUFPDrri));
1685 WorkingMI.setDesc(get(X86::MOVSDrr));
1801 WorkingMI.setDesc(get(Opc));
1852 WorkingMI.setDesc(get(Opc));
1863 WorkingMI.setDesc(get(Opc));
2461 auto MIB = BuildMI(MBB, I, MBB.findDebugLoc(I), get(Opc));
2591 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JCC_1))
2594 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JMP_1))
2784 BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(TBB);
2797 BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(TBB).addImm(X86::COND_NE);
2799 BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(TBB).addImm(X86::COND_P);
2810 BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(FBB).addImm(X86::COND_NE);
2812 BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(TBB).addImm(X86::COND_NP);
2816 BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(TBB).addImm(CC);
2822 BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(FBB);
2876 BuildMI(MBB, I, DL, get(Opc), DstReg)
3031 BuildMI(MBB, MI, DL, get(Opc), DestReg)
3257 addFrameReference(BuildMI(MBB, MI, DebugLoc(), get(Opc)), FrameIdx)
3272 addFrameReference(BuildMI(MBB, MI, DebugLoc(), get(Opc), DestReg), FrameIdx);
3596 CmpInstr.setDesc(get(NewOpcode));
3913 BuildMI(MBB, MIB.getInstr(), DL, TII.get(X86::XOR32rr), Reg)
3918 MIB->setDesc(TII.get(MinusOne ? X86::DEC32r : X86::INC32r));
3943 MIB->setDesc(TII.get(MIB->getOpcode() ==
3951 BuildMI(MBB, I, DL, TII.get(X86::PUSH64i8)).addImm(Imm);
3952 MIB->setDesc(TII.get(X86::POP64r));
3958 BuildMI(MBB, I, DL, TII.get(X86::PUSH32i8)).addImm(Imm);
3959 MIB->setDesc(TII.get(X86::POP32r));
3996 BuildMI(MBB, I, DL, TII.get(X86::MOV64rm), Reg).addReg(X86::RIP).addImm(1)
4000 MIB->setDesc(TII.get(X86::MOV64rm));
4011 MIB->setDesc(TII.get(XorOp));
4082 return Expand2AddrUndef(MIB, get(X86::XOR32rr));
4091 return Expand2AddrUndef(MIB, get(X86::SBB8rr));
4093 return Expand2AddrUndef(MIB, get(X86::SBB16rr));
4095 return Expand2AddrUndef(MIB, get(X86::SBB32rr));
4097 return Expand2AddrUndef(MIB, get(X86::SBB64rr));
4099 return Expand2AddrUndef(MIB, get(X86::MMX_PXORirr));
4104 return Expand2AddrUndef(MIB, get(HasAVX ? X86::VXORPSrr : X86::XORPSrr));
4111 Expand2AddrUndef(MIB, get(X86::VXORPSrr));
4124 get(HasVLX ? X86::VPXORDZ128rr : X86::VXORPSrr));
4129 return Expand2AddrUndef(MIB, get(X86::VPXORDZrr));
4140 get(HasVLX ? X86::VPXORDZ128rr : X86::VXORPSrr));
4150 return Expand2AddrUndef(MIB, get(X86::VPXORDZrr));
4153 return Expand2AddrUndef(MIB, get(HasAVX ? X86::VPCMPEQDrr : X86::PCMPEQDrr));
4155 return Expand2AddrUndef(MIB, get(X86::VPCMPEQDYrr));
4159 MIB->setDesc(get(X86::VCMPPSYrri));
4165 MIB->setDesc(get(X86::VPTERNLOGDZrri));
4180 MIB->setDesc(get(Opc));
4188 return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVAPSrm),
4189 get(X86::VBROADCASTF32X4rm), X86::sub_xmm);
4191 return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVUPSrm),
4192 get(X86::VBROADCASTF32X4rm), X86::sub_xmm);
4194 return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVAPSYrm),
4195 get(X86::VBROADCASTF64X4rm), X86::sub_ymm);
4197 return expandNOVLXLoad(MIB, &getRegisterInfo(), get(X86::VMOVUPSYrm),
4198 get(X86::VBROADCASTF64X4rm), X86::sub_ymm);
4200 return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVAPSmr),
4201 get(X86::VEXTRACTF32x4Zmr), X86::sub_xmm);
4203 return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVUPSmr),
4204 get(X86::VEXTRACTF32x4Zmr), X86::sub_xmm);
4206 return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVAPSYmr),
4207 get(X86::VEXTRACTF64x4Zmr), X86::sub_ymm);
4209 return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVUPSYmr),
4210 get(X86::VEXTRACTF64x4Zmr), X86::sub_ymm);
4214 MI.setDesc(get(X86::MOV32ri));
4227 case X86::KSET0W: return Expand2AddrKreg(MIB, get(X86::KXORWrr), X86::K0);
4228 case X86::KSET0D: return Expand2AddrKreg(MIB, get(X86::KXORDrr), X86::K0);
4229 case X86::KSET0Q: return Expand2AddrKreg(MIB, get(X86::KXORQrr), X86::K0);
4230 case X86::KSET1W: return Expand2AddrKreg(MIB, get(X86::KXNORWrr), X86::K0);
4231 case X86::KSET1D: return Expand2AddrKreg(MIB, get(X86::KXNORDrr), X86::K0);
4232 case X86::KSET1Q: return Expand2AddrKreg(MIB, get(X86::KXNORQrr), X86::K0);
4239 case X86::SHLDROT32ri: return expandSHXDROT(MIB, get(X86::SHLD32rri8));
4240 case X86::SHLDROT64ri: return expandSHXDROT(MIB, get(X86::SHLD64rri8));
4241 case X86::SHRDROT32ri: return expandSHXDROT(MIB, get(X86::SHRD32rri8));
4242 case X86::SHRDROT64ri: return expandSHXDROT(MIB, get(X86::SHRD64rri8));
4243 case X86::ADD8rr_DB: MIB->setDesc(get(X86::OR8rr)); break;
4244 case X86::ADD16rr_DB: MIB->setDesc(get(X86::OR16rr)); break;
4245 case X86::ADD32rr_DB: MIB->setDesc(get(X86::OR32rr)); break;
4246 case X86::ADD64rr_DB: MIB->setDesc(get(X86::OR64rr)); break;
4247 case X86::ADD8ri_DB: MIB->setDesc(get(X86::OR8ri)); break;
4248 case X86::ADD16ri_DB: MIB->setDesc(get(X86::OR16ri)); break;
4249 case X86::ADD32ri_DB: MIB->setDesc(get(X86::OR32ri)); break;
4250 case X86::ADD64ri32_DB: MIB->setDesc(get(X86::OR64ri32)); break;
4251 case X86::ADD16ri8_DB: MIB->setDesc(get(X86::OR16ri8)); break;
4252 case X86::ADD32ri8_DB: MIB->setDesc(get(X86::OR32ri8)); break;
4253 case X86::ADD64ri8_DB: MIB->setDesc(get(X86::OR64ri8)); break;
4578 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(Opc), Reg)
4586 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(X86::VXORPSrr), XReg)
4595 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(X86::XOR32rr), XReg)
4601 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(X86::XOR32rr), Reg)
4666 MF.CreateMachineInstr(TII.get(Opcode), MI.getDebugLoc(), true);
4696 MF.CreateMachineInstr(TII.get(Opcode), MI.getDebugLoc(), true);
4722 MI.getDebugLoc(), TII.get(Opcode));
5046 MI.setDesc(get(NewOpc));
5266 MI.setDesc(get(NewOpc));
5469 const MCInstrDesc &MCID = get(Opc);
5510 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), Reg);
5570 DataMI->setDesc(get(NewOpc));
5585 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
5610 const MCInstrDesc &MCID = get(Opc);
6724 MI.setDesc(get(table[Domain - 1]));
6786 MI.setDesc(get(table[Domain - 1]));
6811 MI.setDesc(get(X86::SHUFPSrri));
6907 MI.setDesc(get(table[Domain - 1]));
7776 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::LEA64r), PC)
7791 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::LEA64r), PBReg)
7798 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOV64ri), GOTReg)
7801 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD64rr), PC)
7810 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0);
7817 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg)
7908 TII->get(TargetOpcode::COPY), is64Bit ? X86::RAX : X86::EAX)
7935 TII->get(TargetOpcode::COPY), *TLSBaseAddrReg)
8114 MachineInstr *retq = BuildMI(MF, DebugLoc(), get(X86::RETQ));
8127 BuildMI(MF, DebugLoc(), get(X86::TAILJMPd64))
8132 BuildMI(MF, DebugLoc(), get(X86::CALL64pcrel32))
lib/Target/X86/X86InstructionSelector.cpp 254 TII.get(TargetOpcode::SUBREG_TO_REG))
303 I.setDesc(TII.get(X86::COPY));
535 I.setDesc(TII.get(NewOpc));
571 I.setDesc(TII.get(NewOpc));
623 I.setDesc(TII.get(NewOpc));
675 I.setDesc(TII.get(NewOpc));
700 I.setDesc(TII.get(X86::COPY));
766 I.setDesc(TII.get(X86::COPY));
829 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(ZextEntryIt->MovOp))
835 TII.get(TargetOpcode::SUBREG_TO_REG))
864 TII.get(TargetOpcode::SUBREG_TO_REG), DefReg)
871 *BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(AndOpc), DstReg)
921 I.setDesc(TII.get(X86::COPY));
926 TII.get(TargetOpcode::SUBREG_TO_REG))
973 *BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(OpCmp))
978 TII.get(X86::SETCCr), I.getOperand(0).getReg()).addImm(CC);
1033 *BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(OpCmp))
1040 TII.get(X86::SETCCr), FlagReg1).addImm(SETFOpc[0]);
1042 TII.get(X86::SETCCr), FlagReg2).addImm(SETFOpc[1]);
1044 TII.get(SETFOpc[2]), ResultReg)
1066 *BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(OpCmp))
1071 *BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::SETCCr), ResultReg).addImm(CC);
1105 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::COPY), X86::EFLAGS)
1122 *BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Opcode), DstReg)
1126 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::COPY), CarryOutReg)
1172 I.setDesc(TII.get(X86::VEXTRACTF32x4Z256rr));
1174 I.setDesc(TII.get(X86::VEXTRACTF128rr));
1179 I.setDesc(TII.get(X86::VEXTRACTF32x4Zrr));
1181 I.setDesc(TII.get(X86::VEXTRACTF64x4Zrr));
1226 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::COPY), DstReg)
1263 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::COPY))
1305 I.setDesc(TII.get(X86::VINSERTF32x4Z256rr));
1307 I.setDesc(TII.get(X86::VINSERTF128rr));
1312 I.setDesc(TII.get(X86::VINSERTF32x4Zrr));
1314 I.setDesc(TII.get(X86::VINSERTF64x4Zrr));
1341 TII.get(TargetOpcode::G_EXTRACT), I.getOperand(Idx).getReg())
1380 TII.get(TargetOpcode::G_INSERT), Tmp)
1392 TII.get(TargetOpcode::COPY), DstReg)
1411 *BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::TEST8ri))
1414 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::JCC_1))
1453 BuildMI(*I.getParent(), I, DbgLoc, TII.get(X86::MOV64ri), AddrReg)
1461 addDirectMem(BuildMI(*I.getParent(), I, DbgLoc, TII.get(Opc), DstReg),
1479 BuildMI(*I.getParent(), I, DbgLoc, TII.get(Opc), DstReg), CPI, PICBase,
1509 I.setDesc(TII.get(X86::IMPLICIT_DEF));
1511 I.setDesc(TII.get(X86::PHI));
1643 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(OpEntry.OpCopy),
1650 TII.get(OpEntry.OpSignExtend));
1653 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::MOV32r0),
1660 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Copy),
1664 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Copy),
1669 TII.get(TargetOpcode::SUBREG_TO_REG), TypeEntry.HighInReg)
1677 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(OpEntry.OpDivRem))
1692 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Copy), SourceSuperReg)
1696 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::SHR16ri),
1703 TII.get(TargetOpcode::SUBREG_TO_REG))
1709 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(TargetOpcode::COPY),
1726 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::TRAP));
lib/Target/X86/X86OptimizeLEAs.cpp 583 return BuildMI(*MBB, MBB->erase(&MI), DL, TII->get(TargetOpcode::DBG_VALUE),
lib/Target/X86/X86PadShortFunction.cpp 208 BuildMI(*MBB, MBBI, DL, TSM.getInstrInfo()->get(X86::NOOP));
lib/Target/X86/X86RetpolineThunks.cpp 233 addRegOffset(BuildMI(&MBB, DebugLoc(), TII->get(MovOpc)), SPReg, false, 0)
259 BuildMI(Entry, DebugLoc(), TII->get(CallOpc)).addSym(TargetSym);
274 BuildMI(CaptureSpec, DebugLoc(), TII->get(X86::PAUSE));
275 BuildMI(CaptureSpec, DebugLoc(), TII->get(X86::LFENCE));
276 BuildMI(CaptureSpec, DebugLoc(), TII->get(X86::JMP_1)).addMBB(CaptureSpec);
285 BuildMI(CallTarget, DebugLoc(), TII->get(RetOpc));
lib/Target/X86/X86SpeculativeLoadHardening.cpp 254 BuildMI(&MBB, DebugLoc(), TII.get(X86::JMP_1)).addMBB(&OldLayoutSucc);
447 BuildMI(Entry, EntryInsertPt, Loc, TII->get(X86::MOV64ri32), PS->PoisonReg)
460 BuildMI(Entry, EntryInsertPt, Loc, TII->get(X86::LFENCE));
481 auto ZeroI = BuildMI(Entry, EntryInsertPt, Loc, TII->get(X86::MOV32r0),
489 BuildMI(Entry, EntryInsertPt, Loc, TII->get(X86::SUBREG_TO_REG),
591 BuildMI(*MBB, InsertPt, DebugLoc(), TII->get(X86::LFENCE));
757 TII->get(CMovOp), UpdatedStateReg)
845 const MCInstrDesc &MCID = TII.get(UnfoldedOpc);
1110 TII->get(X86::MOV64ri32), TargetReg)
1117 auto AddrI = BuildMI(*Pred, InsertPt, DebugLoc(), TII->get(X86::LEA64r),
1148 auto CheckI = BuildMI(MBB, InsertPt, DebugLoc(), TII->get(X86::CMP64ri32))
1158 BuildMI(MBB, InsertPt, DebugLoc(), TII->get(X86::LEA64r), AddrReg)
1167 auto CheckI = BuildMI(MBB, InsertPt, DebugLoc(), TII->get(X86::CMP64rr))
1180 BuildMI(MBB, InsertPt, DebugLoc(), TII->get(CMovOp), UpdatedStateReg)
1884 BuildMI(MBB, InsertPt, Loc, TII->get(X86::COPY), Reg).addReg(X86::EFLAGS);
1897 BuildMI(MBB, InsertPt, Loc, TII->get(X86::COPY), X86::EFLAGS).addReg(Reg);
1912 auto ShiftI = BuildMI(MBB, InsertPt, Loc, TII->get(X86::SHL64ri), TmpReg)
1917 auto OrI = BuildMI(MBB, InsertPt, Loc, TII->get(X86::OR64rr), X86::RSP)
1934 BuildMI(MBB, InsertPt, Loc, TII->get(TargetOpcode::COPY), TmpReg)
1937 BuildMI(MBB, InsertPt, Loc, TII->get(X86::SAR64ri), PredStateReg)
2050 BuildMI(MBB, InsertPt, Loc, TII->get(X86::VMOV64toPQIrr), VStateReg)
2059 TII->get(Is128Bit ? X86::VPBROADCASTQrr
2071 TII->get(Is128Bit ? X86::VPORrr : X86::VPORYrr), TmpReg)
2092 BuildMI(MBB, InsertPt, Loc, TII->get(BroadcastOp), VStateReg)
2102 auto OrI = BuildMI(MBB, InsertPt, Loc, TII->get(OrOp), TmpReg)
2115 auto OrI = BuildMI(MBB, InsertPt, Loc, TII->get(X86::OR64rr), TmpReg)
2125 BuildMI(MBB, InsertPt, Loc, TII->get(X86::SHRX64rr), TmpReg)
2296 BuildMI(MBB, InsertPt, Loc, TII->get(TargetOpcode::COPY), NarrowStateReg)
2308 auto OrI = BuildMI(MBB, InsertPt, Loc, TII->get(OrOpCode), NewReg)
2444 BuildMI(MBB, std::next(InsertPt), Loc, TII->get(X86::LFENCE));
2499 BuildMI(MBB, InsertPt, Loc, TII->get(X86::MOV64ri32), ExpectedRetAddrReg)
2502 BuildMI(MBB, InsertPt, Loc, TII->get(X86::LEA64r), ExpectedRetAddrReg)
2520 BuildMI(MBB, InsertPt, Loc, TII->get(X86::MOV64rm), ExpectedRetAddrReg)
2539 BuildMI(MBB, InsertPt, Loc, TII->get(X86::CMP64ri32))
2544 BuildMI(MBB, InsertPt, Loc, TII->get(X86::LEA64r), ActualRetAddrReg)
2550 BuildMI(MBB, InsertPt, Loc, TII->get(X86::CMP64rr))
2561 auto CMovI = BuildMI(MBB, InsertPt, Loc, TII->get(CMovOp), UpdatedStateReg)
lib/Target/X86/X86VZeroUpper.cpp 181 BuildMI(MBB, I, dl, TII->get(X86::VZEROUPPER));
lib/Target/X86/X86WinAllocaExpander.cpp 220 BuildMI(*MBB, I, DL, TII->get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
234 BuildMI(*MBB, I, DL, TII->get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
239 TII->get(getSubOpcode(Is64BitAlloca, Amount)), StackPtr)
248 BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::COPY), RegA)
257 TII->get(Is64BitAlloca ? X86::SUB64rr : X86::SUB32rr), StackPtr)
lib/Target/XCore/XCoreFrameLowering.cpp 66 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
77 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
88 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
107 BuildMI(MBB, MBBI, dl, TII.get(Opcode)).addImm(OpImm);
129 BuildMI(MBB, MBBI, dl, TII.get(Opcode), XCore::SP).addImm(OpImm);
202 BuildMI(MBB, MBBI, dl, TII.get(Opcode), SpillList[i].Reg)
242 BuildMI(MBB, MBBI, dl, TII.get(XCore::LDWSP_ru6), XCore::R11).addImm(0);
264 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opcode));
289 BuildMI(MBB, MBBI, dl, TII.get(Opcode))
307 BuildMI(MBB, MBBI, dl, TII.get(XCore::LDAWSP_ru6), FramePtr).addImm(0);
372 BuildMI(MBB, MBBI, dl, TII.get(XCore::SETSP_1r)).addReg(EhStackReg);
373 BuildMI(MBB, MBBI, dl, TII.get(XCore::BAU_1r)).addReg(EhHandlerReg);
386 BuildMI(MBB, MBBI, dl, TII.get(XCore::SETSP_1r)).addReg(FramePtr);
401 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opcode))
409 BuildMI(MBB, MBBI, dl, TII.get(Opcode), XCore::SP).addImm(RemainingAdj);
518 New = BuildMI(MF, Old.getDebugLoc(), TII.get(Opcode)).addImm(Amount);
522 New = BuildMI(MF, Old.getDebugLoc(), TII.get(Opcode), XCore::SP)
lib/Target/XCore/XCoreISelLowering.cpp 1559 BuildMI(BB, dl, TII.get(XCore::BRFT_lru6))
1575 BuildMI(*BB, BB->begin(), dl, TII.get(XCore::PHI), MI.getOperand(0).getReg())
lib/Target/XCore/XCoreInstrInfo.cpp 286 BuildMI(&MBB, DL, get(XCore::BRFU_lu6)).addMBB(TBB);
290 BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg())
299 BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg())
301 BuildMI(&MBB, DL, get(XCore::BRFU_lu6)).addMBB(FBB);
339 BuildMI(MBB, I, DL, get(XCore::ADD_2rus), DestReg)
346 BuildMI(MBB, I, DL, get(XCore::LDAWSP_ru6), DestReg).addImm(0);
351 BuildMI(MBB, I, DL, get(XCore::SETSP_1r))
374 BuildMI(MBB, I, DL, get(XCore::STWFI))
396 BuildMI(MBB, I, DL, get(XCore::LDWFI), DestReg)
435 return BuildMI(MBB, MI, dl, get(XCore::MKMSK_rus), Reg)
441 return BuildMI(MBB, MI, dl, get(Opcode), Reg).addImm(Value).getInstr();
447 return BuildMI(MBB, MI, dl, get(XCore::LDWCP_lru6), Reg)
lib/Target/XCore/XCoreRegisterInfo.cpp 70 BuildMI(MBB, II, dl, TII.get(XCore::LDW_2rus), Reg)
76 BuildMI(MBB, II, dl, TII.get(XCore::STW_2rus))
83 BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l2rus), Reg)
106 BuildMI(MBB, II, dl, TII.get(XCore::LDW_3r), Reg)
112 BuildMI(MBB, II, dl, TII.get(XCore::STW_l3r))
119 BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l3r), Reg)
140 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg)
146 BuildMI(MBB, II, dl, TII.get(NewOpcode))
153 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg)
176 BuildMI(MBB, II, dl, TII.get(XCore::LDAWSP_ru6), ScratchBase).addImm(0);
183 BuildMI(MBB, II, dl, TII.get(XCore::LDW_3r), Reg)
189 BuildMI(MBB, II, dl, TII.get(XCore::STW_l3r))
196 BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l3r), Reg)
tools/lldb/source/Plugins/Disassembler/llvm/DisassemblerLLVMC.cpp 1068 return m_instr_info_up->get(mc_inst.getOpcode())
1074 return m_instr_info_up->get(mc_inst.getOpcode()).hasDelaySlot();
1078 return m_instr_info_up->get(mc_inst.getOpcode()).isCall();
tools/lldb/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp 995 return m_insn_info->get(mc_insn.getOpcode()).getSize();
1856 uint32_t current_inst_size = m_insn_info->get(insn.getOpcode()).getSize();
2108 uint32_t current_inst_size = m_insn_info->get(insn.getOpcode()).getSize();
2165 uint32_t current_inst_size = m_insn_info->get(insn.getOpcode()).getSize();
2192 uint32_t current_inst_size = m_insn_info->get(insn.getOpcode()).getSize();
tools/lldb/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp 1662 uint32_t current_inst_size = m_insn_info->get(insn.getOpcode()).getSize();
1742 uint32_t current_inst_size = m_insn_info->get(insn.getOpcode()).getSize();
tools/llvm-cfi-verify/lib/FileAnalysis.cpp 170 const auto &InstrDesc = MII->get(InstrMeta.Instruction.getOpcode());
175 const auto &InstrDesc = MII->get(InstrMeta.Instruction.getOpcode());
192 const auto &InstrDesc = MII->get(InstrMeta.Instruction.getOpcode());
207 const auto &InstrDesc = MII->get(InstrMeta.Instruction.getOpcode());
286 const auto &InstrDesc = MII->get(InstrMetaPtr->Instruction.getOpcode());
329 bool canLoad = !MII->get(IndirectCF.Instruction.getOpcode()).mayLoad();
338 const auto &InstrDesc = MII->get(NodeInstr.Instruction.getOpcode());
499 const auto &InstrDesc = MII->get(Instruction.getOpcode());
tools/llvm-cfi-verify/lib/GraphBuilder.cpp 235 Analysis.getMCInstrInfo()->get(ParentMeta.Instruction.getOpcode());
tools/llvm-exegesis/lib/Assembler.cpp 95 const MCInstrDesc &MCID = MCII->get(Opcode);
127 BuildMI(MBB, DL, TII->get(TII->getReturnOpcode()));
tools/llvm-exegesis/lib/MCInstrDescView.cpp 100 : Description(&InstrInfo.get(Opcode)), Name(InstrInfo.getName(Opcode)) {
tools/llvm-exegesis/lib/SchedClassResolution.cpp 233 unsigned SchedClassId = InstrInfo.get(MCI.getOpcode()).getSchedClass();
tools/llvm-exegesis/lib/X86/Target.cpp 654 BuildMI(&MBB, DebugLoc(), MII.get(X86::ADD64ri8))
658 BuildMI(&MBB, DebugLoc(), MII.get(X86::JCC_1))
tools/llvm-exegesis/llvm-exegesis.cpp 255 State.getInstrInfo().get(Opcode).getSchedClass() == 0) {
tools/llvm-mca/Views/InstructionInfoView.cpp 41 const MCInstrDesc &MCDesc = MCII.get(Inst.getOpcode());
unittests/Target/ARM/MachineInstrTest.cpp 491 const MCInstrDesc &Desc = TII->get(i);
499 uint64_t Flags = MII->get(i).TSFlags;
unittests/tools/llvm-exegesis/X86/SnippetGeneratorTest.cpp 78 EXPECT_THAT(InstrInfo.get(Opcode).getImplicitDefs()[0], X86::AX);
79 EXPECT_THAT(InstrInfo.get(Opcode).getImplicitDefs()[1], X86::EFLAGS);
80 EXPECT_THAT(InstrInfo.get(Opcode).getImplicitUses()[0], X86::AX);
81 EXPECT_THAT(InstrInfo.get(Opcode).getImplicitUses()[1], X86::EFLAGS);
104 EXPECT_THAT(InstrInfo.get(Opcode).getImplicitDefs()[0], X86::EFLAGS);