|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
include/llvm/CodeGen/LiveRegUnits.h 59 if (O->isDef()) {
include/llvm/CodeGen/LiveVariables.h 253 if (MO.isReg() && MO.isDef() && MO.getReg() == reg) {
include/llvm/CodeGen/MachineInstr.h 450 if (MO.isDef() && MO.isImplicit())
1369 if (!MO.isReg() || !MO.isDef() || !MO.isTied())
include/llvm/CodeGen/MachineInstrBuilder.h 498 return getDefRegState(RegOp.isDef()) | getImplRegState(RegOp.isImplicit()) |
include/llvm/CodeGen/MachineRegisterInfo.h 981 (!ReturnDefs && op->isDef()) ||
1001 while (Op && ((!ReturnDefs && Op->isDef()) ||
1087 (!ReturnDefs && op->isDef()) ||
1107 while (Op && ((!ReturnDefs && Op->isDef()) ||
lib/CodeGen/AggressiveAntiDepBreaker.cpp 240 if (MO.isDef())
253 if ((MO.isDef() && MI.isRegTiedToUseOperand(i)) ||
367 if (!MO.isReg() || !MO.isDef()) continue;
377 if (!MO.isReg() || !MO.isDef()) continue;
420 if (!MO.isReg() || !MO.isDef()) continue;
720 if (!Q.second.Operand->isDef() || !Q.second.Operand->isEarlyClobber())
lib/CodeGen/AsmPrinter/AsmPrinter.cpp 811 OS << ' ' << (Op.isDef() ? "def " : "killed ")
lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp 473 for (; MI->getOperand(NumDefs).isReg() && MI->getOperand(NumDefs).isDef();
lib/CodeGen/AsmPrinter/DbgEntityHistoryCalculator.cpp 271 if (MO.isReg() && MO.isDef() && MO.getReg()) {
lib/CodeGen/AsmPrinter/DwarfDebug.cpp 590 if (MO.isReg() && MO.isDef() &&
lib/CodeGen/BranchFolding.cpp 2024 if (MO.isDef()) {
2087 if (!MO.isReg() || !MO.isDef() || MO.isDead())
lib/CodeGen/BreakFalseDeps.cpp 131 if (!CurrMO.isReg() || CurrMO.isDef() || CurrMO.isUndef() ||
lib/CodeGen/CriticalAntiDepBreaker.cpp 277 if (!MO.isDef()) continue;
356 if (RefOper->isDef() && RefOper->isEarlyClobber())
367 if (!CheckOper.isReg() || !CheckOper.isDef() ||
373 if (RefOper->isDef())
622 if (MO.isDef() && Reg != AntiDepReg)
lib/CodeGen/DeadMachineInstructionElim.cpp 77 if (MO.isReg() && MO.isDef()) {
142 if (MO.isReg() && MO.isDef()) {
lib/CodeGen/DetectDeadLanes.cpp 544 if (MO.isDef() && !MO.isDead() && RegInfo.UsedLanes.none()) {
lib/CodeGen/EarlyIfConversion.cpp 265 if (MO.isDef() && Register::isPhysicalRegister(Reg))
386 if (MO.isDef())
lib/CodeGen/ExecutionDomainFix.cpp 387 if (!LiveRegs[rx] || (mo.isDef() && LiveRegs[rx] != dv)) {
lib/CodeGen/ExpandPostRAPseudos.cpp 77 assert((MI->getOperand(0).isReg() && MI->getOperand(0).isDef()) &&
lib/CodeGen/GlobalISel/CSEInfo.cpp 337 if (!MO.isDef())
lib/CodeGen/GlobalISel/CombinerHelper.cpp 114 if (MO.isDef())
126 if (BuildVecMO.isDef())
lib/CodeGen/GlobalISel/RegBankSelect.cpp 153 if (MO.isDef())
174 if (MO.isDef()) {
246 assert(CurRegBank || MO.isDef());
265 if (MO.isDef())
338 assert((!MI.isPHI() || !MO.isDef()) && "Need split for phi def?");
341 if (!MO.isDef()) {
365 assert(MI.isTerminator() && MO.isDef() &&
735 bool Before = !MO.isDef();
lib/CodeGen/GlobalISel/Utils.cpp 61 assert(RegMO.isDef() && "Must be a definition");
168 if (!MO.isReg() || !MO.isDef())
lib/CodeGen/IfConversion.cpp 1951 if (MO.isDef()) {
2119 if (MO.isDef() && !LaterRedefs.count(Reg))
lib/CodeGen/ImplicitNullChecks.cpp 288 if (TRI->regsOverlap(RegA, RegB) && (MOA.isDef() || MOB.isDef()))
288 if (TRI->regsOverlap(RegA, RegB) && (MOA.isDef() || MOB.isDef()))
442 assert(!(DependenceMO.isDef() &&
601 return MO.isReg() && MO.getReg() && MO.isDef() &&
648 assert(MO.isDef() && "Expected def or use");
690 if (!MO.isReg() || !MO.isDef())
700 if (!MO.isReg() || !MO.getReg() || !MO.isDef())
lib/CodeGen/InlineSpiller.cpp 823 if (LoadMI && MO.isDef())
1523 if (MO.isReg() && MO.isImplicit() && MO.isDef() && !MO.isDead())
lib/CodeGen/LiveDebugValues.cpp 815 if (MO.isReg() && MO.isDef() && MO.getReg() &&
1003 !DestRegOp->isDef())
lib/CodeGen/LiveDebugVariables.cpp 246 if (locations.back().isDef())
lib/CodeGen/LiveInterval.cpp 904 if (!MOI->isReg() || !MOI->isDef())
lib/CodeGen/LiveIntervals.cpp 788 assert(MO.isDef());
1522 if (MO.isDef()) {
lib/CodeGen/LivePhysRegs.cpp 47 if (!O->isDef() || O->isDebug())
92 if (O->isDef()) {
292 if (!MO->isReg() || !MO->isDef() || MO->isDebug())
lib/CodeGen/LiveRangeCalc.cpp 83 if (!MO.isDef() && !MO.readsReg())
99 if (MO.isDef())
107 if (MO.isDef() && !LI.hasSubRanges())
174 if (!MO.readsReg() || (IsSubRange && MO.isDef()))
180 if (MO.isDef())
192 assert(!MO.isDef() && "Cannot handle PHI def of partial register.");
200 if (MO.isDef())
lib/CodeGen/LiveRangeEdit.cpp 192 if (MO.isDef()) {
292 if (VRM && MI->getOperand(0).isReg() && MI->getOperand(0).isDef() &&
316 else if (MOI->isDef())
326 if ((MI->readsVirtualRegister(Reg) && (MI->isCopy() || MOI->isDef())) ||
331 if (MOI->isDef()) {
lib/CodeGen/LiveRangeShrink.cpp 184 if (MO.isDef()) {
lib/CodeGen/LiveRegUnits.cpp 48 if (!O->isDef() || O->isDebug())
76 if (!O->isDef() && !O->readsReg())
lib/CodeGen/LiveVariables.cpp 216 if (!MO.isReg() || !MO.isDef() || MO.getReg() == 0)
530 assert(MO.isDef());
786 if (I->isDef())
lib/CodeGen/MIRCanonicalizerPass.cpp 176 if (!MO.isDef())
192 if (!MO.isDef())
360 if (!MO.isDef() && MO.isKill()) {
365 if (MO.isDef() && MO.isDead()) {
lib/CodeGen/MIRParser/MIParser.cpp 1077 return MO.isDef() ? "implicit-def" : "implicit";
1371 if (!DefOperand.isReg() || !DefOperand.isDef())
lib/CodeGen/MIRPrinter.cpp 719 for (; I < E && MI.getOperand(I).isReg() && MI.getOperand(I).isDef() &&
849 if (ShouldPrintRegisterTies && Op.isReg() && Op.isTied() && !Op.isDef())
lib/CodeGen/MIRVRegNamerUtils.cpp 245 if (!MO->isDef())
lib/CodeGen/MachineCSE.cpp 283 if (!MO.isReg() || MO.isDef())
302 if (!MO.isReg() || !MO.isDef())
379 if (!MO.isReg() || !MO.isDef())
596 if (!MO.isReg() || !MO.isDef())
825 assert(MI->getOperand(0).isDef() &&
lib/CodeGen/MachineCombiner.cpp 228 if (!MO.isDef())
lib/CodeGen/MachineCopyPropagation.cpp 396 if (!MOUse.isReg() || MOUse.isTied() || MOUse.isUndef() || MOUse.isDef() ||
528 if (!MO.isReg() || !MO.isDef())
570 if (MO.isDef() && !MO.isEarlyClobber()) {
lib/CodeGen/MachineInstr.cpp 626 if (MO.isDef()) {
684 if (!MO.isReg() || !MO.isDef())
725 if (!MO.isReg() || !MO.isDef() || MO.isImplicit())
1001 if (!MO.isReg() || !MO.isDef())
1053 assert(DefMO.isDef() && "DefIdx must be a def operand");
1412 if (!Operand.isReg() || Operand.isDef())
1491 if (MO.isReg() && MO.isTied() && !MO.isDef())
1501 if (!MO.isReg() || !MO.isDef() || MO.isImplicit())
1873 if (!MO.isReg() || !MO.isDef())
1918 if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg)
1926 if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg || MO.getSubReg() == 0)
1940 if (MO.isReg() && MO.getReg() == Reg && MO.isDef() &&
1958 if (!MO.isReg() || !MO.isDef()) continue;
1983 if (MO.isReg() && MO.isDef() && Register::isVirtualRegister(MO.getReg()))
lib/CodeGen/MachineInstrBundle.cpp 152 if (MO.isDef()) {
300 if (MO.isDef())
305 if (MO.isDef())
347 } else if (MO.isDef()) {
lib/CodeGen/MachineLICM.cpp 432 if (!MO.isDef()) {
554 if (!MO.isReg() || MO.isDef() || !MO.getReg())
579 if (!MO.isReg() || !MO.getReg() || MO.isDef()) continue;
769 if (!MO.isDef() || !MO.isReg() || !MO.getReg())
864 if (MO.isDef())
1061 if (!MO.isReg() || !MO.isDef())
1131 if (!DefMO.isReg() || !DefMO.isDef())
1230 if (MO.isDef() && HasHighOperandLatency(MI, i, Reg)) {
1384 if (MO.isReg() && MO.isDef() &&
1486 if (MO.isReg() && MO.isDef() && !MO.isDead())
lib/CodeGen/MachineOperand.cpp 91 if (isDef())
126 if (isDef())
281 return getReg() == Other.getReg() && isDef() == Other.isDef() &&
281 return getReg() == Other.getReg() && isDef() == Other.isDef() &&
347 return hash_combine(MO.getType(), (unsigned)MO.getReg(), MO.getSubReg(), MO.isDef());
753 OS << (isDef() ? "implicit-def " : "implicit ");
754 else if (PrintDef && isDef())
798 if (ShouldPrintRegisterTies && isTied() && !isDef())
lib/CodeGen/MachineOutliner.cpp 1253 if (MOP.isDef())
lib/CodeGen/MachinePipeliner.cpp 773 if (MOI->isDef()) {
1566 if (MO.isReg() && MO.isDef() && !MO.isDead()) {
2486 if (MO.isDef() && Reads && stageScheduled(*I) <= StageInst1) {
2490 } else if (MO.isDef() && Reads && stageScheduled(*I) > StageInst1) {
2630 if (!DMO.isReg() || !DMO.isDef())
lib/CodeGen/MachineRegisterInfo.cpp 292 if (MO->isDef()) {
lib/CodeGen/MachineScheduler.cpp 946 if (MO2.isReg() && MO2.isDef() && MO2.getReg() == Reg && !MO2.isDead()) {
lib/CodeGen/MachineSink.cpp 953 if (!MO.isReg() || !MO.isDef() || !MO.getReg().isVirtual())
994 if (!MO.isReg() || !MO.isDef() || !MO.getReg().isVirtual())
1191 if (MO.isDef()) {
1312 if (!MO.isReg() || !MO.isDef())
lib/CodeGen/MachineTraceMetrics.cpp 715 if (MO.isDef()) {
910 if (!MO.isDef())
lib/CodeGen/MachineVerifier.cpp 1605 else if (!MO->isDef() && !MCOI.isOptionalDef())
1615 if (MO->isDef() && !MCOI.isOptionalDef())
1974 if (LI.hasSubRanges() && !MO->isDef()) {
2054 if (MO->isDef()) {
2215 if (!MODef.isReg() || !MODef.isDef()) {
2416 if (!MOI->isReg() || !MOI->isDef())
2561 if (MOI->isDef()) {
lib/CodeGen/ModuloSchedule.cpp 78 if (!Op.isReg() || !Op.isDef())
625 if (!MO.isReg() || !MO.isDef() ||
727 if (!MOI->isReg() || !MOI->isDef())
1030 if (MO.isDef()) {
lib/CodeGen/PeepholeOptimizer.cpp 1356 if (!MO.isReg() || MO.isDef())
1664 if (MO.isDef() && isNAPhysCopy(Reg)) {
1853 assert(!MO.isDef() && "We should have skipped all the definitions by now");
2051 assert(((Def->getOperand(DefIdx).isDef() &&
lib/CodeGen/RegAllocFast.cpp 878 if (MO.isDef() && MO.isUndef())
906 if (!MO.isReg() || !MO.isDef()) continue;
962 if (!MO.isReg() || (MO.isDef() && !MO.isEarlyClobber())) continue;
1145 if (!MO.isDef() && !MO.isTied()) continue;
1167 if (!MO.isReg() || !MO.isDef() || !MO.getReg() || MO.isEarlyClobber())
1180 if (!MO.isReg() || !MO.isDef() || !MO.getReg() || MO.isEarlyClobber())
lib/CodeGen/RegisterCoalescer.cpp 1194 if (!Op.isReg() || !Op.isDef() || Op.getReg() != Reg)
1337 if (MO.isReg() && MO.isDef()) {
1588 if (MO.isDef() /*|| MO.isUndef()*/)
1618 if (MO.isReg() && MO.isDef() && MO.getReg() == DstReg)
1628 if (MO.isDef())
1700 if (SubIdx && MO.isDef())
2394 if (!MO.isReg() || MO.getReg() != Reg || !MO.isDef())
2828 if (!MO.isReg() || MO.isDef() || MO.getReg() != Reg)
2944 if (MO.isReg() && MO.isDef() && MO.getReg() == Reg) {
lib/CodeGen/RegisterPressure.cpp 507 assert(MO.isDef());
539 assert(MO.isDef());
lib/CodeGen/RegisterScavenging.cpp 147 assert(MO.isDef());
243 assert(MO.isDef());
333 if (MO.isDef())
636 if (MO.isDef()) {
728 assert((!MO.isUndef() || MO.isDef()) && "Cannot handle undef uses");
732 if (MO.isDef()) {
743 assert((!MO.isUndef() || MO.isDef()) && "Cannot handle undef uses");
lib/CodeGen/RenameIndependentSubregs.cpp 179 if (!MO.isDef() && !MO.readsReg())
189 Pos = MO.isDef() ? Pos.getRegSlot(MO.isEarlyClobber())
218 if (!MO.isDef() && !MO.readsReg())
223 Pos = MO.isDef() ? Pos.getRegSlot(MO.isEarlyClobber())
345 if (!MO.isDef())
lib/CodeGen/ScheduleDAGInstrs.cpp 206 if (!MO.isReg() || MO.isDef()) continue;
231 assert(MO.isDef() && "expect physreg def");
321 if (!MO.isDef()) {
409 if (OtherMO.isReg() && OtherMO.isDef() && OtherMO.getReg() == Reg)
839 if (!MO.isReg() || !MO.isDef())
1120 if (!MO.isDef())
lib/CodeGen/SelectionDAG/FastISel.cpp 173 if (MO.isDef()) {
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp 1639 if (!OPI->isReg() || !OPI->isDef())
lib/CodeGen/ShrinkWrap.cpp 279 if (!MO.isDef() && !MO.readsReg())
lib/CodeGen/SplitKit.cpp 1331 if (MO.isDef() || MO.isUndef())
1346 if (MO.isDef()) {
lib/CodeGen/StackMaps.cpp 55 : MI(MI), HasDef(MI->getOperand(0).isReg() && MI->getOperand(0).isDef() &&
60 MI->getOperand(CheckStartIdx).isDef() &&
77 MI->getOperand(ScratchIdx).isDef() &&
lib/CodeGen/TailDuplicator.cpp 390 if (MO.isDef()) {
lib/CodeGen/TargetInstrInfo.cpp 537 Flags |= MI.getOperand(OpIdx).isDef() ? MachineMemOperand::MOStore
948 if (MO.isDef() && Reg != DefReg)
lib/CodeGen/TargetSchedule.cpp 161 if (MO.isReg() && MO.isDef())
177 if (MO.isReg() && MO.readsReg() && !MO.isDef())
lib/CodeGen/TwoAddressInstructionPass.cpp 238 if (!MO.isDef())
397 if (MO.isDef() && DI->second > LastDef)
916 if (MO.isDef())
960 if (MO.isDef()) {
lib/CodeGen/VirtRegMap.cpp 530 if ((MO.readsReg() && (MO.isDef() || MO.isKill())) ||
531 (MO.isDef() && subRegLiveThrough(*MI, PhysReg)))
534 if (MO.isDef()) {
549 assert(MO.isDef());
557 if (MO.isDef()) {
lib/Target/AArch64/AArch64CollectLOH.cpp 474 if (!MO.isReg() || !MO.isDef())
534 assert(Def.isReg() && Def.isDef() && "Expected reg def");
lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp 144 if (!MO.isReg() || !MO.isDef())
lib/Target/AArch64/AArch64RedundantCopyElimination.cpp 407 return !O.isDead() && O.isReg() && O.isDef() &&
lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp 229 return MachineOperand::CreateReg(DstReg, MO.isDef(), MO.isImplicit(),
lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp 761 if (IRI.isDef()) {
804 if (IRI.isDef()) {
941 if (O.isDef())
lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp 766 if (!Op.isReg() || Op.isDef())
lib/Target/AMDGPU/GCNHazardRecognizer.cpp 776 if (Op.isReg() && Op.isDef()) {
970 if (MO.isDef() && TRI->isSGPRClass(TRI->getPhysRegClass(MO.getReg()))) {
1055 if (MO.isDef() && TRI->isSGPRClass(TRI->getPhysRegClass(MO.getReg())))
1243 if (Op.isDef() && Opc != AMDGPU::V_ACCVGPR_WRITE_B32)
lib/Target/AMDGPU/GCNIterativeScheduler.cpp 392 if (Op.isReg() && Op.isDef())
lib/Target/AMDGPU/GCNRegPressure.cpp 200 assert(MO.isDef() && MO.isReg() && Register::isVirtualRegister(MO.getReg()));
lib/Target/AMDGPU/GCNSchedStrategy.cpp 410 if (Op.isReg() && Op.isDef())
lib/Target/AMDGPU/R600ControlFlowFinalizer.cpp 305 if (MO.isDef()) {
lib/Target/AMDGPU/R600EmitClauseMarkers.cpp 203 if (!MOI->isReg() || !MOI->isDef() ||
lib/Target/AMDGPU/R600MachineScheduler.cpp 366 if (MO.isReg() && !MO.isDef() &&
lib/Target/AMDGPU/SIFixSGPRCopies.cpp 216 if (MO.isDef() || UseMI->getParent() != MI.getParent() ||
439 if ((MO.isReg() && ((MO.isDef() && MO.getReg() != Reg) || !MO.isDef())) ||
439 if ((MO.isReg() && ((MO.isDef() && MO.getReg() != Reg) || !MO.isDef())) ||
lib/Target/AMDGPU/SIFoldOperands.cpp 253 assert(Dst0.isDef() && Dst1.isDef());
253 assert(Dst0.isDef() && Dst1.isDef());
414 assert(MI->getOperand(1).isDef());
lib/Target/AMDGPU/SIFormMemoryClauses.cpp 125 if (!MO.isReg() || MO.isDef())
225 RegUse &Map = MO.isDef() ? Uses : Defs;
275 RegUse &Map = MO.isDef() ? Defs : Uses;
lib/Target/AMDGPU/SIInsertWaitcnts.cpp 466 (Def && !Op.isDef()) || TRI->isAGPR(*MRI, Op.getReg()))
573 if (Op.isReg() && !Op.isDef() && TRI->isVGPR(MRIA, Op.getReg())) {
620 if (DefMO.isReg() && DefMO.isDef() &&
629 if (MO.isReg() && !MO.isDef() && TRI->isVGPR(MRIA, MO.getReg())) {
lib/Target/AMDGPU/SIInstrInfo.cpp 3135 if (MO.isDef())
5016 if (Op.isDef() && !Op.isDead())
5053 bool HasDst = Inst.getOperand(0).isReg() && Inst.getOperand(0).isDef();
5718 assert(Op.isReg() && Op.getReg() == AMDGPU::SCC && Op.isDef() &&
lib/Target/AMDGPU/SILoadStoreOptimizer.cpp 564 if (Op.isDef())
597 (Use.isDef() && RegDefs.count(Use.getReg())) ||
598 (Use.isDef() && Register::isPhysicalRegister(Use.getReg()) &&
lib/Target/AMDGPU/SILowerControlFlow.cpp 140 assert(ImpDefSCC.getReg() == AMDGPU::SCC && ImpDefSCC.isDef());
207 assert(ImpDefSCC.getReg() == AMDGPU::SCC && ImpDefSCC.isDef());
lib/Target/AMDGPU/SIPeepholeSDWA.cpp 296 if (!Reg->isReg() || !Reg->isDef())
lib/Target/ARM/A15SDOptimizer.cpp 214 if ((!MODef.isReg()) || (!MODef.isDef()))
lib/Target/ARM/ARMBaseInstrInfo.cpp 283 if (MO.isDef()) {
551 (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)) {
562 if (MO.isReg() && MO.getReg() == ARM::CPSR && MO.isDef() && !MO.isDead())
2203 if (MO.isDef() && !MO.isDead())
3065 if (MO.isDef()) {
lib/Target/ARM/ARMConstantIslandPass.cpp 2064 if (MO.isDef() && MO.getReg() == BaseReg)
2083 if (MO.isDef() && MO.getReg() == BaseReg)
2144 if (MO.isDef() && MO.getReg() == EntryReg)
lib/Target/ARM/ARMFastISel.cpp 256 if (!MO.isReg() || !MO.isDef()) continue;
lib/Target/ARM/ARMISelLowering.cpp10785 if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR) {
lib/Target/ARM/ARMLoadStoreOptimizer.cpp 207 if (MO.isDef() && MO.getReg() == ARM::CPSR && !MO.isDead())
874 if (!MO.isReg() || !MO.isDef() || MO.isDead())
943 else if (MO.isDef())
2125 if (MO.isDef() && TRI->regsOverlap(Reg, Base))
lib/Target/ARM/ARMLowOverheadLoops.cpp 123 if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg)
lib/Target/ARM/Thumb1FrameLowering.cpp 642 if (MO.isReg() && (MO.isImplicit() || MO.isDef()))
757 if (MO.isReg() && (MO.isImplicit() || MO.isDef()) &&
lib/Target/ARM/Thumb2ITBlockPass.cpp 115 if (!MO.isReg() || MO.isDef() || !MO.isKill())
lib/Target/ARM/Thumb2SizeReduction.cpp 310 if (!MO.isReg() || MO.isUndef() || MO.isDef())
990 if (!MO.isReg() || MO.isUndef() || MO.isDef())
lib/Target/AVR/AVRExpandPseudoInsts.cpp 876 if (MO.isReg() && MO.getReg() != 0 && !MO.isDef() &&
lib/Target/BPF/BTFDebug.cpp 1013 for (; MI->getOperand(NumDefs).isReg() && MI->getOperand(NumDefs).isDef();
lib/Target/Hexagon/BitTracker.cpp 874 if (!MO.isReg() || !MO.isDef())
lib/Target/Hexagon/HexagonBitSimplify.cpp 291 if (!Op.isReg() || !Op.isDef())
1016 if (!Op.isReg() || !Op.isDef())
2723 if (!Op0.isReg() || !Op0.isDef())
lib/Target/Hexagon/HexagonBitTracker.cpp 196 if (!MO.isReg() || !MO.isDef())
1043 if (!Op.isReg() || !Op.isDef())
1190 assert(MD.isReg() && MD.isDef());
lib/Target/Hexagon/HexagonBlockRanges.cpp 337 if (!Op.isReg() || !Op.isDef() || Op.isUndef())
lib/Target/Hexagon/HexagonConstPropagation.cpp 693 if (!MO.isReg() || !MO.isDef())
1923 if (!MD.isDef())
2832 if (!MO.isReg() || !MO.isDef())
lib/Target/Hexagon/HexagonCopyToCombine.cpp 443 if (!Op.isDef() || !Op.getReg())
lib/Target/Hexagon/HexagonEarlyIfConv.cpp 385 if (!MO.isReg() || !MO.isDef())
492 if (!MO.isReg() || !MO.isDef())
lib/Target/Hexagon/HexagonExpandCondsets.cpp 373 if (!Op.isReg() || !Op.isDef())
500 if (Op.isDef()) {
673 assert(MD.isDef());
729 if (!Op.isReg() || !Op.isDef())
765 if (!Op.isReg() || !Op.isDef())
811 if (Op.isDef() && isRefInMap(RR, Uses, Exec_Then))
878 if (!MO.isReg() || !MO.isDef())
926 assert(!Op.isDef() && "Not expecting a def");
1005 ReferenceMap &Map = Op.isDef() ? Defs : Uses;
1006 if (Op.isDef() && Op.isUndef()) {
lib/Target/Hexagon/HexagonGenInsert.cpp 608 if (MO.isReg() && MO.isDef()) {
725 if (!MO.isReg() || !MO.isDef())
1478 if (!MO.isReg() || !MO.isDef())
lib/Target/Hexagon/HexagonGenMux.cpp 175 BitVector &Set = MO.isDef() ? Defs : Uses;
lib/Target/Hexagon/HexagonGenPredicate.cpp 258 assert(DefI->getOperand(0).isDef() && DefI->getOperand(1).isUse());
414 assert(Op0.isDef());
lib/Target/Hexagon/HexagonHardwareLoops.cpp 1038 if (!MO.isReg() || !MO.isDef())
1058 if (!OPO.isReg() || !OPO.isDef())
1093 if (!MO.isReg() || !MO.isDef())
lib/Target/Hexagon/HexagonHazardRecognizer.cpp 116 if (MO.isReg() && MO.isDef() && !MO.isImplicit())
lib/Target/Hexagon/HexagonInstrInfo.cpp 203 if (MO.isDef())
1583 if (!Op.isReg() || !Op.isDef() || Op.isImplicit())
1624 if (!MO.isDef())
2969 if (Op.isReg() && Op.isDef() && Op.getReg() == Stored.getReg())
3101 if (MO.isReg() && MO.isDef() && MO.isImplicit() && (MO.getReg() == PredReg))
4312 for (; MI.getOperand(NumDefs).isReg() && MI.getOperand(NumDefs).isDef();
lib/Target/Hexagon/HexagonNewValueJump.cpp 151 if (!Op.isReg() || !Op.isDef())
177 (II->getOperand(i).isUse() || II->getOperand(i).isDef())) {
601 if (MI.getOperand(0).isReg() && MI.getOperand(0).isDef() &&
lib/Target/Hexagon/HexagonSplitDouble.cpp 621 auto CO = MachineOperand::CreateReg(R, Op.isDef(), Op.isImplicit(), isKill,
lib/Target/Hexagon/HexagonSubtarget.cpp 246 } else if (MO.isDef() && Register::isPhysicalRegister(MO.getReg())) {
427 if (MO.isReg() && MO.isDef() && MO.getReg() == DepR)
lib/Target/Hexagon/HexagonVLIWPacketizer.cpp 150 if (!MO.isReg() || !MO.isDef())
577 if (MO.isReg() && MO.isDef())
790 if (!MO.isReg() || !MO.isDef() || !MO.isImplicit())
835 if (CheckDef == MO.isDef())
1204 if (!MO.isReg() || !MO.isDef() || !MO.isDead())
1210 if (!MO.isReg() || !MO.isDef() || !MO.isDead())
1588 if (Op.isReg() && Op.isDef()) {
lib/Target/Hexagon/HexagonVectorPrint.cpp 110 if (MI.getOperand(0).isReg() && MI.getOperand(0).isDef()) {
lib/Target/Hexagon/RDFGraph.cpp 611 if (Op.isDef() && Op.isDead())
637 const MCPhysReg *ImpR = Op.isDef() ? D.getImplicitDefs()
1292 if (!Op.isReg() || !Op.isDef() || Op.isImplicit())
1337 if (!Op.isReg() || !Op.isDef() || !Op.isImplicit())
lib/Target/Hexagon/RDFLiveness.cpp 890 if (!Op.isReg() || !Op.isDef() || Op.isImplicit())
lib/Target/Lanai/LanaiDelaySlotFiller.cpp 210 if (MO.isDef()) {
239 if (MO.isDef())
lib/Target/Lanai/LanaiInstrInfo.cpp 366 if (MO.isDef()) {
483 if (MO.isDef() && !MO.isDead())
lib/Target/Mips/Mips16InstrInfo.cpp 360 if (MO.isReg() && MO.getReg() != 0 && !MO.isDef() &&
376 if (MO.isReg() && MO.isDef()) {
lib/Target/Mips/MipsDelaySlotFiller.cpp 331 if (!MO.isReg() || !MO.isDef() || !(R = MO.getReg()))
421 HasHazard |= checkRegDefsUses(NewDefs, NewUses, MO.getReg(), MO.isDef());
lib/Target/PowerPC/PPCCTRLoops.cpp 117 if (MO.isDef() && (MO.getReg() == PPC::CTR || MO.getReg() == PPC::CTR8))
lib/Target/PowerPC/PPCInstrInfo.cpp 162 if (!MO.isReg() || !MO.isDef() || MO.isImplicit())
1572 if (MO.isDef() && RC->contains(MO.getReg())) {
lib/Target/PowerPC/PPCPreEmitPeephole.cpp 141 if (DeadOrKillToUnset->isDef())
lib/Target/Sparc/DelaySlotFiller.cpp 258 if (MO.isDef()) {
330 if (MO.isDef())
lib/Target/SystemZ/SystemZElimCompare.cpp 140 MI.getOperand(0).isDef() && MI.getOperand(0).getReg() == Reg)
159 else if (MO.isDef())
lib/Target/WebAssembly/WebAssemblyExplicitLocals.cpp 318 if (MO.isDef()) {
lib/Target/WebAssembly/WebAssemblyRegColoring.cpp 70 Weight += LiveIntervals::getSpillWeight(MO.isDef(), MO.isUse(), MBFI,
lib/Target/WebAssembly/WebAssemblyRegStackify.cpp 359 if (!MO.isDef() && !MRI.hasOneDef(Reg))
392 if (MO.isReg() && MO.isDef() && MO.getReg() == Reg)
921 if (MO.isDef())
lib/Target/WebAssembly/WebAssemblyUtilities.cpp 33 if (!MO.isReg() || MO.isImplicit() || !MO.isDef())
lib/Target/X86/X86CallFrameOptimization.cpp 343 if (MO.isDef()) {
lib/Target/X86/X86CmovConversion.cpp 457 if (!MO.isReg() || !MO.isDef())
lib/Target/X86/X86DomainReassignment.cpp 145 if (MO.isReg() && MO.isDef() && !MO.isDead() &&
lib/Target/X86/X86FastISel.cpp 3957 if (!MO.isReg() || MO.isDef() || MO.getReg() != AM.IndexReg)
lib/Target/X86/X86FixupBWInsts.cpp 253 assert((MO.isDef() || MO.isUse()) && "Expected Def or Use only!");
255 if (MO.isDef() && TRI->isSuperRegisterEq(OrigDestReg, MO.getReg()))
329 if (Op.getReg() != (Op.isDef() ? NewDestReg : NewSrcReg))
lib/Target/X86/X86FixupLEAs.cpp 246 if (opnd.isDef())
lib/Target/X86/X86FixupSetCC.cpp 81 if (Op.isReg() && (Op.getReg() == X86::EFLAGS) && Op.isDef())
lib/Target/X86/X86FlagsCopyLowering.cpp 403 assert(DOp.isDef() && "Expected register def!");
727 assert(MI.getOperand(0).isDef() &&
lib/Target/X86/X86FloatingPoint.cpp 985 assert(MO.isDef() && MO.isImplicit());
1707 if (MO.isDef()) {
lib/Target/X86/X86FrameLowering.cpp 177 if (!MO.isReg() || MO.isDef())
226 if (!MO.isDef())
2763 if (MO.isReg() && MO.isDef() &&
lib/Target/X86/X86InstrInfo.cpp 675 if (MO.isReg() && MO.isDef() &&
3854 if (MO.getSubReg() || MO.isDef())
5019 if (SubReg && (MO.isDef() || SubReg == X86::sub_8bit_hi))
5540 getDefRegState(ImpOp.isDef()) |