|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
include/llvm/CodeGen/MachineBasicBlock.h 614 assert((I == end() || I->getParent() == this) &&
621 assert((I == end() || I->getParent() == this) &&
630 assert((I == end() || I->getParent() == this) &&
930 assert(I == BB->end() || I->getParent() == BB);
948 while (It != End && It->isDebugInstr())
959 while (It != Begin && It->isDebugInstr())
lib/CodeGen/Analysis.cpp 756 if (MBBI == MBB.end() || MBBI->getOpcode() != TII->getCatchReturnOpcode())
761 const MachineBasicBlock *Successor = MBBI->getOperand(0).getMBB();
762 const MachineBasicBlock *SuccessorColor = MBBI->getOperand(1).getMBB();
lib/CodeGen/AsmPrinter/DwarfDebug.cpp 1319 if (Pred->getFlag(MachineInstr::FrameSetup))
1321 auto PredDL = Pred->getDebugLoc();
1322 if (!PredDL || Pred->isMetaInstruction())
lib/CodeGen/BranchFolding.cpp 348 if (!I1->isIdenticalTo(*I2) ||
354 I1->isInlineAsm()) {
366 while (I2->isDebugInstr()) {
375 while (I1->isDebugInstr()) {
405 while (I1 != MBB1->end() && I1->isCFIInstruction()) {
409 while (I2 != MBB2->end() && I2->isCFIInstruction()) {
420 MachineBasicBlock &OldMBB = *OldInst->getParent();
501 if (I->isCall())
503 else if (I->mayLoad() || I->mayStore())
503 else if (I->mayLoad() || I->mayStore())
604 if (!I->isTerminator()) break;
842 MachineBasicBlock *MBB = MBBIStartPos->getParent();
869 assert(MBBICommon->isIdenticalTo(*MBBI) && "Expected matching MIIs!");
872 if (MBBICommon->mayLoad() || MBBICommon->mayStore())
872 if (MBBICommon->mayLoad() || MBBICommon->mayStore())
873 MBBICommon->cloneMergedMemRefs(*MBB->getParent(), {&*MBBICommon, &*MBBI});
875 for (unsigned I = 0, E = MBBICommon->getNumOperands(); I != E; ++I) {
876 MachineOperand &MO = MBBICommon->getOperand(I);
878 const MachineOperand &OtherMO = MBBI->getOperand(I);
920 DL = DILocation::getMergedLocation(DL, Pos->getDebugLoc());
1306 return I->isBranch();
1331 return MBB2I->isCall() && !MBB1I->isCall();
1331 return MBB2I->isCall() && !MBB1I->isCall();
1338 if (I != MBB.end() && I->isBranch())
1339 return I->getDebugLoc();
1488 && PrevBBIter->isDebugInstr() && MBBIter->isDebugInstr()) {
1488 && PrevBBIter->isDebugInstr() && MBBIter->isDebugInstr()) {
1489 if (!MBBIter->isIdenticalTo(*PrevBBIter))
1879 for (const MachineOperand &MO : Loc->operands()) {
1914 for (const MachineOperand &MO : PI->operands()) {
1940 if (!PI->isSafeToMove(nullptr, DontMoveAcrossStore) || TII->isPredicated(*PI))
1945 for (const MachineOperand &MO : PI->operands()) {
2005 if (!TIB->isIdenticalTo(*FIB, MachineInstr::CheckKillDead))
2013 for (MachineOperand &MO : TIB->operands()) {
2064 if (!TIB->isSafeToMove(nullptr, DontMoveAcrossStore))
2068 for (const MachineOperand &MO : TIB->operands()) {
2086 for (const MachineOperand &MO : TIB->operands()) {
lib/CodeGen/BranchRelaxation.cpp 496 if (Last->isUnconditionalBranch()) {
518 if (Next != MBB.end() && Next->isConditionalBranch()) {
lib/CodeGen/EarlyIfConversion.cpp 213 if (I->isDebugInstr())
223 if (I->isPHI()) {
231 if (I->mayLoad()) {
238 if (!I->isSafeToMove(nullptr, DontMoveAcrossStore)) {
308 if (I->isDebugInstr())
318 if (I->isPHI()) {
345 if (I->isDebugInstr())
378 for (const MachineOperand &MO : I->operands()) {
401 if (I != FirstTerm && I->isTerminator())
508 I != E && I->isPHI(); ++I) {
563 DebugLoc HeadDL = FirstTerm->getDebugLoc();
583 DebugLoc HeadDL = FirstTerm->getDebugLoc();
661 DebugLoc HeadDL = Head->getFirstTerminator()->getDebugLoc();
lib/CodeGen/ExpandPostRAPseudos.cpp 72 CopyMI->addOperand(MO);
125 CopyMI->addRegisterDefined(DstReg);
lib/CodeGen/GCRootLowering.cpp 270 MCSymbol *Label = InsertLabel(*CI->getParent(), RAI, CI->getDebugLoc());
270 MCSymbol *Label = InsertLabel(*CI->getParent(), RAI, CI->getDebugLoc());
271 FI->addSafePoint(Label, CI->getDebugLoc());
278 if (MI->isCall()) {
283 if (MI->isTerminator())
lib/CodeGen/GlobalISel/CSEMIRBuilder.cpp 24 assert(A->getParent() == B->getParent() &&
24 assert(A->getParent() == B->getParent() &&
26 const MachineBasicBlock *BBA = A->getParent();
lib/CodeGen/GlobalISel/RegBankSelect.cpp 704 MachineBasicBlock *NextInstBB = MII->getParent();
763 for (auto Begin = Pred.begin(); It != Begin && It->isTerminator(); --It)
764 if (It->modifiesRegister(Reg, &TRI)) {
788 for (; It != REnd && It->isTerminator(); ++It) {
789 assert(!It->modifiesRegister(MO.getReg(), &TRI) &&
807 assert(It->modifiesRegister(MO.getReg(), &TRI) &&
lib/CodeGen/IfConversion.cpp 747 if (!TIB->isIdenticalTo(*FIB))
755 if (!TIB->isBranch())
775 while (RTIE != RTIB && RTIE->isUnconditionalBranch())
777 while (RFIE != RFIB && RFIE->isUnconditionalBranch())
790 if (!RTIE->isIdenticalTo(*RFIE))
794 if (!RTIE->isBranch())
845 assert(!E2->isBranch() && "Branch mis-match, one block is empty.");
849 assert(!E1->isBranch() && "Branch mis-match, one block is empty.");
853 if (E1->isBranch() || E2->isBranch())
853 if (E1->isBranch() || E2->isBranch())
854 assert(E1->isIdenticalTo(*E2) &&
1841 if (!DI1->isDebugInstr())
1847 if (DI2->isCall(MachineInstr::IgnoreBundle))
1853 if (!DI2->isDebugInstr())
1883 if (!Prev->isBranch() && !Prev->isDebugInstr())
1883 if (!Prev->isBranch() && !Prev->isDebugInstr())
1896 if (DI1->isCall(MachineInstr::IgnoreBundle))
1900 if (!DI1->isDebugInstr())
1915 if (!Prev->isBranch() && !Prev->isDebugInstr())
1915 if (!Prev->isBranch() && !Prev->isDebugInstr())
1926 if (!DI2->isDebugInstr())
2013 dl = TIE->getDebugLoc();
lib/CodeGen/ImplicitNullChecks.cpp 525 if (I->modifiesRegister(PointerReg, TRI))
lib/CodeGen/InlineSpiller.cpp 772 MachineOperand *MO = I->findRegisterDefOperand(VReg);
906 MachineBasicBlock &MBB = *MI->getParent();
936 MachineBasicBlock &MBB = *MI->getParent();
945 BuildMI(MBB, std::next(MI), MI->getDebugLoc(), TII.get(TargetOpcode::KILL))
lib/CodeGen/LiveDebugVariables.cpp 690 if (!MBBI->isDebugInstr()) {
704 if ((MBBI->isDebugValue() && handleDebugValue(*MBBI, Idx)) ||
705 (MBBI->isDebugLabel() && handleDebugLabel(*MBBI, Idx))) {
710 } while (MBBI != MBBE && MBBI->isDebugInstr());
974 if (!MBBI->isDebugValue()) {
1272 while (I != MBB->end() && !I->isTerminator()) {
1276 if (I->definesRegister(Reg, &TRI))
lib/CodeGen/LiveIntervals.cpp 1436 if ((--MII)->isDebugInstr())
lib/CodeGen/LiveRangeShrink.cpp 103 for (MachineInstr &I : make_range(Start, Start->getParent()->end()))
220 while (I != MBB.end() && (I->isPHI() || I->isDebugInstr()))
220 while (I != MBB.end() && (I->isPHI() || I->isDebugInstr()))
235 for (; EndIter != MBB.end() && EndIter->isDebugValue() &&
236 EndIter->getOperand(0).isReg() &&
237 EndIter->getOperand(0).getReg() == MI.getOperand(0).getReg();
lib/CodeGen/LiveVariables.cpp 771 for (; BBI != BBE && BBI->isPHI(); ++BBI) {
773 Defs.insert(BBI->getOperand(0).getReg());
776 for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2)
777 if (BBI->getOperand(i+1).getMBB() == BB)
778 getVarInfo(BBI->getOperand(i).getReg()).AliveBlocks.set(NumNew);
783 for (MachineInstr::mop_iterator I = BBI->operands_begin(),
784 E = BBI->operands_end(); I != E; ++I) {
lib/CodeGen/MIRCanonicalizerPass.cpp 129 getPos()->dump();
269 DefI->dump();
271 UseI->dump();
lib/CodeGen/MIRPrinter.cpp 567 IsFallthrough = I == MBB.end() || !I->isBarrier();
lib/CodeGen/MachineBasicBlock.cpp 174 while (I != E && (I->isPHI() || I->isPosition() ||
174 while (I != E && (I->isPHI() || I->isPosition() ||
179 assert((I == E || !I->isInsideBundle()) &&
189 while (I != E && (I->isPHI() || I->isPosition() || I->isDebugInstr() ||
189 while (I != E && (I->isPHI() || I->isPosition() || I->isDebugInstr() ||
189 while (I != E && (I->isPHI() || I->isPosition() || I->isDebugInstr() ||
194 assert((I == E || !I->isInsideBundle()) &&
202 while (I != B && ((--I)->isTerminator() || I->isDebugInstr()))
202 while (I != B && ((--I)->isTerminator() || I->isDebugInstr()))
204 while (I != E && !I->isTerminator())
507 for (;I != E && I->isCopy(); ++I)
508 if (I->getOperand(1).getReg() == PhysReg) {
509 Register VirtReg = I->getOperand(0).getReg();
1315 while (TI != end() && !TI->isBranch())
1319 DL = TI->getDebugLoc();
1321 if (TI->isBranch())
1322 DL = DILocation::getMergedLocation(DL, TI->getDebugLoc());
1393 if (I->isDebugInstr())
1432 if (I->isDebugInstr())
lib/CodeGen/MachineCSE.cpp 234 for (const MachineOperand &MO : I->operands()) {
358 while (I != E && I != EE && I->isDebugInstr())
374 for (const MachineOperand &MO : I->operands()) {
675 if (MachineOperand *MO = II->findRegisterUseOperand(
lib/CodeGen/MachineInstr.cpp 2113 if (!DI->isDebugValue())
2115 if (DI->getOperand(0).isReg() &&
2116 DI->getOperand(0).getReg() == MI.getOperand(0).getReg())
lib/CodeGen/MachineLICM.cpp 525 for (const MachineOperand &MO : TI->operands()) {
lib/CodeGen/MachineLoopUtils.cpp 75 for (MachineOperand &MO : I->uses())
79 for (auto I = NewBB->begin(); I->isPHI(); ++I) {
lib/CodeGen/MachineOutliner.cpp 959 C.front()->getDebugLoc(), C.getMBB());
972 CandidatesForRepeatedSeq[i].front()->getDebugLoc());
997 OF.Candidates[i].front()->getDebugLoc());
1053 MachineBasicBlock *MBB = StartIt->getParent();
1254 CallInst->addOperand(MachineOperand::CreateReg(
lib/CodeGen/MachineSSAUpdater.cpp 89 if (!I->isPHI())
95 while (I != BB->end() && I->isPHI()) {
97 for (unsigned i = 1, e = I->getNumOperands(); i != e; i += 2) {
98 Register SrcReg = I->getOperand(i).getReg();
99 MachineBasicBlock *SrcBB = I->getOperand(i+1).getMBB();
106 return I->getOperand(0).getReg();
lib/CodeGen/MachineScheduler.cpp 281 if (!I->isDebugInstr())
301 if (!I->isDebugInstr())
443 return MI->isCall() || TII->isSchedulingBoundary(*MI, MBB, *MF);
813 << printMBBReference(*begin()->getParent()) << " ***\n";
1042 (RegionEnd->isDebugInstr() &&
1249 << printMBBReference(*begin()->getParent()) << " ***\n";
2748 const MachineFunction &MF = *Begin->getMF();
lib/CodeGen/MachineSink.cpp 773 InsertPos->getDebugLoc()));
947 while (InsertPos != SuccToSinkTo->end() && InsertPos->isPHI())
lib/CodeGen/MachineTraceMetrics.cpp 831 updateDepth(Start->getParent(), *Start, RegUnits);
lib/CodeGen/ModuloSchedule.cpp 217 if (BBI->isPHI())
385 Register Def = BBI->getOperand(0).getReg();
623 for (unsigned i = 0, e = BBI->getNumOperands(); i != e; ++i) {
624 MachineOperand &MO = BBI->getOperand(i);
1312 (I++)->eraseFromParent();
1333 if (MI->isPHI()) {
1334 Register R = MI->getOperand(0).getReg();
1339 for (MachineOperand &Def : MI->defs()) {
1575 for (auto I = BB->begin(), NI = NewBB->begin(); !I->isTerminator();
1657 I != std::next(B->getFirstNonPHI()->getReverseIterator());) {
1862 if (NI->isPHI())
1871 for (; !OI->isTerminator() && !NI->isTerminator(); ++OI, ++NI) {
1871 for (; !OI->isTerminator() && !NI->isTerminator(); ++OI, ++NI) {
1872 while (OI->isPHI() || OI->isFullCopy())
1872 while (OI->isPHI() || OI->isFullCopy())
1874 while (NI->isPHI() || NI->isFullCopy())
1874 while (NI->isPHI() || NI->isFullCopy())
1876 assert(OI->getOpcode() == NI->getOpcode() && "Opcodes don't match?!");
1876 assert(OI->getOpcode() == NI->getOpcode() && "Opcodes don't match?!");
1878 for (auto OOpI = OI->operands_begin(), NOpI = NI->operands_begin();
1878 for (auto OOpI = OI->operands_begin(), NOpI = NI->operands_begin();
1879 OOpI != OI->operands_end(); ++OOpI, ++NOpI)
lib/CodeGen/PHIElimination.cpp 446 if (Term->readsRegister(SrcReg))
458 if (KillInst->isDebugInstr())
460 if (KillInst->readsRegister(SrcReg))
468 assert(KillInst->readsRegister(SrcReg) && "Cannot find kill instruction");
506 if (Term->readsRegister(SrcReg))
518 if (KillInst->isDebugInstr())
520 if (KillInst->readsRegister(SrcReg))
528 assert(KillInst->readsRegister(SrcReg) &&
573 BBI != BBE && BBI->isPHI(); ++BBI) {
574 for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2) {
575 Register Reg = BBI->getOperand(i).getReg();
576 MachineBasicBlock *PreMBB = BBI->getOperand(i+1).getMBB();
lib/CodeGen/PatchableFunction.cpp 72 auto MIB = BuildMI(FirstMBB, FirstActualI, FirstActualI->getDebugLoc(),
75 .addImm(FirstActualI->getOpcode());
77 for (auto &MO : FirstActualI->operands())
80 FirstActualI->eraseFromParent();
lib/CodeGen/PrologEpilogInserter.cpp 322 } else if (I->isInlineAsm()) {
324 unsigned ExtraInfo = I->getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
344 TFI->eliminateCallFramePseudoInstr(MF, *I->getParent(), I);
lib/CodeGen/RegisterCoalescer.cpp 3585 if (!MII->isCopyLike())
lib/CodeGen/RegisterPressure.cpp 765 assert(!CurrPos->isDebugInstr());
864 if (RequireIntervals && !CurrPos->isDebugInstr())
874 if (CurrPos->isDebugValue()) {
lib/CodeGen/RegisterScavenging.cpp 320 if (MI->isDebugInstr()) {
327 for (const MachineOperand &MO : MI->operands()) {
385 MachineBasicBlock &MBB = *From->getParent();
465 const MachineFunction &MF = *Before->getMF();
583 const MachineBasicBlock &MBB = *To->getParent();
708 N->addRegisterKilled(SReg, &TRI, false);
734 I->addRegisterDead(SReg, &TRI, false);
lib/CodeGen/SelectionDAG/FastISel.cpp 533 FuncInfo.MBB = FuncInfo.InsertPt->getParent();
540 FuncInfo.InsertPt->getOpcode() == TargetOpcode::EH_LABEL)
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp 555 if (Term != MBB.end() && Term->isReturn()) {
1936 MBBI != MBBE && MBBI->isPHI(); ++MBBI) {
lib/CodeGen/SplitKit.cpp 104 if (I->isCall()) {
862 while (!AtBegin && (--MBBI)->isDebugInstr());
878 if (AtBegin || !MBBI->readsVirtualRegister(Edit->getReg())) {
lib/CodeGen/StackMapLivenessAnalysis.cpp 134 if (I->getOpcode() == TargetOpcode::PATCHPOINT) {
lib/CodeGen/StackSlotColoring.cpp 452 while ((NextMI != E) && NextMI->isDebugInstr()) {
466 if (NextMI->findRegisterUseOperandIdx(LoadReg, true, nullptr) != -1) {
lib/CodeGen/TailDuplicator.cpp 102 if (!MI->isPHI())
106 for (unsigned i = 1, e = MI->getNumOperands(); i != e; i += 2) {
107 MachineBasicBlock *PHIBB = MI->getOperand(i + 1).getMBB();
122 for (unsigned i = 1, e = MI->getNumOperands(); i != e; i += 2) {
123 MachineBasicBlock *PHIBB = MI->getOperand(i + 1).getMBB();
670 return I->isUnconditionalBranch();
676 if (SuccsB.count(BB) && !BB->empty() && BB->begin()->isPHI())
901 while (I != TailBB->end() && I->isPHI()) {
964 while (I != TailBB->end() && I->isPHI()) {
lib/CodeGen/TargetInstrInfo.cpp 132 MachineBasicBlock *MBB = Tail->getParent();
139 DebugLoc DL = Tail->getDebugLoc();
145 if (MI->isCall())
lib/CodeGen/TwoAddressInstructionPass.cpp 932 if (End->isCopy() && regOverlapsSet(Defs, End->getOperand(1).getReg(), TRI))
932 if (End->isCopy() && regOverlapsSet(Defs, End->getOperand(1).getReg(), TRI))
933 Defs.push_back(End->getOperand(0).getReg());
989 while (Begin != MBB->begin() && std::prev(Begin)->isDebugInstr())
1165 while (InsertPos != MBB->begin() && std::prev(InsertPos)->isDebugInstr())
1169 while (std::prev(From)->isDebugInstr())
1708 if (mi->isDebugInstr() || SunkInstrs.count(&*mi)) {
1715 if (mi->isRegSequence())
1742 Register SrcReg = mi->getOperand(SrcIdx).getReg();
1743 Register DstReg = mi->getOperand(DstIdx).getReg();
1762 if (mi->isInsertSubreg()) {
1765 unsigned SubIdx = mi->getOperand(3).getImm();
1766 mi->RemoveOperand(3);
1767 assert(mi->getOperand(0).getSubReg() == 0 && "Unexpected subreg idx");
1768 mi->getOperand(0).setSubReg(SubIdx);
1769 mi->getOperand(0).setIsUndef(mi->getOperand(1).isUndef());
1769 mi->getOperand(0).setIsUndef(mi->getOperand(1).isUndef());
1770 mi->RemoveOperand(1);
1771 mi->setDesc(TII->get(TargetOpcode::COPY));
lib/CodeGen/UnreachableBlockElim.cpp 133 while (start != succ->end() && start->isPHI()) {
134 for (unsigned i = start->getNumOperands() - 1; i >= 2; i-=2)
135 if (start->getOperand(i).isMBB() &&
136 start->getOperand(i).getMBB() == BB) {
137 start->RemoveOperand(i);
138 start->RemoveOperand(i-1);
166 while (phi != BB->end() && phi->isPHI()) {
167 for (unsigned i = phi->getNumOperands() - 1; i >= 2; i-=2)
168 if (!preds.count(phi->getOperand(i).getMBB())) {
169 phi->RemoveOperand(i);
170 phi->RemoveOperand(i-1);
174 if (phi->getNumOperands() == 3) {
175 const MachineOperand &Input = phi->getOperand(1);
176 const MachineOperand &Output = phi->getOperand(0);
195 BuildMI(*BB, BB->getFirstNonPHI(), phi->getDebugLoc(),
199 phi++->eraseFromParent();
lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp 518 unsigned RegClassID = ChainBegin->getDesc().OpInfo[0].RegClass;
lib/Target/AArch64/AArch64AsmPrinter.cpp 805 if (MII == MBB.end() || MII->isCall() ||
806 MII->getOpcode() == AArch64::DBG_VALUE ||
807 MII->getOpcode() == TargetOpcode::PATCHPOINT ||
808 MII->getOpcode() == TargetOpcode::STACKMAP)
lib/Target/AArch64/AArch64BranchTargets.cpp 122 if (MBBI != MBB.end() && (MBBI->getOpcode() == AArch64::PACIASP ||
123 MBBI->getOpcode() == AArch64::PACIBSP))
lib/Target/AArch64/AArch64CleanupLocalDynamicTLSPass.cpp 69 switch (I->getOpcode()) {
72 if (!I->getOperand(0).isSymbol() ||
73 strcmp(I->getOperand(0).getSymbolName(), "_TLS_MODULE_BASE_"))
lib/Target/AArch64/AArch64CondBrTuning.cpp 199 if (I->modifiesRegister(AArch64::NZCV, TRI) ||
200 I->readsRegister(AArch64::NZCV, TRI))
258 if (I->modifiesRegister(AArch64::NZCV, TRI) ||
259 I->readsRegister(AArch64::NZCV, TRI))
lib/Target/AArch64/AArch64ConditionOptimizer.cpp 151 if (I->getOpcode() != AArch64::Bcc)
162 assert(!I->isTerminator() && "Spurious terminator");
164 if (I->readsRegister(AArch64::NZCV))
166 switch (I->getOpcode()) {
173 unsigned ShiftAmt = AArch64_AM::getShiftValue(I->getOperand(3).getImm());
174 if (!I->getOperand(2).isImm()) {
177 } else if (I->getOperand(2).getImm() << ShiftAmt >= 0xfff) {
181 } else if (!MRI->use_empty(I->getOperand(0).getReg())) {
lib/Target/AArch64/AArch64ConditionalCompares.cpp 303 if (!I->readsRegister(AArch64::NZCV)) {
304 switch (I->getOpcode()) {
320 assert(!I->isTerminator() && "Spurious terminator");
321 switch (I->getOpcode()) {
330 if (I->getOperand(3).getImm() || !isUInt<5>(I->getOperand(2).getImm())) {
330 if (I->getOperand(3).getImm() || !isUInt<5>(I->getOperand(2).getImm())) {
340 if (isDeadDef(I->getOperand(0).getReg()))
612 DebugLoc TermDL = Head->getFirstTerminator()->getDebugLoc();
lib/Target/AArch64/AArch64FastISel.cpp 2053 ResultReg = std::prev(I)->getOperand(0).getReg();
lib/Target/AArch64/AArch64FrameLowering.cpp 278 DebugLoc DL = I->getDebugLoc();
279 unsigned Opc = I->getOpcode();
281 uint64_t CalleePopAmount = IsDestroy ? I->getOperand(1).getImm() : 0;
286 int64_t Amount = I->getOperand(0).getImm();
486 unsigned Opc = MBBI->getOpcode();
487 MachineBasicBlock *MBB = MBBI->getParent();
489 DebugLoc DL = MBBI->getDebugLoc();
490 unsigned ImmIdx = MBBI->getNumOperands() - 1;
491 int Imm = MBBI->getOperand(ImmIdx).getImm();
503 unsigned Reg0 = RegInfo->getSEHRegNum(MBBI->getOperand(1).getReg());
504 unsigned Reg1 = RegInfo->getSEHRegNum(MBBI->getOperand(2).getReg());
516 Register Reg0 = MBBI->getOperand(1).getReg();
517 Register Reg1 = MBBI->getOperand(2).getReg();
534 unsigned Reg = RegInfo->getSEHRegNum(MBBI->getOperand(1).getReg());
545 unsigned Reg = RegInfo->getSEHRegNum(MBBI->getOperand(1).getReg());
554 unsigned Reg0 = RegInfo->getSEHRegNum(MBBI->getOperand(0).getReg());
555 unsigned Reg1 = RegInfo->getSEHRegNum(MBBI->getOperand(1).getReg());
565 Register Reg0 = MBBI->getOperand(0).getReg();
566 Register Reg1 = MBBI->getOperand(1).getReg();
581 int Reg = RegInfo->getSEHRegNum(MBBI->getOperand(0).getReg());
590 unsigned Reg = RegInfo->getSEHRegNum(MBBI->getOperand(0).getReg());
606 unsigned ImmIdx = MBBI->getNumOperands() - 1;
607 switch (MBBI->getOpcode()) {
615 ImmOpnd = &MBBI->getOperand(ImmIdx);
631 while (MBBI->getOpcode() == AArch64::STRXpost ||
632 MBBI->getOpcode() == AArch64::LDRXpre ||
633 MBBI->getOpcode() == AArch64::CFI_INSTRUCTION) {
634 if (MBBI->getOpcode() != AArch64::CFI_INSTRUCTION)
635 assert(MBBI->getOperand(0).getReg() != AArch64::SP);
640 switch (MBBI->getOpcode()) {
690 SEH->eraseFromParent();
698 for (unsigned OpndEnd = MBBI->getNumOperands() - 1; OpndIdx < OpndEnd;
700 MIB.add(MBBI->getOperand(OpndIdx));
702 assert(MBBI->getOperand(OpndIdx).getImm() == 0 &&
705 assert(MBBI->getOperand(OpndIdx - 1).getReg() == AArch64::SP &&
710 MIB.setMIFlags(MBBI->getFlags());
711 MIB.setMemRefs(MBBI->memoperands());
968 while (MBBI != End && MBBI->getFlag(MachineInstr::FrameSetup)) {
1291 DL = MBBI->getDebugLoc();
1298 MBBI->getOpcode() == AArch64::RET_ReallyLR) {
1338 DL = MBBI->getDebugLoc();
1339 unsigned RetOpcode = MBBI->getOpcode();
1359 MachineOperand &StackAdjust = MBBI->getOperand(1);
1426 const MachineOperand &OffsetOp = Pop->getOperand(Pop->getNumOperands() - 1);
1426 const MachineOperand &OffsetOp = Pop->getOperand(Pop->getNumOperands() - 1);
1447 if (!LastPopI->getFlag(MachineInstr::FrameDestroy)) {
1546 if (Prev->getOpcode() != AArch64::LDRXpre ||
1547 Prev->getOperand(0).getReg() == AArch64::SP)
2083 DL = MI->getDebugLoc();
2364 while (MBBI != MBB.end() && MBBI->getFlag(MachineInstr::FrameSetup))
lib/Target/AArch64/AArch64InstrInfo.cpp 278 I->eraseFromParent();
287 I->eraseFromParent();
342 if (!isUncondBranchOpcode(I->getOpcode()) &&
343 !isCondBranchOpcode(I->getOpcode()))
347 I->eraseFromParent();
357 if (!isCondBranchOpcode(I->getOpcode())) {
364 I->eraseFromParent();
1144 if (To == To->getParent()->begin())
1149 if (To->getParent() != From->getParent())
1149 if (To->getParent() != From->getParent())
1153 assert(std::find_if(++To.getReverse(), To->getParent()->rend(),
1156 }) != To->getParent()->rend());
1485 while (FirstEpilogSEH->getFlag(MachineInstr::FrameDestroy) &&
5100 unsigned LastInstrOpcode = RepeatedSequenceLocs[0].back()->getOpcode();
5172 if (RepeatedSequenceLocs[0].back()->isTerminator()) {
5260 FrameID != MachineOutlinerTailCall && FirstCand.back()->isCall())
lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp 732 unsigned Opc = I->getOpcode();
761 DebugLoc DL = I->getDebugLoc();
762 MachineBasicBlock *MBB = I->getParent();
769 .setMIFlags(I->mergeFlagsWith(*MergeMI));
773 LLVM_DEBUG(I->print(dbgs()));
775 LLVM_DEBUG(MergeMI->print(dbgs()));
781 I->eraseFromParent();
782 MergeMI->eraseFromParent();
801 SExtIdx == -1 ? I->getOpcode() : getMatchingNonSExtOpcode(I->getOpcode());
801 SExtIdx == -1 ? I->getOpcode() : getMatchingNonSExtOpcode(I->getOpcode());
816 bool PairedIsUnscaled = TII->isUnscaledLdSt(Paired->getOpcode());
857 DebugLoc DL = I->getDebugLoc();
858 MachineBasicBlock *MBB = I->getParent();
886 .setMIFlags(I->mergeFlagsWith(*Paired));
892 LLVM_DEBUG(I->print(dbgs()));
894 LLVM_DEBUG(Paired->print(dbgs()));
935 I->eraseFromParent();
936 Paired->eraseFromParent();
963 for (MachineInstr &MI : make_range(StoreI->getIterator(),
964 LoadI->getIterator())) {
971 LLVM_DEBUG(LoadI->print(dbgs()));
973 LoadI->eraseFromParent();
978 BuildMI(*LoadI->getParent(), LoadI, LoadI->getDebugLoc(),
978 BuildMI(*LoadI->getParent(), LoadI, LoadI->getDebugLoc(),
983 .setMIFlags(LoadI->getFlags());
1018 BuildMI(*LoadI->getParent(), LoadI, LoadI->getDebugLoc(),
1018 BuildMI(*LoadI->getParent(), LoadI, LoadI->getDebugLoc(),
1023 .setMIFlags(LoadI->getFlags());
1026 BuildMI(*LoadI->getParent(), LoadI, LoadI->getDebugLoc(),
1026 BuildMI(*LoadI->getParent(), LoadI, LoadI->getDebugLoc(),
1032 .setMIFlags(LoadI->getFlags());
1037 for (MachineInstr &MI : make_range(StoreI->getIterator(),
1045 LLVM_DEBUG(StoreI->print(dbgs()));
1047 LLVM_DEBUG(LoadI->print(dbgs()));
1049 LLVM_DEBUG(StoreI->print(dbgs()));
1055 LoadI->eraseFromParent();
1106 MachineBasicBlock::iterator B = I->getParent()->begin();
1216 MachineBasicBlock::iterator E = I->getParent()->end();
1376 assert((Update->getOpcode() == AArch64::ADDXri ||
1377 Update->getOpcode() == AArch64::SUBXri) &&
1386 int Value = Update->getOperand(2).getImm();
1387 assert(AArch64_AM::getShiftValue(Update->getOperand(3).getImm()) == 0 &&
1389 if (Update->getOpcode() == AArch64::SUBXri)
1392 unsigned NewOpc = IsPreIdx ? getPreIndexedOpcode(I->getOpcode())
1393 : getPostIndexedOpcode(I->getOpcode());
1399 MIB = BuildMI(*I->getParent(), I, I->getDebugLoc(), TII->get(NewOpc))
1399 MIB = BuildMI(*I->getParent(), I, I->getDebugLoc(), TII->get(NewOpc))
1404 .setMemRefs(I->memoperands())
1405 .setMIFlags(I->mergeFlagsWith(*Update));
1408 MIB = BuildMI(*I->getParent(), I, I->getDebugLoc(), TII->get(NewOpc))
1408 MIB = BuildMI(*I->getParent(), I, I->getDebugLoc(), TII->get(NewOpc))
1414 .setMemRefs(I->memoperands())
1415 .setMIFlags(I->mergeFlagsWith(*Update));
1427 LLVM_DEBUG(I->print(dbgs()));
1429 LLVM_DEBUG(Update->print(dbgs()));
1435 I->eraseFromParent();
1436 Update->eraseFromParent();
1490 MachineBasicBlock::iterator E = I->getParent()->end();
1549 MachineBasicBlock::iterator B = I->getParent()->begin();
1550 MachineBasicBlock::iterator E = I->getParent()->end();
lib/Target/AArch64/AArch64RedundantCopyElimination.cpp 323 if (PredI->isCopy()) {
324 MCPhysReg CopyDstReg = PredI->getOperand(0).getReg();
325 MCPhysReg CopySrcReg = PredI->getOperand(1).getReg();
364 } while (Itr != PredMBB->begin() && Itr->isTerminator());
lib/Target/AArch64/AArch64RegisterInfo.cpp 412 DL = Ins->getDebugLoc();
lib/Target/AArch64/AArch64SpeculationHardening.cpp 326 (MBB.begin())->getDebugLoc());
lib/Target/AMDGPU/AMDGPUMCInstLower.cpp 111 skipDebugInstructionsForward(SrcBB.begin(), SrcBB.end())->getOpcode() ==
lib/Target/AMDGPU/AMDILCFGStructurizer.cpp 434 if (I->getOpcode() == R600::PRED_X) {
435 switch (I->getOperand(2).getImm()) {
437 I->getOperand(2).setImm(R600::PRED_SETNE_INT);
440 I->getOperand(2).setImm(R600::PRED_SETE_INT);
443 I->getOperand(2).setImm(R600::PRED_SETNE);
446 I->getOperand(2).setImm(R600::PRED_SETE);
689 if (Pre->getOpcode() == R600::CONTINUE
690 && It->getOpcode() == R600::ENDLOOP)
1454 reversePredicateSetter(I, *I->getParent());
lib/Target/AMDGPU/GCNIterativeScheduler.cpp 66 auto BB = Begin->getParent();
72 if (!I->isDebugInstr() && LIS)
79 if (!I->isDebugInstr() && LIS)
95 const auto BB = Begin->getParent();
151 auto BB = R.Begin->getParent();
189 auto BB = R.Begin->getParent();
254 auto const BBEnd = Begin->getParent()->end();
282 auto const BBEnd = R.Begin->getParent()->end();
379 auto BB = R.Begin->getParent();
lib/Target/AMDGPU/GCNSchedStrategy.cpp 456 if (Regions[CurRegion].first->getParent() != MBB)
509 auto *BB = I->first->getParent();
515 } while (I != E && I->first->getParent() == BB);
556 if (RegionBegin->getParent() != MBB) {
558 MBB = RegionBegin->getParent();
lib/Target/AMDGPU/R600ControlFlowFinalizer.cpp 397 MachineBasicBlock *MBB = InsertPos->getParent();
401 InsertPos = BuildMI(MBB, InsertPos->getDebugLoc(),
420 if (!I->isBundle() && !TII->isALUInstr(I->getOpcode()))
420 if (!I->isBundle() && !TII->isALUInstr(I->getOpcode()))
423 if (I->isBundle()) {
443 MachineInstrBuilder MILit = BuildMI(MBB, I, I->getDebugLoc(),
534 LLVM_DEBUG(dbgs() << CfCount << ":"; I->dump(););
542 if (MI->getOpcode() != R600::ENDIF)
544 if (MI->getOpcode() == R600::CF_ALU)
548 CFStack.requiresWorkAroundForInst(MI->getOpcode());
549 switch (MI->getOpcode()) {
557 MI->setDesc(TII->get(R600::CF_ALU));
566 LLVM_DEBUG(dbgs() << CfCount << ":"; MI->dump(););
578 MI->eraseFromParent();
590 MI->eraseFromParent();
602 MI->eraseFromParent();
616 MI->eraseFromParent();
639 MI->eraseFromParent();
648 MI->eraseFromParent();
656 MI->eraseFromParent();
668 MI->eraseFromParent();
676 if (TII->isExport(MI->getOpcode())) {
677 LLVM_DEBUG(dbgs() << CfCount << ":"; MI->dump(););
lib/Target/AMDGPU/R600EmitClauseMarkers.cpp 201 MOI = Def->operands_begin(),
202 MOE = Def->operands_end(); MOI != MOE; ++MOI) {
228 if (UseI->readsRegister(MOI->getReg(), &TRI))
232 if (UseI != Def && UseI->killsRegister(MOI->getReg(), &TRI))
255 if (I->getOpcode() == R600::PRED_X) {
276 if (TII->mustBeLastInClause(I->getOpcode())) {
324 if (I != MBB.end() && I->getOpcode() == R600::CF_ALU)
lib/Target/AMDGPU/R600ISelLowering.cpp 284 if (std::next(I) == I->getParent()->end())
286 return std::next(I)->getOpcode() == R600::RETURN;
434 if (NextExportInst->getOpcode() == R600::EG_ExportSwz ||
435 NextExportInst->getOpcode() == R600::R600_ExportSwz) {
436 unsigned CurrentInstExportType = NextExportInst->getOperand(1)
lib/Target/AMDGPU/R600InstrInfo.cpp 98 for (MachineInstr::const_mop_iterator I = MBBI->operands_begin(),
99 E = MBBI->operands_end(); I != E; ++I) {
688 if (isBranch(I->getOpcode()))
690 if (!isJump(I->getOpcode())) {
695 while (I != MBB.begin() && std::prev(I)->getOpcode() == R600::JUMP) {
698 I->removeFromParent();
705 if (I == MBB.begin() || !isJump((--I)->getOpcode())) {
711 while (!isPredicateSetter(predSet->getOpcode())) {
715 Cond.push_back(predSet->getOperand(1));
716 Cond.push_back(predSet->getOperand(2));
730 while (!isPredicateSetter(predSet->getOpcode())) {
735 Cond.push_back(predSet->getOperand(1));
736 Cond.push_back(predSet->getOperand(2));
749 if (It->getOpcode() == R600::CF_ALU ||
750 It->getOpcode() == R600::CF_ALU_PUSH_BEFORE)
781 assert (CfAlu->getOpcode() == R600::CF_ALU);
782 CfAlu->setDesc(get(R600::CF_ALU_PUSH_BEFORE));
797 assert (CfAlu->getOpcode() == R600::CF_ALU);
798 CfAlu->setDesc(get(R600::CF_ALU_PUSH_BEFORE));
816 switch (I->getOpcode()) {
822 I->eraseFromParent();
826 assert (CfAlu->getOpcode() == R600::CF_ALU_PUSH_BEFORE);
827 CfAlu->setDesc(get(R600::CF_ALU));
831 I->eraseFromParent();
840 switch (I->getOpcode()) {
847 I->eraseFromParent();
851 assert (CfAlu->getOpcode() == R600::CF_ALU_PUSH_BEFORE);
852 CfAlu->setDesc(get(R600::CF_ALU));
856 I->eraseFromParent();
lib/Target/AMDGPU/R600OptimizeVectorRegisters.cpp 202 MachineBasicBlock &MBB = *Pos->getParent();
203 DebugLoc DL = Pos->getDebugLoc();
lib/Target/AMDGPU/R600Packetizer.cpp 72 if (!TII->isALUInstr(I->getOpcode()) && !I->isBundle())
72 if (!TII->isALUInstr(I->getOpcode()) && !I->isBundle())
75 if (I->isBundle())
314 endPacket(std::next(It)->getParent(), std::next(It));
356 if (MI->isKill() || MI->getOpcode() == R600::IMPLICIT_DEF ||
356 if (MI->isKill() || MI->getOpcode() == R600::IMPLICIT_DEF ||
357 (MI->getOpcode() == R600::CF_ALU && !MI->getOperand(8).getImm())) {
357 (MI->getOpcode() == R600::CF_ALU && !MI->getOperand(8).getImm())) {
lib/Target/AMDGPU/SIFixSGPRCopies.cpp 468 const MachineBasicBlock *MBBFrom = From->getParent();
469 const MachineBasicBlock *MBBTo = To->getParent();
529 << printMBBReference(*I->getParent()) << " " << *MI2);
530 I->getParent()->splice(I, MI2->getParent(), MI2);
lib/Target/AMDGPU/SIFrameLowering.cpp 1101 int64_t Amount = I->getOperand(0).getImm();
1107 const DebugLoc &DL = I->getDebugLoc();
1108 unsigned Opc = I->getOpcode();
1110 uint64_t CalleePopAmount = IsDestroy ? I->getOperand(1).getImm() : 0;
lib/Target/AMDGPU/SIISelLowering.cpp 3443 MachineBasicBlock *LoopBB = InsPt->getParent();
3555 MachineBasicBlock *LoopBB = InsPt->getParent();
3684 if (I->getOpcode() != TargetOpcode::COPY ||
3685 I->getOperand(0).getReg() != InputReg)
3691 I->removeFromParent();
10791 if (I != Exit->end() && I->getOpcode() == AMDGPU::S_INST_PREFETCH)
lib/Target/AMDGPU/SIInsertSkips.cpp 128 if (I->getOpcode() == AMDGPU::S_CBRANCH_VCCNZ ||
129 I->getOpcode() == AMDGPU::S_CBRANCH_VCCZ)
137 I->getOpcode() == AMDGPU::S_WAITCNT)
359 if (A->modifiesRegister(ExecReg, TRI))
361 if (A->modifiesRegister(CondReg, TRI)) {
362 if (!A->definesRegister(CondReg, TRI) || A->getOpcode() != And)
362 if (!A->definesRegister(CondReg, TRI) || A->getOpcode() != And)
366 ReadsCond |= A->readsRegister(CondReg, TRI);
371 MachineOperand &Op1 = A->getOperand(1);
372 MachineOperand &Op2 = A->getOperand(2);
388 if (M->definesRegister(SReg, TRI))
390 if (M->modifiesRegister(SReg, TRI))
392 ReadsSreg |= M->readsRegister(SReg, TRI);
395 !M->isMoveImmediate() ||
396 !M->getOperand(1).isImm() ||
397 M->getOperand(1).getImm() != -1)
402 A->getOperand(2).ChangeToImmediate(-1);
403 M->eraseFromParent();
407 if (!ReadsCond && A->registerDefIsDead(AMDGPU::SCC) &&
409 A->eraseFromParent();
522 I->eraseFromParent();
lib/Target/AMDGPU/SIInsertWaitcnts.cpp 1552 if (I->getOpcode() == AMDGPU::S_ENDPGM ||
1553 I->getOpcode() == AMDGPU::SI_RETURN_TO_EPILOG)
1571 if (I->getOpcode() == AMDGPU::S_DCACHE_WB)
1577 if ((I->getOpcode() == AMDGPU::S_ENDPGM ||
1578 I->getOpcode() == AMDGPU::SI_RETURN_TO_EPILOG) &&
1581 BuildMI(*MBB, I, I->getDebugLoc(), TII->get(AMDGPU::S_DCACHE_WB));
lib/Target/AMDGPU/SIInstrInfo.cpp 617 if (!Def->definesRegister(SrcReg, &RI))
619 if (Def->getOpcode() != AMDGPU::V_ACCVGPR_WRITE_B32)
622 MachineOperand &DefOp = Def->getOperand(1);
630 if (I->modifiesRegister(DefOp.getReg(), &RI))
1242 const DebugLoc &DL = Insert->getDebugLoc();
1907 if (I->getOpcode() == AMDGPU::S_BRANCH) {
1909 TBB = I->getOperand(0).getMBB();
1915 if (I->getOpcode() == AMDGPU::SI_NON_UNIFORM_BRCOND_PSEUDO) {
1916 CondBB = I->getOperand(1).getMBB();
1917 Cond.push_back(I->getOperand(0));
1919 BranchPredicate Pred = getBranchPredicate(I->getOpcode());
1923 CondBB = I->getOperand(0).getMBB();
1925 Cond.push_back(I->getOperand(1)); // Save the branch register.
1935 if (I->getOpcode() == AMDGPU::S_BRANCH) {
1937 FBB = I->getOperand(0).getMBB();
1955 while (I != E && !I->isBranch() && !I->isReturn() &&
1955 while (I != E && !I->isBranch() && !I->isReturn() &&
1956 I->getOpcode() != AMDGPU::SI_MASK_BRANCH) {
1957 switch (I->getOpcode()) {
1983 if (I->getOpcode() != AMDGPU::SI_MASK_BRANCH)
1995 MachineBasicBlock *MaskBrDest = I->getOperand(0).getMBB();
2021 if (I->getOpcode() == AMDGPU::SI_MASK_BRANCH) {
2027 I->eraseFromParent();
3859 MachineBasicBlock *MBB = MI->getParent();
3860 DebugLoc DL = MI->getDebugLoc();
6531 if (!Cur->isPHI() && Cur->readsRegister(Dst))
6531 if (!Cur->isPHI() && Cur->readsRegister(Dst))
6544 (InsPt->getOpcode() == AMDGPU::SI_IF ||
6545 InsPt->getOpcode() == AMDGPU::SI_ELSE ||
6546 InsPt->getOpcode() == AMDGPU::SI_IF_BREAK) &&
6547 InsPt->definesRegister(Src)) {
6549 return BuildMI(MBB, InsPt, InsPt->getDebugLoc(),
lib/Target/AMDGPU/SILoadStoreOptimizer.cpp 427 unsigned Opc = MI->getOpcode();
456 Offset0 = I->getOperand(OffsetIdx).getImm();
473 const unsigned Regs = getRegs(I->getOpcode(), TII);
500 AddrIdx[i] = AMDGPU::getNamedOperandIdx(I->getOpcode(), AddrOpName[i]);
501 AddrReg[i] = &I->getOperand(AddrIdx[i]);
510 assert(InstClass == getInstClass(Paired->getOpcode(), TII));
516 AMDGPU::getNamedOperandIdx(I->getOpcode(), AMDGPU::OpName::offset);
517 Offset1 = Paired->getOperand(OffsetIdx).getImm();
551 MachineBasicBlock *MBB = I->getParent();
578 return !(A->mayStore() || B->mayStore()) || !A->mayAlias(AA, *B, true);
578 return !(A->mayStore() || B->mayStore()) || !A->mayAlias(AA, *B, true);
578 return !(A->mayStore() || B->mayStore()) || !A->mayAlias(AA, *B, true);
654 int Idx = AMDGPU::getNamedOperandIdx(CI.I->getOpcode(), op);
655 if (AMDGPU::getNamedOperandIdx(CI.Paired->getOpcode(), op) != Idx)
658 CI.I->getOperand(Idx).getImm() != CI.Paired->getOperand(Idx).getImm())
658 CI.I->getOperand(Idx).getImm() != CI.Paired->getOperand(Idx).getImm())
753 MachineBasicBlock *MBB = CI.I->getParent();
757 const unsigned Opc = CI.I->getOpcode();
767 AMDGPU::getNamedOperandIdx(CI.I->getOpcode(), AMDGPU::OpName::swz);
768 if (Swizzled != -1 && CI.I->getOperand(Swizzled).getImm())
779 if ((getInstClass(MBBI->getOpcode(), *TII) != InstClass) ||
780 (getInstSubclass(MBBI->getOpcode(), *TII) != InstSubclass)) {
787 if (MBBI->hasUnmodeledSideEffects()) {
793 if (MBBI->mayLoadOrStore() &&
813 if (MBBI->hasOrderedMemoryRef())
873 MachineBasicBlock *MBB = CI.I->getParent();
905 DebugLoc DL = CI.I->getDebugLoc();
947 CI.I->eraseFromParent();
948 CI.Paired->eraseFromParent();
972 MachineBasicBlock *MBB = CI.I->getParent();
998 DebugLoc DL = CI.I->getDebugLoc();
1030 CI.I->eraseFromParent();
1031 CI.Paired->eraseFromParent();
1039 MachineBasicBlock *MBB = CI.I->getParent();
1040 DebugLoc DL = CI.I->getDebugLoc();
1048 AMDGPU::getNamedOperandIdx(CI.I->getOpcode(), AMDGPU::OpName::dmask);
1061 assert(CI.I->hasOneMemOperand() && CI.Paired->hasOneMemOperand());
1061 assert(CI.I->hasOneMemOperand() && CI.Paired->hasOneMemOperand());
1063 const MachineMemOperand *MMOa = *CI.I->memoperands_begin();
1064 const MachineMemOperand *MMOb = *CI.Paired->memoperands_begin();
1086 CI.I->eraseFromParent();
1087 CI.Paired->eraseFromParent();
1093 MachineBasicBlock *MBB = CI.I->getParent();
1094 DebugLoc DL = CI.I->getDebugLoc();
1105 assert(CI.I->hasOneMemOperand() && CI.Paired->hasOneMemOperand());
1105 assert(CI.I->hasOneMemOperand() && CI.Paired->hasOneMemOperand());
1107 const MachineMemOperand *MMOa = *CI.I->memoperands_begin();
1108 const MachineMemOperand *MMOb = *CI.Paired->memoperands_begin();
1136 CI.I->eraseFromParent();
1137 CI.Paired->eraseFromParent();
1143 MachineBasicBlock *MBB = CI.I->getParent();
1144 DebugLoc DL = CI.I->getDebugLoc();
1164 assert(CI.I->hasOneMemOperand() && CI.Paired->hasOneMemOperand());
1164 assert(CI.I->hasOneMemOperand() && CI.Paired->hasOneMemOperand());
1166 const MachineMemOperand *MMOa = *CI.I->memoperands_begin();
1167 const MachineMemOperand *MMOb = *CI.Paired->memoperands_begin();
1198 CI.I->eraseFromParent();
1199 CI.Paired->eraseFromParent();
1210 return AMDGPU::getMUBUFOpcode(AMDGPU::getMUBUFBaseOpcode(CI.I->getOpcode()),
1225 return AMDGPU::getMaskedMIMGOp(CI.I->getOpcode(), Width);
1297 MachineBasicBlock *MBB = CI.I->getParent();
1298 DebugLoc DL = CI.I->getDebugLoc();
1331 assert(CI.I->hasOneMemOperand() && CI.Paired->hasOneMemOperand());
1331 assert(CI.I->hasOneMemOperand() && CI.Paired->hasOneMemOperand());
1333 const MachineMemOperand *MMOa = *CI.I->memoperands_begin();
1334 const MachineMemOperand *MMOb = *CI.Paired->memoperands_begin();
1349 CI.I->eraseFromParent();
1350 CI.Paired->eraseFromParent();
lib/Target/AMDGPU/SILowerControlFlow.cpp 190 if (J != MBB->end() && J->getOpcode() == FalseTermOpc &&
191 J->getOperand(1).isReg() && J->getOperand(1).getReg() == SaveExecReg) {
191 J->getOperand(1).isReg() && J->getOperand(1).getReg() == SaveExecReg) {
192 SaveExecReg = J->getOperand(0).getReg();
193 J->eraseFromParent();
lib/Target/AMDGPU/SIMachineScheduler.cpp 1279 if (!I->isDebugInstr())
2047 << printMBBReference(*begin()->getParent()) << " ***\n";
lib/Target/AMDGPU/SIMemoryLegalizer.cpp 105 int BitIdx = AMDGPU::getNamedOperandIdx(MI->getOpcode(), BitName);
109 MachineOperand &Bit = MI->getOperand(BitIdx);
446 const Function &Func = MI->getParent()->getParent()->getFunction();
447 DiagnosticInfoUnsupported Diag(Func, Msg, MI->getDebugLoc());
518 assert(MI->getNumMemOperands() > 0);
528 for (const auto &MMO : MI->memoperands()) {
577 assert(MI->getDesc().TSFlags & SIInstrFlags::maybeAtomic);
579 if (!(MI->mayLoad() && !MI->mayStore()))
579 if (!(MI->mayLoad() && !MI->mayStore()))
583 if (MI->getNumMemOperands() == 0)
591 assert(MI->getDesc().TSFlags & SIInstrFlags::maybeAtomic);
593 if (!(!MI->mayLoad() && MI->mayStore()))
593 if (!(!MI->mayLoad() && MI->mayStore()))
597 if (MI->getNumMemOperands() == 0)
605 assert(MI->getDesc().TSFlags & SIInstrFlags::maybeAtomic);
607 if (MI->getOpcode() != AMDGPU::ATOMIC_FENCE)
611 static_cast<AtomicOrdering>(MI->getOperand(0).getImm());
613 SyncScope::ID SSID = static_cast<SyncScope::ID>(MI->getOperand(1).getImm());
638 assert(MI->getDesc().TSFlags & SIInstrFlags::maybeAtomic);
640 if (!(MI->mayLoad() && MI->mayStore()))
640 if (!(MI->mayLoad() && MI->mayStore()))
644 if (MI->getNumMemOperands() == 0)
669 assert(MI->mayLoad() && !MI->mayStore());
669 assert(MI->mayLoad() && !MI->mayStore());
703 assert(MI->mayLoad() ^ MI->mayStore());
703 assert(MI->mayLoad() ^ MI->mayStore());
719 MachineBasicBlock &MBB = *MI->getParent();
720 DebugLoc DL = MI->getDebugLoc();
763 MachineBasicBlock &MBB = *MI->getParent();
764 DebugLoc DL = MI->getDebugLoc();
857 MachineBasicBlock &MBB = *MI->getParent();
858 DebugLoc DL = MI->getDebugLoc();
903 assert(MI->mayLoad() && !MI->mayStore());
903 assert(MI->mayLoad() && !MI->mayStore());
944 assert(MI->mayLoad() ^ MI->mayStore());
944 assert(MI->mayLoad() ^ MI->mayStore());
959 MachineBasicBlock &MBB = *MI->getParent();
960 DebugLoc DL = MI->getDebugLoc();
1013 MachineBasicBlock &MBB = *MI->getParent();
1014 DebugLoc DL = MI->getDebugLoc();
1129 MI->eraseFromParent();
1137 assert(MI->mayLoad() && !MI->mayStore());
1137 assert(MI->mayLoad() && !MI->mayStore());
1182 assert(!MI->mayLoad() && MI->mayStore());
1182 assert(!MI->mayLoad() && MI->mayStore());
1209 assert(MI->getOpcode() == AMDGPU::ATOMIC_FENCE);
1247 assert(MI->mayLoad() && MI->mayStore());
1247 assert(MI->mayLoad() && MI->mayStore());
1292 if (!(MI->getDesc().TSFlags & SIInstrFlags::maybeAtomic))
lib/Target/AMDGPU/SIOptimizeExecMasking.cpp 227 if (!I->isTerminator())
309 PrepareExecInst->getOperand(0).setReg(Exec);
325 Register CopyFromExec = CopyFromExecInst->getOperand(0).getReg();
330 = std::next(CopyFromExecInst->getIterator()), JE = I->getIterator();
330 = std::next(CopyFromExecInst->getIterator()), JE = I->getIterator();
332 if (SaveExecInst && J->readsRegister(Exec, TRI)) {
340 bool ReadsCopyFromExec = J->readsRegister(CopyFromExec, TRI);
342 if (J->modifiesRegister(CopyToExec, TRI)) {
350 unsigned SaveExecOp = getSaveExecOp(J->getOpcode());
377 if (SaveExecInst && J->readsRegister(CopyToExec, TRI)) {
403 CopyFromExecInst->eraseFromParent();
lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp 337 if (I->isUnconditionalBranch() || I->getOpcode() == AMDGPU::S_ENDPGM)
337 if (I->isUnconditionalBranch() || I->getOpcode() == AMDGPU::S_ENDPGM)
339 else if (I->isBranch())
344 if (I->isDebugInstr()) {
349 if (I->mayStore() || I->isBarrier() || I->isCall() ||
349 if (I->mayStore() || I->isBarrier() || I->isCall() ||
349 if (I->mayStore() || I->isBarrier() || I->isCall() ||
350 I->hasUnmodeledSideEffects() || I->hasOrderedMemoryRef())
350 I->hasUnmodeledSideEffects() || I->hasOrderedMemoryRef())
356 for (auto &Op : I->operands()) {
363 I->eraseFromParent();
397 for (auto &Op : Lead->operands()) {
403 Lead->eraseFromParent();
lib/Target/AMDGPU/SIRegisterInfo.cpp 350 DL = Ins->getDebugLoc();
549 MachineBasicBlock *MBB = MI->getParent();
550 MachineFunction *MF = MI->getParent()->getParent();
559 bool IsStore = MI->mayStore();
568 return BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(Opc), Dst)
580 MachineBasicBlock *MBB = MI->getParent();
581 const DebugLoc &DL = MI->getDebugLoc();
582 bool IsStore = MI->mayStore();
584 unsigned Opc = MI->getOpcode();
624 MachineBasicBlock *MBB = MI->getParent();
625 MachineFunction *MF = MI->getParent()->getParent();
630 const DebugLoc &DL = MI->getDebugLoc();
749 MachineBasicBlock *MBB = MI->getParent();
762 Register SuperReg = MI->getOperand(0).getReg();
763 bool IsKill = MI->getOperand(0).isKill();
764 const DebugLoc &DL = MI->getDebugLoc();
858 MI->eraseFromParent();
867 MachineFunction *MF = MI->getParent()->getParent();
868 MachineBasicBlock *MBB = MI->getParent();
879 const DebugLoc &DL = MI->getDebugLoc();
881 Register SuperReg = MI->getOperand(0).getReg();
939 MIB.addReg(MI->getOperand(0).getReg(), RegState::ImplicitDefine);
948 MI->eraseFromParent();
959 switch (MI->getOpcode()) {
986 MachineFunction *MF = MI->getParent()->getParent();
987 MachineBasicBlock *MBB = MI->getParent();
991 DebugLoc DL = MI->getDebugLoc();
995 MachineOperand &FIOp = MI->getOperand(FIOperandNum);
996 int Index = MI->getOperand(FIOperandNum).getIndex();
1000 switch (MI->getOpcode()) {
1052 *MI->memoperands_begin(),
1054 MFI->addToSpilledVGPRs(getNumSubRegsForSpillOp(MI->getOpcode()));
1055 MI->eraseFromParent();
1082 *MI->memoperands_begin(),
1084 MI->eraseFromParent();
1089 const DebugLoc &DL = MI->getDebugLoc();
1105 bool IsCopy = MI->getOpcode() == AMDGPU::V_MOV_B32_e32;
1107 MI->getOperand(0).getReg() :
1194 MI->eraseFromParent();
1203 AMDGPU::getNamedOperandIdx(MI->getOpcode(),
1218 MI->eraseFromParent();
lib/Target/ARC/ARCExpandPseudos.cpp 84 switch (MBBI->getOpcode()) {
lib/Target/ARC/ARCInstrInfo.cpp 181 while (isPredicated(*I) || I->isTerminator() || I->isDebugValue()) {
181 while (isPredicated(*I) || I->isTerminator() || I->isDebugValue()) {
188 while (I->isDebugInstr() || !I->isTerminator()) {
188 while (I->isDebugInstr() || !I->isTerminator()) {
194 if (isJumpOpcode(I->getOpcode())) {
198 } else if (isUncondBranchOpcode(I->getOpcode())) {
199 TBB = I->getOperand(0).getMBB();
200 } else if (isCondBranchOpcode(I->getOpcode())) {
207 TBB = I->getOperand(0).getMBB();
208 Cond.push_back(I->getOperand(1));
209 Cond.push_back(I->getOperand(2));
210 Cond.push_back(I->getOperand(3));
211 } else if (I->isReturn()) {
221 if (!isPredicated(*I) && (isUncondBranchOpcode(I->getOpcode()) ||
222 isJumpOpcode(I->getOpcode()) || I->isReturn())) {
222 isJumpOpcode(I->getOpcode()) || I->isReturn())) {
261 if (!isUncondBranchOpcode(I->getOpcode()) &&
262 !isCondBranchOpcode(I->getOpcode()))
266 I->eraseFromParent();
273 if (!isCondBranchOpcode(I->getOpcode()))
277 I->eraseFromParent();
lib/Target/ARC/ARCOptAddrMode.cpp 396 if (MI->isDebugValue())
398 if (MI->mayStore() || MI->isCall() || MI->isInlineAsm() ||
398 if (MI->mayStore() || MI->isCall() || MI->isInlineAsm() ||
398 if (MI->mayStore() || MI->isCall() || MI->isInlineAsm() ||
399 MI->hasUnmodeledSideEffects())
401 if (IsStore && MI->mayLoad())
427 if (MI->isDebugValue())
429 if (MI->mayStore() || MI->isCall() || MI->isInlineAsm() ||
429 if (MI->mayStore() || MI->isCall() || MI->isInlineAsm() ||
429 if (MI->mayStore() || MI->isCall() || MI->isInlineAsm() ||
430 MI->hasUnmodeledSideEffects())
432 if (IsStore && MI->mayLoad())
434 if (ValReg && MI->readsVirtualRegister(ValReg))
470 if (MI->isDebugValue())
472 if (!MI->mayLoad() && !MI->mayStore())
472 if (!MI->mayLoad() && !MI->mayStore())
474 if (ARC::getPostIncOpcode(MI->getOpcode()) < 0)
lib/Target/ARM/ARMBaseInstrInfo.cpp 326 while (isPredicated(*I) || I->isTerminator() || I->isDebugValue()) {
326 while (isPredicated(*I) || I->isTerminator() || I->isDebugValue()) {
333 while (I->isDebugInstr() || !I->isTerminator()) {
333 while (I->isDebugInstr() || !I->isTerminator()) {
339 if (isIndirectBranchOpcode(I->getOpcode()) ||
340 isJumpTableBranchOpcode(I->getOpcode())) {
344 } else if (isUncondBranchOpcode(I->getOpcode())) {
345 TBB = I->getOperand(0).getMBB();
346 } else if (isCondBranchOpcode(I->getOpcode())) {
353 TBB = I->getOperand(0).getMBB();
354 Cond.push_back(I->getOperand(1));
355 Cond.push_back(I->getOperand(2));
356 } else if (I->isReturn()) {
367 (isUncondBranchOpcode(I->getOpcode()) ||
368 isIndirectBranchOpcode(I->getOpcode()) ||
369 isJumpTableBranchOpcode(I->getOpcode()) ||
370 I->isReturn())) {
409 if (!isUncondBranchOpcode(I->getOpcode()) &&
410 !isCondBranchOpcode(I->getOpcode()))
414 I->eraseFromParent();
420 if (!isCondBranchOpcode(I->getOpcode()))
424 I->eraseFromParent();
777 BuildMI(MBB, I, I->getDebugLoc(), get(Opc), DestReg);
796 MachineInstrBuilder MIB = BuildMI(MBB, I, I->getDebugLoc(), get(Opc));
931 BuildMI(MBB, I, I->getDebugLoc(), get(ARM::VMSR_P0), DestReg)
937 BuildMI(MBB, I, I->getDebugLoc(), get(ARM::VMRS_P0), DestReg)
943 BuildMI(MBB, I, I->getDebugLoc(), get(ARM::VMSR_FPSCR_NZCVQC), DestReg)
949 BuildMI(MBB, I, I->getDebugLoc(), get(ARM::VMRS_FPSCR_NZCVQC), DestReg)
976 Mov = BuildMI(MBB, I, I->getDebugLoc(), get(Opc), Dst).addReg(Src);
1274 if (I != MBB.end()) DL = I->getDebugLoc();
1518 DebugLoc dl = MI->getDebugLoc();
1519 MachineBasicBlock *BB = MI->getParent();
1522 if (isThumb1 || !MI->getOperand(1).isDead()) {
1523 MachineOperand LDWb(MI->getOperand(1));
1532 if (isThumb1 || !MI->getOperand(0).isDead()) {
1533 MachineOperand STWb(MI->getOperand(0));
1542 MachineOperand LDBase(MI->getOperand(3));
1545 MachineOperand STBase(MI->getOperand(2));
1551 for(unsigned I = 5; I < MI->getNumOperands(); ++I)
1552 ScratchRegs.push_back(MI->getOperand(I).getReg());
1973 while (++I != MBB->end() && I->isDebugInstr())
1975 if (I != MBB->end() && I->getOpcode() == ARM::t2IT)
2981 if (I->getOpcode() != ARM::tMOVi8) {
4773 MachineBasicBlock &MBB = *MI->getParent();
4774 DebugLoc DL = MI->getDebugLoc();
4775 Register Reg = MI->getOperand(0).getReg();
4777 cast<GlobalValue>((*MI->memoperands_begin())->getValue());
5358 if (I->modifiesRegister(Reg, TRI))
5371 if (CmpMI->modifiesRegister(ARM::CPSR, TRI))
5373 if (CmpMI->readsRegister(ARM::CPSR, TRI))
5379 if (CmpMI->getOpcode() != ARM::tCMPi8 && CmpMI->getOpcode() != ARM::t2CMPri)
5379 if (CmpMI->getOpcode() != ARM::tCMPi8 && CmpMI->getOpcode() != ARM::t2CMPri)
5381 Register Reg = CmpMI->getOperand(0).getReg();
5384 if (Pred != ARMCC::AL || CmpMI->getOperand(1).getImm() != 0)
5388 if (registerDefinedBetween(Reg, CmpMI->getNextNode(), Br, TRI))
lib/Target/ARM/ARMBaseRegisterInfo.cpp 640 DL = Ins->getDebugLoc();
lib/Target/ARM/ARMConstantIslandPass.cpp 568 switch (MI->getOpcode()) {
591 unsigned NumOps = MI->getDesc().getNumOperands();
593 MI->getOperand(NumOps - (MI->isPredicable() ? 2 : 1));
593 MI->getOperand(NumOps - (MI->isPredicable() ? 2 : 1));
1369 I->getOpcode() != ARM::t2IT &&
1405 if (MI->getOpcode() == ARM::t2IT)
1426 if (STI->isTargetWindows() && isThumb && MI->getOpcode() == ARM::t2MOVTi16 &&
1427 (MI->getOperand(2).getTargetFlags() & ARMII::MO_OPTION_MASK) ==
1430 assert(MI->getOpcode() == ARM::t2MOVi16 &&
1431 (MI->getOperand(1).getTargetFlags() & ARMII::MO_OPTION_MASK) ==
1963 if (KillMI->killsRegister(Reg, TRI)) {
1964 KillMI->clearRegisterKills(Reg, TRI);
2060 for (unsigned K = 0, E = I->getNumOperands(); K != E; ++K) {
2061 const MachineOperand &MO = I->getOperand(K);
2079 for (unsigned K = 0, E = I->getNumOperands(); K != E; ++K) {
2080 const MachineOperand &MO = I->getOperand(K);
2130 if (I->getOpcode() == ARM::t2ADDrs && I->getOperand(0).getReg() == EntryReg)
2130 if (I->getOpcode() == ARM::t2ADDrs && I->getOperand(0).getReg() == EntryReg)
2140 for (unsigned K = 0, E = J->getNumOperands(); K != E; ++K) {
2141 const MachineOperand &MO = J->getOperand(K);
lib/Target/ARM/ARMExpandPseudoInsts.cpp 914 finalizeBundle(MBB, LO16->getIterator(), MBBI->getIterator());
1165 assert(MBBI->isReturn() &&
1167 unsigned RetOpcode = MBBI->getOpcode();
1168 DebugLoc dl = MBBI->getDebugLoc();
1174 MachineOperand &JumpTarget = MBBI->getOperand(0);
1205 for (unsigned i = 1, e = MBBI->getNumOperands(); i != e; ++i)
1206 NewMI->addOperand(MBBI->getOperand(i));
1206 NewMI->addOperand(MBBI->getOperand(i));
lib/Target/ARM/ARMFrameLowering.cpp 501 while (MBBI != MBB.end() && MBBI->getOpcode() == ARM::VSTMDDB_UPD) {
792 DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
860 while (MBBI != MBB.end() && MBBI->getOpcode() == ARM::VLDMDIA_UPD)
1064 DL = MI->getDebugLoc();
1065 unsigned RetOpcode = MI->getOpcode();
1128 MI->eraseFromParent();
1169 DebugLoc DL = MI != MBB.end() ? MI->getDebugLoc() : DebugLoc();
1299 std::prev(MI)->addRegisterKilled(ARM::R4, TRI);
1311 assert(MI->mayStore() && "Expecting spill instruction");
1317 assert(MI->mayStore() && "Expecting spill instruction");
1321 assert(MI->mayStore() && "Expecting spill instruction");
1326 assert(MI->killsRegister(ARM::R4) && "Missed kill flag");
1342 DebugLoc DL = MI != MBB.end() ? MI->getDebugLoc() : DebugLoc();
1422 std::prev(MI)->addRegisterKilled(ARM::R4, TRI);
lib/Target/ARM/ARMISelLowering.cpp 9488 if (!II->isEHLabel()) continue;
9490 MCSymbol *Sym = II->getOperand(0).getMCSymbol();
9837 if (!II->isCall()) continue;
9841 OI = II->operands_begin(), OE = II->operands_end();
9841 OI = II->operands_begin(), OE = II->operands_end();
10393 SelectItr->addRegisterKilled(ARM::CPSR, TRI);
lib/Target/ARM/ARMInstrInfo.cpp 93 MachineFunction &MF = *MI->getParent()->getParent();
111 cast<GlobalValue>((*MI->memoperands_begin())->getValue());
118 MachineBasicBlock &MBB = *MI->getParent();
119 DebugLoc DL = MI->getDebugLoc();
120 Register Reg = MI->getOperand(0).getReg();
lib/Target/ARM/ARMLoadStoreOptimizer.cpp 492 unsigned Opc = MBBI->getOpcode();
494 if (MBBI->readsRegister(Base)) {
507 MBBI->getOperand(MBBI->getDesc().getNumOperands() - 3);
507 MBBI->getOperand(MBBI->getDesc().getNumOperands() - 3);
524 MBBI->getOperand(MBBI->getDesc().getNumOperands() - 3);
524 MBBI->getOperand(MBBI->getDesc().getNumOperands() - 3);
541 } else if (definesCPSR(*MBBI) || MBBI->isCall() || MBBI->isBranch()) {
541 } else if (definesCPSR(*MBBI) || MBBI->isCall() || MBBI->isBranch()) {
559 if (MBBI->killsRegister(Base) || MBBI->definesRegister(Base))
559 if (MBBI->killsRegister(Base) || MBBI->definesRegister(Base))
1214 MachineBasicBlock &MBB = *MBBI->getParent();
1222 while (PrevMBBI->isDebugInstr() && PrevMBBI != BeginMBBI)
1234 MachineBasicBlock &MBB = *MBBI->getParent();
1238 while (NextMBBI != EndMBBI && NextMBBI->isDebugInstr())
1628 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MBBI->getDebugLoc(),
1637 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MBBI->getDebugLoc(),
1698 BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII->get(NewOpc))
1706 BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII->get(NewOpc))
1784 unsigned Opcode = MBBI->getOpcode();
1785 const MachineOperand &MO = MBBI->getOperand(0);
1851 } else if (MBBI->isDebugInstr()) {
1853 } else if (MBBI->getOpcode() == ARM::t2LDRDi8 ||
1854 MBBI->getOpcode() == ARM::t2STRDi8) {
1931 (MBBI->getOpcode() == ARM::BX_RET ||
1932 MBBI->getOpcode() == ARM::tBX_RET ||
1933 MBBI->getOpcode() == ARM::MOVPCLR)) {
1936 while (PrevI->isDebugInstr() && PrevI != MBB.begin())
1973 MBBI->getOpcode() != ARM::tBX_RET)
1978 if (Prev->getOpcode() != ARM::tMOVr || !Prev->definesRegister(ARM::LR))
1978 if (Prev->getOpcode() != ARM::tMOVr || !Prev->definesRegister(ARM::LR))
1981 for (auto Use : Prev->uses())
1984 BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII->get(ARM::tBX))
2112 if (I->isDebugInstr() || MemOps.count(&*I))
2114 if (I->isCall() || I->isTerminator() || I->hasUnmodeledSideEffects())
2114 if (I->isCall() || I->isTerminator() || I->hasUnmodeledSideEffects())
2114 if (I->isCall() || I->isTerminator() || I->hasUnmodeledSideEffects())
2116 if (I->mayStore() || (!isLd && I->mayLoad()))
2116 if (I->mayStore() || (!isLd && I->mayLoad()))
2118 if (I->mayAlias(AA, *MemOp, /*UseTBAA*/ false))
2120 for (unsigned j = 0, NumOps = I->getNumOperands(); j != NumOps; ++j) {
2121 MachineOperand &MO = I->getOperand(j);
2302 (MemOps.count(&*InsertPos) || InsertPos->isDebugInstr()))
lib/Target/ARM/MVEVPTBlockPass.cpp 144 while (CmpMI != MI->getParent()->begin()) {
146 if (CmpMI->modifiesRegister(ARM::VPR, TRI))
148 if (CmpMI->readsRegister(ARM::VPR, TRI))
154 NewOpcode = VCMPOpcodeToVPT(CmpMI->getOpcode());
159 if (registerDefinedBetween(CmpMI->getOperand(1).getReg(), std::next(CmpMI),
162 if (registerDefinedBetween(CmpMI->getOperand(2).getReg(), std::next(CmpMI),
lib/Target/ARM/Thumb1FrameLowering.cpp 233 if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPUSH) {
335 while (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tMOVr)
337 if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPUSH) {
473 DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
539 if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tBX_RET &&
540 &MBB.front() != &*MBBI && std::prev(MBBI)->getOpcode() == ARM::tPOP) {
619 if (MBBI != MBB.end() && MBBI->getOpcode() != ARM::tB)
620 CanRestoreDirectly = (MBBI->getOpcode() == ARM::tBX_RET ||
621 MBBI->getOpcode() == ARM::tPOP_RET);
625 assert(MBBI_prev->getOpcode() == ARM::tPOP);
627 if ((*MBB.succ_begin())->begin()->getOpcode() == ARM::tBX_RET)
635 if (!DoIt || MBBI->getOpcode() == ARM::tPOP_RET)
638 BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII.get(ARM::tPOP_RET))
641 for (auto MO: MBBI->operands())
665 dl = MBBI->getDebugLoc();
703 if (PrevMBBI->getOpcode() == ARM::tPOP) {
724 .addImm(MBBI->getNumExplicitOperands() - 2)
749 if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPOP_RET) {
753 BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII.get(ARM::tPOP))
756 for (auto MO: MBBI->operands())
945 DebugLoc DL = MI != MBB.end() ? MI->getDebugLoc() : DebugLoc();
973 if (Terminator != MBB.end() && Terminator->getOpcode() == ARM::tBX_RET) {
978 for (auto Op : Terminator->implicit_operands()) {
1036 MI->getOpcode() == ARM::TCRETURNdi ||
1037 MI->getOpcode() == ARM::TCRETURNri)
lib/Target/ARM/Thumb1InstrInfo.cpp 89 if (I != MBB.end()) DL = I->getDebugLoc();
118 if (I != MBB.end()) DL = I->getDebugLoc();
135 MachineFunction &MF = *MI->getParent()->getParent();
lib/Target/ARM/Thumb2ITBlockPass.cpp 182 while (I != E && I->isDebugInstr())
236 if (MBBI->isDebugInstr())
lib/Target/ARM/Thumb2InstrInfo.cpp 60 MachineBasicBlock *MBB = Tail->getParent();
62 if (!AFI->hasITBlocks() || Tail->isBranch()) {
84 if (MBBI->isDebugInstr()) {
88 if (MBBI->getOpcode() == ARM::t2IT) {
89 unsigned Mask = MBBI->getOperand(1).getImm();
91 MBBI->eraseFromParent();
95 MBBI->getOperand(1).setImm((Mask & MaskOff) | MaskOn);
111 while (MBBI->isDebugInstr()) {
140 if (I != MBB.end()) DL = I->getDebugLoc();
188 if (I != MBB.end()) DL = I->getDebugLoc();
223 MachineFunction &MF = *MI->getParent()->getParent();
lib/Target/AVR/AVRExpandPseudoInsts.cpp 63 return BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII->get(Opcode));
68 return BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII->get(Opcode), DstReg);
962 MBBI->eraseFromParent();
1511 int Opcode = MBBI->getOpcode();
lib/Target/AVR/AVRFrameLowering.cpp 57 DebugLoc DL = (MBBI != MBB.end()) ? MBBI->getDebugLoc() : DebugLoc();
108 (MBBI != MBB.end()) && MBBI->getFlag(MachineInstr::FrameSetup) &&
109 (MBBI->getOpcode() == AVR::PUSHRr || MBBI->getOpcode() == AVR::PUSHWRr)) {
109 (MBBI->getOpcode() == AVR::PUSHRr || MBBI->getOpcode() == AVR::PUSHWRr)) {
157 assert(MBBI->getDesc().isReturn() &&
160 DebugLoc DL = MBBI->getDebugLoc();
188 int Opc = PI->getOpcode();
190 if (Opc != AVR::POPRd && Opc != AVR::POPWRd && !PI->isTerminator()) {
312 for (auto I = MI, E = MBB.end(); I != E && !I->isCall();) {
315 unsigned Opcode = I->getOpcode();
375 DebugLoc DL = MI->getDebugLoc();
376 unsigned int Opcode = MI->getOpcode();
525 DL = MBBI->getDebugLoc();
lib/Target/AVR/AVRISelLowering.cpp 1570 if (I->getOpcode() == AVR::COPY) {
1571 Register SrcReg = I->getOperand(1).getReg();
lib/Target/AVR/AVRInstrInfo.cpp 133 DL = MI->getDebugLoc();
166 DL = MI->getDebugLoc();
275 if (I->isDebugInstr()) {
287 if (!I->getDesc().isBranch()) {
293 if (I->getOpcode() == AVR::RJMPk) {
297 TBB = I->getOperand(0).getMBB();
303 std::next(I)->eraseFromParent();
310 if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
312 I->eraseFromParent();
319 TBB = I->getOperand(0).getMBB();
324 AVRCC::CondCodes BranchCode = getCondFromBranchOpc(I->getOpcode());
331 MachineBasicBlock *TargetBB = I->getOperand(0).getMBB();
356 .addMBB(UnCondBrIter->getOperand(0).getMBB());
360 OldInst->eraseFromParent();
361 UnCondBrIter->eraseFromParent();
370 TBB = I->getOperand(0).getMBB();
382 if (TBB != I->getOperand(0).getMBB()) {
446 if (I->isDebugInstr()) {
451 if (I->getOpcode() != AVR::RJMPk &&
452 getCondFromBranchOpc(I->getOpcode()) == AVRCC::COND_INVALID) {
458 I->eraseFromParent();
lib/Target/AVR/AVRRelaxMemOperations.cpp 54 return BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII->get(Opcode));
126 int Opcode = MBBI->getOpcode();
lib/Target/BPF/BPFInstrInfo.cpp 46 Register DstReg = MI->getOperand(0).getReg();
47 Register SrcReg = MI->getOperand(1).getReg();
48 uint64_t CopyLen = MI->getOperand(2).getImm();
49 uint64_t Alignment = MI->getOperand(3).getImm();
50 Register ScratchReg = MI->getOperand(4).getReg();
51 MachineBasicBlock *BB = MI->getParent();
52 DebugLoc dl = MI->getDebugLoc();
131 DL = I->getDebugLoc();
154 DL = I->getDebugLoc();
174 if (I->isDebugInstr())
184 if (!I->isBranch())
188 if (I->getOpcode() == BPF::JMP) {
190 TBB = I->getOperand(0).getMBB();
196 std::next(I)->eraseFromParent();
201 if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
203 I->eraseFromParent();
209 TBB = I->getOperand(0).getMBB();
249 if (I->isDebugInstr())
251 if (I->getOpcode() != BPF::JMP)
254 I->eraseFromParent();
lib/Target/Hexagon/BitTracker.cpp 1066 while (It != End && It->isPHI()) {
1080 while (It != End && !It->isBranch()) {
lib/Target/Hexagon/HexagonBitSimplify.cpp 1476 DebugLoc DL = I->getDebugLoc();
1477 auto At = I->isPHI() ? B.getFirstNonPHI() : I;
1596 unsigned Opc = I->getOpcode();
1601 DebugLoc DL = I->getDebugLoc();
1602 auto At = I->isPHI() ? B.getFirstNonPHI() : I;
3072 BuildMI(LB, At, At->getDebugLoc(), HII->get(TargetOpcode::PHI), PhiR)
3152 if (I->isTerminator())
3154 if (I->isPHI())
3288 DebugLoc DL = (T != C.PB->end()) ? T->getDebugLoc() : DebugLoc();
lib/Target/Hexagon/HexagonConstExtenders.cpp 198 assert(It->getParent() == B);
lib/Target/Hexagon/HexagonConstPropagation.cpp 893 while (It != End && It->isPHI()) {
902 while (It != End && It->isDebugInstr())
904 assert(It == End || !It->isPHI());
910 while (It != End && !It->isBranch()) {
911 if (!It->isDebugInstr()) {
996 if (I->isPHI())
1001 if (P->isPHI())
1037 if (I->isBranch() && !InstrExec.count(&*I))
lib/Target/Hexagon/HexagonCopyToCombine.cpp 302 if (I->isDebugInstr())
312 I->readsRegister(KilledOperand, TRI))
425 if (!It->isDebugInstr())
528 while (I2 != I1.getParent()->end() && I2->isDebugInstr())
536 if (I2->modifiesRegister(I1DestReg, TRI))
547 Register I2DestReg = I2->getOperand(0).getReg();
632 MachineBasicBlock *BB = InsertPt->getParent();
652 DebugLoc DL = InsertPt->getDebugLoc();
653 MachineBasicBlock *BB = InsertPt->getParent();
667 DebugLoc DL = InsertPt->getDebugLoc();
668 MachineBasicBlock *BB = InsertPt->getParent();
764 DebugLoc DL = InsertPt->getDebugLoc();
765 MachineBasicBlock *BB = InsertPt->getParent();
812 DebugLoc DL = InsertPt->getDebugLoc();
813 MachineBasicBlock *BB = InsertPt->getParent();
863 DebugLoc DL = InsertPt->getDebugLoc();
864 MachineBasicBlock *BB = InsertPt->getParent();
lib/Target/Hexagon/HexagonEarlyIfConv.cpp 250 unsigned Opc = T1I->getOpcode();
253 Register PredR = T1I->getOperand(0).getReg();
259 MachineBasicBlock *T1B = T1I->getOperand(1).getMBB();
262 assert(T2I == B->end() || T2I->getOpcode() == Hexagon::J2_jump);
264 : T2I->getOperand(0).getMBB();
353 if (I->isBarrier())
713 DL = At->getDebugLoc();
767 assert(!I->isPHI());
862 DebugLoc DL = OldTI->getDebugLoc();
lib/Target/Hexagon/HexagonExpandCondsets.cpp 627 MachineBasicBlock &B = *At->getParent();
746 MachineBasicBlock &B = *UseIt->getParent();
870 DebugLoc DL = Where->getDebugLoc(); // "Where" points to an instruction.
975 if (!I->modifiesRegister(PredR, nullptr))
1074 unsigned Opc = I->getOpcode();
1080 if (RegisterRef(I->getOperand(0)) == RegisterRef(I->getOperand(2))) {
1080 if (RegisterRef(I->getOperand(0)) == RegisterRef(I->getOperand(2))) {
1081 for (auto &Op : I->operands())
lib/Target/Hexagon/HexagonFixupHwLoops.cpp 140 if (MII->isMetaInstruction()) {
145 assert(MII->getOperand(0).isMBB() &&
147 MachineBasicBlock *TargetBB = MII->getOperand(0).getMBB();
171 MachineBasicBlock *MBB = MII->getParent();
172 DebugLoc DL = MII->getDebugLoc();
175 switch (MII->getOpcode()) {
193 for (unsigned i = 0; i < MII->getNumOperands(); ++i)
194 MIB.add(MII->getOperand(i));
lib/Target/Hexagon/HexagonFrameLowering.cpp 340 unsigned RetOpc = I->getOpcode();
347 if (I->isReturn())
690 if (!It->isLabel())
704 unsigned COpc = PrevIt->getOpcode();
1233 DebugLoc DL = MI != MBB.end() ? MI->getDebugLoc() : DebugLoc();
1298 DebugLoc DL = MI != MBB.end() ? MI->getDebugLoc()
1315 assert(It->isReturn() && std::next(It) == MBB.end());
lib/Target/Hexagon/HexagonGenInsert.cpp 785 const MachineBasicBlock *FB = FromI->getParent(), *TB = ToI->getParent();
785 const MachineBasicBlock *FB = FromI->getParent(), *TB = ToI->getParent();
lib/Target/Hexagon/HexagonGenMux.cpp 335 MachineBasicBlock &B = *MX.At->getParent();
358 if (I->isDebugInstr())
364 for (MachineOperand &Op : I->operands()) {
lib/Target/Hexagon/HexagonHardwareLoops.cpp 833 DL = InsertPos->getDebugLoc();
1243 DL = InsertPos->getDebugLoc();
1279 DebugLoc LastIDL = LastI->getDebugLoc();
1285 if (LastI->getOpcode() == Hexagon::J2_jumpt ||
1286 LastI->getOpcode() == Hexagon::J2_jumpf) {
1288 MachineBasicBlock *BranchTarget = LastI->getOperand(1).getMBB();
lib/Target/Hexagon/HexagonInstrInfo.cpp 564 if (I->isDebugInstr())
567 if (!I->isBranch())
569 if (Count && (I->getOpcode() == Hexagon::J2_jump))
759 if (I != LoopBB->end() && isEndLoopN(I->getOpcode())) {
762 LoopBB, I->getOpcode(), I->getOperand(0).getMBB(), VisitedBBs);
762 LoopBB, I->getOpcode(), I->getOperand(0).getMBB(), VisitedBBs);
1050 std::prev(MBBI)->copyImplicitOps(*MBB.getParent(), MI);
3034 if (I->isBarrier())
4344 assert(BundleHead->isBundle() && "Not a bundle header");
4391 DebugLoc DL = I->getDebugLoc();
lib/Target/Hexagon/HexagonMachineScheduler.cpp 247 << printMBBReference(*begin()->getParent()) << " ***\n";
lib/Target/Hexagon/HexagonNewValueJump.cpp 136 if (II->getOpcode() == TargetOpcode::KILL)
139 if (II->isImplicitDef())
150 for (const MachineOperand &Op : II->operands()) {
175 for (unsigned i = 0; i < II->getNumOperands(); ++i) {
176 if (II->getOperand(i).isReg() &&
177 (II->getOperand(i).isUse() || II->getOperand(i).isDef())) {
177 (II->getOperand(i).isUse() || II->getOperand(i).isDef())) {
180 Register Reg = II->getOperand(i).getReg();
186 if (localBegin->modifiesRegister(Reg, TRI) ||
187 localBegin->readsRegister(Reg, TRI))
202 if (MII->mayStore())
206 if (MII->isCall())
220 if (MII->getOpcode() == TargetOpcode::KILL ||
221 MII->getOpcode() == TargetOpcode::PHI ||
222 MII->getOpcode() == TargetOpcode::COPY)
229 if (MII->getOpcode() == Hexagon::LDriw_pred ||
230 MII->getOpcode() == Hexagon::STriw_pred)
304 if (localII->isDebugInstr())
314 if (localII->modifiesRegister(pReg, TRI) ||
315 localII->readsRegister(pReg, TRI))
325 if (localII->modifiesRegister(cmpReg1, TRI) ||
326 (secondReg && localII->modifiesRegister(cmpOp2, TRI)))
675 bool MO1IsKill = cmpPos->killsRegister(cmpReg1, QRI);
676 bool MO2IsKill = isSecondOpReg && cmpPos->killsRegister(cmpOp2, QRI);
lib/Target/Hexagon/HexagonVLIWPacketizer.cpp 197 MachineInstr &SingleI = *BundleIt->getNextNode();
200 BundleIt->eraseFromParent();
236 if (MI->isKill()) {
lib/Target/Lanai/LanaiAsmPrinter.cpp 233 while (I != Pred->begin() && !(--I)->isTerminator()) {
236 return !I->isBarrier();
lib/Target/Lanai/LanaiFrameLowering.cpp 183 DebugLoc DL = MBBI->getDebugLoc();
lib/Target/Lanai/LanaiInstrInfo.cpp 56 DL = Position->getDebugLoc();
76 DL = Position->getDebugLoc();
576 if (Instruction->isDebugInstr())
586 if (!Instruction->isBranch())
590 if (Instruction->getOpcode() == Lanai::BT) {
592 TrueBlock = Instruction->getOperand(0).getMBB();
598 std::next(Instruction)->eraseFromParent();
605 if (MBB.isLayoutSuccessor(Instruction->getOperand(0).getMBB())) {
607 Instruction->eraseFromParent();
613 TrueBlock = Instruction->getOperand(0).getMBB();
618 unsigned Opcode = Instruction->getOpcode();
626 static_cast<LPCC::CondCode>(Instruction->getOperand(1).getImm());
630 TrueBlock = Instruction->getOperand(0).getMBB();
701 if (Instruction->isDebugInstr())
703 if (Instruction->getOpcode() != Lanai::BT &&
704 Instruction->getOpcode() != Lanai::BRCC) {
709 Instruction->eraseFromParent();
lib/Target/Lanai/LanaiMemAluCombiner.cpp 191 for (MachineInstr::const_mop_iterator Mop = Instr->operands_begin();
192 Mop != Instr->operands_end(); ++Mop) {
241 MachineOperand Dest = MemInstr->getOperand(0);
242 MachineOperand Base = MemInstr->getOperand(1);
243 MachineOperand MemOffset = MemInstr->getOperand(2);
244 MachineOperand AluOffset = AluInstr->getOperand(2);
251 LPAC::AluCode AluOpcode = mergedAluCode(AluInstr->getOpcode());
252 unsigned NewOpc = mergedOpcode(MemInstr->getOpcode(), AluOffset.isImm());
259 BuildMI(*BB, MemInstr, MemInstr->getDebugLoc(), TII->get(NewOpc));
280 InstrBuilder.setMemRefs(MemInstr->memoperands());
289 if (AluIter->getNumOperands() != 3)
292 MachineOperand &Dest = AluIter->getOperand(0);
293 MachineOperand &Op1 = AluIter->getOperand(1);
294 MachineOperand &Op2 = AluIter->getOperand(2);
304 if (AluIter->getOpcode() != Lanai::ADD_I_LO)
331 MachineOperand *Base = &MemInstr->getOperand(1);
332 MachineOperand *Offset = &MemInstr->getOperand(2);
333 bool IsSpls = isSpls(MemInstr->getOpcode());
345 if (First->isDebugInstr())
372 MachineOperand AluOperand = MBBIter->getOperand(3);
373 unsigned int DestReg = MBBIter->getOperand(0).getReg(),
374 BaseReg = MBBIter->getOperand(1).getReg();
lib/Target/MSP430/MSP430BranchSelector.cpp 124 if (MI->getOpcode() != MSP430::JCC && MI->getOpcode() != MSP430::JMP) {
124 if (MI->getOpcode() != MSP430::JCC && MI->getOpcode() != MSP430::JMP) {
128 MachineBasicBlock *DestBB = MI->getOperand(0).getMBB();
146 if (MI->getOpcode() == MSP430::JCC && std::next(MI) != EE) {
183 if (MI->getOpcode() == MSP430::JCC) {
192 Cond.push_back(MI->getOperand(1));
lib/Target/MSP430/MSP430FrameLowering.cpp 49 DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
82 while (MBBI != MBB.end() && (MBBI->getOpcode() == MSP430::PUSH16r))
86 DL = MBBI->getDebugLoc();
114 unsigned RetOpcode = MBBI->getOpcode();
115 DebugLoc DL = MBBI->getDebugLoc();
142 unsigned Opc = PI->getOpcode();
143 if (Opc != MSP430::POP16r && !PI->isTerminator())
148 DL = MBBI->getDebugLoc();
188 if (MI != MBB.end()) DL = MI->getDebugLoc();
214 if (MI != MBB.end()) DL = MI->getDebugLoc();
270 } else if (I->getOpcode() == TII.getCallFrameDestroyOpcode()) {
lib/Target/MSP430/MSP430InstrInfo.cpp 42 if (MI != MBB.end()) DL = MI->getDebugLoc();
69 if (MI != MBB.end()) DL = MI->getDebugLoc();
115 if (I->isDebugInstr())
117 if (I->getOpcode() != MSP430::JMP &&
118 I->getOpcode() != MSP430::JCC &&
119 I->getOpcode() != MSP430::Br &&
120 I->getOpcode() != MSP430::Bm)
123 I->eraseFromParent();
185 if (I->isDebugInstr())
195 if (!I->isBranch())
199 if (I->getOpcode() == MSP430::Br ||
200 I->getOpcode() == MSP430::Bm)
204 if (I->getOpcode() == MSP430::JMP) {
206 TBB = I->getOperand(0).getMBB();
212 std::next(I)->eraseFromParent();
217 if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
219 I->eraseFromParent();
225 TBB = I->getOperand(0).getMBB();
230 assert(I->getOpcode() == MSP430::JCC && "Invalid conditional branch");
232 static_cast<MSP430CC::CondCodes>(I->getOperand(1).getImm());
239 TBB = I->getOperand(0).getMBB();
251 if (TBB != I->getOperand(0).getMBB())
lib/Target/Mips/Mips16FrameLowering.cpp 97 DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
lib/Target/Mips/Mips16InstrInfo.cpp 117 if (I != MBB.end()) DL = I->getDebugLoc();
135 if (I != MBB.end()) DL = I->getDebugLoc();
247 DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
356 (*II->getParent()->getParent(), &Mips::CPU16RegsRegClass);
358 for (unsigned i = 0, e = II->getNumOperands(); i != e; ++i) {
359 MachineOperand &MO = II->getOperand(i);
374 for (unsigned i = 0, e = II->getNumOperands(); i != e; ++i) {
375 MachineOperand &MO = II->getOperand(i);
455 BuildMI(MBB, I, I->getDebugLoc(), get(Opc));
lib/Target/Mips/Mips16RegisterInfo.cpp 135 DebugLoc DL = II->getDebugLoc();
lib/Target/Mips/MipsAsmPrinter.cpp 508 while (I != Pred->begin() && !(--I)->isTerminator()) ;
510 return !I->isBarrier();
lib/Target/Mips/MipsBranchExpansion.cpp 193 Iter I = Position, E = Position->getParent()->end();
195 [](const Iter &Insn) { return Insn->isTransient(); });
240 if (!B->isDebugInstr())
253 (!LastBr->isConditionalBranch() && !LastBr->isUnconditionalBranch()))
253 (!LastBr->isConditionalBranch() && !LastBr->isUnconditionalBranch()))
261 (!FirstBr->isConditionalBranch() && !FirstBr->isUnconditionalBranch()))
261 (!FirstBr->isConditionalBranch() && !FirstBr->isUnconditionalBranch()))
264 assert(!FirstBr->isIndirectBranch() && "Unexpected indirect branch found.");
337 unsigned NewOpc = TII->getOppositeBranchOpc(Br->getOpcode());
342 for (unsigned I = 0, E = Br->getDesc().getNumOperands(); I < E; ++I) {
343 MachineOperand &MO = Br->getOperand(I);
355 if (Br->hasDelaySlot()) {
358 assert(Br->isBundledWithSucc());
362 Br->eraseFromParent();
497 LongBrMBB->rbegin()->bundleWithPred();
529 BalTgtMBB->rbegin()->bundleWithPred();
608 LongBrMBB->rbegin()->bundleWithPred();
631 BalTgtMBB->rbegin()->bundleWithPred();
757 MachineBasicBlock::instr_iterator Iit = I->getIterator();
762 BuildMI(*MFp, I->getDebugLoc(), TII->get(Mips::NOP)));
792 if ((Br != End) && Br->isBranch() && !Br->isIndirectBranch() &&
792 if ((Br != End) && Br->isBranch() && !Br->isIndirectBranch() &&
793 (Br->isConditionalBranch() ||
794 (Br->isUnconditionalBranch() && IsPIC))) {
806 !TII->isBranchOffsetInRange(Br->getOpcode(), Offset)) {
lib/Target/Mips/MipsDelaySlotFiller.cpp 313 MachineFunction *MF = Filler->getParent()->getParent();
327 for (unsigned I = 0, E = Filler->getNumOperands(); I != E; ++I) {
328 const MachineOperand &MO = Filler->getOperand(I);
564 std::next(Branch)->eraseFromParent();
617 } else if (I->isTerminator()) {
660 I = replaceWithCompactBranch(MBB, I, I->getDebugLoc());
666 BuildMI(MBB, std::next(I), I->getDebugLoc(), TII->get(Mips::NOP));
685 if (CurrI->isDebugInstr())
691 assert((!CurrI->isCall() && !CurrI->isReturn() && !CurrI->isBranch()) &&
691 assert((!CurrI->isCall() && !CurrI->isReturn() && !CurrI->isBranch()) &&
691 assert((!CurrI->isCall() && !CurrI->isReturn() && !CurrI->isBranch()) &&
694 if (CurrI->isKill()) {
695 CurrI->eraseFromParent();
709 if ((isBasePlusOffsetMemoryAccess(CurrI->getOpcode(), &AddrIdx) &&
710 baseRegNeedsLoadStoreMask(CurrI->getOperand(AddrIdx).getReg())) ||
711 CurrI->modifiesRegister(Mips::SP, STI.getRegisterInfo()))
767 if (DisableForwardSearch || !Slot->isCall())
827 Filler->eraseFromParent();
lib/Target/Mips/MipsExpandPseudo.cpp 81 DebugLoc DL = I->getDebugLoc();
88 I->getOpcode() == Mips::ATOMIC_CMP_SWAP_I8_POSTRA ? Mips::SEB : Mips::SEH;
102 Register Dest = I->getOperand(0).getReg();
103 Register Ptr = I->getOperand(1).getReg();
104 Register Mask = I->getOperand(2).getReg();
105 Register ShiftCmpVal = I->getOperand(3).getReg();
106 Register Mask2 = I->getOperand(4).getReg();
107 Register ShiftNewVal = I->getOperand(5).getReg();
108 Register ShiftAmnt = I->getOperand(6).getReg();
109 Register Scratch = I->getOperand(7).getReg();
110 Register Scratch2 = I->getOperand(8).getReg();
182 I->getOpcode() == Mips::ATOMIC_CMP_SWAP_I16_POSTRA ? 16 : 24;
198 I->eraseFromParent();
207 I->getOpcode() == Mips::ATOMIC_CMP_SWAP_I32_POSTRA ? 4 : 8;
211 DebugLoc DL = I->getDebugLoc();
243 Register Dest = I->getOperand(0).getReg();
244 Register Ptr = I->getOperand(1).getReg();
245 Register OldVal = I->getOperand(2).getReg();
246 Register NewVal = I->getOperand(3).getReg();
247 Register Scratch = I->getOperand(4).getReg();
298 I->eraseFromParent();
309 DebugLoc DL = I->getDebugLoc();
330 switch (I->getOpcode()) {
377 Register Dest = I->getOperand(0).getReg();
378 Register Ptr = I->getOperand(1).getReg();
379 Register Incr = I->getOperand(2).getReg();
380 Register Mask = I->getOperand(3).getReg();
381 Register Mask2 = I->getOperand(4).getReg();
382 Register ShiftAmnt = I->getOperand(5).getReg();
383 Register OldVal = I->getOperand(6).getReg();
384 Register BinOpRes = I->getOperand(7).getReg();
385 Register StoreVal = I->getOperand(8).getReg();
477 I->eraseFromParent();
489 DebugLoc DL = I->getDebugLoc();
516 Register OldVal = I->getOperand(0).getReg();
517 Register Ptr = I->getOperand(1).getReg();
518 Register Incr = I->getOperand(2).getReg();
519 Register Scratch = I->getOperand(3).getReg();
526 switch (I->getOpcode()) {
611 I->eraseFromParent();
626 switch (MBBI->getOpcode()) {
lib/Target/Mips/MipsFrameLowering.cpp 143 int64_t Amount = I->getOperand(0).getImm();
144 if (I->getOpcode() == Mips::ADJCALLSTACKDOWN)
lib/Target/Mips/MipsInstrInfo.cpp 165 if (I->isDebugInstr()) {
169 if (!getAnalyzableBrOpc(I->getOpcode()))
172 I->eraseFromParent();
197 while (I != REnd && I->isDebugInstr())
222 while (I != REnd && I->isDebugInstr())
440 unsigned Opcode = I->getOpcode();
451 if (I->getOperand(1).getReg() == Subtarget.getABI().GetZeroReg())
465 if (Subtarget.hasMips32r6() && (I->getNumOperands() > 1) &&
466 (I->getOperand(0).isReg() &&
467 (I->getOperand(0).getReg() == Mips::ZERO ||
468 I->getOperand(0).getReg() == Mips::ZERO_64)) &&
469 (I->getOperand(1).isReg() &&
470 (I->getOperand(1).getReg() == Mips::ZERO ||
471 I->getOperand(1).getReg() == Mips::ZERO_64)))
484 else if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
484 else if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
491 else if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
491 else if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
495 if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
495 if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
499 if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
499 if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
509 if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
509 if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
513 if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
513 if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
519 if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
519 if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
523 if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
523 if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
609 if (I->isBranch() && !I->isPseudo()) {
609 if (I->isBranch() && !I->isPseudo()) {
610 auto TRI = I->getParent()->getParent()->getSubtarget().getRegisterInfo();
611 ZeroOperandPosition = I->findRegisterUseOperandIdx(Mips::ZERO, false, TRI);
638 MIB = BuildMI(*I->getParent(), I, I->getDebugLoc(), get(NewOpc));
638 MIB = BuildMI(*I->getParent(), I, I->getDebugLoc(), get(NewOpc));
650 for (unsigned J = 0, E = I->getDesc().getNumOperands(); J < E; ++J) {
651 MIB.add(I->getOperand(J));
658 for (unsigned J = I->getDesc().getNumOperands(), E = I->getNumOperands();
658 for (unsigned J = I->getDesc().getNumOperands(), E = I->getNumOperands();
660 const MachineOperand &MO = I->getOperand(J);
667 for (unsigned J = 0, E = I->getDesc().getNumOperands(); J < E; ++J) {
671 MIB.add(I->getOperand(J));
lib/Target/Mips/MipsOptimizePICCall.cpp 154 Register SrcReg = I->getOperand(0).getReg();
156 BuildMI(*MBB, I, I->getDebugLoc(), TII.get(TargetOpcode::COPY), DstReg)
158 I->getOperand(0).setReg(DstReg);
lib/Target/Mips/MipsSEFrameLowering.cpp 116 switch(I->getOpcode()) {
171 assert(I->getOperand(0).isReg() && I->getOperand(1).isFI());
171 assert(I->getOperand(0).isReg() && I->getOperand(1).isFI());
175 Register Dst = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex();
175 Register Dst = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex();
178 BuildMI(MBB, I, I->getDebugLoc(), TII.get(TargetOpcode::COPY), Dst)
186 assert(I->getOperand(0).isReg() && I->getOperand(1).isFI());
186 assert(I->getOperand(0).isReg() && I->getOperand(1).isFI());
190 Register Src = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex();
190 Register Src = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex();
192 BuildMI(MBB, I, I->getDebugLoc(), TII.get(TargetOpcode::COPY), VR)
193 .addReg(Src, getKillRegState(I->getOperand(0).isKill()));
204 assert(I->getOperand(0).isReg() && I->getOperand(1).isFI());
204 assert(I->getOperand(0).isReg() && I->getOperand(1).isFI());
209 Register Dst = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex();
209 Register Dst = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex();
212 DebugLoc DL = I->getDebugLoc();
229 assert(I->getOperand(0).isReg() && I->getOperand(1).isFI());
229 assert(I->getOperand(0).isReg() && I->getOperand(1).isFI());
234 Register Src = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex();
234 Register Src = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex();
235 unsigned SrcKill = getKillRegState(I->getOperand(0).isKill());
236 DebugLoc DL = I->getDebugLoc();
245 Register Src = I->getOperand(1).getReg();
261 unsigned Dst = I->getOperand(0).getReg(), Src = I->getOperand(1).getReg();
261 unsigned Dst = I->getOperand(0).getReg(), Src = I->getOperand(1).getReg();
267 unsigned SrcKill = getKillRegState(I->getOperand(1).isKill());
270 DebugLoc DL = I->getDebugLoc();
305 if (I->getNumOperands() == 4 && I->getOperand(3).isReg()
305 if (I->getNumOperands() == 4 && I->getOperand(3).isReg()
306 && I->getOperand(3).getReg() == Mips::SP) {
307 Register DstReg = I->getOperand(0).getReg();
308 Register LoReg = I->getOperand(1).getReg();
309 Register HiReg = I->getOperand(2).getReg();
326 TII.storeRegToStack(MBB, I, LoReg, I->getOperand(1).isKill(), FI, RC,
328 TII.storeRegToStack(MBB, I, HiReg, I->getOperand(2).isKill(), FI, RC,
345 const MachineOperand &Op1 = I->getOperand(1);
346 const MachineOperand &Op2 = I->getOperand(2);
349 Register DstReg = I->getOperand(0).getReg();
350 BuildMI(MBB, I, I->getDebugLoc(), TII.get(Mips::IMPLICIT_DEF), DstReg);
370 if (I->getNumOperands() == 4 && I->getOperand(3).isReg()
370 if (I->getNumOperands() == 4 && I->getOperand(3).isReg()
371 && I->getOperand(3).getReg() == Mips::SP) {
372 Register DstReg = I->getOperand(0).getReg();
564 DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
699 DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
751 DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
818 DebugLoc DL = MI->getDebugLoc();
lib/Target/Mips/MipsSEInstrInfo.cpp 328 if (I != MBB.end()) DL = I->getDebugLoc();
682 MIB = BuildMI(MBB, I, I->getDebugLoc(), get(Mips::PseudoReturn64))
685 MIB = BuildMI(MBB, I, I->getDebugLoc(), get(Mips::PseudoReturn))
689 for (auto & MO : I->operands()) {
697 BuildMI(MBB, I, I->getDebugLoc(), get(Mips::ERET));
715 BuildMI(MBB, I, I->getDebugLoc(), get(NewOpc), I->getOperand(0).getReg());
715 BuildMI(MBB, I, I->getDebugLoc(), get(NewOpc), I->getOperand(0).getReg());
729 DebugLoc DL = I->getDebugLoc();
730 const MachineOperand &SrcLo = I->getOperand(1), &SrcHi = I->getOperand(2);
730 const MachineOperand &SrcLo = I->getOperand(1), &SrcHi = I->getOperand(2);
737 Register DstReg = I->getOperand(0).getReg();
753 const MachineOperand &Dst = I->getOperand(0), &Src = I->getOperand(1);
753 const MachineOperand &Dst = I->getOperand(0), &Src = I->getOperand(1);
756 DebugLoc DL = I->getDebugLoc();
776 Register DstReg = I->getOperand(0).getReg();
777 Register SrcReg = I->getOperand(1).getReg();
778 unsigned N = I->getOperand(2).getImm();
779 DebugLoc dl = I->getDebugLoc();
818 Register DstReg = I->getOperand(0).getReg();
819 unsigned LoReg = I->getOperand(1).getReg(), HiReg = I->getOperand(2).getReg();
819 unsigned LoReg = I->getOperand(1).getReg(), HiReg = I->getOperand(2).getReg();
821 DebugLoc dl = I->getDebugLoc();
886 Register OffsetReg = I->getOperand(0).getReg();
887 Register TargetReg = I->getOperand(1).getReg();
894 BuildMI(MBB, I, I->getDebugLoc(), get(ADDU), T9)
897 BuildMI(MBB, I, I->getDebugLoc(), get(ADDU), RA)
900 BuildMI(MBB, I, I->getDebugLoc(), get(ADDU), SP).addReg(SP).addReg(OffsetReg);
lib/Target/Mips/MipsSERegisterInfo.cpp 221 DebugLoc DL = II->getDebugLoc();
240 DebugLoc DL = II->getDebugLoc();
lib/Target/NVPTX/NVPTXInstrInfo.cpp 146 I->eraseFromParent();
161 if (I->getOpcode() != NVPTX::GOTO && I->getOpcode() != NVPTX::CBranch)
161 if (I->getOpcode() != NVPTX::GOTO && I->getOpcode() != NVPTX::CBranch)
165 I->eraseFromParent();
172 if (I->getOpcode() != NVPTX::CBranch)
176 I->eraseFromParent();
lib/Target/PowerPC/PPCAsmPrinter.cpp 363 if (MII == MBB.end() || MII->isCall() ||
364 MII->getOpcode() == PPC::DBG_VALUE ||
365 MII->getOpcode() == TargetOpcode::PATCHPOINT ||
366 MII->getOpcode() == TargetOpcode::STACKMAP)
lib/Target/PowerPC/PPCBranchCoalescing.cpp 539 for (auto &Def : I->defs())
lib/Target/PowerPC/PPCBranchSelector.cpp 304 if (I->getOpcode() == PPC::BCC && !I->getOperand(2).isImm())
304 if (I->getOpcode() == PPC::BCC && !I->getOperand(2).isImm())
305 Dest = I->getOperand(2).getMBB();
306 else if ((I->getOpcode() == PPC::BC || I->getOpcode() == PPC::BCn) &&
306 else if ((I->getOpcode() == PPC::BC || I->getOpcode() == PPC::BCn) &&
307 !I->getOperand(1).isImm())
308 Dest = I->getOperand(1).getMBB();
309 else if ((I->getOpcode() == PPC::BDNZ8 || I->getOpcode() == PPC::BDNZ ||
309 else if ((I->getOpcode() == PPC::BDNZ8 || I->getOpcode() == PPC::BDNZ ||
310 I->getOpcode() == PPC::BDZ8 || I->getOpcode() == PPC::BDZ) &&
310 I->getOpcode() == PPC::BDZ8 || I->getOpcode() == PPC::BDZ) &&
311 !I->getOperand(0).isImm())
312 Dest = I->getOperand(0).getMBB();
333 if (I->getOpcode() == PPC::BCC) {
338 PPC::Predicate Pred = (PPC::Predicate)I->getOperand(0).getImm();
339 Register CRReg = I->getOperand(1).getReg();
344 } else if (I->getOpcode() == PPC::BC) {
345 Register CRBit = I->getOperand(0).getReg();
347 } else if (I->getOpcode() == PPC::BCn) {
348 Register CRBit = I->getOperand(0).getReg();
350 } else if (I->getOpcode() == PPC::BDNZ) {
352 } else if (I->getOpcode() == PPC::BDNZ8) {
354 } else if (I->getOpcode() == PPC::BDZ) {
356 } else if (I->getOpcode() == PPC::BDZ8) {
lib/Target/PowerPC/PPCCTRLoops.cpp 148 unsigned Opc = I->getOpcode();
158 << printMBBReference(*BI->getParent()) << " ("
159 << BI->getParent()->getFullName() << ") instruction "
175 << printMBBReference(*BI->getParent()) << " ("
176 << BI->getParent()->getFullName() << ") instruction "
210 unsigned Opc = MII->getOpcode();
lib/Target/PowerPC/PPCEarlyReturn.cpp 60 (I->getOpcode() != PPC::BLR && I->getOpcode() != PPC::BLR8) ||
60 (I->getOpcode() != PPC::BLR && I->getOpcode() != PPC::BLR8) ||
76 if (J->getOpcode() == PPC::B) {
77 if (J->getOperand(0).getMBB() == &ReturnMBB) {
80 BuildMI(**PI, J, J->getDebugLoc(), TII->get(I->getOpcode()))
80 BuildMI(**PI, J, J->getDebugLoc(), TII->get(I->getOpcode()))
83 K->eraseFromParent();
88 } else if (J->getOpcode() == PPC::BCC) {
89 if (J->getOperand(2).getMBB() == &ReturnMBB) {
92 BuildMI(**PI, J, J->getDebugLoc(), TII->get(PPC::BCCLR))
93 .addImm(J->getOperand(0).getImm())
94 .addReg(J->getOperand(1).getReg())
97 K->eraseFromParent();
102 } else if (J->getOpcode() == PPC::BC || J->getOpcode() == PPC::BCn) {
102 } else if (J->getOpcode() == PPC::BC || J->getOpcode() == PPC::BCn) {
103 if (J->getOperand(1).getMBB() == &ReturnMBB) {
107 **PI, J, J->getDebugLoc(),
108 TII->get(J->getOpcode() == PPC::BC ? PPC::BCLR : PPC::BCLRn))
109 .addReg(J->getOperand(0).getReg())
112 K->eraseFromParent();
117 } else if (J->isBranch()) {
118 if (J->isIndirectBranch()) {
122 for (unsigned i = 0; i < J->getNumOperands(); ++i)
123 if (J->getOperand(i).isMBB() &&
124 J->getOperand(i).getMBB() == &ReturnMBB)
126 } else if (!J->isTerminator() && !J->isDebugInstr())
126 } else if (!J->isTerminator() && !J->isDebugInstr())
lib/Target/PowerPC/PPCFrameLowering.cpp 300 assert(MBBI != Entry->end() && MBBI->getOpcode() == PPC::MTVRSAVE);
301 MBBI->eraseFromParent();
312 if (MBBI->getOpcode() == PPC::MTVRSAVE) {
313 MBBI->eraseFromParent(); // remove it.
328 assert(MBBI->getOpcode() == PPC::MFVRSAVE && "VRSAVE instrs wandered?");
329 MBBI->eraseFromParent();
572 for (unsigned I = 0, E = MBBI->getNumOperands(); I != E; ++I) {
573 MachineOperand &MO = MBBI->getOperand(I);
801 if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) {
1377 dl = MBBI->getDebugLoc();
1463 bool IsReturnBlock = (MBBI != MBB.end() && MBBI->isReturn());
1466 unsigned RetOpcode = MBBI->getOpcode();
1476 MachineOperand &StackAdjust = MBBI->getOperand(1);
1697 unsigned RetOpcode = MBBI->getOpcode();
1730 DebugLoc dl = MBBI->getDebugLoc();
1734 unsigned RetOpcode = MBBI->getOpcode();
1737 MachineOperand &JumpTarget = MBBI->getOperand(0);
1742 assert(MBBI->getOperand(0).isReg() && "Expecting register operand.");
1746 MachineOperand &JumpTarget = MBBI->getOperand(0);
1750 MachineOperand &JumpTarget = MBBI->getOperand(0);
1755 assert(MBBI->getOperand(0).isReg() && "Expecting register operand.");
1759 MachineOperand &JumpTarget = MBBI->getOperand(0);
2313 I->getOpcode() == PPC::ADJCALLSTACKUP) {
2315 if (int CalleeAmt = I->getOperand(1).getImm()) {
2324 const DebugLoc &dl = I->getDebugLoc();
lib/Target/PowerPC/PPCISelDAGToDAG.cpp 418 while (I2 != BB->begin() && (--I2)->isTerminator())
lib/Target/PowerPC/PPCInstrInfo.cpp 513 if (I->getOpcode() == PPC::B &&
514 MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
515 I->eraseFromParent();
662 I->eraseFromParent();
678 if (I->getOpcode() != PPC::B && I->getOpcode() != PPC::BCC &&
678 if (I->getOpcode() != PPC::B && I->getOpcode() != PPC::BCC &&
679 I->getOpcode() != PPC::BC && I->getOpcode() != PPC::BCn &&
679 I->getOpcode() != PPC::BC && I->getOpcode() != PPC::BCn &&
680 I->getOpcode() != PPC::BDNZ8 && I->getOpcode() != PPC::BDNZ &&
680 I->getOpcode() != PPC::BDNZ8 && I->getOpcode() != PPC::BDNZ &&
681 I->getOpcode() != PPC::BDZ8 && I->getOpcode() != PPC::BDZ)
681 I->getOpcode() != PPC::BDZ8 && I->getOpcode() != PPC::BDZ)
685 I->eraseFromParent();
691 if (I->getOpcode() != PPC::BCC &&
692 I->getOpcode() != PPC::BC && I->getOpcode() != PPC::BCn &&
692 I->getOpcode() != PPC::BC && I->getOpcode() != PPC::BCn &&
693 I->getOpcode() != PPC::BDNZ8 && I->getOpcode() != PPC::BDNZ &&
693 I->getOpcode() != PPC::BDNZ8 && I->getOpcode() != PPC::BDNZ &&
694 I->getOpcode() != PPC::BDZ8 && I->getOpcode() != PPC::BDZ)
694 I->getOpcode() != PPC::BDZ8 && I->getOpcode() != PPC::BDZ)
698 I->eraseFromParent();
1285 if (MI != MBB.end()) DL = MI->getDebugLoc();
1395 if (I->definesRegister(PPC::CTR) || I->definesRegister(PPC::CTR8))
1395 if (I->definesRegister(PPC::CTR) || I->definesRegister(PPC::CTR8))
2332 if (It->modifiesRegister(Reg, TRI))
2334 if (It->readsRegister(Reg, TRI))
2496 if (It->isDebugInstr() || It->isPosition())
2496 if (It->isDebugInstr() || It->isPosition())
2502 for (int i = 0, e = It->getNumOperands(); i != e; ++i)
2508 if ((MO = It->findRegisterUseOperand(RegNo, false, &getRegisterInfo()))) {
2513 } else if ((MO = It->findRegisterDefOperand(RegNo, false, true,
2605 if (It->modifiesRegister(Reg, &getRegisterInfo()))
3525 if (It->modifiesRegister(Reg, &getRegisterInfo()) && (&*It) != &DefMI)
3527 else if (It->killsRegister(Reg, &getRegisterInfo()) && (&*It) != &DefMI)
4236 if (I != LoopBB->end() && isBDNZ(I->getOpcode())) {
lib/Target/PowerPC/PPCPreEmitPeephole.cpp 231 if (It->modifiesRegister(CRBit, TRI)) {
232 if ((It->getOpcode() == PPC::CRUNSET ||
233 It->getOpcode() == PPC::CRSET) &&
234 It->getOperand(0).getReg() == CRBit)
238 if (It->readsRegister(CRBit, TRI))
255 if (It->isDebugInstr()) continue;
256 assert(It->isTerminator() && "Non-terminator after a terminator");
lib/Target/PowerPC/PPCReduceCRLogicals.cpp 232 assert(FirstTerminator->getOperand(0).isReg() &&
234 FirstTerminator->getOperand(0).setReg(BSI.NewCond->getOperand(0).getReg());
237 FirstTerminator->setDesc(TII->get(InvertedOpcode));
560 if ((--Me)->modifiesRegister(CopySrc, TRI))
lib/Target/PowerPC/PPCRegisterInfo.cpp 754 if (Ins->modifiesRegister(SrcReg, TRI))
762 if (!Ins->isDebugInstr())
771 switch (Ins->getOpcode()) {
1228 DL = Ins->getDebugLoc();
lib/Target/PowerPC/PPCVSXFMAMutate.cpp 163 if (J->readsVirtualRegister(AddendMI->getOperand(0).getReg())) {
167 if (J->modifiesRegister(AddendSrcReg, TRI) ||
168 J->killsRegister(AddendSrcReg, TRI)) {
lib/Target/PowerPC/PPCVSXSwapRemoval.cpp 919 LLVM_DEBUG(std::prev(InsertPoint)->dump());
922 LLVM_DEBUG(std::prev(InsertPoint)->dump());
927 LLVM_DEBUG(std::prev(InsertPoint)->dump());
931 LLVM_DEBUG(std::prev(InsertPoint)->dump());
lib/Target/RISCV/RISCVExpandPseudoInsts.cpp 101 switch (MBBI->getOpcode()) {
lib/Target/RISCV/RISCVFrameLowering.cpp 237 DebugLoc DL = MBBI->getDebugLoc();
280 if (I->mayLoad() && I->getOperand(0).isReg()) {
280 if (I->mayLoad() && I->getOperand(0).isReg()) {
281 Register DestReg = I->getOperand(0).getReg();
443 DebugLoc DL = MI->getDebugLoc();
451 int64_t Amount = MI->getOperand(0).getImm();
457 if (MI->getOpcode() == RISCV::ADJCALLSTACKDOWN)
lib/Target/RISCV/RISCVISelLowering.cpp 1264 if (SequenceMBBI->isDebugInstr())
1267 if (SequenceMBBI->getOperand(1).getReg() != LHS ||
1268 SequenceMBBI->getOperand(2).getReg() != RHS ||
1269 SequenceMBBI->getOperand(3).getImm() != CC ||
1270 SelectDests.count(SequenceMBBI->getOperand(4).getReg()) ||
1271 SelectDests.count(SequenceMBBI->getOperand(5).getReg()))
1274 SequenceMBBI->collectDebugValues(SelectDebugValues);
1275 SelectDests.insert(SequenceMBBI->getOperand(0).getReg());
1277 if (SequenceMBBI->hasUnmodeledSideEffects() ||
1278 SequenceMBBI->mayLoadOrStore())
1280 if (llvm::any_of(SequenceMBBI->operands(), [&](MachineOperand &MO) {
lib/Target/RISCV/RISCVInstrInfo.cpp 117 DL = I->getDebugLoc();
144 DL = I->getDebugLoc();
253 if (J->getDesc().isUnconditionalBranch() ||
254 J->getDesc().isIndirectBranch()) {
263 std::next(FirstUncondOrIndirectBr)->eraseFromParent();
270 if (I->getDesc().isIndirectBranch())
278 if (NumTerminators == 1 && I->getDesc().isUnconditionalBranch()) {
279 TBB = I->getOperand(0).getMBB();
284 if (NumTerminators == 1 && I->getDesc().isConditionalBranch()) {
290 if (NumTerminators == 2 && std::prev(I)->getDesc().isConditionalBranch() &&
291 I->getDesc().isUnconditionalBranch()) {
293 FBB = I->getOperand(0).getMBB();
309 if (!I->getDesc().isUnconditionalBranch() &&
310 !I->getDesc().isConditionalBranch())
316 I->eraseFromParent();
323 if (!I->getDesc().isConditionalBranch())
329 I->eraseFromParent();
lib/Target/Sparc/DelaySlotFiller.cpp 117 (MI->getOpcode() == SP::RESTORErr
118 || MI->getOpcode() == SP::RESTOREri)) {
126 (MI->getOpcode() == SP::FCMPS || MI->getOpcode() == SP::FCMPD
126 (MI->getOpcode() == SP::FCMPS || MI->getOpcode() == SP::FCMPD
127 || MI->getOpcode() == SP::FCMPQ)) {
128 BuildMI(MBB, I, MI->getDebugLoc(), TII->get(SP::NOP));
134 if (!MI->hasDelaySlot())
146 BuildMI(MBB, I, MI->getDebugLoc(), TII->get(SP::NOP));
155 BuildMI(MBB, ++J, MI->getDebugLoc(),
178 if (slot->getOpcode() == SP::RET || slot->getOpcode() == SP::TLS_CALL)
178 if (slot->getOpcode() == SP::RET || slot->getOpcode() == SP::TLS_CALL)
181 if (slot->getOpcode() == SP::RETL) {
185 if (J->getOpcode() == SP::RESTORErr
186 || J->getOpcode() == SP::RESTOREri) {
188 slot->setDesc(Subtarget->getInstrInfo()->get(SP::RET));
194 if (slot->isCall())
210 if (I->isDebugInstr())
213 if (I->hasUnmodeledSideEffects() || I->isInlineAsm() || I->isPosition() ||
213 if (I->hasUnmodeledSideEffects() || I->isInlineAsm() || I->isPosition() ||
213 if (I->hasUnmodeledSideEffects() || I->isInlineAsm() || I->isPosition() ||
214 I->hasDelaySlot() || I->isBundledWithSucc())
214 I->hasDelaySlot() || I->isBundledWithSucc())
234 if (candidate->isImplicitDef() || candidate->isKill())
234 if (candidate->isImplicitDef() || candidate->isKill())
237 if (candidate->mayLoad()) {
243 if (candidate->mayStore()) {
251 for (unsigned i = 0, e = candidate->getNumOperands(); i!= e; ++i) {
252 const MachineOperand &MO = candidate->getOperand(i);
270 unsigned Opcode = candidate->getOpcode();
296 switch(MI->getOpcode()) {
301 assert(MI->getNumOperands() >= 2);
302 const MachineOperand &Reg = MI->getOperand(0);
307 const MachineOperand &Operand1 = MI->getOperand(1);
322 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
323 const MachineOperand &MO = MI->getOperand(i);
335 if (MO.isImplicit() && MI->getOpcode() == SP::RETL)
355 if (!I->isCall())
359 switch (I->getOpcode()) {
367 const MachineOperand &MO = I->getOperand(structSizeOpNum);
383 Register reg = AddMI->getOperand(0).getReg();
388 RestoreMI->eraseFromParent();
391 AddMI->setDesc(TII->get((AddMI->getOpcode() == SP::ADDrr)
391 AddMI->setDesc(TII->get((AddMI->getOpcode() == SP::ADDrr)
396 AddMI->getOperand(0).setReg(reg - SP::I0 + SP::O0);
411 Register reg = OrMI->getOperand(0).getReg();
416 if (OrMI->getOpcode() == SP::ORrr
417 && OrMI->getOperand(1).getReg() != SP::G0
418 && OrMI->getOperand(2).getReg() != SP::G0)
421 if (OrMI->getOpcode() == SP::ORri
422 && OrMI->getOperand(1).getReg() != SP::G0
423 && (!OrMI->getOperand(2).isImm() || OrMI->getOperand(2).getImm() != 0))
423 && (!OrMI->getOperand(2).isImm() || OrMI->getOperand(2).getImm() != 0))
427 RestoreMI->eraseFromParent();
430 OrMI->setDesc(TII->get((OrMI->getOpcode() == SP::ORrr)
430 OrMI->setDesc(TII->get((OrMI->getOpcode() == SP::ORrr)
435 OrMI->getOperand(0).setReg(reg - SP::I0 + SP::O0);
449 Register reg = SetHiMI->getOperand(0).getReg();
453 if (!SetHiMI->getOperand(1).isImm())
456 int64_t imm = SetHiMI->getOperand(1).getImm();
465 assert(RestoreMI->getOpcode() == SP::RESTORErr);
467 RestoreMI->setDesc(TII->get(SP::RESTOREri));
469 RestoreMI->getOperand(0).setReg(reg - SP::I0 + SP::O0);
470 RestoreMI->getOperand(1).setReg(SP::G0);
471 RestoreMI->getOperand(2).ChangeToImmediate(imm);
475 SetHiMI->eraseFromParent();
488 assert(MBBI->getOpcode() == SP::RESTORErr
489 && MBBI->getOperand(0).getReg() == SP::G0
490 && MBBI->getOperand(1).getReg() == SP::G0
491 && MBBI->getOperand(2).getReg() == SP::G0);
496 if (PrevInst->isBundledWithSucc())
501 switch (PrevInst->getOpcode()) {
lib/Target/Sparc/SparcFrameLowering.cpp 226 DebugLoc dl = MBBI->getDebugLoc();
227 assert(MBBI->getOpcode() == SP::RETL &&
lib/Target/Sparc/SparcInstrInfo.cpp 234 I->eraseFromParent();
282 if (I->isDebugInstr())
285 if (I->getOpcode() != SP::BA
286 && I->getOpcode() != SP::BCOND
287 && I->getOpcode() != SP::FBCOND)
290 I->eraseFromParent();
400 if (I != MBB.end()) DL = I->getDebugLoc();
439 if (I != MBB.end()) DL = I->getDebugLoc();
lib/Target/SystemZ/SystemZAsmPrinter.cpp 585 MII->getOpcode() == TargetOpcode::PATCHPOINT ||
586 MII->getOpcode() == TargetOpcode::STACKMAP)
589 if (MII->isCall())
lib/Target/SystemZ/SystemZElimCompare.cpp 397 MBBI->clearRegisterKills(SystemZ::CC, TRI);
530 if (MBBI->modifiesRegister(SrcReg, TRI) ||
531 (SrcReg2 && MBBI->modifiesRegister(SrcReg2, TRI)))
535 MachineOperand CCMask(MBBI->getOperand(1));
539 MachineOperand Target(MBBI->getOperand(
543 RegMask = MBBI->getOperand(2).getRegMask();
546 int CCUse = MBBI->findRegisterUseOperandIdx(SystemZ::CC, false, TRI);
582 MBBI->clearRegisterKills(SrcReg, TRI);
584 MBBI->clearRegisterKills(SrcReg2, TRI);
lib/Target/SystemZ/SystemZFrameLowering.cpp 236 DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
363 if (MBBI != MBB.end() && MBBI->getOpcode() == SystemZ::STMG)
441 (MBBI->getOpcode() == SystemZ::STD ||
442 MBBI->getOpcode() == SystemZ::STDY))
448 MBBI->getOpcode() == SystemZ::VST)
482 assert(MBBI->isReturn() && "Can only insert epilogue into returning blocks");
487 unsigned Opcode = MBBI->getOpcode();
492 DebugLoc DL = MBBI->getDebugLoc();
493 uint64_t Offset = StackSize + MBBI->getOperand(AddrOpNo + 1).getImm();
500 emitIncrement(MBB, MBBI, DL, MBBI->getOperand(AddrOpNo).getReg(),
507 MBBI->setDesc(ZII->get(NewOpcode));
508 MBBI->getOperand(AddrOpNo + 1).ChangeToImmediate(Offset);
510 DebugLoc DL = MBBI->getDebugLoc();
534 switch (MI->getOpcode()) {
lib/Target/SystemZ/SystemZISelLowering.cpp 6638 if (NextMIIt->definesRegister(SystemZ::CC))
6641 assert(NextMIIt->getOperand(3).getImm() == CCValid &&
6643 if (NextMIIt->getOperand(4).getImm() == CCMask ||
6644 NextMIIt->getOperand(4).getImm() == (CCValid ^ CCMask)) {
6652 if (NextMIIt->readsVirtualRegister(SelMI->getOperand(0).getReg())) {
6656 if (NextMIIt->isDebugInstr()) {
6658 assert(NextMIIt->isDebugValue() && "Unhandled debug opcode.");
lib/Target/SystemZ/SystemZInstrInfo.cpp 67 MachineBasicBlock *MBB = MI->getParent();
77 MachineOperand &LowRegOp = MI->getOperand(0);
84 if (MI->mayStore()) {
97 MachineOperand &LowOffsetOp = MI->getOperand(2);
112 MI->setDesc(get(LowOpcode));
117 MachineBasicBlock *MBB = MI->getParent();
120 MachineOperand &OffsetMO = MI->getOperand(2);
127 MI->setDesc(get(NewOpcode));
365 if (I->isDebugInstr())
375 if (!I->isBranch())
396 std::next(I)->eraseFromParent();
404 I->eraseFromParent();
455 if (I->isDebugInstr())
457 if (!I->isBranch())
462 I->eraseFromParent();
694 if (MBB.getLastNonDebugInstr()->getOpcode() != SystemZ::Trap &&
875 DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
890 DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
1020 MachineInstr *BuiltMI = BuildMI(*InsertPt->getParent(), InsertPt,
1048 BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(), get(Opcode))
1063 BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(), get(Opcode))
1078 BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(), get(Opcode))
1093 return BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(),
1104 return BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(),
1131 return BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(),
1142 return BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(),
1191 MachineInstrBuilder MIB = BuildMI(*InsertPt->getParent(), InsertPt,
1735 DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
lib/Target/SystemZ/SystemZLDCleanup.cpp 94 switch (I->getOpcode()) {
lib/Target/SystemZ/SystemZLongBranch.cpp 289 while (MI != End && !MI->isTerminator()) {
297 if (!MI->isDebugInstr()) {
298 assert(MI->isTerminator() && "Terminator followed by non-terminator");
lib/Target/SystemZ/SystemZMachineScheduler.cpp 64 ((LastEmittedMI != nullptr && LastEmittedMI->getParent() == MBB) ?
68 if (I->isPosition() || I->isDebugInstr())
68 if (I->isPosition() || I->isDebugInstr())
110 LLVM_DEBUG(dbgs() << "** Emitting incoming branch: "; I->dump(););
111 bool TakenBranch = (I->isBranch() &&
150 if (Begin->isTerminator())
lib/Target/SystemZ/SystemZPostRewrite.cpp 89 Register DestReg = MBBI->getOperand(0).getReg();
90 Register SrcReg = MBBI->getOperand(2).getReg();
95 MBBI->setDesc(TII->get(LowOpcode));
97 MBBI->setDesc(TII->get(HighOpcode));
110 Register DestReg = MBBI->getOperand(0).getReg();
111 Register Src1Reg = MBBI->getOperand(1).getReg();
112 Register Src2Reg = MBBI->getOperand(2).getReg();
122 BuildMI(*MBBI->getParent(), MBBI, MBBI->getDebugLoc(),
122 BuildMI(*MBBI->getParent(), MBBI, MBBI->getDebugLoc(),
124 .addReg(MBBI->getOperand(1).getReg(), getRegState(MBBI->getOperand(1)));
124 .addReg(MBBI->getOperand(1).getReg(), getRegState(MBBI->getOperand(1)));
125 MBBI->getOperand(1).setReg(DestReg);
129 BuildMI(*MBBI->getParent(), MBBI, MBBI->getDebugLoc(),
129 BuildMI(*MBBI->getParent(), MBBI, MBBI->getDebugLoc(),
131 .addReg(MBBI->getOperand(2).getReg(), getRegState(MBBI->getOperand(2)));
131 .addReg(MBBI->getOperand(2).getReg(), getRegState(MBBI->getOperand(2)));
132 MBBI->getOperand(2).setReg(DestReg);
146 MBBI->setDesc(TII->get(LowOpcode));
148 MBBI->setDesc(TII->get(HighOpcode));
lib/Target/SystemZ/SystemZRegisterInfo.cpp 257 MachineBasicBlock &MBB = *MI->getParent();
262 DebugLoc DL = MI->getDebugLoc();
265 int FrameIndex = MI->getOperand(FIOperandNum).getIndex();
268 MI->getOperand(FIOperandNum + 1).getImm());
271 if (MI->isDebugValue()) {
272 MI->getOperand(FIOperandNum).ChangeToRegister(BasePtr, /*isDef*/ false);
273 MI->getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
279 unsigned Opcode = MI->getOpcode();
287 MI->getOperand(FIOperandNum).ChangeToRegister(BasePtr, false);
305 if (MI->getDesc().TSFlags & SystemZII::HasIndex
306 && MI->getOperand(FIOperandNum + 2).getReg() == 0) {
310 MI->getOperand(FIOperandNum).ChangeToRegister(BasePtr, false);
311 MI->getOperand(FIOperandNum + 2).ChangeToRegister(ScratchReg,
328 MI->getOperand(FIOperandNum).ChangeToRegister(ScratchReg,
332 MI->setDesc(TII->get(OpcodeForOffset));
333 MI->getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
388 for (const MachineOperand &MO : MII->operands())
lib/Target/WebAssembly/WebAssemblyCFGStackify.cpp 229 if (Pred->getFirstTerminator()->getOpcode() == WebAssembly::BR_ON_EXN) {
302 if (std::prev(I)->isDebugInstr() || std::prev(I)->isPosition())
302 if (std::prev(I)->isDebugInstr() || std::prev(I)->isPosition())
539 TermPos->getOpcode() != WebAssembly::RETHROW) {
566 if (std::prev(I)->isDebugInstr() || std::prev(I)->isPosition())
566 if (std::prev(I)->isDebugInstr() || std::prev(I)->isPosition())
1076 : EHPadLayoutPred->rbegin()->getDebugLoc();
lib/Target/WebAssembly/WebAssemblyFastISel.cpp 1150 assert(Iter->isBitcast());
1151 Iter->setPhysRegsDeadExcept(ArrayRef<Register>(), TRI);
lib/Target/WebAssembly/WebAssemblyFrameLowering.cpp 141 assert(!I->getOperand(0).getImm() && (hasFP(MF) || hasBP(MF)) &&
144 if (I->getOpcode() == TII->getCallFrameDestroyOpcode() &&
146 DebugLoc DL = I->getDebugLoc();
168 WebAssembly::isArgument(InsertPt->getOpcode()))
236 DL = InsertPt->getDebugLoc();
lib/Target/WebAssembly/WebAssemblyLateEHPrepare.cpp 133 if (InsertPos->isEHLabel()) // EH pad starts with an EH label
136 BuildMI(MBB, InsertPos, MBB.begin()->getDebugLoc(),
169 if (CatchPos->isEHLabel()) // EH pad starts with an EH label
274 if (CatchPos->isEHLabel()) // EH pad starts with an EH label
383 if (InsertPos->isEHLabel()) // EH pad starts with an EH label
385 if (InsertPos->getOpcode() == WebAssembly::CATCH)
388 MBB.begin()->getDebugLoc());
lib/Target/WebAssembly/WebAssemblyPeephole.cpp 86 assert(End->getOpcode() == WebAssembly::END_FUNCTION);
lib/Target/WebAssembly/WebAssemblyRegStackify.cpp 326 for (auto E = MBB->end(); NextI != E && NextI->isDebugInstr(); ++NextI)
391 for (const MachineOperand &MO : I->operands())
lib/Target/WebAssembly/WebAssemblyRegisterInfo.cpp 121 BuildMI(MBB, *II, II->getDebugLoc(), TII->get(WebAssembly::CONST_I32),
125 BuildMI(MBB, *II, II->getDebugLoc(), TII->get(WebAssembly::ADD_I32),
lib/Target/X86/X86AvoidStoreForwardingBlocks.cpp 344 if (PBInst->isMetaInstruction())
369 if (PBInst->isMetaInstruction())
374 if (PBInst->getDesc().isCall())
lib/Target/X86/X86AvoidTrailingCall.cpp 96 LastRealInstr->dump();
101 BuildMI(*LastRealInstr->getParent(), MBBI, LastRealInstr->getDebugLoc(),
101 BuildMI(*LastRealInstr->getParent(), MBBI, LastRealInstr->getDebugLoc(),
lib/Target/X86/X86CallFrameOptimization.cpp 287 switch (MI->getOpcode()) {
291 MachineOperand ImmOp = MI->getOperand(X86::AddrNumOperands);
297 MachineOperand ImmOp = MI->getOperand(X86::AddrNumOperands);
332 if (MI->isCall() || MI->mayStore())
332 if (MI->isCall() || MI->mayStore())
335 for (const MachineOperand &MO : MI->operands()) {
363 assert(I->getOpcode() == TII->getCallFrameSetupOpcode());
380 while (I->getOpcode() == X86::LEA32r || I->isDebugInstr())
380 while (I->getOpcode() == X86::LEA32r || I->isDebugInstr())
393 for (auto J = I; !J->isCall(); ++J)
394 if (J->isCopy() && J->getOperand(0).isReg() && J->getOperand(1).isReg() &&
394 if (J->isCopy() && J->getOperand(0).isReg() && J->getOperand(1).isReg() &&
394 if (J->isCopy() && J->getOperand(0).isReg() && J->getOperand(1).isReg() &&
395 J->getOperand(1).getReg() == StackPtr) {
427 if (!I->getOperand(X86::AddrBaseReg).isReg() ||
428 (I->getOperand(X86::AddrBaseReg).getReg() != StackPtr) ||
429 !I->getOperand(X86::AddrScaleAmt).isImm() ||
430 (I->getOperand(X86::AddrScaleAmt).getImm() != 1) ||
431 (I->getOperand(X86::AddrIndexReg).getReg() != X86::NoRegister) ||
432 (I->getOperand(X86::AddrSegmentReg).getReg() != X86::NoRegister) ||
433 !I->getOperand(X86::AddrDisp).isImm())
436 int64_t StackDisp = I->getOperand(X86::AddrDisp).getImm();
453 for (const MachineOperand &MO : I->uses()) {
466 if (I == MBB.end() || !I->isCall())
470 if ((++I)->getOpcode() != TII->getCallFrameDestroyOpcode())
499 MachineBasicBlock &MBB = *(FrameSetup->getParent());
502 DebugLoc DL = FrameSetup->getDebugLoc();
509 MachineOperand PushOp = Store->getOperand(X86::AddrNumOperands);
512 switch (Store->getOpcode()) {
541 if (Is64Bit && Store->getOpcode() == X86::MOV32mr) {
564 Push->addOperand(DefMov->getOperand(i));
624 DefMI.getParent() != FrameSetup->getParent())
630 if (I->isLoadFoldBarrier())
lib/Target/X86/X86CmovConversion.cpp 575 if (I->readsRegister(X86::EFLAGS))
577 if (I->definesRegister(X86::EFLAGS))
813 Register DestReg = MIIt->getOperand(0).getReg();
814 Register Op1Reg = MIIt->getOperand(1).getReg();
815 Register Op2Reg = MIIt->getOperand(2).getReg();
840 LLVM_DEBUG(dbgs() << "\tFrom: "; MIIt->dump());
lib/Target/X86/X86CondBrFolding.cpp 501 if (I->isDebugValue())
503 if (I->getOpcode() == X86::JMP_1) {
506 FBB = I->getOperand(0).getMBB();
509 if (I->isBranch()) {
524 TBB = I->getOperand(0).getMBB();
lib/Target/X86/X86ExpandPseudo.cpp 183 DebugLoc DL = MBBI->getDebugLoc();
196 MachineOperand &JumpTarget = MBBI->getOperand(0);
197 MachineOperand &StackAdjust = MBBI->getOperand(isMem ? X86::AddrNumOperands
255 MIB.addImm(MBBI->getOperand(2).getImm());
264 MIB.add(MBBI->getOperand(i));
277 NewMI.copyImplicitOps(*MBBI->getParent()->getParent(), *MBBI);
287 MachineOperand &DestAddr = MBBI->getOperand(0);
300 int64_t StackAdj = MBBI->getOperand(0).getImm();
310 int64_t StackAdj = MBBI->getOperand(0).getImm();
329 for (unsigned I = 1, E = MBBI->getNumOperands(); I != E; ++I)
330 MIB.add(MBBI->getOperand(I));
339 MBBI->eraseFromParent();
350 const MachineOperand &InArg = MBBI->getOperand(6);
351 Register SaveRbx = MBBI->getOperand(7).getReg();
365 NewInstr->addOperand(MBBI->getOperand(Idx));
371 MBBI->eraseFromParent();
lib/Target/X86/X86FixupLEAs.cpp 213 if (!isLEA(I->getOpcode()))
282 if (CurInst->isCall() || CurInst->isInlineAsm())
282 if (CurInst->isCall() || CurInst->isInlineAsm())
469 LLVM_DEBUG(dbgs() << "FixLEA: Candidate to replace:"; MBI->dump(););
502 LLVM_DEBUG(dbgs() << "FixLEA: Candidate to replace:"; I->dump(););
lib/Target/X86/X86FixupSetCC.cpp 80 for (auto &Op : MI->implicit_operands())
lib/Target/X86/X86FlagsCopyLowering.cpp 476 if (HasEFLAGSClobber(HoistMBB->getFirstTerminator()->getIterator(),
482 TestPos = TestMBB->getFirstTerminator()->getIterator();
lib/Target/X86/X86FloatingPoint.cpp 225 DebugLoc dl = I == MBB->end() ? DebugLoc() : I->getDebugLoc();
246 DebugLoc dl = I == MBB->end() ? DebugLoc() : I->getDebugLoc();
489 Start->print(dbgs());
841 int Opcode = Lookup(PopTable, I->getOpcode());
843 I->setDesc(TII->get(Opcode));
845 I->RemoveOperand(0);
975 const MachineFunction* MF = I->getParent()->getParent();
977 for (const auto &MO : I->operands()) {
1691 if (I->isDebugInstr())
1698 for (auto &MO : I->operands()) {
lib/Target/X86/X86FrameLowering.cpp 158 switch (MBBI->getOpcode()) {
175 for (unsigned i = 0, e = MBBI->getNumOperands(); i != e; ++i) {
176 MachineOperand &MO = MBBI->getOperand(i);
415 if (doMergeWithPrevious && PI != MBB.begin() && PI->isCFIInstruction())
418 unsigned Opc = PI->getOpcode();
423 PI->getOperand(0).getReg() == StackPtr){
424 assert(PI->getOperand(1).getReg() == StackPtr);
425 Offset = PI->getOperand(2).getImm();
427 PI->getOperand(0).getReg() == StackPtr &&
428 PI->getOperand(1).getReg() == StackPtr &&
429 PI->getOperand(2).getImm() == 1 &&
430 PI->getOperand(3).getReg() == X86::NoRegister &&
431 PI->getOperand(5).getReg() == X86::NoRegister) {
433 Offset = PI->getOperand(4).getImm();
436 PI->getOperand(0).getReg() == StackPtr) {
437 assert(PI->getOperand(1).getReg() == StackPtr);
438 Offset = -PI->getOperand(2).getImm();
443 if (PI != MBB.end() && PI->isCFIInstruction()) PI = MBB.erase(PI);
746 BeforeMBBI->setFlag(MachineInstr::FrameSetup);
756 CMBBI->setFlag(MachineInstr::FrameSetup);
820 ExpansionMBBI->setFlag(MachineInstr::FrameSetup);
1184 MBBI->getFlag(MachineInstr::FrameSetup) &&
1185 (MBBI->getOpcode() == X86::PUSH32r ||
1186 MBBI->getOpcode() == X86::PUSH64r)) {
1188 Register Reg = MBBI->getOperand(0).getReg();
1384 while (MBBI != MBB.end() && MBBI->getFlag(MachineInstr::FrameSetup)) {
1598 DL = MBBI->getDebugLoc();
1657 unsigned Opc = PI->getOpcode();
1659 if (Opc != X86::DBG_VALUE && !PI->isTerminator()) {
1660 if ((Opc != X86::POP32r || !PI->getFlag(MachineInstr::FrameDestroy)) &&
1661 (Opc != X86::POP64r || !PI->getFlag(MachineInstr::FrameDestroy)))
1670 if (IsFunclet && Terminator->getOpcode() == X86::CATCHRET)
1674 DL = MBBI->getDebugLoc();
1738 unsigned Opc = PI->getOpcode();
1748 if (Terminator == MBB.end() || !isTailCallOpcode(Terminator->getOpcode())) {
2129 MI->setFlag(MachineInstr::FrameSetup);
2180 if (MI->getOpcode() == X86::CATCHRET) {
2737 if (!Prev->isCall() || !Prev->getOperand(1).isRegMask())
2737 if (!Prev->isCall() || !Prev->getOperand(1).isRegMask())
2744 auto RegMask = Prev->getOperand(1);
2762 for (const MachineOperand &MO : Prev->implicit_operands()) {
2796 unsigned Opcode = I->getOpcode();
2798 DebugLoc DL = I->getDebugLoc();
2897 while (CI != B && !std::prev(CI)->isCall())
3218 while (MBBI != MBB.end() && MBBI->getFlag(MachineInstr::FrameSetup))
lib/Target/X86/X86ISelLowering.cpp29619 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
29667 DebugLoc DL = MIItBegin->getDebugLoc();
29669 X86::CondCode CC = X86::CondCode(MIItBegin->getOperand(3).getImm());
29684 Register DestReg = MIIt->getOperand(0).getReg();
29685 Register Op1Reg = MIIt->getOperand(1).getReg();
29686 Register Op2Reg = MIIt->getOperand(2).getReg();
29691 if (MIIt->getOperand(3).getImm() == OppCC)
29936 (NextMIIt->getOperand(3).getImm() == CC ||
29937 NextMIIt->getOperand(3).getImm() == OppCC)) {
29947 NextMIIt->getOpcode() == MI.getOpcode() &&
29948 NextMIIt->getOperand(2).getReg() == MI.getOperand(2).getReg() &&
29949 NextMIIt->getOperand(1).getReg() == MI.getOperand(0).getReg() &&
29950 NextMIIt->getOperand(1).isKill()) {
29977 if (DbgIt->isDebugInstr())
29978 SinkMBB->push_back(DbgIt->removeFromParent());
31391 while (RMBBI != BB->rend() && (RMBBI->definesRegister(X86::EAX) ||
31392 RMBBI->definesRegister(X86::EBX) ||
31393 RMBBI->definesRegister(X86::ECX) ||
31394 RMBBI->definesRegister(X86::EDX))) {
lib/Target/X86/X86IndirectBranchTracking.cpp 79 if (I == MBB.end() || I->getOpcode() != EndbrOpcode) {
131 if (!I->isCall())
133 if (IsCallReturnTwice(I->getOperand(0)))
lib/Target/X86/X86InstrInfo.cpp 158 if (I->getOpcode() == getCallFrameDestroyOpcode() ||
159 I->isCall())
165 if (I->getOpcode() != getCallFrameDestroyOpcode())
168 return -(I->getOperand(1).getImm());
2445 if (I->isDebugInstr())
2447 if (!I->isBranch())
2478 I->eraseFromParent();
2513 if (I->isDebugInstr())
2523 if (!I->isBranch())
2527 if (I->getOpcode() == X86::JMP_1) {
2531 TBB = I->getOperand(0).getMBB();
2537 std::next(I)->eraseFromParent();
2543 if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
2545 I->eraseFromParent();
2552 TBB = I->getOperand(0).getMBB();
2563 if (I->findRegisterUseOperand(X86::EFLAGS)->isUndef())
2568 MachineBasicBlock *TargetBB = I->getOperand(0).getMBB();
2592 .addMBB(UnCondBrIter->getOperand(0).getMBB())
2597 OldInst->eraseFromParent();
2598 UnCondBrIter->eraseFromParent();
2607 TBB = I->getOperand(0).getMBB();
2621 auto NewTBB = I->getOperand(0).getMBB();
2702 if (I->modifiesRegister(X86::EFLAGS, TRI)) {
2707 if (I->readsRegister(X86::EFLAGS, TRI))
2755 if (I->isDebugInstr())
2757 if (I->getOpcode() != X86::JMP_1 &&
2761 I->eraseFromParent();
3630 if (NewCC != X86::COND_INVALID && J->getOperand(1).isReg() &&
3631 J->getOperand(1).getReg() == SrcReg) {
3632 assert(J->definesRegister(X86::EFLAGS) && "Must be an EFLAGS def!");
4683 MachineBasicBlock *MBB = InsertPt->getParent();
4711 MachineBasicBlock *MBB = InsertPt->getParent();
4721 MachineInstrBuilder MIB = BuildMI(*InsertPt->getParent(), InsertPt,
7797 std::prev(MBBI)->setPreInstrSymbol(MF, MF.getPICBaseSymbol());
7873 switch (I->getOpcode()) {
8005 if (RepeatedSequenceLocs[0].back()->isTerminator()) {
lib/Target/X86/X86MCInstLower.cpp 1593 const MachineBasicBlock *MBB = MBBI->getParent();
2096 if (!MBBI->isPseudo()) {
2097 if (MBBI->isCall())
lib/Target/X86/X86PadShortFunction.cpp 128 while (ReturnLoc->isDebugInstr())
130 assert(ReturnLoc->isReturn() && !ReturnLoc->isCall() &&
130 assert(ReturnLoc->isReturn() && !ReturnLoc->isCall() &&
204 DebugLoc DL = MBBI->getDebugLoc();
lib/Target/X86/X86RegisterInfo.cpp 680 unsigned Opc = II->getOpcode();
lib/Target/X86/X86SpeculativeLoadHardening.cpp 578 if (TermIt == MBB.end() || !TermIt->isBranch())
741 assert((InsertPt == CheckingMBB.end() || !InsertPt->isPHI()) &&
lib/Target/X86/X86VZeroUpper.cpp 180 DebugLoc dl = I->getDebugLoc();
lib/Target/XCore/XCoreFrameLowering.cpp 349 DebugLoc dl = MBBI->getDebugLoc();
350 unsigned RetOpcode = MBBI->getOpcode();
370 Register EhStackReg = MBBI->getOperand(0).getReg();
371 Register EhHandlerReg = MBBI->getOperand(1).getReg();
403 for (unsigned i = 3, e = MBBI->getNumOperands(); i < e; ++i)
404 MIB->addOperand(MBBI->getOperand(i)); // copy any variadic operands
429 if (MI != MBB.end() && !MI->isDebugInstr())
430 DL = MI->getDebugLoc();
lib/Target/XCore/XCoreFrameToArgsOffsetElim.cpp 56 if (MBBI->getOpcode() == XCore::FRAME_TO_ARGS_OFFSET) {
lib/Target/XCore/XCoreInstrInfo.cpp 255 I->eraseFromParent();
263 I->eraseFromParent();
313 if (!IsBRU(I->getOpcode()) && !IsCondBranch(I->getOpcode()))
313 if (!IsBRU(I->getOpcode()) && !IsCondBranch(I->getOpcode()))
317 I->eraseFromParent();
323 if (!IsCondBranch(I->getOpcode()))
327 I->eraseFromParent();
366 if (I != MBB.end() && !I->isDebugInstr())
367 DL = I->getDebugLoc();
388 if (I != MBB.end() && !I->isDebugInstr())
389 DL = I->getDebugLoc();
431 if (MI != MBB.end() && !MI->isDebugInstr())
432 dl = MI->getDebugLoc();