|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h 59 LLVM_DEBUG(dbgs() << ".. Combine MI: " << MI;);
108 LLVM_DEBUG(dbgs() << ".. Combine MI: " << MI;);
148 LLVM_DEBUG(dbgs() << ".. Combine MI: " << MI;);
203 LLVM_DEBUG(dbgs() << ".. Combine G_ANYEXT(G_IMPLICIT_DEF): " << MI;);
210 LLVM_DEBUG(dbgs() << ".. Combine G_[SZ]EXT(G_IMPLICIT_DEF): " << MI;);
526 LLVM_DEBUG(dbgs() << *DeadMI << "Is dead, eagerly deleting\n");
include/llvm/Transforms/Utils/SSAUpdaterImpl.h 380 LLVM_DEBUG(dbgs() << " Inserted PHI: " << *PHI << "\n");
lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp 598 << "' for machine instr: " << *MI;
lib/CodeGen/AsmPrinter/DbgEntityHistoryCalculator.cpp 64 << "\t" << Entries.back().getInstr() << "\t" << MI
364 dbgs() << " Instr: " << *Entry.getInstr();
lib/CodeGen/AsmPrinter/DwarfDebug.cpp 1423 LLVM_DEBUG(dbgs() << "DotDebugLoc: " << *Instr << "\n");
lib/CodeGen/BranchFolding.cpp 1351 << MI);
1363 << MI);
lib/CodeGen/BranchRelaxation.cpp 292 << MI);
363 << MBB->back());
400 << " Insert a new BB after " << MBB->back());
lib/CodeGen/DFAPacketizer.cpp 216 dbgs() << " * [res:0x" << utohexstr(R) << "] " << *MI;
277 LLVM_DEBUG(dbgs() << "Checking resources for adding MI to packet " << MI);
292 LLVM_DEBUG(dbgs() << " Checking against MJ " << *MJ);
311 << MI);
318 LLVM_DEBUG(dbgs() << "* Adding MI to packet " << MI << '\n');
lib/CodeGen/DeadMachineInstructionElim.cpp 129 LLVM_DEBUG(dbgs() << "DeadMachineInstructionElim: DELETING: " << *MI);
lib/CodeGen/DetectDeadLanes.cpp 441 LLVM_DEBUG(dbgs() << "Copy across incompatible classes: " << UseMI);
546 << "Marking operand '" << MO << "' as dead in " << MI);
553 << "Marking operand '" << MO << "' as undef in " << MI);
557 << "Marking operand '" << MO << "' as undef in " << MI);
lib/CodeGen/EarlyIfConversion.cpp 224 LLVM_DEBUG(dbgs() << "Can't hoist: " << *I);
232 LLVM_DEBUG(dbgs() << "Won't speculate load: " << *I);
239 LLVM_DEBUG(dbgs() << "Can't speculate: " << *I);
257 LLVM_DEBUG(dbgs() << "Won't speculate regmask: " << *I);
276 << *DefMI);
319 LLVM_DEBUG(dbgs() << "Can't predicate: " << *I);
373 LLVM_DEBUG(dbgs() << "Can't insert code after " << *I);
412 dbgs() << " live before " << *I;
419 LLVM_DEBUG(dbgs() << "Can insert before " << *I);
524 LLVM_DEBUG(dbgs() << "Can't convert: " << *PI.PHI);
568 LLVM_DEBUG(dbgs() << "If-converting " << *PI.PHI);
571 LLVM_DEBUG(dbgs() << " --> " << *std::prev(FirstTerm));
590 LLVM_DEBUG(dbgs() << "If-converting " << *PI.PHI);
600 LLVM_DEBUG(dbgs() << " --> " << *std::prev(FirstTerm));
614 LLVM_DEBUG(dbgs() << " --> " << *PI.PHI);
844 LLVM_DEBUG(dbgs() << "Slack " << Slack << ":\t" << *PI.PHI);
lib/CodeGen/ExecutionDomainFix.cpp 248 LLVM_DEBUG(dbgs() << printReg(RC->getRegister(rx), TRI) << ":\t" << *MI);
lib/CodeGen/ExpandPostRAPseudos.cpp 95 LLVM_DEBUG(dbgs() << "subreg: CONVERTING: " << *MI);
101 LLVM_DEBUG(dbgs() << "subreg: replaced by: " << *MI);
114 LLVM_DEBUG(dbgs() << "subreg: replace by: " << *MI);
126 LLVM_DEBUG(dbgs() << "subreg: " << *CopyMI);
137 LLVM_DEBUG(dbgs() << "dead copy: " << *MI);
139 LLVM_DEBUG(dbgs() << "replaced by: " << *MI);
149 << *MI);
156 LLVM_DEBUG(dbgs() << "replaced by: " << *MI);
164 LLVM_DEBUG(dbgs() << "real copy: " << *MI);
172 dbgs() << "replaced by: " << *(--dMI);
lib/CodeGen/GlobalISel/CSEInfo.cpp 153 LLVM_DEBUG(dbgs() << "CSEInfo::Found Instr " << *Inst->MI;);
172 LLVM_DEBUG(dbgs() << "CSEInfo::Recording new MI " << *MI);
179 LLVM_DEBUG(dbgs() << "CSEInfo::Handling recorded MI " << *MI);
238 LLVM_DEBUG(dbgs() << "CSEInfo::Add MI: " << MI);
lib/CodeGen/GlobalISel/Combiner.cpp 65 LLVM_DEBUG(dbgs() << "Erasing: " << MI << "\n");
69 LLVM_DEBUG(dbgs() << "Creating: " << MI << "\n");
74 LLVM_DEBUG(dbgs() << "Changing: " << MI << "\n");
78 LLVM_DEBUG(dbgs() << "Changed: " << MI << "\n");
140 LLVM_DEBUG(dbgs() << *CurMI << "Is dead; erasing.\n");
151 LLVM_DEBUG(dbgs() << "\nTry combining " << *CurrInst;);
lib/CodeGen/GlobalISel/CombinerHelper.cpp 419 LLVM_DEBUG(dbgs() << "Preferred use is: " << *Preferred.MI);
571 LLVM_DEBUG(dbgs() << "Searching for post-indexing opportunity for: " << MI);
581 << Use);
591 << Use);
610 << Use);
614 LLVM_DEBUG(dbgs() << " Found match: " << Use);
641 LLVM_DEBUG(dbgs() << "Found potential pre-indexed load_store: " << MI);
1095 LLVM_DEBUG(dbgs() << "Inlining memcpy: " << MI << " into loads & stores\n");
1202 LLVM_DEBUG(dbgs() << "Inlining memmove: " << MI << " into loads & stores\n");
lib/CodeGen/GlobalISel/GISelKnownBits.cpp 317 dbgs() << '[' << Depth << "] Shift not known constant: " << *RHSMI);
366 LLVM_DEBUG(dbgs() << "[" << Depth << "] Compute known bits: " << MI << "["
367 << Depth << "] Computed for: " << MI << "[" << Depth
lib/CodeGen/GlobalISel/IRTranslator.cpp 138 << " was copied to " << MI);
lib/CodeGen/GlobalISel/InstructionSelect.cpp 125 LLVM_DEBUG(dbgs() << "Selecting: \n " << MI);
147 dbgs() << " " << InsertedMI;
lib/CodeGen/GlobalISel/Legalizer.cpp 110 LLVM_DEBUG(dbgs() << ".. .. New MI: " << MI);
118 dbgs() << ".. .. New MI: " << *MI;
124 LLVM_DEBUG(dbgs() << ".. .. Erasing: " << MI);
130 LLVM_DEBUG(dbgs() << ".. .. Changing MI: " << MI);
136 LLVM_DEBUG(dbgs() << ".. .. Changed MI: " << MI);
223 LLVM_DEBUG(dbgs() << MI << "Is dead; erasing.\n");
262 LLVM_DEBUG(dbgs() << MI << "Is dead\n");
272 LLVM_DEBUG(dbgs() << *DeadMI << "Is dead\n");
lib/CodeGen/GlobalISel/Localizer.cpp 121 LLVM_DEBUG(dbgs() << "Should localize: " << MI);
134 dbgs() << "Checking use: " << MIUse
159 LLVM_DEBUG(dbgs() << "Inserted: " << *LocalizedMI);
198 LLVM_DEBUG(dbgs() << "Intra-block: moving " << *MI << " before " << *&*II
198 LLVM_DEBUG(dbgs() << "Intra-block: moving " << *MI << " before " << *&*II
lib/CodeGen/GlobalISel/RegBankSelect.cpp 454 LLVM_DEBUG(dbgs() << "Evaluating mapping cost for: " << MI);
623 LLVM_DEBUG(dbgs() << "Assign: " << MI);
lib/CodeGen/GlobalISel/RegisterBankInfo.cpp 760 OS << "Mapping for " << getMI() << "\nwith " << getInstrMapping() << '\n';
lib/CodeGen/IfConversion.cpp 309 LLVM_DEBUG(dbgs() << "Common inst: " << I);
313 LLVM_DEBUG(dbgs() << "Common inst: " << I);
323 LLVM_DEBUG(dbgs() << "Saving branch: " << I);
326 LLVM_DEBUG(dbgs() << "Common inst: " << I);
332 LLVM_DEBUG(dbgs() << "Saving branch: " << I);
335 LLVM_DEBUG(dbgs() << "Common inst: " << I);
341 LLVM_DEBUG(dbgs() << "Saving branch: " << I);
354 LLVM_DEBUG(dbgs() << "Predicating: " << I);
360 LLVM_DEBUG(dbgs() << "Predicating: " << I);
2149 dbgs() << "Unable to predicate " << I << "!\n";
2198 dbgs() << "Unable to predicate " << I << "!\n";
lib/CodeGen/InlineSpiller.cpp 416 LLVM_DEBUG(dbgs() << "\thoisted: " << SrcVNI->def << '\t' << *MII);
472 LLVM_DEBUG(dbgs() << "Redundant spill " << Idx << '\t' << MI);
562 LLVM_DEBUG(dbgs() << UseIdx << '\t' << MI);
576 LLVM_DEBUG(dbgs() << "\tcannot remat for " << UseIdx << '\t' << MI);
584 LLVM_DEBUG(dbgs() << "\tcannot remat tied reg: " << UseIdx << '\t' << MI);
601 LLVM_DEBUG(dbgs() << "\tcannot remat for " << UseIdx << '\t' << MI);
619 << *LIS.getInstructionFromIndex(DefIdx));
629 LLVM_DEBUG(dbgs() << "\t " << UseIdx << '\t' << MI << '\n');
677 LLVM_DEBUG(dbgs() << "All defs dead: " << *MI);
732 LLVM_DEBUG(dbgs() << "Coalescing stack access: " << *MI);
777 dbgs() << SlotIndent << Idx << '\t' << *I;
976 LLVM_DEBUG(dbgs() << "Modifying debug info due to spill:\t" << *MI);
1010 LLVM_DEBUG(dbgs() << "Found new snippet copy: " << *MI);
1053 LLVM_DEBUG(dbgs() << "\trewrite: " << Idx << '\t' << *MI << '\n');
lib/CodeGen/LiveDebugVariables.cpp 604 LLVM_DEBUG(dbgs() << "Can't handle " << MI);
624 << " " << MI);
636 << " " << MI);
661 LLVM_DEBUG(dbgs() << "Can't handle " << MI);
lib/CodeGen/LiveIntervals.cpp 473 dbgs() << Idx << '\t' << UseMI
534 LLVM_DEBUG(dbgs() << "All defs dead: " << Def << '\t' << *MI);
974 << *MI);
lib/CodeGen/LiveRangeCalc.cpp 371 errs() << Use << " " << *MI;
lib/CodeGen/LiveRangeEdit.cpp 222 LLVM_DEBUG(dbgs() << "Try to fold single def: " << *DefMI
223 << " into single use: " << *UseMI);
232 LLVM_DEBUG(dbgs() << " folded: " << *FoldMI);
271 LLVM_DEBUG(dbgs() << "Won't delete: " << Idx << '\t' << *MI);
278 LLVM_DEBUG(dbgs() << "Can't delete: " << Idx << '\t' << *MI);
282 LLVM_DEBUG(dbgs() << "Deleting dead def " << Idx << '\t' << *MI);
356 LLVM_DEBUG(dbgs() << "Converted physregs to:\t" << *MI);
lib/CodeGen/LiveVariables.cpp 78 dbgs() << "\n #" << i << ": " << *Kills[i];
lib/CodeGen/LocalStackSlotAllocation.cpp 362 LLVM_DEBUG(dbgs() << "Considering: " << MI);
378 LLVM_DEBUG(dbgs() << " Replacing FI in: " << MI);
439 LLVM_DEBUG(dbgs() << "Resolved: " << MI);
lib/CodeGen/MachineBasicBlock.cpp 915 LLVM_DEBUG(dbgs() << "Removing terminator kill: " << *MI);
1001 LLVM_DEBUG(dbgs() << "Restored terminator kill: " << *I);
lib/CodeGen/MachineCSE.cpp 198 LLVM_DEBUG(dbgs() << "Coalescing: " << *DefMI);
199 LLVM_DEBUG(dbgs() << "*** to: " << *MI);
587 LLVM_DEBUG(dbgs() << "Examining: " << *MI);
588 LLVM_DEBUG(dbgs() << "*** Found a common subexpression: " << *CSMI);
lib/CodeGen/MachineCombiner.cpp 312 LLVM_DEBUG(dbgs() << " Dependence data for " << *Root << "\tNewRootDepth: "
lib/CodeGen/MachineCopyPropagation.cpp 421 << MI);
437 << MI);
443 << "\n in " << MI << " from " << *Copy);
443 << "\n in " << MI << " from " << *Copy);
449 LLVM_DEBUG(dbgs() << "MCP: After replacement: " << MI << "\n");
lib/CodeGen/MachineLICM.cpp 596 << *MI);
1212 LLVM_DEBUG(dbgs() << "Won't hoist cheap instr with loop PHI use: " << MI);
1231 LLVM_DEBUG(dbgs() << "Hoist High Latency: " << MI);
1249 LLVM_DEBUG(dbgs() << "Hoist non-reg-pressure: " << MI);
1256 LLVM_DEBUG(dbgs() << "Won't hoist instr with loop PHI use: " << MI);
1265 LLVM_DEBUG(dbgs() << "Won't speculate: " << MI);
1273 LLVM_DEBUG(dbgs() << "Can't remat / high reg-pressure: " << MI);
1370 LLVM_DEBUG(dbgs() << "CSEing " << *MI << " with " << *Dup);
1370 LLVM_DEBUG(dbgs() << "CSEing " << *MI << " with " << *Dup);
1451 dbgs() << "Hoisting " << *MI;
lib/CodeGen/MachinePipeliner.cpp 2864 os << " SU(" << I->NodeNum << ") " << *(I->getInstr());
lib/CodeGen/MachineRegisterInfo.cpp 235 << " doesn't belong to parent MI: " << *MI;
lib/CodeGen/MachineSSAUpdater.cpp 206 LLVM_DEBUG(dbgs() << " Inserted PHI: " << *InsertedPHI << "\n");
lib/CodeGen/MachineScheduler.cpp 563 << " " << MBB->getName() << "\n From: " << *I
565 if (RegionEnd != MBB->end()) dbgs() << *RegionEnd;
1120 << PrintLaneMask(P.LaneMask) << ' ' << *SU.getInstr();
1154 << *SU->getInstr();
3249 << *SU->getInstr());
3442 << *SU->getInstr());
3539 << "Scheduling " << *SU->getInstr());
lib/CodeGen/MachineSink.cpp 220 LLVM_DEBUG(dbgs() << "Coalescing: " << *DefMI);
221 LLVM_DEBUG(dbgs() << "*** to: " << MI);
888 LLVM_DEBUG(dbgs() << "Sink instr " << MI << "\tinto block " << *SuccToSinkTo);
lib/CodeGen/MachineTraceMetrics.cpp 814 LLVM_DEBUG(dbgs() << TBI.CriticalPath << '\t' << Cycle << '\t' << UseMI);
816 LLVM_DEBUG(dbgs() << Cycle << '\t' << UseMI);
1082 LLVM_DEBUG(dbgs() << "pred\t" << Height << '\t' << PHI);
1123 LLVM_DEBUG(dbgs() << Cycle << '\t' << MI);
1128 LLVM_DEBUG(dbgs() << TBI.CriticalPath << '\t' << Cycle << '\t' << MI);
lib/CodeGen/MachineVerifier.cpp 415 errs() << "Instruction: " << *MBBI;
845 errs() << "First terminator was:\t" << *FirstTerminator;
lib/CodeGen/ModuloSchedule.cpp 26 OS << "[stage " << getStage(MI) << " @" << getCycle(MI) << "c] " << *MI;
1557 << *Source->getParent();
1997 dbgs() << "Parsing post-instr symbol for " << MI;
lib/CodeGen/PHIElimination.cpp 279 << *MPhi);
302 LLVM_DEBUG(dbgs() << "Remove old kill from " << *OldKill);
601 << printMBBReference(MBB) << ": " << *BBI);
lib/CodeGen/PeepholeOptimizer.cpp 1147 LLVM_DEBUG(dbgs() << " Replacing: " << OrigPHI);
1148 LLVM_DEBUG(dbgs() << " With: " << NewPHI);
1245 LLVM_DEBUG(dbgs() << " Replacing: " << CopyLike);
1246 LLVM_DEBUG(dbgs() << " With: " << *NewCopy);
1464 << MI);
1472 LLVM_DEBUG(dbgs() << "NAPhysCopy: erasing " << MI);
1481 LLVM_DEBUG(dbgs() << "NAPhysCopy: missed opportunity " << MI);
1577 LLVM_DEBUG(dbgs() << "Optimize recurrence chain from " << PHI);
1579 LLVM_DEBUG(dbgs() << "\tInst: " << *(RI.getMI()));
1585 LLVM_DEBUG(dbgs() << "\t\tCommuted: " << *(RI.getMI()));
1670 << "NAPhysCopy: invalidating because of " << *MI);
1680 << "NAPhysCopy: invalidating because of " << *MI);
1697 << *MI);
1773 LLVM_DEBUG(dbgs() << "Replacing: " << *MI);
1774 LLVM_DEBUG(dbgs() << " With: " << *FoldMI);
1798 LLVM_DEBUG(dbgs() << "Encountered load fold barrier on " << *MI);
lib/CodeGen/ProcessImplicitDefs.cpp 75 LLVM_DEBUG(dbgs() << "Processing " << *MI);
86 LLVM_DEBUG(dbgs() << "Converting to IMPLICIT_DEF: " << *UserMI);
118 LLVM_DEBUG(dbgs() << "Physreg user: " << *UserMI);
127 LLVM_DEBUG(dbgs() << "Keeping physreg: " << *MI);
lib/CodeGen/ReachingDefAnalysis.cpp 113 << '\t' << *MI);
lib/CodeGen/RegAllocFast.cpp 333 LLVM_DEBUG(dbgs() << "Inserting debug info due to spill:\n" << *NewDV);
1203 LLVM_DEBUG(dbgs() << "<< " << MI);
1231 LLVM_DEBUG(dbgs() << "Modifying debug info due to spill:" << "\t" << MI);
1265 dbgs() << "\n>> " << MI << "Regs:";
lib/CodeGen/RegAllocGreedy.cpp 2118 LLVM_DEBUG(dbgs() << " skip:\t" << Uses[i] << '\t' << *MI);
lib/CodeGen/RegUsageInfoPropagate.cpp 122 LLVM_DEBUG(dbgs() << MI << "\n");
144 << MI << '\n');
lib/CodeGen/RegisterCoalescer.cpp 829 << *DefMI);
898 LLVM_DEBUG(dbgs() << "\t\tnoop: " << DefIdx << '\t' << *UseMI);
1120 << printMBBReference(*CopyLeftBB) << '\t' << CopyMI);
1138 << printMBBReference(MBB) << '\t' << CopyMI);
1474 LLVM_DEBUG(dbgs() << "Remat: " << NewMI);
1490 LLVM_DEBUG(dbgs() << "\t\tupdated: " << *UseMI);
1609 LLVM_DEBUG(dbgs() << "\tnew undef: " << UseIdx << '\t' << MI);
1728 dbgs() << *UseMI;
1753 LLVM_DEBUG(dbgs() << LIS->getInstructionIndex(*CopyMI) << '\t' << *CopyMI);
2066 LLVM_DEBUG(dbgs() << "\t\tInterference (read): " << *MI);
2883 LLVM_DEBUG(dbgs() << "\t\ttainted lanes used by: " << *MI);
3198 LLVM_DEBUG(dbgs() << "\t\terased:\t" << Def << '\t' << *MI);
lib/CodeGen/RegisterPressure.cpp 1126 dbgs() << "DELTA: " << *MI;
lib/CodeGen/RegisterScavenging.cpp 609 LLVM_DEBUG(dbgs() << "Reload before: " << *ReloadBefore << '\n');
614 << " until " << *SpillBefore);
lib/CodeGen/SelectionDAG/FastISel.cpp 266 << LocalMI);
317 LLVM_DEBUG(dbgs() << "sinking local value to first use " << LocalMI);
lib/CodeGen/ShrinkWrap.cpp 272 LLVM_DEBUG(dbgs() << "Frame instruction: " << MI << '\n');
304 << MO.isFI() << "): " << MI << '\n');
lib/CodeGen/SlotIndexes.cpp 244 dbgs() << *itr->getInstr();
lib/CodeGen/SplitKit.cpp 864 LLVM_DEBUG(dbgs() << "Removing " << Def << '\t' << *MI);
884 LLVM_DEBUG(dbgs() << " move kill to " << Kill << '\t' << *MBBI);
1322 LLVM_DEBUG(dbgs() << "Zapping " << *MI);
1339 << '\t' << Idx << ':' << RegIdx << '\t' << *MI);
1424 LLVM_DEBUG(dbgs() << "All defs dead: " << *MI);
lib/CodeGen/StackMapLivenessAnalysis.cpp 140 LLVM_DEBUG(dbgs() << " " << LiveRegs << " " << *I);
lib/CodeGen/TailDuplicator.cpp 115 << *MI;
126 << ": " << *MI;
133 << *MI;
lib/CodeGen/TargetSchedule.cpp 245 << *DefMI << " (Try with MCSchedModel.CompleteModel set to false)";
lib/CodeGen/TwoAddressInstructionPass.cpp 686 LLVM_DEBUG(dbgs() << "2addr: COMMUTING : " << *MI);
694 LLVM_DEBUG(dbgs() << "2addr: COMMUTED TO: " << *NewMI);
741 LLVM_DEBUG(dbgs() << "2addr: CONVERTING 2-ADDR: " << *mi);
742 LLVM_DEBUG(dbgs() << "2addr: TO 3-ADDR: " << *NewMI);
1018 LLVM_DEBUG(dbgs() << "\trescheduled below kill: " << *KillMI);
1184 LLVM_DEBUG(dbgs() << "\trescheduled kill: " << *KillMI);
1360 LLVM_DEBUG(dbgs() << "2addr: UNFOLDING: " << MI);
1382 LLVM_DEBUG(dbgs() << "2addr: NEW LOAD: " << *NewMIs[0]
1383 << "2addr: NEW INST: " << *NewMIs[1]);
1491 LLVM_DEBUG(dbgs() << "\t\trewrite undef:\t" << *MI);
1589 LLVM_DEBUG(dbgs() << "\t\tprepend:\t" << *MIB);
1731 LLVM_DEBUG(dbgs() << '\t' << *mi);
1758 LLVM_DEBUG(dbgs() << "\t\trewrite to:\t" << *mi);
1772 LLVM_DEBUG(dbgs() << "\t\tconvert to:\t" << *mi);
1804 LLVM_DEBUG(dbgs() << "Illegal REG_SEQUENCE instruction:" << MI);
1855 LLVM_DEBUG(dbgs() << "Inserted: " << *CopyMI);
1862 LLVM_DEBUG(dbgs() << "Turned: " << MI << " into an IMPLICIT_DEF");
1867 LLVM_DEBUG(dbgs() << "Eliminated: " << MI);
lib/CodeGen/VirtRegMap.cpp 377 LLVM_DEBUG(dbgs() << "Identity copy: " << MI);
388 LLVM_DEBUG(dbgs() << " replace by: " << MI);
584 LLVM_DEBUG(dbgs() << "> " << *MI);
lib/Target/AArch64/AArch64A53Fix835769.cpp 209 LLVM_DEBUG(dbgs() << " Examining: " << MI);
211 LLVM_DEBUG(dbgs() << " PrevInstr: " << *PrevInstr
212 << " CurrInstr: " << *CurrInstr
lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp 617 << printReg(DestReg, TRI) << " at " << *MI);
637 << printReg(AccumReg, TRI) << " in MI " << *MI);
lib/Target/AArch64/AArch64AdvSIMDScalarPass.cpp 279 LLVM_DEBUG(dbgs() << " adding copy: " << *MIB);
288 LLVM_DEBUG(dbgs() << "Scalar transform: " << MI);
lib/Target/AArch64/AArch64CollectLOH.cpp 388 << '\t' << MI << '\t' << *Info.LastADRP);
388 << '\t' << MI << '\t' << *Info.LastADRP);
398 << '\t' << MI << '\t' << *Info.MI0);
398 << '\t' << MI << '\t' << *Info.MI0);
405 << '\t' << MI << '\t' << *Info.MI0);
405 << '\t' << MI << '\t' << *Info.MI0);
412 << '\t' << MI << '\t' << *Info.MI1 << '\t'
412 << '\t' << MI << '\t' << *Info.MI1 << '\t'
413 << *Info.MI0);
420 << '\t' << MI << '\t' << *Info.MI1 << '\t'
420 << '\t' << MI << '\t' << *Info.MI1 << '\t'
421 << *Info.MI0);
428 << '\t' << MI << '\t' << *Info.MI1 << '\t'
428 << '\t' << MI << '\t' << *Info.MI1 << '\t'
429 << *Info.MI0);
435 << '\t' << MI << '\t' << *Info.MI1 << '\t'
435 << '\t' << MI << '\t' << *Info.MI1 << '\t'
436 << *Info.MI0);
442 << '\t' << MI << '\t' << *Info.MI0);
442 << '\t' << MI << '\t' << *Info.MI0);
lib/Target/AArch64/AArch64ConditionOptimizer.cpp 175 LLVM_DEBUG(dbgs() << "Immediate of cmp is symbolic, " << *I << '\n');
178 LLVM_DEBUG(dbgs() << "Immediate of cmp may be out of range, " << *I
182 LLVM_DEBUG(dbgs() << "Destination of cmp is not dead, " << *I << '\n');
lib/Target/AArch64/AArch64ConditionalCompares.cpp 313 LLVM_DEBUG(dbgs() << "Flags not used by terminator: " << *I);
331 LLVM_DEBUG(dbgs() << "Immediate out of range for ccmp: " << *I);
343 << *I);
361 LLVM_DEBUG(dbgs() << "Can't create ccmp with multiple uses: " << *I);
367 LLVM_DEBUG(dbgs() << "Not convertible compare: " << *I);
407 LLVM_DEBUG(dbgs() << "Can't hoist: " << I);
415 LLVM_DEBUG(dbgs() << "Won't speculate load: " << I);
422 LLVM_DEBUG(dbgs() << "Can't speculate: " << I);
428 LLVM_DEBUG(dbgs() << "Clobbers flags: " << I);
lib/Target/AArch64/AArch64FalkorHWPFFix.cpp 733 LLVM_DEBUG(dbgs() << "Attempting to fix tag collision: " << MI);
736 LLVM_DEBUG(dbgs() << "Skipping fix due to debug counter:\n " << MI);
lib/Target/AArch64/AArch64RedundantCopyElimination.cpp 414 LLVM_DEBUG(dbgs() << "Remove redundant Copy : " << *MI);
416 LLVM_DEBUG(dbgs() << "Remove redundant Move : " << *MI);
460 LLVM_DEBUG(dbgs() << "Clearing kill flags.\n\tFirstUse: " << *FirstUse
461 << "\tLastChange: " << *LastChange);
lib/Target/AArch64/AArch64SpeculationHardening.cpp 311 dbgs() << "to be available at MI " << MI);
336 << " on instruction: " << *MI_Reg.first);
346 << " around instruction: " << *MI_Reg.first);
475 LLVM_DEBUG(dbgs() << "About to harden: " << MI);
lib/Target/AArch64/AArch64StorePairSuppress.cpp 160 LLVM_DEBUG(dbgs() << "Unpairing store " << MI << "\n");
lib/Target/AMDGPU/AMDILCFGStructurizer.cpp 461 SHOWNEWINSTR(MI);
473 SHOWNEWINSTR(MI);
485 SHOWNEWINSTR(NewMBB);
498 SHOWNEWINSTR(NewMI);
510 SHOWNEWINSTR(NewInstr);
1560 LLVM_DEBUG(dbgs() << "migrateInstruction see branch instr: " << *BranchMI);
1590 LLVM_DEBUG(dbgs() << "Old branch instr: " << *BranchMI << "\n";);
1603 LLVM_DEBUG(dbgs() << "Removing uncond branch instr: " << *BranchMI);
1619 LLVM_DEBUG(dbgs() << "Removing unneeded cond branch instr: " << *BranchMI);
lib/Target/AMDGPU/GCNDPPCombine.cpp 257 LLVM_DEBUG(dbgs() << " combined: " << *DPPInst.getInstr());
352 LLVM_DEBUG(dbgs() << "\nDPP combine: " << MovMI);
455 LLVM_DEBUG(dbgs() << " try: " << OrigMI);
506 LLVM_DEBUG(dbgs() << " combining: " << OrigMI);
519 LLVM_DEBUG(dbgs() << " commuted: " << *NewMI);
lib/Target/AMDGPU/GCNIterativeScheduler.cpp 74 OS << '\t' << *I;
81 OS << '\t' << *I;
86 OS << *End;
lib/Target/AMDGPU/GCNNSAReassign.cpp 295 LLVM_DEBUG(dbgs() << "Attempting to reassign NSA: " << *MI
316 LLVM_DEBUG(dbgs() << "\tNSA conversion conflict with " << *I->first);
lib/Target/AMDGPU/GCNRegPressure.cpp 40 << *LIS.getInstructionFromIndex(SI);
lib/Target/AMDGPU/GCNSchedStrategy.cpp 308 << *SU->getInstr());
426 LLVM_DEBUG(dbgs() << "Scheduling " << *MI);
575 << MBB->getName() << "\n From: " << *begin()
577 if (RegionEnd != MBB->end()) dbgs() << *RegionEnd;
lib/Target/AMDGPU/SIFixSGPRCopies.cpp 498 << printMBBReference(*MI2->getParent()) << " " << *MI2);
508 << printMBBReference(*MI1->getParent()) << " " << *MI1);
526 << printMBBReference(*MI1->getParent()) << " " << *MI1
529 << printMBBReference(*I->getParent()) << " " << *MI2);
670 LLVM_DEBUG(dbgs() << "Fixing REG_SEQUENCE: " << MI);
682 LLVM_DEBUG(dbgs() << " Fixing INSERT_SUBREG: " << MI);
805 LLVM_DEBUG(dbgs() << "Moving PHI to AGPR: " << MI);
834 LLVM_DEBUG(dbgs() << "Fixing PHI: " << MI);
838 LLVM_DEBUG(dbgs() << "Legalizing PHI: " << MI);
lib/Target/AMDGPU/SIFixVGPRCopies.cpp 61 LLVM_DEBUG(dbgs() << "Add exec use to " << MI);
lib/Target/AMDGPU/SIFixupVectorISel.cpp 173 LLVM_DEBUG(dbgs() << "Global Mem opp " << MI << '\n');
214 LLVM_DEBUG(dbgs() << "New Global Mem " << *NewGlob << '\n');
lib/Target/AMDGPU/SIFoldOperands.cpp 325 << " operand " << OpNo << "\n " << *MI << '\n');
673 << "\n into " << *UseMI << '\n');
757 LLVM_DEBUG(dbgs() << "Folded " << *UseMI << '\n');
1093 LLVM_DEBUG(dbgs() << "Folded " << *MI << " into ");
1105 LLVM_DEBUG(dbgs() << *MI << '\n');
1146 LLVM_DEBUG(dbgs() << "Constant folded " << *UseMI << '\n');
1227 LLVM_DEBUG(dbgs() << "Folded source from " << MI << " into OpNo "
1229 << *Fold.UseMI << '\n');
1310 LLVM_DEBUG(dbgs() << "Folding clamp " << *DefClamp << " into " << *Def
1434 LLVM_DEBUG(dbgs() << "Folding omod " << MI << " into " << *Def << '\n');
1434 LLVM_DEBUG(dbgs() << "Folding omod " << MI << " into " << *Def << '\n');
lib/Target/AMDGPU/SIInsertWaitcnts.cpp 1142 << "Old Instr: " << MI << '\n'
1143 << "New Instr: " << *II << '\n');
1159 << "Old Instr: " << MI << '\n'
1160 << "New Instr: " << *SWaitInst << '\n');
1175 << "Old Instr: " << MI << '\n'
1176 << "New Instr: " << *SWaitInst << '\n');
lib/Target/AMDGPU/SILoadStoreOptimizer.cpp 950 LLVM_DEBUG(dbgs() << "Inserted read2: " << *Read2 << '\n');
1033 LLVM_DEBUG(dbgs() << "Inserted write2 inst: " << *Write2 << '\n');
lib/Target/AMDGPU/SILowerI1Copies.cpp 518 LLVM_DEBUG(dbgs() << "Lower copy from i1: " << MI);
567 LLVM_DEBUG(dbgs() << "Lower PHI: " << *MI);
689 LLVM_DEBUG(dbgs() << "Lower Other: " << MI);
lib/Target/AMDGPU/SIMachineScheduler.cpp 2038 << *SU->getInstr());
lib/Target/AMDGPU/SIOptimizeExecMasking.cpp 307 LLVM_DEBUG(dbgs() << "Fold exec copy: " << *PrepareExecInst);
311 LLVM_DEBUG(dbgs() << "into: " << *PrepareExecInst << '\n');
333 LLVM_DEBUG(dbgs() << "exec read prevents saveexec: " << *J << '\n');
356 LLVM_DEBUG(dbgs() << "Found save exec op: " << *SaveExecInst << '\n');
360 << "Instruction does not read exec copy: " << *J << '\n');
372 LLVM_DEBUG(dbgs() << "Found second use of save inst candidate: " << *J
386 LLVM_DEBUG(dbgs() << "Insert save exec op: " << *SaveExecInst << '\n');
lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp 253 LLVM_DEBUG(dbgs() << "Folding sequence:\n\t" << *Sel << '\t' << *Cmp << '\t'
253 LLVM_DEBUG(dbgs() << "Folding sequence:\n\t" << *Sel << '\t' << *Cmp << '\t'
254 << *And);
266 LLVM_DEBUG(dbgs() << "=>\n\t" << *Andn2 << '\n');
276 LLVM_DEBUG(dbgs() << "Erasing: " << *Cmp << '\n');
283 LLVM_DEBUG(dbgs() << "Erasing: " << *Sel << '\n');
354 << "Removing no effect instruction: " << *I << '\n');
393 LLVM_DEBUG(dbgs() << "Redundant EXEC = S_OR_B64 found: " << *Lead << '\n');
424 LLVM_DEBUG(dbgs() << "Redundant EXEC COPY: " << *SaveExec << '\n');
lib/Target/AMDGPU/SIPeepholeSDWA.cpp 855 LLVM_DEBUG(dbgs() << "Match: " << MI << "To: " << *Operand << '\n');
992 LLVM_DEBUG(dbgs() << "Convert instruction:" << MI);
1143 LLVM_DEBUG(dbgs() << *SDWAInst << "\nOperand: " << *Operand);
1164 LLVM_DEBUG(dbgs() << "\nInto:" << *SDWAInst << '\n');
lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp 195 LLVM_DEBUG(dbgs() << "entering WWM region: " << MI << "\n");
201 LLVM_DEBUG(dbgs() << "exiting WWM region: " << MI << "\n");
208 LLVM_DEBUG(dbgs() << "processing " << MI << "\n");
lib/Target/AMDGPU/SIShrinkInstructions.cpp 522 LLVM_DEBUG(dbgs() << "Matched v_swap_b32:\n" << MovT << *MovX << MovY);
522 LLVM_DEBUG(dbgs() << "Matched v_swap_b32:\n" << MovT << *MovX << MovY);
522 LLVM_DEBUG(dbgs() << "Matched v_swap_b32:\n" << MovT << *MovX << MovY);
783 LLVM_DEBUG(dbgs() << "Shrinking " << MI);
794 LLVM_DEBUG(dbgs() << "e32 MI = " << *Inst32 << '\n');
lib/Target/AMDGPU/SIWholeQuadMode.cpp 241 dbgs() << " " << MI << " Needs = " << PrintState(III->second.Needs)
lib/Target/ARC/ARCBranchFinalize.cpp 130 LLVM_DEBUG(dbgs() << "Branch: " << *MI << "\n");
158 LLVM_DEBUG(dbgs() << "Unknown (or size 0) size for: " << MI << "\n");
lib/Target/ARC/ARCOptAddrMode.cpp 192 LLVM_DEBUG(dbgs() << "[ABAW] tryToCombine " << Ldst);
237 dbgs() << "[ABAW] Instructions " << *First << " and " << *Last
237 dbgs() << "[ABAW] Instructions " << *First << " and " << *Last
275 LLVM_DEBUG(dbgs() << "canJoinInstructions: " << *First << *Last);
275 LLVM_DEBUG(dbgs() << "canJoinInstructions: " << *First << *Last);
356 << ": " << *MI);
464 LLVM_DEBUG(dbgs() << "[ABAW] New Ldst: " << Ldst);
lib/Target/ARC/ARCRegisterInfo.cpp 183 LLVM_DEBUG(dbgs() << MI << "\n");
lib/Target/ARM/A15SDOptimizer.cpp 182 LLVM_DEBUG(dbgs() << "Deleting base instruction " << *MI << "\n");
234 LLVM_DEBUG(dbgs() << "Deleting instruction " << *Def << "\n");
266 LLVM_DEBUG(dbgs() << "Found a subreg copy: " << *SPRMI);
389 LLVM_DEBUG(dbgs() << "Found partial copy" << *MI << "\n");
lib/Target/ARM/ARMBaseInstrInfo.cpp 1614 LLVM_DEBUG(dbgs() << "widening: " << MI);
1643 LLVM_DEBUG(dbgs() << "replaced by: " << MI);
lib/Target/ARM/ARMBasicBlockInfo.cpp 104 << int(DestOffset - BrOffset) << "\t" << *MI);
lib/Target/ARM/ARMConstantIslandPass.cpp 1075 << format("%#x-%x\t", BBI.Offset, BBI.postOffset()) << *MI
1639 LLVM_DEBUG(dbgs() << " Changed B to long jump " << *MI);
1685 << *BMI);
1806 LLVM_DEBUG(dbgs() << "Shrink: " << *U.MI);
1844 LLVM_DEBUG(dbgs() << "Shrink branch: " << *Br.MI);
1971 LLVM_DEBUG(dbgs() << "Fold: " << *Cmp.MI << " and: " << *Br.MI);
1971 LLVM_DEBUG(dbgs() << "Fold: " << *Cmp.MI << " and: " << *Br.MI);
2151 LLVM_DEBUG(dbgs() << "Removing Dead Add: " << *RemovableAdd);
2288 LLVM_DEBUG(dbgs() << "Shrink JT: " << *MI);
2302 LLVM_DEBUG(dbgs() << printMBBReference(*MBB) << ": " << *NewJTMI);
lib/Target/ARM/ARMLoadStoreOptimizer.cpp 2340 LLVM_DEBUG(dbgs() << "Formed " << *MIB << "\n");
2354 LLVM_DEBUG(dbgs() << "Formed " << *MIB << "\n");
lib/Target/ARM/ARMLowOverheadLoops.cpp 296 LLVM_DEBUG(dbgs() << "ARM Loops: Found LR Use/Def: " << MI);
307 LLVM_DEBUG(if (Start) dbgs() << "ARM Loops: Found Loop Start: " << *Start;
308 if (Dec) dbgs() << "ARM Loops: Found Loop Dec: " << *Dec;
309 if (End) dbgs() << "ARM Loops: Found Loop End: " << *End;);
349 LLVM_DEBUG(dbgs() << "ARM Loops: Start insertion point: " << *InsertPt);
360 LLVM_DEBUG(dbgs() << "ARM Loops: Reverting to cmp: " << *MI);
382 LLVM_DEBUG(dbgs() << "ARM Loops: Reverting to sub: " << *MI);
415 LLVM_DEBUG(dbgs() << "ARM Loops: Reverting to cmp, br: " << *MI);
462 LLVM_DEBUG(dbgs() << "ARM Loops: Inserted start: " << *MIB);
475 LLVM_DEBUG(dbgs() << "ARM Loops: Inserted LE: " << *MIB);
493 LLVM_DEBUG(dbgs() << "ARM Loops: Removing branch: " << *Terminator);
lib/Target/ARM/MLxExpansionPass.cpp 310 dbgs() << "Expanding: " << *MI;
317 dbgs() << " " << MI1;
318 dbgs() << " " << MI2;
lib/Target/ARM/Thumb2SizeReduction.cpp 613 LLVM_DEBUG(errs() << "Converted 32-bit: " << *MI
614 << " to 16-bit: " << *MIB);
661 LLVM_DEBUG(errs() << "Converted 32-bit: " << *MI
662 << " to 16-bit: " << *MIB);
841 LLVM_DEBUG(errs() << "Converted 32-bit: " << *MI
842 << " to 16-bit: " << *MIB);
964 LLVM_DEBUG(errs() << "Converted 32-bit: " << *MI
965 << " to 16-bit: " << *MIB);
lib/Target/Hexagon/BitTracker.cpp 801 dbgs() << "Visit FI(" << printMBBReference(*PI.getParent()) << "): " << PI;
845 dbgs() << "Visit MI(" << printMBBReference(*MI.getParent()) << "): " << MI;
930 dbgs() << "Visit BR(" << printMBBReference(B) << "): " << MI;
lib/Target/Hexagon/HexagonBitSimplify.cpp 2460 << ", MI: " << *MI;
3258 dbgs() << " " << *G.Ins[j];
lib/Target/Hexagon/HexagonBlockRanges.cpp 524 OS << Idx << (Idx == M.Last ? ". " : " ") << In;
lib/Target/Hexagon/HexagonBranchRelaxation.cpp 203 << HII->isConstExtended(MI) << ") " << MI);
lib/Target/Hexagon/HexagonConstExtenders.cpp 1578 << *InitI);
1693 dbgs() << '\n' << MI;
1743 << " for " << MI;
1819 dbgs() << '\n' << PrintInit(ExtI, *HRI) << " " << MI;
lib/Target/Hexagon/HexagonConstPropagation.cpp 622 LLVM_DEBUG(dbgs() << "Visiting FI(" << printMBBReference(*MB) << "): " << PN);
678 << "): " << MI);
735 << printMBBReference(B) << "): " << MI);
2802 << " in MI: " << MI;
2812 dbgs() << "CONST: " << MI;
2936 dbgs() << "Rewrite: for " << MI << " created " << *NewInstrs[0];
2936 dbgs() << "Rewrite: for " << MI << " created " << *NewInstrs[0];
2938 dbgs() << " " << *NewInstrs[i];
3101 dbgs() << "Rewrite: for " << MI;
3103 dbgs() << " created " << *NewMI;
3105 dbgs() << " modified the instruction itself and created:" << *NewMI;
3139 LLVM_DEBUG(dbgs() << "Rewrite(" << printMBBReference(B) << "):" << BrI);
lib/Target/Hexagon/HexagonEarlyIfConv.cpp 752 dbgs() << *MI;
lib/Target/Hexagon/HexagonExpandCondsets.cpp 656 LLVM_DEBUG(dbgs() << "created an initial copy: " << *MIB);
670 << ": " << MI);
941 << ": " << TfrI);
962 LLVM_DEBUG(dbgs() << "Source def: " << *DefI);
lib/Target/Hexagon/HexagonGenPredicate.cpp 368 LLVM_DEBUG(dbgs() << __func__ << ": " << MI << " " << *MI);
430 LLVM_DEBUG(dbgs() << "generated: " << *MIB);
lib/Target/Hexagon/HexagonHardwareLoops.cpp 1086 LLVM_DEBUG(dbgs() << "HW looping will remove: " << *MI);
1771 << ") = " << *(MRI->getVRegDef(I->first)));
1779 << ") = " << *(MRI->getVRegDef(MO.getReg())));
lib/Target/Hexagon/HexagonHazardRecognizer.cpp 45 LLVM_DEBUG(dbgs() << "*** Hazard in cycle " << PacketNum << ", " << *MI);
70 << *MI);
136 LLVM_DEBUG(dbgs() << " Add instruction " << *MI);
lib/Target/Hexagon/HexagonOptAddrMode.cpp 400 << ">]: " << *UseMI << "\n");
454 LLVM_DEBUG(dbgs() << "\nGetting ReachedUses for === " << MI << "\n");
519 LLVM_DEBUG(dbgs() << "[Changing]: " << *OldMI << "\n");
520 LLVM_DEBUG(dbgs() << "[TO]: " << *MIB << "\n");
531 LLVM_DEBUG(dbgs() << "[Changing]: " << *OldMI << "\n");
532 LLVM_DEBUG(dbgs() << "[TO]: " << *MIB << "\n");
574 LLVM_DEBUG(dbgs() << "[Changing]: " << *OldMI << "\n");
575 LLVM_DEBUG(dbgs() << "[TO]: " << *MIB << "\n");
584 LLVM_DEBUG(dbgs() << "[Changing]: " << *OldMI << "\n");
585 LLVM_DEBUG(dbgs() << "[TO]: " << *MIB << "\n");
608 LLVM_DEBUG(dbgs() << "Processing addasl :" << *AddAslMI << "\n");
623 << ">]: " << *UseMI << "\n");
702 << "]: " << *MI << "\n\t[InstrNode]: "
750 << ">]: " << *UseMI << "\n");
lib/Target/Hexagon/HexagonRDFOpt.cpp 181 dbgs() << "Partly dead: " << *SA.Addr->getCode();
271 dbgs() << "Rewriting: " << MI;
276 dbgs() << " to: " << MI;
lib/Target/Hexagon/HexagonSplitDouble.cpp 998 LLVM_DEBUG(dbgs() << "Splitting: " << *MI);
lib/Target/Hexagon/HexagonStoreWidening.cpp 140 dbgs() << *MI;
477 dbgs() << " " << *I;
480 dbgs() << " " << *I;
lib/Target/Hexagon/HexagonVLIWPacketizer.cpp 1773 dbgs() << " * [res:0x" << utohexstr(R) << "] " << *MI;
lib/Target/Hexagon/RDFCopy.cpp 107 dbgs() << "Instr: " << *DFG.addr<StmtNode*>(I).Addr->getCode();
176 << *NodeAddr<StmtNode*>(IA).Addr->getCode();
lib/Target/Hexagon/RDFDeadCode.cpp 239 dbgs() << "erasing: " << *MI;
lib/Target/Hexagon/RDFGraph.cpp 1107 << Print<RegisterRef>(RR, *this) << " in\n " << *MI << "in "
lib/Target/Mips/MicroMipsSizeReduction.cpp 700 LLVM_DEBUG(dbgs() << "Converting 32-bit: " << *MI);
705 LLVM_DEBUG(dbgs() << " to 16-bit: " << *MI);
754 LLVM_DEBUG(dbgs() << "and converting 32-bit: " << *MI2
755 << " to: " << *MIB);
768 LLVM_DEBUG(dbgs() << " to 16-bit: " << *MIB);
lib/Target/Mips/MipsConstantIslandPass.cpp 988 << format("%#x-%x\t", BBI.Offset, BBI.postOffset()) << *MI
1469 << int(DestOffset - BrOffset) << "\t" << *MI);
1534 LLVM_DEBUG(dbgs() << " Changed B to long jump " << *MI);
1591 << *BMI);
1649 LLVM_DEBUG(dbgs() << "constant island constant " << *I << "\n");
1661 LLVM_DEBUG(dbgs() << "constant island constant " << *I << "\n");
lib/Target/Mips/MipsRegisterInfo.cpp 264 << MI);
lib/Target/PowerPC/PPCBranchCoalescing.cpp 245 LLVM_DEBUG(dbgs() << "Looking at terminator : " << I << "\n");
264 << I << "\n");
364 LLVM_DEBUG(dbgs() << "Op1Def: " << *Op1Def << " and " << *Op2Def
364 LLVM_DEBUG(dbgs() << "Op1Def: " << *Op1Def << " and " << *Op2Def
425 LLVM_DEBUG(dbgs() << "Checking if " << MI << " can move to beginning of "
456 LLVM_DEBUG(dbgs() << "Checking if " << MI << " can move to end of "
543 << "PHI " << *I
550 LLVM_DEBUG(dbgs() << "PHI " << *I
565 LLVM_DEBUG(dbgs() << "Instruction " << *I
570 LLVM_DEBUG(dbgs() << "Instruction " << *I
lib/Target/PowerPC/PPCCTRLoops.cpp 156 << ") instruction " << *I
160 << *BI << "\n");
177 << *BI << "\n");
lib/Target/PowerPC/PPCExpandISEL.cpp 214 LLVM_DEBUG(dbgs() << "Remove redundant ISEL instruction: " << **I
230 LLVM_DEBUG(dbgs() << "ISEL: " << **I << "\n");
242 LLVM_DEBUG(dbgs() << "ISEL: " << **I << "\n");
250 LLVM_DEBUG(dbgs() << "ISEL: " << **I << "\n");
270 LLVM_DEBUG(dbgs() << "ISEL: " << **MI << "\n");
lib/Target/PowerPC/PPCPreEmitPeephole.cpp 102 << " from load immediate " << *BBI
117 << *AfterBBI << " is a unsetting candidate\n");
140 << " from " << *DeadOrKillToUnset->getParent());
151 << *AfterBBI << " is a unsetting candidate\n");
lib/Target/PowerPC/PPCTLSDynamicCall.cpp 75 LLVM_DEBUG(dbgs() << "TLS Dynamic Call Fixup:\n " << MI);
lib/Target/PowerPC/PPCVSXFMAMutate.cpp 243 LLVM_DEBUG(dbgs() << "VSX FMA Mutation:\n " << MI);
275 LLVM_DEBUG(dbgs() << " -> " << MI);
333 LLVM_DEBUG(dbgs() << " removing: " << *AddendMI << '\n');
lib/Target/RISCV/RISCVMergeBaseOffset.cpp 113 << " " << HiLUI << " " << LoADDI;);
113 << " " << HiLUI << " " << LoADDI;);
163 LLVM_DEBUG(dbgs() << " Offset Instrs: " << OffsetTail
164 << " " << OffsetLui);
171 LLVM_DEBUG(dbgs() << " Offset Instr: " << OffsetTail);
188 << Tail);
193 LLVM_DEBUG(dbgs() << " Offset Instr: " << Tail);
lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp 309 LLVM_DEBUG(dbgs() << "EmitInstruction: " << *MI << '\n');
lib/Target/WebAssembly/WebAssemblyCallIndirectFixup.cpp 113 LLVM_DEBUG(dbgs() << "Found call_indirect: " << MI << '\n');
141 LLVM_DEBUG(dbgs() << " After transform: " << MI);
lib/Target/WebAssembly/WebAssemblyMemIntrinsicResults.cpp 120 LLVM_DEBUG(dbgs() << "Setting operand " << O << " in " << *Where << " from "
121 << MI << "\n");
lib/Target/X86/X86FloatingPoint.cpp 443 LLVM_DEBUG(dbgs() << "\nFPInst:\t" << MI);
lib/Target/X86/X86InstrInfo.cpp 4995 dbgs() << "We failed to fuse operand " << OpNum << " in " << MI;