|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/AArch64/AArch64GenInstrInfo.inc18018 AArch64_AM::getArithShiftValue(MI.getOperand(3).getImm()) == 0
18021 AArch64_AM::getArithExtendType(MI.getOperand(3).getImm()) == AArch64_AM::UXTW
18022 || AArch64_AM::getArithExtendType(MI.getOperand(3).getImm()) == AArch64_AM::UXTX
18025 AArch64_AM::getArithShiftValue(MI.getOperand(3).getImm()) == 1
18026 || AArch64_AM::getArithShiftValue(MI.getOperand(3).getImm()) == 2
18027 || AArch64_AM::getArithShiftValue(MI.getOperand(3).getImm()) == 3
18040 AArch64_AM::getShiftValue(MI.getOperand(3).getImm()) == 0
18042 AArch64_AM::getShiftType(MI.getOperand(3).getImm()) == AArch64_AM::LSL
18044 AArch64_AM::getShiftValue(MI.getOperand(3).getImm()) == 1
18045 || AArch64_AM::getShiftValue(MI.getOperand(3).getImm()) == 2
18046 || AArch64_AM::getShiftValue(MI.getOperand(3).getImm()) == 3
18110 AArch64_AM::getShiftValue(MI.getOperand(3).getImm()) == 0
18112 AArch64_AM::getShiftType(MI.getOperand(3).getImm()) == AArch64_AM::LSL
18114 AArch64_AM::getShiftValue(MI.getOperand(3).getImm()) == 1
18115 || AArch64_AM::getShiftValue(MI.getOperand(3).getImm()) == 2
18116 || AArch64_AM::getShiftValue(MI.getOperand(3).getImm()) == 3
18121 AArch64_AM::getShiftType(MI.getOperand(3).getImm()) == AArch64_AM::LSL
18122 && AArch64_AM::getShiftValue(MI.getOperand(3).getImm()) == 8
18166 AArch64_AM::getShiftValue(MI.getOperand(3).getImm()) == 0
18168 AArch64_AM::getShiftType(MI.getOperand(3).getImm()) == AArch64_AM::LSL
18170 AArch64_AM::getShiftValue(MI.getOperand(3).getImm()) == 1
18171 || AArch64_AM::getShiftValue(MI.getOperand(3).getImm()) == 2
18172 || AArch64_AM::getShiftValue(MI.getOperand(3).getImm()) == 3
18210 MI.getOperand(1).isReg()
18212 MI.getOperand(1).getReg() == AArch64::WZR
18213 || MI.getOperand(1).getReg() == AArch64::XZR
18271 AArch64_AM::getMemExtendType(MI.getOperand(3).getImm()) == AArch64_AM::SXTW
18272 || AArch64_AM::getMemExtendType(MI.getOperand(3).getImm()) == AArch64_AM::UXTW
18273 || AArch64_AM::getMemDoShift(MI.getOperand(3).getImm())
18285 MI.getOperand(0).isReg()
18286 && MI.getOperand(1).isReg()
18288 MI.getOperand(0).getReg() == AArch64::WSP
18289 || MI.getOperand(0).getReg() == AArch64::SP
18290 || MI.getOperand(1).getReg() == AArch64::WSP
18291 || MI.getOperand(1).getReg() == AArch64::SP
18293 && MI.getOperand(2).getImm() == 0
18298 MI.getOperand(1).isReg()
18299 && MI.getOperand(2).isReg()
18301 MI.getOperand(1).getReg() == AArch64::WZR
18302 || MI.getOperand(1).getReg() == AArch64::XZR
18304 && AArch64_AM::getShiftValue(MI.getOperand(3).getImm()) == 0
18317 return MI.getOperand(1).getImm() == 0;
18323 MI.getOperand(1).getImm() == 0
18324 && MI.getOperand(2).getImm() == 0
18336 MI.getOperand(1).isReg()
18338 MI.getOperand(1).getReg() == AArch64::WZR
18339 || MI.getOperand(1).getReg() == AArch64::XZR
18341 && MI.getOperand(2).getImm() == 0
18362 return MI.getOperand(3).getImm() != 0;
18394 return MI.getOperand(3).getImm() != 0;
18447 AArch64_AM::getMemExtendType(MI.getOperand(3).getImm()) != AArch64_AM::UXTX
18448 || AArch64_AM::getMemDoShift(MI.getOperand(3).getImm())
gen/lib/Target/AArch64/AArch64GenSubtargetInfo.inc18036 && MI->getOperand(1).getReg() == MI->getOperand(2).getReg()
18036 && MI->getOperand(1).getReg() == MI->getOperand(2).getReg()
18047 && MI->getOperand(1).getReg() == MI->getOperand(2).getReg()
18047 && MI->getOperand(1).getReg() == MI->getOperand(2).getReg()
18057 MI->getOperand(0).isReg()
18059 MI->getOperand(0).getReg() == AArch64::D0
18060 || MI->getOperand(0).getReg() == AArch64::D1
18061 || MI->getOperand(0).getReg() == AArch64::D2
18062 || MI->getOperand(0).getReg() == AArch64::D3
18063 || MI->getOperand(0).getReg() == AArch64::D4
18064 || MI->getOperand(0).getReg() == AArch64::D5
18065 || MI->getOperand(0).getReg() == AArch64::D6
18066 || MI->getOperand(0).getReg() == AArch64::D7
18067 || MI->getOperand(0).getReg() == AArch64::D8
18068 || MI->getOperand(0).getReg() == AArch64::D9
18069 || MI->getOperand(0).getReg() == AArch64::D10
18070 || MI->getOperand(0).getReg() == AArch64::D11
18071 || MI->getOperand(0).getReg() == AArch64::D12
18072 || MI->getOperand(0).getReg() == AArch64::D13
18073 || MI->getOperand(0).getReg() == AArch64::D14
18074 || MI->getOperand(0).getReg() == AArch64::D15
18075 || MI->getOperand(0).getReg() == AArch64::D16
18076 || MI->getOperand(0).getReg() == AArch64::D17
18077 || MI->getOperand(0).getReg() == AArch64::D18
18078 || MI->getOperand(0).getReg() == AArch64::D19
18079 || MI->getOperand(0).getReg() == AArch64::D20
18080 || MI->getOperand(0).getReg() == AArch64::D21
18081 || MI->getOperand(0).getReg() == AArch64::D22
18082 || MI->getOperand(0).getReg() == AArch64::D23
18083 || MI->getOperand(0).getReg() == AArch64::D24
18084 || MI->getOperand(0).getReg() == AArch64::D25
18085 || MI->getOperand(0).getReg() == AArch64::D26
18086 || MI->getOperand(0).getReg() == AArch64::D27
18087 || MI->getOperand(0).getReg() == AArch64::D28
18088 || MI->getOperand(0).getReg() == AArch64::D29
18089 || MI->getOperand(0).getReg() == AArch64::D30
18090 || MI->getOperand(0).getReg() == AArch64::D31
18094 MI->getOperand(0).isReg()
18096 MI->getOperand(0).getReg() == AArch64::Q0
18097 || MI->getOperand(0).getReg() == AArch64::Q1
18098 || MI->getOperand(0).getReg() == AArch64::Q2
18099 || MI->getOperand(0).getReg() == AArch64::Q3
18100 || MI->getOperand(0).getReg() == AArch64::Q4
18101 || MI->getOperand(0).getReg() == AArch64::Q5
18102 || MI->getOperand(0).getReg() == AArch64::Q6
18103 || MI->getOperand(0).getReg() == AArch64::Q7
18104 || MI->getOperand(0).getReg() == AArch64::Q8
18105 || MI->getOperand(0).getReg() == AArch64::Q9
18106 || MI->getOperand(0).getReg() == AArch64::Q10
18107 || MI->getOperand(0).getReg() == AArch64::Q11
18108 || MI->getOperand(0).getReg() == AArch64::Q12
18109 || MI->getOperand(0).getReg() == AArch64::Q13
18110 || MI->getOperand(0).getReg() == AArch64::Q14
18111 || MI->getOperand(0).getReg() == AArch64::Q15
18112 || MI->getOperand(0).getReg() == AArch64::Q16
18113 || MI->getOperand(0).getReg() == AArch64::Q17
18114 || MI->getOperand(0).getReg() == AArch64::Q18
18115 || MI->getOperand(0).getReg() == AArch64::Q19
18116 || MI->getOperand(0).getReg() == AArch64::Q20
18117 || MI->getOperand(0).getReg() == AArch64::Q21
18118 || MI->getOperand(0).getReg() == AArch64::Q22
18119 || MI->getOperand(0).getReg() == AArch64::Q23
18120 || MI->getOperand(0).getReg() == AArch64::Q24
18121 || MI->getOperand(0).getReg() == AArch64::Q25
18122 || MI->getOperand(0).getReg() == AArch64::Q26
18123 || MI->getOperand(0).getReg() == AArch64::Q27
18124 || MI->getOperand(0).getReg() == AArch64::Q28
18125 || MI->getOperand(0).getReg() == AArch64::Q29
18126 || MI->getOperand(0).getReg() == AArch64::Q30
18127 || MI->getOperand(0).getReg() == AArch64::Q31
18203 MI->getOperand(0).isReg()
18205 MI->getOperand(0).getReg() == AArch64::D0
18206 || MI->getOperand(0).getReg() == AArch64::D1
18207 || MI->getOperand(0).getReg() == AArch64::D2
18208 || MI->getOperand(0).getReg() == AArch64::D3
18209 || MI->getOperand(0).getReg() == AArch64::D4
18210 || MI->getOperand(0).getReg() == AArch64::D5
18211 || MI->getOperand(0).getReg() == AArch64::D6
18212 || MI->getOperand(0).getReg() == AArch64::D7
18213 || MI->getOperand(0).getReg() == AArch64::D8
18214 || MI->getOperand(0).getReg() == AArch64::D9
18215 || MI->getOperand(0).getReg() == AArch64::D10
18216 || MI->getOperand(0).getReg() == AArch64::D11
18217 || MI->getOperand(0).getReg() == AArch64::D12
18218 || MI->getOperand(0).getReg() == AArch64::D13
18219 || MI->getOperand(0).getReg() == AArch64::D14
18220 || MI->getOperand(0).getReg() == AArch64::D15
18221 || MI->getOperand(0).getReg() == AArch64::D16
18222 || MI->getOperand(0).getReg() == AArch64::D17
18223 || MI->getOperand(0).getReg() == AArch64::D18
18224 || MI->getOperand(0).getReg() == AArch64::D19
18225 || MI->getOperand(0).getReg() == AArch64::D20
18226 || MI->getOperand(0).getReg() == AArch64::D21
18227 || MI->getOperand(0).getReg() == AArch64::D22
18228 || MI->getOperand(0).getReg() == AArch64::D23
18229 || MI->getOperand(0).getReg() == AArch64::D24
18230 || MI->getOperand(0).getReg() == AArch64::D25
18231 || MI->getOperand(0).getReg() == AArch64::D26
18232 || MI->getOperand(0).getReg() == AArch64::D27
18233 || MI->getOperand(0).getReg() == AArch64::D28
18234 || MI->getOperand(0).getReg() == AArch64::D29
18235 || MI->getOperand(0).getReg() == AArch64::D30
18236 || MI->getOperand(0).getReg() == AArch64::D31
18240 MI->getOperand(0).isReg()
18242 MI->getOperand(0).getReg() == AArch64::Q0
18243 || MI->getOperand(0).getReg() == AArch64::Q1
18244 || MI->getOperand(0).getReg() == AArch64::Q2
18245 || MI->getOperand(0).getReg() == AArch64::Q3
18246 || MI->getOperand(0).getReg() == AArch64::Q4
18247 || MI->getOperand(0).getReg() == AArch64::Q5
18248 || MI->getOperand(0).getReg() == AArch64::Q6
18249 || MI->getOperand(0).getReg() == AArch64::Q7
18250 || MI->getOperand(0).getReg() == AArch64::Q8
18251 || MI->getOperand(0).getReg() == AArch64::Q9
18252 || MI->getOperand(0).getReg() == AArch64::Q10
18253 || MI->getOperand(0).getReg() == AArch64::Q11
18254 || MI->getOperand(0).getReg() == AArch64::Q12
18255 || MI->getOperand(0).getReg() == AArch64::Q13
18256 || MI->getOperand(0).getReg() == AArch64::Q14
18257 || MI->getOperand(0).getReg() == AArch64::Q15
18258 || MI->getOperand(0).getReg() == AArch64::Q16
18259 || MI->getOperand(0).getReg() == AArch64::Q17
18260 || MI->getOperand(0).getReg() == AArch64::Q18
18261 || MI->getOperand(0).getReg() == AArch64::Q19
18262 || MI->getOperand(0).getReg() == AArch64::Q20
18263 || MI->getOperand(0).getReg() == AArch64::Q21
18264 || MI->getOperand(0).getReg() == AArch64::Q22
18265 || MI->getOperand(0).getReg() == AArch64::Q23
18266 || MI->getOperand(0).getReg() == AArch64::Q24
18267 || MI->getOperand(0).getReg() == AArch64::Q25
18268 || MI->getOperand(0).getReg() == AArch64::Q26
18269 || MI->getOperand(0).getReg() == AArch64::Q27
18270 || MI->getOperand(0).getReg() == AArch64::Q28
18271 || MI->getOperand(0).getReg() == AArch64::Q29
18272 || MI->getOperand(0).getReg() == AArch64::Q30
18273 || MI->getOperand(0).getReg() == AArch64::Q31
18283 MI->getOperand(0).isReg()
18285 MI->getOperand(0).getReg() == AArch64::D0
18286 || MI->getOperand(0).getReg() == AArch64::D1
18287 || MI->getOperand(0).getReg() == AArch64::D2
18288 || MI->getOperand(0).getReg() == AArch64::D3
18289 || MI->getOperand(0).getReg() == AArch64::D4
18290 || MI->getOperand(0).getReg() == AArch64::D5
18291 || MI->getOperand(0).getReg() == AArch64::D6
18292 || MI->getOperand(0).getReg() == AArch64::D7
18293 || MI->getOperand(0).getReg() == AArch64::D8
18294 || MI->getOperand(0).getReg() == AArch64::D9
18295 || MI->getOperand(0).getReg() == AArch64::D10
18296 || MI->getOperand(0).getReg() == AArch64::D11
18297 || MI->getOperand(0).getReg() == AArch64::D12
18298 || MI->getOperand(0).getReg() == AArch64::D13
18299 || MI->getOperand(0).getReg() == AArch64::D14
18300 || MI->getOperand(0).getReg() == AArch64::D15
18301 || MI->getOperand(0).getReg() == AArch64::D16
18302 || MI->getOperand(0).getReg() == AArch64::D17
18303 || MI->getOperand(0).getReg() == AArch64::D18
18304 || MI->getOperand(0).getReg() == AArch64::D19
18305 || MI->getOperand(0).getReg() == AArch64::D20
18306 || MI->getOperand(0).getReg() == AArch64::D21
18307 || MI->getOperand(0).getReg() == AArch64::D22
18308 || MI->getOperand(0).getReg() == AArch64::D23
18309 || MI->getOperand(0).getReg() == AArch64::D24
18310 || MI->getOperand(0).getReg() == AArch64::D25
18311 || MI->getOperand(0).getReg() == AArch64::D26
18312 || MI->getOperand(0).getReg() == AArch64::D27
18313 || MI->getOperand(0).getReg() == AArch64::D28
18314 || MI->getOperand(0).getReg() == AArch64::D29
18315 || MI->getOperand(0).getReg() == AArch64::D30
18316 || MI->getOperand(0).getReg() == AArch64::D31
18320 MI->getOperand(0).isReg()
18322 MI->getOperand(0).getReg() == AArch64::Q0
18323 || MI->getOperand(0).getReg() == AArch64::Q1
18324 || MI->getOperand(0).getReg() == AArch64::Q2
18325 || MI->getOperand(0).getReg() == AArch64::Q3
18326 || MI->getOperand(0).getReg() == AArch64::Q4
18327 || MI->getOperand(0).getReg() == AArch64::Q5
18328 || MI->getOperand(0).getReg() == AArch64::Q6
18329 || MI->getOperand(0).getReg() == AArch64::Q7
18330 || MI->getOperand(0).getReg() == AArch64::Q8
18331 || MI->getOperand(0).getReg() == AArch64::Q9
18332 || MI->getOperand(0).getReg() == AArch64::Q10
18333 || MI->getOperand(0).getReg() == AArch64::Q11
18334 || MI->getOperand(0).getReg() == AArch64::Q12
18335 || MI->getOperand(0).getReg() == AArch64::Q13
18336 || MI->getOperand(0).getReg() == AArch64::Q14
18337 || MI->getOperand(0).getReg() == AArch64::Q15
18338 || MI->getOperand(0).getReg() == AArch64::Q16
18339 || MI->getOperand(0).getReg() == AArch64::Q17
18340 || MI->getOperand(0).getReg() == AArch64::Q18
18341 || MI->getOperand(0).getReg() == AArch64::Q19
18342 || MI->getOperand(0).getReg() == AArch64::Q20
18343 || MI->getOperand(0).getReg() == AArch64::Q21
18344 || MI->getOperand(0).getReg() == AArch64::Q22
18345 || MI->getOperand(0).getReg() == AArch64::Q23
18346 || MI->getOperand(0).getReg() == AArch64::Q24
18347 || MI->getOperand(0).getReg() == AArch64::Q25
18348 || MI->getOperand(0).getReg() == AArch64::Q26
18349 || MI->getOperand(0).getReg() == AArch64::Q27
18350 || MI->getOperand(0).getReg() == AArch64::Q28
18351 || MI->getOperand(0).getReg() == AArch64::Q29
18352 || MI->getOperand(0).getReg() == AArch64::Q30
18353 || MI->getOperand(0).getReg() == AArch64::Q31
18363 MI->getOperand(0).isReg()
18365 MI->getOperand(0).getReg() == AArch64::D0
18366 || MI->getOperand(0).getReg() == AArch64::D1
18367 || MI->getOperand(0).getReg() == AArch64::D2
18368 || MI->getOperand(0).getReg() == AArch64::D3
18369 || MI->getOperand(0).getReg() == AArch64::D4
18370 || MI->getOperand(0).getReg() == AArch64::D5
18371 || MI->getOperand(0).getReg() == AArch64::D6
18372 || MI->getOperand(0).getReg() == AArch64::D7
18373 || MI->getOperand(0).getReg() == AArch64::D8
18374 || MI->getOperand(0).getReg() == AArch64::D9
18375 || MI->getOperand(0).getReg() == AArch64::D10
18376 || MI->getOperand(0).getReg() == AArch64::D11
18377 || MI->getOperand(0).getReg() == AArch64::D12
18378 || MI->getOperand(0).getReg() == AArch64::D13
18379 || MI->getOperand(0).getReg() == AArch64::D14
18380 || MI->getOperand(0).getReg() == AArch64::D15
18381 || MI->getOperand(0).getReg() == AArch64::D16
18382 || MI->getOperand(0).getReg() == AArch64::D17
18383 || MI->getOperand(0).getReg() == AArch64::D18
18384 || MI->getOperand(0).getReg() == AArch64::D19
18385 || MI->getOperand(0).getReg() == AArch64::D20
18386 || MI->getOperand(0).getReg() == AArch64::D21
18387 || MI->getOperand(0).getReg() == AArch64::D22
18388 || MI->getOperand(0).getReg() == AArch64::D23
18389 || MI->getOperand(0).getReg() == AArch64::D24
18390 || MI->getOperand(0).getReg() == AArch64::D25
18391 || MI->getOperand(0).getReg() == AArch64::D26
18392 || MI->getOperand(0).getReg() == AArch64::D27
18393 || MI->getOperand(0).getReg() == AArch64::D28
18394 || MI->getOperand(0).getReg() == AArch64::D29
18395 || MI->getOperand(0).getReg() == AArch64::D30
18396 || MI->getOperand(0).getReg() == AArch64::D31
18400 MI->getOperand(0).isReg()
18402 MI->getOperand(0).getReg() == AArch64::Q0
18403 || MI->getOperand(0).getReg() == AArch64::Q1
18404 || MI->getOperand(0).getReg() == AArch64::Q2
18405 || MI->getOperand(0).getReg() == AArch64::Q3
18406 || MI->getOperand(0).getReg() == AArch64::Q4
18407 || MI->getOperand(0).getReg() == AArch64::Q5
18408 || MI->getOperand(0).getReg() == AArch64::Q6
18409 || MI->getOperand(0).getReg() == AArch64::Q7
18410 || MI->getOperand(0).getReg() == AArch64::Q8
18411 || MI->getOperand(0).getReg() == AArch64::Q9
18412 || MI->getOperand(0).getReg() == AArch64::Q10
18413 || MI->getOperand(0).getReg() == AArch64::Q11
18414 || MI->getOperand(0).getReg() == AArch64::Q12
18415 || MI->getOperand(0).getReg() == AArch64::Q13
18416 || MI->getOperand(0).getReg() == AArch64::Q14
18417 || MI->getOperand(0).getReg() == AArch64::Q15
18418 || MI->getOperand(0).getReg() == AArch64::Q16
18419 || MI->getOperand(0).getReg() == AArch64::Q17
18420 || MI->getOperand(0).getReg() == AArch64::Q18
18421 || MI->getOperand(0).getReg() == AArch64::Q19
18422 || MI->getOperand(0).getReg() == AArch64::Q20
18423 || MI->getOperand(0).getReg() == AArch64::Q21
18424 || MI->getOperand(0).getReg() == AArch64::Q22
18425 || MI->getOperand(0).getReg() == AArch64::Q23
18426 || MI->getOperand(0).getReg() == AArch64::Q24
18427 || MI->getOperand(0).getReg() == AArch64::Q25
18428 || MI->getOperand(0).getReg() == AArch64::Q26
18429 || MI->getOperand(0).getReg() == AArch64::Q27
18430 || MI->getOperand(0).getReg() == AArch64::Q28
18431 || MI->getOperand(0).getReg() == AArch64::Q29
18432 || MI->getOperand(0).getReg() == AArch64::Q30
18433 || MI->getOperand(0).getReg() == AArch64::Q31
18445 && MI->getOperand(0).getReg() == AArch64::LR
18453 && MI->getOperand(0).getReg() == AArch64::LR
18461 && MI->getOperand(0).getReg() == AArch64::LR
18517 && MI->getOperand(1).getReg() == MI->getOperand(2).getReg()
18517 && MI->getOperand(1).getReg() == MI->getOperand(2).getReg()
18528 && MI->getOperand(1).getReg() == MI->getOperand(2).getReg()
18528 && MI->getOperand(1).getReg() == MI->getOperand(2).getReg()
18541 && MI->getOperand(1).getReg() == MI->getOperand(2).getReg()
18541 && MI->getOperand(1).getReg() == MI->getOperand(2).getReg()
18552 && MI->getOperand(1).getReg() == MI->getOperand(2).getReg()
18552 && MI->getOperand(1).getReg() == MI->getOperand(2).getReg()
18573 MI->getOperand(0).isReg()
18575 MI->getOperand(0).getReg() == AArch64::Q0
18576 || MI->getOperand(0).getReg() == AArch64::Q1
18577 || MI->getOperand(0).getReg() == AArch64::Q2
18578 || MI->getOperand(0).getReg() == AArch64::Q3
18579 || MI->getOperand(0).getReg() == AArch64::Q4
18580 || MI->getOperand(0).getReg() == AArch64::Q5
18581 || MI->getOperand(0).getReg() == AArch64::Q6
18582 || MI->getOperand(0).getReg() == AArch64::Q7
18583 || MI->getOperand(0).getReg() == AArch64::Q8
18584 || MI->getOperand(0).getReg() == AArch64::Q9
18585 || MI->getOperand(0).getReg() == AArch64::Q10
18586 || MI->getOperand(0).getReg() == AArch64::Q11
18587 || MI->getOperand(0).getReg() == AArch64::Q12
18588 || MI->getOperand(0).getReg() == AArch64::Q13
18589 || MI->getOperand(0).getReg() == AArch64::Q14
18590 || MI->getOperand(0).getReg() == AArch64::Q15
18591 || MI->getOperand(0).getReg() == AArch64::Q16
18592 || MI->getOperand(0).getReg() == AArch64::Q17
18593 || MI->getOperand(0).getReg() == AArch64::Q18
18594 || MI->getOperand(0).getReg() == AArch64::Q19
18595 || MI->getOperand(0).getReg() == AArch64::Q20
18596 || MI->getOperand(0).getReg() == AArch64::Q21
18597 || MI->getOperand(0).getReg() == AArch64::Q22
18598 || MI->getOperand(0).getReg() == AArch64::Q23
18599 || MI->getOperand(0).getReg() == AArch64::Q24
18600 || MI->getOperand(0).getReg() == AArch64::Q25
18601 || MI->getOperand(0).getReg() == AArch64::Q26
18602 || MI->getOperand(0).getReg() == AArch64::Q27
18603 || MI->getOperand(0).getReg() == AArch64::Q28
18604 || MI->getOperand(0).getReg() == AArch64::Q29
18605 || MI->getOperand(0).getReg() == AArch64::Q30
18606 || MI->getOperand(0).getReg() == AArch64::Q31
20241 if (MI->getOperand(1).isImm() &&
20242 MI->getOperand(1).getImm() == 0)
20274 MI->getOperand(0).isReg()
20276 MI->getOperand(0).getReg() == AArch64::D0
20277 || MI->getOperand(0).getReg() == AArch64::D1
20278 || MI->getOperand(0).getReg() == AArch64::D2
20279 || MI->getOperand(0).getReg() == AArch64::D3
20280 || MI->getOperand(0).getReg() == AArch64::D4
20281 || MI->getOperand(0).getReg() == AArch64::D5
20282 || MI->getOperand(0).getReg() == AArch64::D6
20283 || MI->getOperand(0).getReg() == AArch64::D7
20284 || MI->getOperand(0).getReg() == AArch64::D8
20285 || MI->getOperand(0).getReg() == AArch64::D9
20286 || MI->getOperand(0).getReg() == AArch64::D10
20287 || MI->getOperand(0).getReg() == AArch64::D11
20288 || MI->getOperand(0).getReg() == AArch64::D12
20289 || MI->getOperand(0).getReg() == AArch64::D13
20290 || MI->getOperand(0).getReg() == AArch64::D14
20291 || MI->getOperand(0).getReg() == AArch64::D15
20292 || MI->getOperand(0).getReg() == AArch64::D16
20293 || MI->getOperand(0).getReg() == AArch64::D17
20294 || MI->getOperand(0).getReg() == AArch64::D18
20295 || MI->getOperand(0).getReg() == AArch64::D19
20296 || MI->getOperand(0).getReg() == AArch64::D20
20297 || MI->getOperand(0).getReg() == AArch64::D21
20298 || MI->getOperand(0).getReg() == AArch64::D22
20299 || MI->getOperand(0).getReg() == AArch64::D23
20300 || MI->getOperand(0).getReg() == AArch64::D24
20301 || MI->getOperand(0).getReg() == AArch64::D25
20302 || MI->getOperand(0).getReg() == AArch64::D26
20303 || MI->getOperand(0).getReg() == AArch64::D27
20304 || MI->getOperand(0).getReg() == AArch64::D28
20305 || MI->getOperand(0).getReg() == AArch64::D29
20306 || MI->getOperand(0).getReg() == AArch64::D30
20307 || MI->getOperand(0).getReg() == AArch64::D31
20311 MI->getOperand(0).isReg()
20313 MI->getOperand(0).getReg() == AArch64::Q0
20314 || MI->getOperand(0).getReg() == AArch64::Q1
20315 || MI->getOperand(0).getReg() == AArch64::Q2
20316 || MI->getOperand(0).getReg() == AArch64::Q3
20317 || MI->getOperand(0).getReg() == AArch64::Q4
20318 || MI->getOperand(0).getReg() == AArch64::Q5
20319 || MI->getOperand(0).getReg() == AArch64::Q6
20320 || MI->getOperand(0).getReg() == AArch64::Q7
20321 || MI->getOperand(0).getReg() == AArch64::Q8
20322 || MI->getOperand(0).getReg() == AArch64::Q9
20323 || MI->getOperand(0).getReg() == AArch64::Q10
20324 || MI->getOperand(0).getReg() == AArch64::Q11
20325 || MI->getOperand(0).getReg() == AArch64::Q12
20326 || MI->getOperand(0).getReg() == AArch64::Q13
20327 || MI->getOperand(0).getReg() == AArch64::Q14
20328 || MI->getOperand(0).getReg() == AArch64::Q15
20329 || MI->getOperand(0).getReg() == AArch64::Q16
20330 || MI->getOperand(0).getReg() == AArch64::Q17
20331 || MI->getOperand(0).getReg() == AArch64::Q18
20332 || MI->getOperand(0).getReg() == AArch64::Q19
20333 || MI->getOperand(0).getReg() == AArch64::Q20
20334 || MI->getOperand(0).getReg() == AArch64::Q21
20335 || MI->getOperand(0).getReg() == AArch64::Q22
20336 || MI->getOperand(0).getReg() == AArch64::Q23
20337 || MI->getOperand(0).getReg() == AArch64::Q24
20338 || MI->getOperand(0).getReg() == AArch64::Q25
20339 || MI->getOperand(0).getReg() == AArch64::Q26
20340 || MI->getOperand(0).getReg() == AArch64::Q27
20341 || MI->getOperand(0).getReg() == AArch64::Q28
20342 || MI->getOperand(0).getReg() == AArch64::Q29
20343 || MI->getOperand(0).getReg() == AArch64::Q30
20344 || MI->getOperand(0).getReg() == AArch64::Q31
20355 MI->getOperand(0).isReg()
20357 MI->getOperand(0).getReg() == AArch64::Q0
20358 || MI->getOperand(0).getReg() == AArch64::Q1
20359 || MI->getOperand(0).getReg() == AArch64::Q2
20360 || MI->getOperand(0).getReg() == AArch64::Q3
20361 || MI->getOperand(0).getReg() == AArch64::Q4
20362 || MI->getOperand(0).getReg() == AArch64::Q5
20363 || MI->getOperand(0).getReg() == AArch64::Q6
20364 || MI->getOperand(0).getReg() == AArch64::Q7
20365 || MI->getOperand(0).getReg() == AArch64::Q8
20366 || MI->getOperand(0).getReg() == AArch64::Q9
20367 || MI->getOperand(0).getReg() == AArch64::Q10
20368 || MI->getOperand(0).getReg() == AArch64::Q11
20369 || MI->getOperand(0).getReg() == AArch64::Q12
20370 || MI->getOperand(0).getReg() == AArch64::Q13
20371 || MI->getOperand(0).getReg() == AArch64::Q14
20372 || MI->getOperand(0).getReg() == AArch64::Q15
20373 || MI->getOperand(0).getReg() == AArch64::Q16
20374 || MI->getOperand(0).getReg() == AArch64::Q17
20375 || MI->getOperand(0).getReg() == AArch64::Q18
20376 || MI->getOperand(0).getReg() == AArch64::Q19
20377 || MI->getOperand(0).getReg() == AArch64::Q20
20378 || MI->getOperand(0).getReg() == AArch64::Q21
20379 || MI->getOperand(0).getReg() == AArch64::Q22
20380 || MI->getOperand(0).getReg() == AArch64::Q23
20381 || MI->getOperand(0).getReg() == AArch64::Q24
20382 || MI->getOperand(0).getReg() == AArch64::Q25
20383 || MI->getOperand(0).getReg() == AArch64::Q26
20384 || MI->getOperand(0).getReg() == AArch64::Q27
20385 || MI->getOperand(0).getReg() == AArch64::Q28
20386 || MI->getOperand(0).getReg() == AArch64::Q29
20387 || MI->getOperand(0).getReg() == AArch64::Q30
20388 || MI->getOperand(0).getReg() == AArch64::Q31
20606 if (MI->getOperand(1).getReg() == AArch64::WZR ||
20608 MI->getOperand(1).getReg() == AArch64::XZR)
20855 MI->getOperand(0).isReg()
20857 MI->getOperand(0).getReg() == AArch64::D0
20858 || MI->getOperand(0).getReg() == AArch64::D1
20859 || MI->getOperand(0).getReg() == AArch64::D2
20860 || MI->getOperand(0).getReg() == AArch64::D3
20861 || MI->getOperand(0).getReg() == AArch64::D4
20862 || MI->getOperand(0).getReg() == AArch64::D5
20863 || MI->getOperand(0).getReg() == AArch64::D6
20864 || MI->getOperand(0).getReg() == AArch64::D7
20865 || MI->getOperand(0).getReg() == AArch64::D8
20866 || MI->getOperand(0).getReg() == AArch64::D9
20867 || MI->getOperand(0).getReg() == AArch64::D10
20868 || MI->getOperand(0).getReg() == AArch64::D11
20869 || MI->getOperand(0).getReg() == AArch64::D12
20870 || MI->getOperand(0).getReg() == AArch64::D13
20871 || MI->getOperand(0).getReg() == AArch64::D14
20872 || MI->getOperand(0).getReg() == AArch64::D15
20873 || MI->getOperand(0).getReg() == AArch64::D16
20874 || MI->getOperand(0).getReg() == AArch64::D17
20875 || MI->getOperand(0).getReg() == AArch64::D18
20876 || MI->getOperand(0).getReg() == AArch64::D19
20877 || MI->getOperand(0).getReg() == AArch64::D20
20878 || MI->getOperand(0).getReg() == AArch64::D21
20879 || MI->getOperand(0).getReg() == AArch64::D22
20880 || MI->getOperand(0).getReg() == AArch64::D23
20881 || MI->getOperand(0).getReg() == AArch64::D24
20882 || MI->getOperand(0).getReg() == AArch64::D25
20883 || MI->getOperand(0).getReg() == AArch64::D26
20884 || MI->getOperand(0).getReg() == AArch64::D27
20885 || MI->getOperand(0).getReg() == AArch64::D28
20886 || MI->getOperand(0).getReg() == AArch64::D29
20887 || MI->getOperand(0).getReg() == AArch64::D30
20888 || MI->getOperand(0).getReg() == AArch64::D31
20892 MI->getOperand(0).isReg()
20894 MI->getOperand(0).getReg() == AArch64::Q0
20895 || MI->getOperand(0).getReg() == AArch64::Q1
20896 || MI->getOperand(0).getReg() == AArch64::Q2
20897 || MI->getOperand(0).getReg() == AArch64::Q3
20898 || MI->getOperand(0).getReg() == AArch64::Q4
20899 || MI->getOperand(0).getReg() == AArch64::Q5
20900 || MI->getOperand(0).getReg() == AArch64::Q6
20901 || MI->getOperand(0).getReg() == AArch64::Q7
20902 || MI->getOperand(0).getReg() == AArch64::Q8
20903 || MI->getOperand(0).getReg() == AArch64::Q9
20904 || MI->getOperand(0).getReg() == AArch64::Q10
20905 || MI->getOperand(0).getReg() == AArch64::Q11
20906 || MI->getOperand(0).getReg() == AArch64::Q12
20907 || MI->getOperand(0).getReg() == AArch64::Q13
20908 || MI->getOperand(0).getReg() == AArch64::Q14
20909 || MI->getOperand(0).getReg() == AArch64::Q15
20910 || MI->getOperand(0).getReg() == AArch64::Q16
20911 || MI->getOperand(0).getReg() == AArch64::Q17
20912 || MI->getOperand(0).getReg() == AArch64::Q18
20913 || MI->getOperand(0).getReg() == AArch64::Q19
20914 || MI->getOperand(0).getReg() == AArch64::Q20
20915 || MI->getOperand(0).getReg() == AArch64::Q21
20916 || MI->getOperand(0).getReg() == AArch64::Q22
20917 || MI->getOperand(0).getReg() == AArch64::Q23
20918 || MI->getOperand(0).getReg() == AArch64::Q24
20919 || MI->getOperand(0).getReg() == AArch64::Q25
20920 || MI->getOperand(0).getReg() == AArch64::Q26
20921 || MI->getOperand(0).getReg() == AArch64::Q27
20922 || MI->getOperand(0).getReg() == AArch64::Q28
20923 || MI->getOperand(0).getReg() == AArch64::Q29
20924 || MI->getOperand(0).getReg() == AArch64::Q30
20925 || MI->getOperand(0).getReg() == AArch64::Q31
20933 if (MI->getOperand(1).getReg() == AArch64::WZR ||
20935 MI->getOperand(1).getReg() == AArch64::XZR)
21387 if (MI->getOperand(1).getReg() == AArch64::WZR ||
21389 MI->getOperand(1).getReg() == AArch64::XZR)
21398 MI->getOperand(0).isReg()
21400 MI->getOperand(0).getReg() == AArch64::D0
21401 || MI->getOperand(0).getReg() == AArch64::D1
21402 || MI->getOperand(0).getReg() == AArch64::D2
21403 || MI->getOperand(0).getReg() == AArch64::D3
21404 || MI->getOperand(0).getReg() == AArch64::D4
21405 || MI->getOperand(0).getReg() == AArch64::D5
21406 || MI->getOperand(0).getReg() == AArch64::D6
21407 || MI->getOperand(0).getReg() == AArch64::D7
21408 || MI->getOperand(0).getReg() == AArch64::D8
21409 || MI->getOperand(0).getReg() == AArch64::D9
21410 || MI->getOperand(0).getReg() == AArch64::D10
21411 || MI->getOperand(0).getReg() == AArch64::D11
21412 || MI->getOperand(0).getReg() == AArch64::D12
21413 || MI->getOperand(0).getReg() == AArch64::D13
21414 || MI->getOperand(0).getReg() == AArch64::D14
21415 || MI->getOperand(0).getReg() == AArch64::D15
21416 || MI->getOperand(0).getReg() == AArch64::D16
21417 || MI->getOperand(0).getReg() == AArch64::D17
21418 || MI->getOperand(0).getReg() == AArch64::D18
21419 || MI->getOperand(0).getReg() == AArch64::D19
21420 || MI->getOperand(0).getReg() == AArch64::D20
21421 || MI->getOperand(0).getReg() == AArch64::D21
21422 || MI->getOperand(0).getReg() == AArch64::D22
21423 || MI->getOperand(0).getReg() == AArch64::D23
21424 || MI->getOperand(0).getReg() == AArch64::D24
21425 || MI->getOperand(0).getReg() == AArch64::D25
21426 || MI->getOperand(0).getReg() == AArch64::D26
21427 || MI->getOperand(0).getReg() == AArch64::D27
21428 || MI->getOperand(0).getReg() == AArch64::D28
21429 || MI->getOperand(0).getReg() == AArch64::D29
21430 || MI->getOperand(0).getReg() == AArch64::D30
21431 || MI->getOperand(0).getReg() == AArch64::D31
21435 MI->getOperand(0).isReg()
21437 MI->getOperand(0).getReg() == AArch64::Q0
21438 || MI->getOperand(0).getReg() == AArch64::Q1
21439 || MI->getOperand(0).getReg() == AArch64::Q2
21440 || MI->getOperand(0).getReg() == AArch64::Q3
21441 || MI->getOperand(0).getReg() == AArch64::Q4
21442 || MI->getOperand(0).getReg() == AArch64::Q5
21443 || MI->getOperand(0).getReg() == AArch64::Q6
21444 || MI->getOperand(0).getReg() == AArch64::Q7
21445 || MI->getOperand(0).getReg() == AArch64::Q8
21446 || MI->getOperand(0).getReg() == AArch64::Q9
21447 || MI->getOperand(0).getReg() == AArch64::Q10
21448 || MI->getOperand(0).getReg() == AArch64::Q11
21449 || MI->getOperand(0).getReg() == AArch64::Q12
21450 || MI->getOperand(0).getReg() == AArch64::Q13
21451 || MI->getOperand(0).getReg() == AArch64::Q14
21452 || MI->getOperand(0).getReg() == AArch64::Q15
21453 || MI->getOperand(0).getReg() == AArch64::Q16
21454 || MI->getOperand(0).getReg() == AArch64::Q17
21455 || MI->getOperand(0).getReg() == AArch64::Q18
21456 || MI->getOperand(0).getReg() == AArch64::Q19
21457 || MI->getOperand(0).getReg() == AArch64::Q20
21458 || MI->getOperand(0).getReg() == AArch64::Q21
21459 || MI->getOperand(0).getReg() == AArch64::Q22
21460 || MI->getOperand(0).getReg() == AArch64::Q23
21461 || MI->getOperand(0).getReg() == AArch64::Q24
21462 || MI->getOperand(0).getReg() == AArch64::Q25
21463 || MI->getOperand(0).getReg() == AArch64::Q26
21464 || MI->getOperand(0).getReg() == AArch64::Q27
21465 || MI->getOperand(0).getReg() == AArch64::Q28
21466 || MI->getOperand(0).getReg() == AArch64::Q29
21467 || MI->getOperand(0).getReg() == AArch64::Q30
21468 || MI->getOperand(0).getReg() == AArch64::Q31
21480 MI->getOperand(0).isReg()
21482 MI->getOperand(0).getReg() == AArch64::D0
21483 || MI->getOperand(0).getReg() == AArch64::D1
21484 || MI->getOperand(0).getReg() == AArch64::D2
21485 || MI->getOperand(0).getReg() == AArch64::D3
21486 || MI->getOperand(0).getReg() == AArch64::D4
21487 || MI->getOperand(0).getReg() == AArch64::D5
21488 || MI->getOperand(0).getReg() == AArch64::D6
21489 || MI->getOperand(0).getReg() == AArch64::D7
21490 || MI->getOperand(0).getReg() == AArch64::D8
21491 || MI->getOperand(0).getReg() == AArch64::D9
21492 || MI->getOperand(0).getReg() == AArch64::D10
21493 || MI->getOperand(0).getReg() == AArch64::D11
21494 || MI->getOperand(0).getReg() == AArch64::D12
21495 || MI->getOperand(0).getReg() == AArch64::D13
21496 || MI->getOperand(0).getReg() == AArch64::D14
21497 || MI->getOperand(0).getReg() == AArch64::D15
21498 || MI->getOperand(0).getReg() == AArch64::D16
21499 || MI->getOperand(0).getReg() == AArch64::D17
21500 || MI->getOperand(0).getReg() == AArch64::D18
21501 || MI->getOperand(0).getReg() == AArch64::D19
21502 || MI->getOperand(0).getReg() == AArch64::D20
21503 || MI->getOperand(0).getReg() == AArch64::D21
21504 || MI->getOperand(0).getReg() == AArch64::D22
21505 || MI->getOperand(0).getReg() == AArch64::D23
21506 || MI->getOperand(0).getReg() == AArch64::D24
21507 || MI->getOperand(0).getReg() == AArch64::D25
21508 || MI->getOperand(0).getReg() == AArch64::D26
21509 || MI->getOperand(0).getReg() == AArch64::D27
21510 || MI->getOperand(0).getReg() == AArch64::D28
21511 || MI->getOperand(0).getReg() == AArch64::D29
21512 || MI->getOperand(0).getReg() == AArch64::D30
21513 || MI->getOperand(0).getReg() == AArch64::D31
21517 MI->getOperand(0).isReg()
21519 MI->getOperand(0).getReg() == AArch64::Q0
21520 || MI->getOperand(0).getReg() == AArch64::Q1
21521 || MI->getOperand(0).getReg() == AArch64::Q2
21522 || MI->getOperand(0).getReg() == AArch64::Q3
21523 || MI->getOperand(0).getReg() == AArch64::Q4
21524 || MI->getOperand(0).getReg() == AArch64::Q5
21525 || MI->getOperand(0).getReg() == AArch64::Q6
21526 || MI->getOperand(0).getReg() == AArch64::Q7
21527 || MI->getOperand(0).getReg() == AArch64::Q8
21528 || MI->getOperand(0).getReg() == AArch64::Q9
21529 || MI->getOperand(0).getReg() == AArch64::Q10
21530 || MI->getOperand(0).getReg() == AArch64::Q11
21531 || MI->getOperand(0).getReg() == AArch64::Q12
21532 || MI->getOperand(0).getReg() == AArch64::Q13
21533 || MI->getOperand(0).getReg() == AArch64::Q14
21534 || MI->getOperand(0).getReg() == AArch64::Q15
21535 || MI->getOperand(0).getReg() == AArch64::Q16
21536 || MI->getOperand(0).getReg() == AArch64::Q17
21537 || MI->getOperand(0).getReg() == AArch64::Q18
21538 || MI->getOperand(0).getReg() == AArch64::Q19
21539 || MI->getOperand(0).getReg() == AArch64::Q20
21540 || MI->getOperand(0).getReg() == AArch64::Q21
21541 || MI->getOperand(0).getReg() == AArch64::Q22
21542 || MI->getOperand(0).getReg() == AArch64::Q23
21543 || MI->getOperand(0).getReg() == AArch64::Q24
21544 || MI->getOperand(0).getReg() == AArch64::Q25
21545 || MI->getOperand(0).getReg() == AArch64::Q26
21546 || MI->getOperand(0).getReg() == AArch64::Q27
21547 || MI->getOperand(0).getReg() == AArch64::Q28
21548 || MI->getOperand(0).getReg() == AArch64::Q29
21549 || MI->getOperand(0).getReg() == AArch64::Q30
21550 || MI->getOperand(0).getReg() == AArch64::Q31
21558 if (MI->getOperand(1).getReg() == AArch64::WZR ||
21560 MI->getOperand(1).getReg() == AArch64::XZR)
22064 MI->getOperand(0).isReg()
22066 MI->getOperand(0).getReg() == AArch64::D0
22067 || MI->getOperand(0).getReg() == AArch64::D1
22068 || MI->getOperand(0).getReg() == AArch64::D2
22069 || MI->getOperand(0).getReg() == AArch64::D3
22070 || MI->getOperand(0).getReg() == AArch64::D4
22071 || MI->getOperand(0).getReg() == AArch64::D5
22072 || MI->getOperand(0).getReg() == AArch64::D6
22073 || MI->getOperand(0).getReg() == AArch64::D7
22074 || MI->getOperand(0).getReg() == AArch64::D8
22075 || MI->getOperand(0).getReg() == AArch64::D9
22076 || MI->getOperand(0).getReg() == AArch64::D10
22077 || MI->getOperand(0).getReg() == AArch64::D11
22078 || MI->getOperand(0).getReg() == AArch64::D12
22079 || MI->getOperand(0).getReg() == AArch64::D13
22080 || MI->getOperand(0).getReg() == AArch64::D14
22081 || MI->getOperand(0).getReg() == AArch64::D15
22082 || MI->getOperand(0).getReg() == AArch64::D16
22083 || MI->getOperand(0).getReg() == AArch64::D17
22084 || MI->getOperand(0).getReg() == AArch64::D18
22085 || MI->getOperand(0).getReg() == AArch64::D19
22086 || MI->getOperand(0).getReg() == AArch64::D20
22087 || MI->getOperand(0).getReg() == AArch64::D21
22088 || MI->getOperand(0).getReg() == AArch64::D22
22089 || MI->getOperand(0).getReg() == AArch64::D23
22090 || MI->getOperand(0).getReg() == AArch64::D24
22091 || MI->getOperand(0).getReg() == AArch64::D25
22092 || MI->getOperand(0).getReg() == AArch64::D26
22093 || MI->getOperand(0).getReg() == AArch64::D27
22094 || MI->getOperand(0).getReg() == AArch64::D28
22095 || MI->getOperand(0).getReg() == AArch64::D29
22096 || MI->getOperand(0).getReg() == AArch64::D30
22097 || MI->getOperand(0).getReg() == AArch64::D31
22101 MI->getOperand(0).isReg()
22103 MI->getOperand(0).getReg() == AArch64::Q0
22104 || MI->getOperand(0).getReg() == AArch64::Q1
22105 || MI->getOperand(0).getReg() == AArch64::Q2
22106 || MI->getOperand(0).getReg() == AArch64::Q3
22107 || MI->getOperand(0).getReg() == AArch64::Q4
22108 || MI->getOperand(0).getReg() == AArch64::Q5
22109 || MI->getOperand(0).getReg() == AArch64::Q6
22110 || MI->getOperand(0).getReg() == AArch64::Q7
22111 || MI->getOperand(0).getReg() == AArch64::Q8
22112 || MI->getOperand(0).getReg() == AArch64::Q9
22113 || MI->getOperand(0).getReg() == AArch64::Q10
22114 || MI->getOperand(0).getReg() == AArch64::Q11
22115 || MI->getOperand(0).getReg() == AArch64::Q12
22116 || MI->getOperand(0).getReg() == AArch64::Q13
22117 || MI->getOperand(0).getReg() == AArch64::Q14
22118 || MI->getOperand(0).getReg() == AArch64::Q15
22119 || MI->getOperand(0).getReg() == AArch64::Q16
22120 || MI->getOperand(0).getReg() == AArch64::Q17
22121 || MI->getOperand(0).getReg() == AArch64::Q18
22122 || MI->getOperand(0).getReg() == AArch64::Q19
22123 || MI->getOperand(0).getReg() == AArch64::Q20
22124 || MI->getOperand(0).getReg() == AArch64::Q21
22125 || MI->getOperand(0).getReg() == AArch64::Q22
22126 || MI->getOperand(0).getReg() == AArch64::Q23
22127 || MI->getOperand(0).getReg() == AArch64::Q24
22128 || MI->getOperand(0).getReg() == AArch64::Q25
22129 || MI->getOperand(0).getReg() == AArch64::Q26
22130 || MI->getOperand(0).getReg() == AArch64::Q27
22131 || MI->getOperand(0).getReg() == AArch64::Q28
22132 || MI->getOperand(0).getReg() == AArch64::Q29
22133 || MI->getOperand(0).getReg() == AArch64::Q30
22134 || MI->getOperand(0).getReg() == AArch64::Q31
22146 MI->getOperand(0).isReg()
22148 MI->getOperand(0).getReg() == AArch64::D0
22149 || MI->getOperand(0).getReg() == AArch64::D1
22150 || MI->getOperand(0).getReg() == AArch64::D2
22151 || MI->getOperand(0).getReg() == AArch64::D3
22152 || MI->getOperand(0).getReg() == AArch64::D4
22153 || MI->getOperand(0).getReg() == AArch64::D5
22154 || MI->getOperand(0).getReg() == AArch64::D6
22155 || MI->getOperand(0).getReg() == AArch64::D7
22156 || MI->getOperand(0).getReg() == AArch64::D8
22157 || MI->getOperand(0).getReg() == AArch64::D9
22158 || MI->getOperand(0).getReg() == AArch64::D10
22159 || MI->getOperand(0).getReg() == AArch64::D11
22160 || MI->getOperand(0).getReg() == AArch64::D12
22161 || MI->getOperand(0).getReg() == AArch64::D13
22162 || MI->getOperand(0).getReg() == AArch64::D14
22163 || MI->getOperand(0).getReg() == AArch64::D15
22164 || MI->getOperand(0).getReg() == AArch64::D16
22165 || MI->getOperand(0).getReg() == AArch64::D17
22166 || MI->getOperand(0).getReg() == AArch64::D18
22167 || MI->getOperand(0).getReg() == AArch64::D19
22168 || MI->getOperand(0).getReg() == AArch64::D20
22169 || MI->getOperand(0).getReg() == AArch64::D21
22170 || MI->getOperand(0).getReg() == AArch64::D22
22171 || MI->getOperand(0).getReg() == AArch64::D23
22172 || MI->getOperand(0).getReg() == AArch64::D24
22173 || MI->getOperand(0).getReg() == AArch64::D25
22174 || MI->getOperand(0).getReg() == AArch64::D26
22175 || MI->getOperand(0).getReg() == AArch64::D27
22176 || MI->getOperand(0).getReg() == AArch64::D28
22177 || MI->getOperand(0).getReg() == AArch64::D29
22178 || MI->getOperand(0).getReg() == AArch64::D30
22179 || MI->getOperand(0).getReg() == AArch64::D31
22183 MI->getOperand(0).isReg()
22185 MI->getOperand(0).getReg() == AArch64::Q0
22186 || MI->getOperand(0).getReg() == AArch64::Q1
22187 || MI->getOperand(0).getReg() == AArch64::Q2
22188 || MI->getOperand(0).getReg() == AArch64::Q3
22189 || MI->getOperand(0).getReg() == AArch64::Q4
22190 || MI->getOperand(0).getReg() == AArch64::Q5
22191 || MI->getOperand(0).getReg() == AArch64::Q6
22192 || MI->getOperand(0).getReg() == AArch64::Q7
22193 || MI->getOperand(0).getReg() == AArch64::Q8
22194 || MI->getOperand(0).getReg() == AArch64::Q9
22195 || MI->getOperand(0).getReg() == AArch64::Q10
22196 || MI->getOperand(0).getReg() == AArch64::Q11
22197 || MI->getOperand(0).getReg() == AArch64::Q12
22198 || MI->getOperand(0).getReg() == AArch64::Q13
22199 || MI->getOperand(0).getReg() == AArch64::Q14
22200 || MI->getOperand(0).getReg() == AArch64::Q15
22201 || MI->getOperand(0).getReg() == AArch64::Q16
22202 || MI->getOperand(0).getReg() == AArch64::Q17
22203 || MI->getOperand(0).getReg() == AArch64::Q18
22204 || MI->getOperand(0).getReg() == AArch64::Q19
22205 || MI->getOperand(0).getReg() == AArch64::Q20
22206 || MI->getOperand(0).getReg() == AArch64::Q21
22207 || MI->getOperand(0).getReg() == AArch64::Q22
22208 || MI->getOperand(0).getReg() == AArch64::Q23
22209 || MI->getOperand(0).getReg() == AArch64::Q24
22210 || MI->getOperand(0).getReg() == AArch64::Q25
22211 || MI->getOperand(0).getReg() == AArch64::Q26
22212 || MI->getOperand(0).getReg() == AArch64::Q27
22213 || MI->getOperand(0).getReg() == AArch64::Q28
22214 || MI->getOperand(0).getReg() == AArch64::Q29
22215 || MI->getOperand(0).getReg() == AArch64::Q30
22216 || MI->getOperand(0).getReg() == AArch64::Q31
22228 MI->getOperand(0).isReg()
22230 MI->getOperand(0).getReg() == AArch64::D0
22231 || MI->getOperand(0).getReg() == AArch64::D1
22232 || MI->getOperand(0).getReg() == AArch64::D2
22233 || MI->getOperand(0).getReg() == AArch64::D3
22234 || MI->getOperand(0).getReg() == AArch64::D4
22235 || MI->getOperand(0).getReg() == AArch64::D5
22236 || MI->getOperand(0).getReg() == AArch64::D6
22237 || MI->getOperand(0).getReg() == AArch64::D7
22238 || MI->getOperand(0).getReg() == AArch64::D8
22239 || MI->getOperand(0).getReg() == AArch64::D9
22240 || MI->getOperand(0).getReg() == AArch64::D10
22241 || MI->getOperand(0).getReg() == AArch64::D11
22242 || MI->getOperand(0).getReg() == AArch64::D12
22243 || MI->getOperand(0).getReg() == AArch64::D13
22244 || MI->getOperand(0).getReg() == AArch64::D14
22245 || MI->getOperand(0).getReg() == AArch64::D15
22246 || MI->getOperand(0).getReg() == AArch64::D16
22247 || MI->getOperand(0).getReg() == AArch64::D17
22248 || MI->getOperand(0).getReg() == AArch64::D18
22249 || MI->getOperand(0).getReg() == AArch64::D19
22250 || MI->getOperand(0).getReg() == AArch64::D20
22251 || MI->getOperand(0).getReg() == AArch64::D21
22252 || MI->getOperand(0).getReg() == AArch64::D22
22253 || MI->getOperand(0).getReg() == AArch64::D23
22254 || MI->getOperand(0).getReg() == AArch64::D24
22255 || MI->getOperand(0).getReg() == AArch64::D25
22256 || MI->getOperand(0).getReg() == AArch64::D26
22257 || MI->getOperand(0).getReg() == AArch64::D27
22258 || MI->getOperand(0).getReg() == AArch64::D28
22259 || MI->getOperand(0).getReg() == AArch64::D29
22260 || MI->getOperand(0).getReg() == AArch64::D30
22261 || MI->getOperand(0).getReg() == AArch64::D31
22265 MI->getOperand(0).isReg()
22267 MI->getOperand(0).getReg() == AArch64::Q0
22268 || MI->getOperand(0).getReg() == AArch64::Q1
22269 || MI->getOperand(0).getReg() == AArch64::Q2
22270 || MI->getOperand(0).getReg() == AArch64::Q3
22271 || MI->getOperand(0).getReg() == AArch64::Q4
22272 || MI->getOperand(0).getReg() == AArch64::Q5
22273 || MI->getOperand(0).getReg() == AArch64::Q6
22274 || MI->getOperand(0).getReg() == AArch64::Q7
22275 || MI->getOperand(0).getReg() == AArch64::Q8
22276 || MI->getOperand(0).getReg() == AArch64::Q9
22277 || MI->getOperand(0).getReg() == AArch64::Q10
22278 || MI->getOperand(0).getReg() == AArch64::Q11
22279 || MI->getOperand(0).getReg() == AArch64::Q12
22280 || MI->getOperand(0).getReg() == AArch64::Q13
22281 || MI->getOperand(0).getReg() == AArch64::Q14
22282 || MI->getOperand(0).getReg() == AArch64::Q15
22283 || MI->getOperand(0).getReg() == AArch64::Q16
22284 || MI->getOperand(0).getReg() == AArch64::Q17
22285 || MI->getOperand(0).getReg() == AArch64::Q18
22286 || MI->getOperand(0).getReg() == AArch64::Q19
22287 || MI->getOperand(0).getReg() == AArch64::Q20
22288 || MI->getOperand(0).getReg() == AArch64::Q21
22289 || MI->getOperand(0).getReg() == AArch64::Q22
22290 || MI->getOperand(0).getReg() == AArch64::Q23
22291 || MI->getOperand(0).getReg() == AArch64::Q24
22292 || MI->getOperand(0).getReg() == AArch64::Q25
22293 || MI->getOperand(0).getReg() == AArch64::Q26
22294 || MI->getOperand(0).getReg() == AArch64::Q27
22295 || MI->getOperand(0).getReg() == AArch64::Q28
22296 || MI->getOperand(0).getReg() == AArch64::Q29
22297 || MI->getOperand(0).getReg() == AArch64::Q30
22298 || MI->getOperand(0).getReg() == AArch64::Q31
gen/lib/Target/AMDGPU/AMDGPUGenMCPseudoLowering.inc 19 lowerOperand(MI->getOperand(0), MCOp);
22 lowerOperand(MI->getOperand(1), MCOp);
gen/lib/Target/ARM/ARMGenGlobalISel.inc 756 const auto &MO = MI.getOperand(1);
766 const auto &MO = MI.getOperand(1);
776 const auto &MO = MI.getOperand(1);
gen/lib/Target/ARM/ARMGenMCPseudoLowering.inc 19 lowerOperand(MI->getOperand(0), MCOp);
32 lowerOperand(MI->getOperand(0), MCOp);
35 lowerOperand(MI->getOperand(1), MCOp);
38 lowerOperand(MI->getOperand(2), MCOp);
40 lowerOperand(MI->getOperand(3), MCOp);
43 lowerOperand(MI->getOperand(4), MCOp);
47 if (lowerOperand(MI->getOperand(i), MCOp))
57 lowerOperand(MI->getOperand(0), MCOp);
60 lowerOperand(MI->getOperand(1), MCOp);
63 lowerOperand(MI->getOperand(2), MCOp);
66 lowerOperand(MI->getOperand(3), MCOp);
69 lowerOperand(MI->getOperand(4), MCOp);
71 lowerOperand(MI->getOperand(5), MCOp);
74 lowerOperand(MI->getOperand(6), MCOp);
86 lowerOperand(MI->getOperand(0), MCOp);
101 lowerOperand(MI->getOperand(0), MCOp);
104 lowerOperand(MI->getOperand(1), MCOp);
107 lowerOperand(MI->getOperand(2), MCOp);
110 lowerOperand(MI->getOperand(3), MCOp);
112 lowerOperand(MI->getOperand(4), MCOp);
115 lowerOperand(MI->getOperand(5), MCOp);
125 lowerOperand(MI->getOperand(0), MCOp);
128 lowerOperand(MI->getOperand(1), MCOp);
131 lowerOperand(MI->getOperand(2), MCOp);
134 lowerOperand(MI->getOperand(3), MCOp);
137 lowerOperand(MI->getOperand(4), MCOp);
140 lowerOperand(MI->getOperand(5), MCOp);
143 lowerOperand(MI->getOperand(6), MCOp);
145 lowerOperand(MI->getOperand(7), MCOp);
148 lowerOperand(MI->getOperand(8), MCOp);
158 lowerOperand(MI->getOperand(0), MCOp);
161 lowerOperand(MI->getOperand(1), MCOp);
164 lowerOperand(MI->getOperand(2), MCOp);
167 lowerOperand(MI->getOperand(3), MCOp);
170 lowerOperand(MI->getOperand(4), MCOp);
172 lowerOperand(MI->getOperand(5), MCOp);
175 lowerOperand(MI->getOperand(6), MCOp);
185 lowerOperand(MI->getOperand(0), MCOp);
198 lowerOperand(MI->getOperand(0), MCOp);
210 lowerOperand(MI->getOperand(0), MCOp);
225 lowerOperand(MI->getOperand(0), MCOp);
228 lowerOperand(MI->getOperand(1), MCOp);
231 lowerOperand(MI->getOperand(2), MCOp);
234 lowerOperand(MI->getOperand(3), MCOp);
237 lowerOperand(MI->getOperand(4), MCOp);
240 lowerOperand(MI->getOperand(5), MCOp);
243 lowerOperand(MI->getOperand(6), MCOp);
245 lowerOperand(MI->getOperand(7), MCOp);
248 lowerOperand(MI->getOperand(8), MCOp);
258 lowerOperand(MI->getOperand(0), MCOp);
261 lowerOperand(MI->getOperand(1), MCOp);
264 lowerOperand(MI->getOperand(2), MCOp);
267 lowerOperand(MI->getOperand(3), MCOp);
270 lowerOperand(MI->getOperand(4), MCOp);
272 lowerOperand(MI->getOperand(5), MCOp);
275 lowerOperand(MI->getOperand(6), MCOp);
285 lowerOperand(MI->getOperand(0), MCOp);
300 lowerOperand(MI->getOperand(0), MCOp);
315 lowerOperand(MI->getOperand(0), MCOp);
318 lowerOperand(MI->getOperand(1), MCOp);
321 lowerOperand(MI->getOperand(2), MCOp);
323 lowerOperand(MI->getOperand(3), MCOp);
326 lowerOperand(MI->getOperand(4), MCOp);
330 if (lowerOperand(MI->getOperand(i), MCOp))
342 lowerOperand(MI->getOperand(0), MCOp);
345 lowerOperand(MI->getOperand(1), MCOp);
347 lowerOperand(MI->getOperand(2), MCOp);
359 lowerOperand(MI->getOperand(0), MCOp);
361 lowerOperand(MI->getOperand(1), MCOp);
371 lowerOperand(MI->getOperand(0), MCOp);
374 lowerOperand(MI->getOperand(1), MCOp);
376 lowerOperand(MI->getOperand(2), MCOp);
386 lowerOperand(MI->getOperand(1), MCOp);
388 lowerOperand(MI->getOperand(2), MCOp);
391 lowerOperand(MI->getOperand(0), MCOp);
401 lowerOperand(MI->getOperand(1), MCOp);
404 lowerOperand(MI->getOperand(2), MCOp);
406 lowerOperand(MI->getOperand(3), MCOp);
409 lowerOperand(MI->getOperand(4), MCOp);
413 if (lowerOperand(MI->getOperand(i), MCOp))
423 lowerOperand(MI->getOperand(0), MCOp);
425 lowerOperand(MI->getOperand(1), MCOp);
428 lowerOperand(MI->getOperand(2), MCOp);
432 if (lowerOperand(MI->getOperand(i), MCOp))
442 lowerOperand(MI->getOperand(0), MCOp);
445 lowerOperand(MI->getOperand(1), MCOp);
447 lowerOperand(MI->getOperand(2), MCOp);
457 lowerOperand(MI->getOperand(0), MCOp);
460 lowerOperand(MI->getOperand(1), MCOp);
462 lowerOperand(MI->getOperand(2), MCOp);
472 lowerOperand(MI->getOperand(0), MCOp);
gen/lib/Target/ARM/ARMGenSubtargetInfo.inc19932 && (Register::isVirtualRegister(MI->getOperand(0).getReg()))
19936 && (Register::isVirtualRegister(MI->getOperand(0).getReg()))
19940 && (Register::isVirtualRegister(MI->getOperand(0).getReg()))
19944 && (Register::isVirtualRegister(MI->getOperand(0).getReg()))
19948 && (Register::isVirtualRegister(MI->getOperand(0).getReg()))
19952 && (Register::isVirtualRegister(MI->getOperand(0).getReg()))
19956 && (Register::isVirtualRegister(MI->getOperand(0).getReg()))
19960 && (Register::isVirtualRegister(MI->getOperand(0).getReg()))
19964 && (Register::isVirtualRegister(MI->getOperand(0).getReg()))
19968 && (Register::isPhysicalRegister(MI->getOperand(0).getReg()))
19972 && (Register::isPhysicalRegister(MI->getOperand(0).getReg()))
19976 && (Register::isPhysicalRegister(MI->getOperand(0).getReg()))
19980 && (Register::isPhysicalRegister(MI->getOperand(0).getReg()))
19984 && (Register::isPhysicalRegister(MI->getOperand(0).getReg()))
19988 && (Register::isPhysicalRegister(MI->getOperand(0).getReg()))
19992 && (Register::isPhysicalRegister(MI->getOperand(0).getReg()))
19996 && (Register::isPhysicalRegister(MI->getOperand(0).getReg()))
20000 && (Register::isPhysicalRegister(MI->getOperand(0).getReg()))
20007 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
20010 if ((Register::isPhysicalRegister(MI->getOperand(0).getReg()))
20013 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
20016 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
20019 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
20022 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
20025 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
20028 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
20031 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
20034 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
20037 if ((Register::isPhysicalRegister(MI->getOperand(0).getReg()))
20040 if ((Register::isPhysicalRegister(MI->getOperand(0).getReg()))
20043 if ((Register::isPhysicalRegister(MI->getOperand(0).getReg()))
20046 if ((Register::isPhysicalRegister(MI->getOperand(0).getReg()))
20049 if ((Register::isPhysicalRegister(MI->getOperand(0).getReg()))
20052 if ((Register::isPhysicalRegister(MI->getOperand(0).getReg()))
20055 if ((Register::isPhysicalRegister(MI->getOperand(0).getReg()))
20058 if ((Register::isPhysicalRegister(MI->getOperand(0).getReg()))
21450 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
21453 if ((Register::isPhysicalRegister(MI->getOperand(0).getReg()))
21456 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
21459 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
21462 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
21465 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
21468 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
21471 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
21474 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
21477 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
21480 if ((Register::isPhysicalRegister(MI->getOperand(0).getReg()))
21483 if ((Register::isPhysicalRegister(MI->getOperand(0).getReg()))
21486 if ((Register::isPhysicalRegister(MI->getOperand(0).getReg()))
21489 if ((Register::isPhysicalRegister(MI->getOperand(0).getReg()))
21492 if ((Register::isPhysicalRegister(MI->getOperand(0).getReg()))
21495 if ((Register::isPhysicalRegister(MI->getOperand(0).getReg()))
21498 if ((Register::isPhysicalRegister(MI->getOperand(0).getReg()))
21501 if ((Register::isPhysicalRegister(MI->getOperand(0).getReg()))
21508 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
21511 if ((Register::isPhysicalRegister(MI->getOperand(0).getReg()))
21514 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
21517 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
21520 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
21523 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
21526 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
21529 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
21532 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
21535 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
21538 if ((Register::isPhysicalRegister(MI->getOperand(0).getReg()))
21541 if ((Register::isPhysicalRegister(MI->getOperand(0).getReg()))
21544 if ((Register::isPhysicalRegister(MI->getOperand(0).getReg()))
21547 if ((Register::isPhysicalRegister(MI->getOperand(0).getReg()))
21550 if ((Register::isPhysicalRegister(MI->getOperand(0).getReg()))
21553 if ((Register::isPhysicalRegister(MI->getOperand(0).getReg()))
21556 if ((Register::isPhysicalRegister(MI->getOperand(0).getReg()))
21559 if ((Register::isPhysicalRegister(MI->getOperand(0).getReg()))
21680 && (Register::isVirtualRegister(MI->getOperand(0).getReg()))
21684 && (Register::isVirtualRegister(MI->getOperand(0).getReg()))
21688 && (Register::isVirtualRegister(MI->getOperand(0).getReg()))
21692 && (Register::isVirtualRegister(MI->getOperand(0).getReg()))
21696 && (Register::isVirtualRegister(MI->getOperand(0).getReg()))
21700 && (Register::isVirtualRegister(MI->getOperand(0).getReg()))
21704 && (Register::isVirtualRegister(MI->getOperand(0).getReg()))
21708 && (Register::isVirtualRegister(MI->getOperand(0).getReg()))
21712 && (Register::isVirtualRegister(MI->getOperand(0).getReg()))
21716 && (Register::isPhysicalRegister(MI->getOperand(0).getReg()))
21720 && (Register::isPhysicalRegister(MI->getOperand(0).getReg()))
21724 && (Register::isPhysicalRegister(MI->getOperand(0).getReg()))
21728 && (Register::isPhysicalRegister(MI->getOperand(0).getReg()))
21732 && (Register::isPhysicalRegister(MI->getOperand(0).getReg()))
21736 && (Register::isPhysicalRegister(MI->getOperand(0).getReg()))
21740 && (Register::isPhysicalRegister(MI->getOperand(0).getReg()))
21744 && (Register::isPhysicalRegister(MI->getOperand(0).getReg()))
21748 && (Register::isPhysicalRegister(MI->getOperand(0).getReg()))
22385 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
22388 if ((Register::isPhysicalRegister(MI->getOperand(0).getReg()))
22391 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
22394 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
22397 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
22400 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
22403 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
22406 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
22409 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
22412 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
22415 if ((Register::isPhysicalRegister(MI->getOperand(0).getReg()))
22418 if ((Register::isPhysicalRegister(MI->getOperand(0).getReg()))
22421 if ((Register::isPhysicalRegister(MI->getOperand(0).getReg()))
22424 if ((Register::isPhysicalRegister(MI->getOperand(0).getReg()))
22427 if ((Register::isPhysicalRegister(MI->getOperand(0).getReg()))
22430 if ((Register::isPhysicalRegister(MI->getOperand(0).getReg()))
22433 if ((Register::isPhysicalRegister(MI->getOperand(0).getReg()))
22436 if ((Register::isPhysicalRegister(MI->getOperand(0).getReg()))
gen/lib/Target/Mips/MipsGenMCPseudoLowering.inc 19 lowerOperand(MI->getOperand(0), MCOp);
22 lowerOperand(MI->getOperand(1), MCOp);
25 lowerOperand(MI->getOperand(2), MCOp);
35 lowerOperand(MI->getOperand(0), MCOp);
38 lowerOperand(MI->getOperand(1), MCOp);
41 lowerOperand(MI->getOperand(2), MCOp);
51 lowerOperand(MI->getOperand(0), MCOp);
54 lowerOperand(MI->getOperand(1), MCOp);
57 lowerOperand(MI->getOperand(2), MCOp);
71 lowerOperand(MI->getOperand(0), MCOp);
83 lowerOperand(MI->getOperand(0), MCOp);
95 lowerOperand(MI->getOperand(0), MCOp);
105 lowerOperand(MI->getOperand(0), MCOp);
108 lowerOperand(MI->getOperand(1), MCOp);
111 lowerOperand(MI->getOperand(2), MCOp);
114 lowerOperand(MI->getOperand(3), MCOp);
124 lowerOperand(MI->getOperand(0), MCOp);
127 lowerOperand(MI->getOperand(1), MCOp);
130 lowerOperand(MI->getOperand(2), MCOp);
133 lowerOperand(MI->getOperand(3), MCOp);
143 lowerOperand(MI->getOperand(0), MCOp);
146 lowerOperand(MI->getOperand(1), MCOp);
149 lowerOperand(MI->getOperand(2), MCOp);
152 lowerOperand(MI->getOperand(3), MCOp);
162 lowerOperand(MI->getOperand(0), MCOp);
165 lowerOperand(MI->getOperand(1), MCOp);
168 lowerOperand(MI->getOperand(2), MCOp);
171 lowerOperand(MI->getOperand(3), MCOp);
181 lowerOperand(MI->getOperand(0), MCOp);
184 lowerOperand(MI->getOperand(1), MCOp);
187 lowerOperand(MI->getOperand(2), MCOp);
190 lowerOperand(MI->getOperand(3), MCOp);
204 lowerOperand(MI->getOperand(0), MCOp);
214 lowerOperand(MI->getOperand(0), MCOp);
217 lowerOperand(MI->getOperand(1), MCOp);
220 lowerOperand(MI->getOperand(1), MCOp);
230 lowerOperand(MI->getOperand(0), MCOp);
233 lowerOperand(MI->getOperand(1), MCOp);
236 lowerOperand(MI->getOperand(1), MCOp);
248 lowerOperand(MI->getOperand(0), MCOp);
260 lowerOperand(MI->getOperand(0), MCOp);
272 lowerOperand(MI->getOperand(0), MCOp);
284 lowerOperand(MI->getOperand(0), MCOp);
294 lowerOperand(MI->getOperand(0), MCOp);
317 lowerOperand(MI->getOperand(0), MCOp);
320 lowerOperand(MI->getOperand(1), MCOp);
323 lowerOperand(MI->getOperand(2), MCOp);
333 lowerOperand(MI->getOperand(0), MCOp);
336 lowerOperand(MI->getOperand(1), MCOp);
339 lowerOperand(MI->getOperand(2), MCOp);
349 lowerOperand(MI->getOperand(0), MCOp);
352 lowerOperand(MI->getOperand(1), MCOp);
355 lowerOperand(MI->getOperand(2), MCOp);
365 lowerOperand(MI->getOperand(0), MCOp);
368 lowerOperand(MI->getOperand(1), MCOp);
371 lowerOperand(MI->getOperand(2), MCOp);
381 lowerOperand(MI->getOperand(0), MCOp);
384 lowerOperand(MI->getOperand(1), MCOp);
387 lowerOperand(MI->getOperand(2), MCOp);
397 lowerOperand(MI->getOperand(0), MCOp);
400 lowerOperand(MI->getOperand(1), MCOp);
403 lowerOperand(MI->getOperand(2), MCOp);
413 lowerOperand(MI->getOperand(1), MCOp);
416 lowerOperand(MI->getOperand(2), MCOp);
426 lowerOperand(MI->getOperand(1), MCOp);
429 lowerOperand(MI->getOperand(2), MCOp);
439 lowerOperand(MI->getOperand(1), MCOp);
442 lowerOperand(MI->getOperand(2), MCOp);
452 lowerOperand(MI->getOperand(1), MCOp);
455 lowerOperand(MI->getOperand(2), MCOp);
465 lowerOperand(MI->getOperand(1), MCOp);
468 lowerOperand(MI->getOperand(2), MCOp);
478 lowerOperand(MI->getOperand(1), MCOp);
481 lowerOperand(MI->getOperand(2), MCOp);
491 lowerOperand(MI->getOperand(1), MCOp);
494 lowerOperand(MI->getOperand(2), MCOp);
504 lowerOperand(MI->getOperand(1), MCOp);
507 lowerOperand(MI->getOperand(2), MCOp);
517 lowerOperand(MI->getOperand(1), MCOp);
520 lowerOperand(MI->getOperand(2), MCOp);
530 lowerOperand(MI->getOperand(1), MCOp);
533 lowerOperand(MI->getOperand(2), MCOp);
543 lowerOperand(MI->getOperand(0), MCOp);
553 lowerOperand(MI->getOperand(0), MCOp);
565 lowerOperand(MI->getOperand(0), MCOp);
577 lowerOperand(MI->getOperand(0), MCOp);
587 lowerOperand(MI->getOperand(0), MCOp);
597 lowerOperand(MI->getOperand(0), MCOp);
607 lowerOperand(MI->getOperand(0), MCOp);
617 lowerOperand(MI->getOperand(0), MCOp);
627 lowerOperand(MI->getOperand(0), MCOp);
637 lowerOperand(MI->getOperand(0), MCOp);
647 lowerOperand(MI->getOperand(1), MCOp);
650 lowerOperand(MI->getOperand(2), MCOp);
660 lowerOperand(MI->getOperand(1), MCOp);
663 lowerOperand(MI->getOperand(2), MCOp);
673 lowerOperand(MI->getOperand(1), MCOp);
676 lowerOperand(MI->getOperand(2), MCOp);
686 lowerOperand(MI->getOperand(1), MCOp);
689 lowerOperand(MI->getOperand(2), MCOp);
699 lowerOperand(MI->getOperand(1), MCOp);
702 lowerOperand(MI->getOperand(2), MCOp);
712 lowerOperand(MI->getOperand(1), MCOp);
715 lowerOperand(MI->getOperand(2), MCOp);
725 lowerOperand(MI->getOperand(1), MCOp);
728 lowerOperand(MI->getOperand(2), MCOp);
738 lowerOperand(MI->getOperand(1), MCOp);
741 lowerOperand(MI->getOperand(2), MCOp);
751 lowerOperand(MI->getOperand(1), MCOp);
754 lowerOperand(MI->getOperand(2), MCOp);
764 lowerOperand(MI->getOperand(1), MCOp);
767 lowerOperand(MI->getOperand(2), MCOp);
777 lowerOperand(MI->getOperand(1), MCOp);
780 lowerOperand(MI->getOperand(2), MCOp);
790 lowerOperand(MI->getOperand(1), MCOp);
793 lowerOperand(MI->getOperand(2), MCOp);
803 lowerOperand(MI->getOperand(0), MCOp);
806 lowerOperand(MI->getOperand(2), MCOp);
809 lowerOperand(MI->getOperand(3), MCOp);
819 lowerOperand(MI->getOperand(0), MCOp);
822 lowerOperand(MI->getOperand(2), MCOp);
825 lowerOperand(MI->getOperand(3), MCOp);
835 lowerOperand(MI->getOperand(1), MCOp);
838 lowerOperand(MI->getOperand(2), MCOp);
848 lowerOperand(MI->getOperand(1), MCOp);
851 lowerOperand(MI->getOperand(2), MCOp);
861 lowerOperand(MI->getOperand(1), MCOp);
864 lowerOperand(MI->getOperand(2), MCOp);
874 lowerOperand(MI->getOperand(0), MCOp);
886 lowerOperand(MI->getOperand(0), MCOp);
896 lowerOperand(MI->getOperand(0), MCOp);
906 lowerOperand(MI->getOperand(0), MCOp);
918 lowerOperand(MI->getOperand(0), MCOp);
928 lowerOperand(MI->getOperand(0), MCOp);
938 lowerOperand(MI->getOperand(0), MCOp);
948 lowerOperand(MI->getOperand(0), MCOp);
958 lowerOperand(MI->getOperand(0), MCOp);
968 lowerOperand(MI->getOperand(0), MCOp);
978 lowerOperand(MI->getOperand(0), MCOp);
988 lowerOperand(MI->getOperand(0), MCOp);
998 lowerOperand(MI->getOperand(0), MCOp);
1030 lowerOperand(MI->getOperand(1), MCOp);
1033 lowerOperand(MI->getOperand(2), MCOp);
1043 lowerOperand(MI->getOperand(0), MCOp);
1046 lowerOperand(MI->getOperand(1), MCOp);
1049 lowerOperand(MI->getOperand(2), MCOp);
1059 lowerOperand(MI->getOperand(0), MCOp);
1062 lowerOperand(MI->getOperand(1), MCOp);
1065 lowerOperand(MI->getOperand(2), MCOp);
1075 lowerOperand(MI->getOperand(0), MCOp);
1078 lowerOperand(MI->getOperand(1), MCOp);
1081 lowerOperand(MI->getOperand(2), MCOp);
gen/lib/Target/RISCV/RISCVGenMCPseudoLowering.inc 21 lowerOperand(MI->getOperand(0), MCOp);
33 lowerOperand(MI->getOperand(0), MCOp);
36 lowerOperand(MI->getOperand(1), MCOp);
48 lowerOperand(MI->getOperand(0), MCOp);
75 lowerOperand(MI->getOperand(0), MCOp);
gen/lib/Target/X86/X86GenInstrInfo.inc49350 MI.getOperand(1).isReg()
49351 && MI.getOperand(1).getReg() != 0
49352 && MI.getOperand(3).isReg()
49353 && MI.getOperand(3).getReg() != 0
49356 MI.getOperand(4).isImm()
49357 && MI.getOperand(4).getImm() != 0
49359 || (MI.getOperand(4).isGlobal())
gen/lib/Target/X86/X86GenSubtargetInfo.inc21530 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
21530 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
21535 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
21535 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
21924 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
21924 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
21929 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
21929 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
21934 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
21934 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
21939 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
21939 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
21944 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
21944 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
21949 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
21949 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
21954 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
21954 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
21961 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
21961 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
21966 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
21966 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
21971 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
21971 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
21976 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
21976 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
21981 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
21981 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
21986 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
21986 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
21991 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
21991 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
21998 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
21998 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22003 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22003 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22008 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22008 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22013 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22013 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22018 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22018 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22023 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22023 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22030 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22030 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22035 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22035 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22040 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22040 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22045 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22045 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22050 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22050 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22055 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22055 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22060 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22060 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22067 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22067 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22072 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22072 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22077 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22077 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22082 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22082 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22087 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22087 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22092 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22092 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22097 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22097 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22104 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22104 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22109 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22109 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22114 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22114 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22119 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22119 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22124 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22124 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22129 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22129 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22134 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22134 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22141 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22141 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22146 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22146 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22151 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22151 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22156 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22156 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22161 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22161 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22166 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22166 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22174 MI->getOperand(3).getImm() == X86::COND_A
22175 || MI->getOperand(3).getImm() == X86::COND_BE
22182 MI->getOperand(3).getImm() == X86::COND_A
22183 || MI->getOperand(3).getImm() == X86::COND_BE
22190 MI->getOperand(3).getImm() == X86::COND_A
22191 || MI->getOperand(3).getImm() == X86::COND_BE
22198 MI->getOperand(3).getImm() == X86::COND_A
22199 || MI->getOperand(3).getImm() == X86::COND_BE
22206 MI->getOperand(3).getImm() == X86::COND_A
22207 || MI->getOperand(3).getImm() == X86::COND_BE
22215 if (MI->getOperand(7).getImm() == X86::COND_BE)
22217 if (MI->getOperand(7).getImm() == X86::COND_A)
22219 if (MI->getOperand(7).getImm() == X86::COND_L)
22221 if (MI->getOperand(7).getImm() == X86::COND_GE)
22223 if (MI->getOperand(7).getImm() == X86::COND_LE)
22225 if (MI->getOperand(7).getImm() == X86::COND_G)
22231 MI->getOperand(7).getImm() == X86::COND_A
22232 || MI->getOperand(7).getImm() == X86::COND_BE
22239 MI->getOperand(7).getImm() == X86::COND_A
22240 || MI->getOperand(7).getImm() == X86::COND_BE
22247 MI->getOperand(7).getImm() == X86::COND_A
22248 || MI->getOperand(7).getImm() == X86::COND_BE
22255 MI->getOperand(7).getImm() == X86::COND_A
22256 || MI->getOperand(7).getImm() == X86::COND_BE
22263 MI->getOperand(7).getImm() == X86::COND_A
22264 || MI->getOperand(7).getImm() == X86::COND_BE
22273 MI->getOperand(1).getImm() == X86::COND_A
22274 || MI->getOperand(1).getImm() == X86::COND_BE
22281 MI->getOperand(1).getImm() == X86::COND_A
22282 || MI->getOperand(1).getImm() == X86::COND_BE
22289 MI->getOperand(1).getImm() == X86::COND_A
22290 || MI->getOperand(1).getImm() == X86::COND_BE
22297 MI->getOperand(1).getImm() == X86::COND_A
22298 || MI->getOperand(1).getImm() == X86::COND_BE
22305 MI->getOperand(1).getImm() == X86::COND_A
22306 || MI->getOperand(1).getImm() == X86::COND_BE
22314 if (MI->getOperand(5).getImm() == X86::COND_GE)
22316 if (MI->getOperand(5).getImm() == X86::COND_G)
22318 if (MI->getOperand(5).getImm() == X86::COND_LE)
22320 if (MI->getOperand(5).getImm() == X86::COND_L)
22326 MI->getOperand(5).getImm() == X86::COND_A
22327 || MI->getOperand(5).getImm() == X86::COND_BE
22334 MI->getOperand(5).getImm() == X86::COND_A
22335 || MI->getOperand(5).getImm() == X86::COND_BE
22342 MI->getOperand(5).getImm() == X86::COND_A
22343 || MI->getOperand(5).getImm() == X86::COND_BE
22350 MI->getOperand(5).getImm() == X86::COND_A
22351 || MI->getOperand(5).getImm() == X86::COND_BE
22358 MI->getOperand(5).getImm() == X86::COND_A
22359 || MI->getOperand(5).getImm() == X86::COND_BE
22367 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22367 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22372 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22372 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22377 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22377 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22382 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22382 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22389 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22389 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22394 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22394 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22399 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22399 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22404 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22404 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22411 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22411 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22416 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22416 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22421 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22421 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22426 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22426 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22434 MI->getOperand(2).getImm() == 0
22435 && MI->getOperand(1).getReg() != X86::AX
22436 && MI->getOperand(1).getReg() != X86::EAX
22437 && MI->getOperand(1).getReg() != X86::RAX
22453 MI->getOperand(1).getReg() == MI->getOperand(2).getReg()
22453 MI->getOperand(1).getReg() == MI->getOperand(2).getReg()
22454 && MI->getOperand(3).getImm() == 136
22469 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22469 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22474 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22474 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22481 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22481 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22486 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22486 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22493 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22493 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22498 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22498 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22505 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22505 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22510 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22510 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22742 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22742 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22749 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22749 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22756 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22756 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22766 MI->getOperand(2).isImm()
22767 && MI->getOperand(2).getImm() != 1
22776 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22776 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22781 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22781 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22788 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22788 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22793 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22793 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22798 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22798 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22803 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22803 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22808 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22808 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22813 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22813 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22818 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22818 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22825 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22825 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22830 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22830 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22835 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22835 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22840 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22840 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22847 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22847 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22854 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22854 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22861 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22861 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22868 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22868 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22875 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22875 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22882 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22882 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22889 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22889 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22896 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22896 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22903 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22903 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22925 return MI->getOperand(1).getReg() == MI->getOperand(2).getReg();
22925 return MI->getOperand(1).getReg() == MI->getOperand(2).getReg();
22933 MI->getOperand(1).getReg() == MI->getOperand(2).getReg()
22933 MI->getOperand(1).getReg() == MI->getOperand(2).getReg()
22934 && MI->getOperand(3).getImm() == 136
22997 return MI->getOperand(1).getReg() == MI->getOperand(2).getReg();
22997 return MI->getOperand(1).getReg() == MI->getOperand(2).getReg();
23017 return MI->getOperand(1).getReg() == MI->getOperand(2).getReg();
23017 return MI->getOperand(1).getReg() == MI->getOperand(2).getReg();
23034 return MI->getOperand(1).getReg() == MI->getOperand(2).getReg();
23034 return MI->getOperand(1).getReg() == MI->getOperand(2).getReg();
23042 return MI->getOperand(0).getReg() == MI->getOperand(1).getReg();
23042 return MI->getOperand(0).getReg() == MI->getOperand(1).getReg();
include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h 470 return MI.getOperand(MI.getNumOperands() - 1).getReg();
472 return MI.getOperand(1).getReg();
include/llvm/CodeGen/MachineInstr.h 449 const MachineOperand &MO = getOperand(I);
463 assert(getOperand(OpIdx).getType() == MachineOperand::MO_Immediate &&
781 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
858 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
871 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1065 && getOperand(0).isReg()
1066 && getOperand(1).isImm();
1076 return isDebugValue() && getOperand(0).isReg() && !getOperand(0).getReg().isValid();
1076 return isDebugValue() && getOperand(0).isReg() && !getOperand(0).getReg().isValid();
1120 return isCopy() && !getOperand(0).getSubReg() && !getOperand(1).getSubReg();
1120 return isCopy() && !getOperand(0).getSubReg() && !getOperand(1).getSubReg();
1135 return isCopy() && getOperand(0).getReg() == getOperand(1).getReg() &&
1135 return isCopy() && getOperand(0).getReg() == getOperand(1).getReg() &&
1136 getOperand(0).getSubReg() == getOperand(1).getSubReg();
1136 getOperand(0).getSubReg() == getOperand(1).getSubReg();
1368 const MachineOperand &MO = getOperand(DefOpIdx);
1381 const MachineOperand &MO = getOperand(UseOpIdx);
1664 return getOperand(getNumExplicitDefs()).getIntrinsicID();
include/llvm/CodeGen/StackMaps.h 47 uint64_t getID() const { return MI->getOperand(IDPos).getImm(); }
51 return MI->getOperand(NBytesPos).getImm();
91 return MI->getOperand(getMetaIdx(Pos));
122 return MI->getOperand(getMetaIdx(NArgPos)).getImm();
173 return MI->getOperand(NCallArgsPos).getImm() + MetaEnd;
177 uint64_t getID() const { return MI->getOperand(IDPos).getImm(); }
181 return MI->getOperand(NBytesPos).getImm();
186 return MI->getOperand(CallTargetPos);
include/llvm/CodeGen/TargetInstrInfo.h 190 assert(I.getOperand(0).getImm() >= 0);
191 return I.getOperand(0).getImm();
199 assert(I.getOperand(1).getImm() >= 0 &&
201 return getFrameSize(I) + I.getOperand(1).getImm();
940 Destination = &MI.getOperand(0);
941 Source = &MI.getOperand(1);
lib/CodeGen/Analysis.cpp 761 const MachineBasicBlock *Successor = MBBI->getOperand(0).getMBB();
762 const MachineBasicBlock *SuccessorColor = MBBI->getOperand(1).getMBB();
lib/CodeGen/AsmPrinter/AsmPrinter.cpp 793 Register RegNo = MI->getOperand(0).getReg();
809 const MachineOperand &Op = MI->getOperand(i);
840 bool MemLoc = MI->getOperand(0).isReg() && MI->getOperand(1).isImm();
840 bool MemLoc = MI->getOperand(0).isReg() && MI->getOperand(1).isImm();
841 int64_t Offset = MemLoc ? MI->getOperand(1).getImm() : 0;
859 if (MI->getOperand(0).isFPImm()) {
860 APFloat APF = APFloat(MI->getOperand(0).getFPImm()->getValueAPF());
861 if (MI->getOperand(0).getFPImm()->getType()->isFloatTy()) {
863 } else if (MI->getOperand(0).getFPImm()->getType()->isDoubleTy()) {
873 } else if (MI->getOperand(0).isImm()) {
874 OS << MI->getOperand(0).getImm();
875 } else if (MI->getOperand(0).isCImm()) {
876 MI->getOperand(0).getCImm()->getValue().print(OS, false /*isSigned*/);
879 if (MI->getOperand(0).isReg()) {
880 Reg = MI->getOperand(0).getReg();
882 assert(MI->getOperand(0).isFI() && "Unknown operand type");
885 MI->getOperand(0).getIndex(), Reg);
968 unsigned CFIIndex = MI.getOperand(0).getCFIIndex();
975 MCSymbol *FrameAllocSym = MI.getOperand(0).getMCSymbol();
976 int FrameOffset = MI.getOperand(1).getImm();
lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp 250 unsigned OpFlags = MI->getOperand(OpNo).getImm();
258 MI->getOperand(OpNo).isMetadata()) {
261 unsigned OpFlags = MI->getOperand(OpNo).getImm();
414 unsigned OpFlags = MI->getOperand(OpNo).getImm();
422 MI->getOperand(OpNo).isMetadata()) {
425 unsigned OpFlags = MI->getOperand(OpNo).getImm();
431 if (MI->getOperand(OpNo).isBlockAddress()) {
432 const BlockAddress *BA = MI->getOperand(OpNo).getBlockAddress();
436 } else if (MI->getOperand(OpNo).isMBB()) {
437 const MCSymbol *Sym = MI->getOperand(OpNo).getMBB()->getSymbol();
473 for (; MI->getOperand(NumDefs).isReg() && MI->getOperand(NumDefs).isDef();
473 for (; MI->getOperand(NumDefs).isReg() && MI->getOperand(NumDefs).isDef();
477 assert(MI->getOperand(NumDefs).isSymbol() && "No asm string?");
480 const char *AsmStr = MI->getOperand(NumDefs).getSymbolName();
499 if (MI->getOperand(i-1).isMetadata() &&
500 (LocMD = MI->getOperand(i-1).getMetadata()) &&
529 const MachineOperand &MO = MI->getOperand(I);
534 !TRI->isAsmClobberable(*MF, MI->getOperand(I + 1).getReg())) {
535 RestrRegs.push_back(TRI->getName(MI->getOperand(I + 1).getReg()));
620 const MachineOperand &MO = MI->getOperand(OpNo);
lib/CodeGen/AsmPrinter/DbgEntityHistoryCalculator.cpp 50 return MI.getOperand(0).isReg() ? MI.getOperand(0).getReg() : Register();
50 return MI.getOperand(0).isReg() ? MI.getOperand(0).getReg() : Register();
lib/CodeGen/AsmPrinter/DebugHandlerBase.cpp 35 if (!Instruction.getOperand(0).isReg())
37 Location.Register = Instruction.getOperand(0).getReg();
218 return MI->getOperand(0).isReg() && MI->getOperand(0).getReg();
218 return MI->getOperand(0).isReg() && MI->getOperand(0).getReg();
lib/CodeGen/AsmPrinter/DwarfDebug.cpp 235 if (MI->getOperand(0).isReg()) {
236 auto RegOp = MI->getOperand(0);
237 auto Op1 = MI->getOperand(1);
244 if (MI->getOperand(0).isImm())
245 return DbgValueLoc(Expr, MI->getOperand(0).getImm());
246 if (MI->getOperand(0).isFPImm())
247 return DbgValueLoc(Expr, MI->getOperand(0).getFPImm());
248 if (MI->getOperand(0).isCImm())
249 return DbgValueLoc(Expr, MI->getOperand(0).getCImm());
722 const MachineOperand &CalleeOp = MI.getOperand(0);
1346 if (DbgValue->getOperand(0).isImm() && MBB->pred_empty())
lib/CodeGen/AsmPrinter/EHStreamer.cpp 175 const MachineOperand &MO = MI->getOperand(I);
252 MCSymbol *BeginLabel = MI.getOperand(0).getMCSymbol();
lib/CodeGen/AsmPrinter/WinException.cpp 475 MCSymbol *Label = MI.getOperand(0).getMCSymbol();
lib/CodeGen/BranchFolding.cpp 259 const MachineOperand &Op = MI.getOperand(i);
lib/CodeGen/CalcSpillWeights.cpp 56 if (mi->getOperand(0).getReg() == reg) {
57 sub = mi->getOperand(0).getSubReg();
58 hreg = mi->getOperand(1).getReg();
59 hsub = mi->getOperand(1).getSubReg();
61 sub = mi->getOperand(1).getSubReg();
62 hreg = mi->getOperand(0).getReg();
63 hsub = mi->getOperand(0).getSubReg();
lib/CodeGen/DeadMachineInstructionElim.cpp 76 const MachineOperand &MO = MI->getOperand(i);
lib/CodeGen/DetectDeadLanes.cpp 169 DstSubIdx = MI.getOperand(3).getImm();
173 DstSubIdx = MI.getOperand(OpNum+1).getImm();
177 unsigned SubReg = MI.getOperand(2).getImm();
234 DefinedByCopy[Register::virtReg2Index(MI.getOperand(0).getReg())]);
242 unsigned SubIdx = MI.getOperand(OpNum + 1).getImm();
246 unsigned SubIdx = MI.getOperand(3).getImm();
252 const MachineOperand &Def = MI.getOperand(0);
266 unsigned SubIdx = MI.getOperand(2).getImm();
316 unsigned SubIdx = MI.getOperand(OpNum + 1).getImm();
322 unsigned SubIdx = MI.getOperand(3).getImm();
334 unsigned SubIdx = MI.getOperand(2).getImm();
472 const MachineOperand &Def = MI.getOperand(0);
lib/CodeGen/GlobalISel/GISelKnownBits.cpp 45 int FrameIdx = MI.getOperand(1).getIndex();
lib/CodeGen/GlobalISel/LegalizerHelper.cpp 3161 MI, KShiftAmt->getOperand(1).getCImm()->getValue(), HalfTy, ShiftAmtTy);
lib/CodeGen/GlobalISel/LegalizerInfo.cpp 398 return MRI.getType(MI.getOperand(MI.getNumOperands() - 1).getReg());
399 return MRI.getType(MI.getOperand(OpIdx).getReg());
lib/CodeGen/GlobalISel/Localizer.cpp 82 Register Reg = MI.getOperand(0).getReg();
lib/CodeGen/GlobalISel/RegBankSelect.cpp 331 assert(&MI.getOperand(RepairPt.getOpIdx()) == &MO &&
lib/CodeGen/GlobalISel/RegisterBankInfo.cpp 179 const MachineOperand &MO = MI.getOperand(OpIdx);
216 unsigned ResultSize = getSizeInBits(MI.getOperand(0).getReg(),
228 const MachineOperand &MO = MI.getOperand(OpIdx);
604 const MachineOperand &MO = MI.getOperand(Idx);
lib/CodeGen/GlobalISel/Utils.cpp 229 const MachineOperand &CstVal = MI.getOperand(1);
235 MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
lib/CodeGen/InlineSpiller.cpp 264 if (MI.getOperand(0).getReg() == Reg)
265 return MI.getOperand(1).getReg();
266 if (MI.getOperand(1).getReg() == Reg)
267 return MI.getOperand(0).getReg();
930 return !Def.getOperand(0).getSubReg();
lib/CodeGen/LiveDebugValues.cpp 89 return MI.getOperand(0).isReg() ? MI.getOperand(0).getReg() : Register();
89 return MI.getOperand(0).isReg() ? MI.getOperand(0).getReg() : Register();
232 } else if (MI.getOperand(0).isImm()) {
234 Loc.Immediate = MI.getOperand(0).getImm();
235 } else if (MI.getOperand(0).isFPImm()) {
237 Loc.FPImm = MI.getOperand(0).getFPImm();
238 } else if (MI.getOperand(0).isCImm()) {
240 Loc.CImm = MI.getOperand(0).getCImm();
308 MachineOperand MO = MI.getOperand(0);
687 if (isDbgValueDescribedByReg(MI) || MI.getOperand(0).isImm() ||
688 MI.getOperand(0).isFPImm() || MI.getOperand(0).isCImm()) {
688 MI.getOperand(0).isFPImm() || MI.getOperand(0).isCImm()) {
697 assert(MI.getOperand(0).isReg() && MI.getOperand(0).getReg() == 0 &&
697 assert(MI.getOperand(0).isReg() && MI.getOperand(0).getReg() == 0 &&
907 Reg = MI.getOperand(0).getReg();
lib/CodeGen/LiveRangeCalc.cpp 189 unsigned OpNo = (&MO - &MI->getOperand(0));
195 UseIdx = Indexes->getMBBEndIdx(MI->getOperand(OpNo+1).getMBB());
205 isEarlyClobber = MI->getOperand(DefIdx).isEarlyClobber();
lib/CodeGen/LiveRangeEdit.cpp 112 const MachineOperand &MO = OrigMI->getOperand(i);
lib/CodeGen/LiveVariables.cpp 714 if (BBI.getOperand(i).readsReg())
715 PHIVarInfo[BBI.getOperand(i + 1).getMBB()->getNumber()]
716 .push_back(BBI.getOperand(i).getReg());
lib/CodeGen/MIRPrinter.cpp 719 for (; I < E && MI.getOperand(I).isReg() && MI.getOperand(I).isDef() &&
719 for (; I < E && MI.getOperand(I).isReg() && MI.getOperand(I).isDef() &&
720 !MI.getOperand(I).isImplicit();
822 const MachineOperand &Op = MI.getOperand(OpIdx);
lib/CodeGen/MachineCopyPropagation.cpp 265 Register PreviousSrc = PreviousCopy.getOperand(1).getReg();
266 Register PreviousDef = PreviousCopy.getOperand(0).getReg();
322 Register CopySrcReg = Copy.getOperand(1).getReg();
350 TRI->getMinimalPhysRegClass(UseI.getOperand(0).getReg());
lib/CodeGen/MachineFrameInfo.cpp 206 unsigned ExtraInfo = MI.getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
lib/CodeGen/MachineInstr.cpp 615 const MachineOperand &MO = getOperand(i);
616 const MachineOperand &OMO = Other.getOperand(i);
705 const MachineOperand &MO = getOperand(I);
724 const MachineOperand &MO = getOperand(I);
770 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
779 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
796 const MachineOperand &FlagMO = getOperand(i);
813 return cast<DILabel>(getOperand(0).getMetadata());
818 return cast<DILocalVariable>(getOperand(2).getMetadata());
823 return cast<DIExpression>(getOperand(3).getMetadata());
842 if (!getOperand(OpIdx).isReg())
847 if (getOperand(OpIdx).isUse() && isRegTiedToDefOperand(OpIdx, &DefIdx))
855 unsigned Flag = getOperand(FlagIdx).getImm();
892 const MachineOperand &MO = getOperand(OpIdx);
903 const MachineOperand &MO = getOperand(OpIdx);
933 const MachineOperand &MO = getOperand(i);
946 const MachineOperand &MO = getOperand(i);
970 const MachineOperand &MO = getOperand(i);
996 const MachineOperand &MO = getOperand(i);
1076 const MachineOperand &MO = getOperand(OpIdx);
1090 const MachineOperand &UseMO = getOperand(i);
1104 const MachineOperand &FlagMO = getOperand(i);
1361 Register Reg = getOperand(1).getReg();
1363 if (getOperand(i).getReg() != Reg)
1372 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1402 const MachineOperand &MO = MI.getOperand(i);
1411 const auto &Operand = getOperand(I);
1425 const MachineOperand &Op = getOperand(OpIdx);
1490 const MachineOperand &MO = getOperand(OpIdx);
1500 const MachineOperand &MO = getOperand(StartOp);
1564 getOperand(OpIdx).print(OS, MST, TypeToPrint, /*PrintDef=*/true, IsStandalone,
1569 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1590 const MachineOperand &MO = getOperand(i);
1760 if (isDebugValue() && getOperand(e - 2).isMetadata()) {
1765 auto *DV = cast<DILocalVariable>(getOperand(e - 2).getMetadata());
1996 if (getOperand(i-1).isMetadata() &&
1997 (LocMD = getOperand(i-1).getMetadata()) &&
2073 assert(MI.getOperand(0).isReg() && "can't spill non-register");
2079 assert(MI.getOperand(1).getImm() == 0 && "DBG_VALUE with nonzero offset");
lib/CodeGen/MachineLICM.cpp 851 const MachineOperand &MO = MI->getOperand(i);
957 Register CopySrcReg = MI.getOperand(1).getReg();
964 Register CopyDstReg = MI.getOperand(0).getReg();
1381 MO.getReg() == Dup->getOperand(i).getReg()) &&
1393 Register DupReg = Dup->getOperand(Idx).getReg();
1399 MRI->setRegClass(Dup->getOperand(Defs[j]).getReg(), OrigRCs[j]);
1406 Register DupReg = Dup->getOperand(Idx).getReg();
lib/CodeGen/MachineSSAUpdater.cpp 214 if (&MI->getOperand(i) == U)
215 return MI->getOperand(i+1).getMBB();
lib/CodeGen/MachineScheduler.cpp 2919 if (Register::isPhysicalRegister(MI->getOperand(ScheduledOper).getReg()))
2924 if (Register::isPhysicalRegister(MI->getOperand(UnscheduledOper).getReg()))
lib/CodeGen/MachineTraceMetrics.cpp 689 if (UseMI.getOperand(i + 1).getMBB() == Pred) {
690 Register Reg = UseMI.getOperand(i).getReg();
742 for (MCRegUnitIterator Units(UseMI->getOperand(DefOp).getReg(), TRI);
933 Register Reg = MI.getOperand(ReadOps[i]).getReg();
981 unsigned Reg = DefMI->getOperand(DefOp).getReg();
lib/CodeGen/MachineVerifier.cpp 440 const MachineOperand &Op = MI.getOperand(I);
857 if (!MI->getOperand(0).isSymbol())
859 if (!MI->getOperand(1).isImm())
864 if (!isUInt<6>(MI->getOperand(1).getImm()))
865 report("Unknown asm flags", &MI->getOperand(1), 1);
872 const MachineOperand &MO = MI->getOperand(OpNo);
883 if (OpNo < MI->getNumOperands() && MI->getOperand(OpNo).isMetadata())
888 const MachineOperand &MO = MI->getOperand(OpNo);
935 const MachineOperand *MO = &MI->getOperand(I);
959 const MachineOperand *MO = &MI->getOperand(I);
979 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
984 if (!MI->getOperand(1).isCImm()) {
989 const ConstantInt *CI = MI->getOperand(1).getCImm();
993 if (!MI->getOperand(1).isFPImm()) {
997 const ConstantFP *CF = MI->getOperand(1).getFPImm();
1011 LLT ValTy = MRI->getType(MI->getOperand(0).getReg());
1012 LLT PtrTy = MRI->getType(MI->getOperand(1).getReg());
1039 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1056 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1057 LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
1071 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1072 LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
1104 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1105 LLT PtrTy = MRI->getType(MI->getOperand(1).getReg());
1106 LLT OffsetTy = MRI->getType(MI->getOperand(2).getReg());
1131 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1132 LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
1160 LLT SelTy = MRI->getType(MI->getOperand(0).getReg());
1161 LLT CondTy = MRI->getType(MI->getOperand(1).getReg());
1175 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1176 LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
1185 if (MRI->getType(MI->getOperand(I).getReg()) != SrcTy)
1192 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1193 LLT SrcTy = MRI->getType(MI->getOperand(MI->getNumOperands()-1).getReg());
1196 if (MRI->getType(MI->getOperand(i).getReg()) != DstTy)
1209 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1210 LLT SrcEltTy = MRI->getType(MI->getOperand(1).getReg());
1223 if (MRI->getType(MI->getOperand(1).getReg()) !=
1224 MRI->getType(MI->getOperand(i).getReg()))
1233 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1234 LLT SrcEltTy = MRI->getType(MI->getOperand(1).getReg());
1239 if (MRI->getType(MI->getOperand(1).getReg()) !=
1240 MRI->getType(MI->getOperand(i).getReg()))
1253 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1254 LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
1259 if (MRI->getType(MI->getOperand(1).getReg()) !=
1260 MRI->getType(MI->getOperand(i).getReg()))
1270 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1271 LLT SrcTy = MRI->getType(MI->getOperand(2).getReg());
1280 const MachineOperand &SrcOp = MI->getOperand(1);
1286 const MachineOperand &OffsetOp = MI->getOperand(2);
1292 unsigned DstSize = MRI->getType(MI->getOperand(0).getReg()).getSizeInBits();
1302 const MachineOperand &SrcOp = MI->getOperand(2);
1308 const MachineOperand &OffsetOp = MI->getOperand(3);
1314 unsigned DstSize = MRI->getType(MI->getOperand(0).getReg()).getSizeInBits();
1326 if (!MI->getOperand(1).isJTI())
1328 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1334 if (!MRI->getType(MI->getOperand(0).getReg()).isPointer())
1337 if (!MI->getOperand(1).isJTI())
1340 const auto &IdxOp = MI->getOperand(2);
1349 const MachineOperand &IntrIDOp = MI->getOperand(MI->getNumExplicitDefs());
1388 if (!MI->getOperand(2).isImm()) {
1393 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1394 LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
1397 int64_t Imm = MI->getOperand(2).getImm();
1405 const MachineOperand &MaskOp = MI->getOperand(3);
1423 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1424 LLT Src0Ty = MRI->getType(MI->getOperand(1).getReg());
1425 LLT Src1Ty = MRI->getType(MI->getOperand(2).getReg());
1455 const MachineOperand &DstOp = MI->getOperand(0);
1456 const MachineOperand &AllocOp = MI->getOperand(1);
1457 const MachineOperand &AlignOp = MI->getOperand(2);
1542 const MachineOperand &DstOp = MI->getOperand(0);
1543 const MachineOperand &SrcOp = MI->getOperand(1);
1570 if (!MI->getOperand(StatepointOpers::IDPos).isImm() ||
1571 !MI->getOperand(StatepointOpers::NBytesPos).isImm() ||
1572 !MI->getOperand(StatepointOpers::NCallArgsPos).isImm())
1577 if (!MI->getOperand(Offset).isImm() ||
1578 MI->getOperand(Offset).getImm() != StackMaps::ConstantOp ||
1579 !MI->getOperand(Offset + 1).isImm())
1630 const MachineOperand &MOTied = MI->getOperand(TiedTo);
1656 const MachineOperand &OtherMO = MI->getOperand(OtherIdx);
1679 Reg != MI->getOperand(DefIdx).getReg())
2214 const MachineOperand &MODef = Phi.getOperand(0);
2227 const MachineOperand &MO0 = Phi.getOperand(I);
2236 const MachineOperand &MO1 = Phi.getOperand(I + 1);
lib/CodeGen/PHIElimination.cpp 233 const MachineOperand &MO = MPhi.getOperand(I);
557 ++VRegPHIUseCount[BBVRegPair(BBI.getOperand(i+1).getMBB()->getNumber(),
558 BBI.getOperand(i).getReg())];
lib/CodeGen/PeepholeOptimizer.cpp 1817 if (Def->getOperand(DefIdx).getSubReg() != DefSubReg)
1822 const MachineOperand &Src = Def->getOperand(1);
1838 const MachineOperand DefOp = Def->getOperand(DefIdx);
1847 const MachineOperand &MO = Def->getOperand(OpIdx);
1872 const MachineOperand &Src = Def->getOperand(SrcIdx);
1882 if (Def->getOperand(DefIdx).getSubReg())
1926 if (Def->getOperand(DefIdx).getSubReg())
1955 const MachineOperand &MODef = Def->getOperand(DefIdx);
2013 if (DefSubReg != Def->getOperand(3).getImm())
2017 if (Def->getOperand(2).getSubReg())
2020 return ValueTrackerResult(Def->getOperand(2).getReg(),
2021 Def->getOperand(3).getImm());
2031 if (Def->getOperand(0).getSubReg() != DefSubReg)
2036 const MachineOperand &MO = Def->getOperand(i);
2051 assert(((Def->getOperand(DefIdx).isDef() &&
2054 Def->getOperand(DefIdx).isImplicit()) &&
lib/CodeGen/RegAllocFast.cpp 648 Register Reg = MI.getOperand(1).getReg();
790 Hint = UseMI.getOperand(0).getReg();
lib/CodeGen/RegAllocGreedy.cpp 2877 Register OtherReg = Instr.getOperand(0).getReg();
2879 OtherReg = Instr.getOperand(1).getReg();
lib/CodeGen/RegisterCoalescer.cpp 366 Dst = MI->getOperand(0).getReg();
367 DstSub = MI->getOperand(0).getSubReg();
368 Src = MI->getOperand(1).getReg();
369 SrcSub = MI->getOperand(1).getSubReg();
371 Dst = MI->getOperand(0).getReg();
372 DstSub = tri.composeSubRegIndices(MI->getOperand(0).getSubReg(),
373 MI->getOperand(3).getImm());
374 Src = MI->getOperand(2).getReg();
375 SrcSub = MI->getOperand(2).getSubReg();
lib/CodeGen/ScheduleDAGInstrs.cpp 510 const MachineOperand &MO = MI->getOperand(OperIdx);
lib/CodeGen/StackColoring.cpp 571 const MachineOperand &MO = MI.getOperand(0);
lib/CodeGen/StackMaps.cpp 55 : MI(MI), HasDef(MI->getOperand(0).isReg() && MI->getOperand(0).isDef() &&
55 : MI(MI), HasDef(MI->getOperand(0).isReg() && MI->getOperand(0).isDef() &&
56 !MI->getOperand(0).isImplicit()) {
59 while (CheckStartIdx < e && MI->getOperand(CheckStartIdx).isReg() &&
60 MI->getOperand(CheckStartIdx).isDef() &&
61 !MI->getOperand(CheckStartIdx).isImplicit())
76 !(MI->getOperand(ScratchIdx).isReg() &&
77 MI->getOperand(ScratchIdx).isDef() &&
78 MI->getOperand(ScratchIdx).isImplicit() &&
79 MI->getOperand(ScratchIdx).isEarlyClobber()))
367 const int64_t ID = MI.getOperand(PatchPointOpers::IDPos).getImm();
lib/CodeGen/TailDuplicator.cpp 315 Register SrcReg = MI.getOperand(i).getReg();
lib/CodeGen/TargetInstrInfo.cpp 303 if (!MI.getOperand(SrcOpIdx1).isReg() || !MI.getOperand(SrcOpIdx2).isReg())
303 if (!MI.getOperand(SrcOpIdx1).isReg() || !MI.getOperand(SrcOpIdx2).isReg())
440 const MachineOperand &FoldOp = MI.getOperand(FoldIdx);
441 const MachineOperand &LiveOp = MI.getOperand(1 - FoldIdx);
669 const MachineOperand &Op1 = Inst.getOperand(1);
670 const MachineOperand &Op2 = Inst.getOperand(2);
690 MachineInstr *MI1 = MRI.getUniqueVRegDef(Inst.getOperand(1).getReg());
691 MachineInstr *MI2 = MRI.getUniqueVRegDef(Inst.getOperand(2).getReg());
888 if (!MI.getNumOperands() || !MI.getOperand(0).isReg())
890 Register DefReg = MI.getOperand(0).getReg();
896 if (Register::isVirtualRegister(DefReg) && MI.getOperand(0).getSubReg() &&
925 const MachineOperand &MO = MI.getOperand(i);
1180 const MachineOperand &MOReg = MI.getOperand(OpIdx);
1183 const MachineOperand &MOSubIdx = MI.getOperand(OpIdx + 1);
1205 const MachineOperand &MOReg = MI.getOperand(1);
1208 const MachineOperand &MOSubIdx = MI.getOperand(2);
1230 const MachineOperand &MOBaseReg = MI.getOperand(1);
1231 const MachineOperand &MOInsertedReg = MI.getOperand(2);
1234 const MachineOperand &MOSubIdx = MI.getOperand(3);
lib/CodeGen/TargetRegisterInfo.cpp 504 CopySrcReg = MI->getOperand(1).getReg();
507 CopySrcReg = MI->getOperand(2).getReg();
lib/CodeGen/TargetSchedule.cpp 160 const MachineOperand &MO = MI->getOperand(i);
176 const MachineOperand &MO = MI->getOperand(i);
241 if (SCDesc->isValid() && !DefMI->getOperand(DefOperIdx).isImplicit()
303 Register Reg = DefMI->getOperand(DefOperIdx).getReg();
lib/CodeGen/VirtRegMap.cpp 425 if (TRI->regsOverlap(Dst->getOperand(0).getReg(),
426 Src->getOperand(1).getReg()))
lib/Target/AArch64/AArch64AdvSIMDScalarPass.cpp 204 Register OrigSrc0 = MI.getOperand(1).getReg();
205 Register OrigSrc1 = MI.getOperand(2).getReg();
239 Register Dst = MI.getOperand(0).getReg();
lib/Target/AArch64/AArch64AsmPrinter.cpp 240 Register Reg = MI.getOperand(0).getReg();
243 uint32_t AccessInfo = MI.getOperand(1).getImm();
500 const MachineOperand &MO = MI->getOperand(OpNum);
562 const MachineOperand &MO = MI->getOperand(OpNum);
660 const MachineOperand &MO = MI->getOperand(OpNum);
672 OS << cast<DILocalVariable>(MI->getOperand(NOps - 2).getMetadata())
676 assert(MI->getOperand(0).isReg() && MI->getOperand(1).isImm());
676 assert(MI->getOperand(0).isReg() && MI->getOperand(1).isImm());
757 Register DestReg = MI.getOperand(0).getReg();
758 Register ScratchReg = MI.getOperand(1).getReg();
761 Register TableReg = MI.getOperand(2).getReg();
762 Register EntryReg = MI.getOperand(3).getReg();
763 int JTIdx = MI.getOperand(4).getIndex();
832 Register ScratchReg = MI.getOperand(Opers.getNextScratchIdx()).getReg();
862 Register DestReg = MI.getOperand(0).getReg();
926 Register DestReg = MI->getOperand(0).getReg();
927 const MachineOperand &MO_Sym = MI->getOperand(1);
957 MI->getOperand(1).getImm() == 0) {
960 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
961 TmpInst.addOperand(MCOperand::createImm(MI->getOperand(1).getImm()));
998 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
1004 MCInstLowering.lowerOperand(MI->getOperand(0), Dest);
1019 const MachineOperand &MO_Sym = MI->getOperand(0);
1069 unsigned DestReg = MI->getOperand(0).getReg(),
1070 ScratchReg = MI->getOperand(1).getReg(),
1071 TableReg = MI->getOperand(2).getReg(),
1072 EntryReg = MI->getOperand(3).getReg();
1121 TS->EmitARM64WinCFIAllocStack(MI->getOperand(0).getImm());
1125 TS->EmitARM64WinCFISaveFPLR(MI->getOperand(0).getImm());
1129 assert(MI->getOperand(0).getImm() < 0 &&
1131 TS->EmitARM64WinCFISaveFPLRX(-MI->getOperand(0).getImm());
1135 TS->EmitARM64WinCFISaveReg(MI->getOperand(0).getImm(),
1136 MI->getOperand(1).getImm());
1140 assert(MI->getOperand(1).getImm() < 0 &&
1142 TS->EmitARM64WinCFISaveRegX(MI->getOperand(0).getImm(),
1143 -MI->getOperand(1).getImm());
1147 assert((MI->getOperand(1).getImm() - MI->getOperand(0).getImm() == 1) &&
1147 assert((MI->getOperand(1).getImm() - MI->getOperand(0).getImm() == 1) &&
1149 TS->EmitARM64WinCFISaveRegP(MI->getOperand(0).getImm(),
1150 MI->getOperand(2).getImm());
1154 assert((MI->getOperand(1).getImm() - MI->getOperand(0).getImm() == 1) &&
1154 assert((MI->getOperand(1).getImm() - MI->getOperand(0).getImm() == 1) &&
1156 assert(MI->getOperand(2).getImm() < 0 &&
1158 TS->EmitARM64WinCFISaveRegPX(MI->getOperand(0).getImm(),
1159 -MI->getOperand(2).getImm());
1163 TS->EmitARM64WinCFISaveFReg(MI->getOperand(0).getImm(),
1164 MI->getOperand(1).getImm());
1168 assert(MI->getOperand(1).getImm() < 0 &&
1170 TS->EmitARM64WinCFISaveFRegX(MI->getOperand(0).getImm(),
1171 -MI->getOperand(1).getImm());
1175 assert((MI->getOperand(1).getImm() - MI->getOperand(0).getImm() == 1) &&
1175 assert((MI->getOperand(1).getImm() - MI->getOperand(0).getImm() == 1) &&
1177 TS->EmitARM64WinCFISaveFRegP(MI->getOperand(0).getImm(),
1178 MI->getOperand(2).getImm());
1182 assert((MI->getOperand(1).getImm() - MI->getOperand(0).getImm() == 1) &&
1182 assert((MI->getOperand(1).getImm() - MI->getOperand(0).getImm() == 1) &&
1184 assert(MI->getOperand(2).getImm() < 0 &&
1186 TS->EmitARM64WinCFISaveFRegPX(MI->getOperand(0).getImm(),
1187 -MI->getOperand(2).getImm());
1195 TS->EmitARM64WinCFIAddFP(MI->getOperand(0).getImm());
lib/Target/AArch64/AArch64CollectLOH.cpp 162 switch (MI.getOperand(2).getType()) {
187 switch (MI.getOperand(2).getType()) {
191 return MI.getOperand(2).getTargetFlags() & AArch64II::MO_GOT;
216 MI.getOperand(0).getReg() != MI.getOperand(1).getReg();
216 MI.getOperand(0).getReg() != MI.getOperand(1).getReg();
238 return !(MI.getOperand(2).getTargetFlags() & AArch64II::MO_GOT);
319 MI.getOperand(2).getTargetFlags() & AArch64II::MO_GOT) {
366 assert((MI.getOperand(2).getTargetFlags() & AArch64II::MO_GOT) &&
532 const MachineOperand &Def = MI.getOperand(0);
533 const MachineOperand &Op = MI.getOperand(1);
544 const MachineOperand &Op0 = MI.getOperand(0);
lib/Target/AArch64/AArch64FalkorHWPFFix.cpp 645 Register BaseReg = MI.getOperand(BaseRegIdx).getReg();
650 LI.DestReg = DestRegIdx == -1 ? Register() : MI.getOperand(DestRegIdx).getReg();
653 LI.OffsetOpnd = OffsetIdx == -1 ? nullptr : &MI.getOperand(OffsetIdx);
lib/Target/AArch64/AArch64FastISel.cpp 4544 LoadMI->getOperand(1).getSubReg() == AArch64::sub_32) {
lib/Target/AArch64/AArch64InstrInfo.cpp 83 return getInlineAsmLength(MI.getOperand(0).getSymbolName(), *MAI);
119 NumBytes = MI.getOperand(1).getImm();
192 return MI.getOperand(0).getMBB();
197 return MI.getOperand(2).getMBB();
203 return MI.getOperand(1).getMBB();
422 VReg = DefMI->getOperand(1).getReg();
451 if (!DefMI->getOperand(2).isImm() || DefMI->getOperand(2).getImm() != 1 ||
451 if (!DefMI->getOperand(2).isImm() || DefMI->getOperand(2).getImm() != 1 ||
452 DefMI->getOperand(3).getImm() != 0)
461 unsigned ZReg = removeCopies(MRI, DefMI->getOperand(1).getReg());
479 unsigned ZReg = removeCopies(MRI, DefMI->getOperand(1).getReg());
492 *NewVReg = DefMI->getOperand(SrcOpNum).getReg();
676 uint64_t Imm = MI.getOperand(1).getImm();
701 (MI.getOperand(1).getReg() == AArch64::WZR ||
702 MI.getOperand(1).getReg() == AArch64::XZR))
726 return (MI.getOperand(3).getImm() == 0);
772 unsigned Imm = MI.getOperand(3).getImm();
785 unsigned Imm = MI.getOperand(3).getImm();
799 unsigned Imm = MI.getOperand(3).getImm();
807 unsigned Imm = MI.getOperand(3).getImm();
819 unsigned Imm = MI.getOperand(3).getImm();
879 unsigned IsSigned = MI.getOperand(3).getImm();
921 if (MI.getOperand(2).getImm() != 0 || MI.getOperand(3).getImm() != 31)
921 if (MI.getOperand(2).getImm() != 0 || MI.getOperand(3).getImm() != 31)
924 SrcReg = MI.getOperand(1).getReg();
925 DstReg = MI.getOperand(0).getReg();
971 if (MI.getOperand(0).getImm() == 0x14)
992 if (!MI.getOperand(1).isReg())
1011 SrcReg = MI.getOperand(1).getReg();
1012 SrcReg2 = MI.getOperand(2).getReg();
1020 SrcReg = MI.getOperand(1).getReg();
1024 CmpValue = MI.getOperand(2).getImm() != 0;
1030 SrcReg = MI.getOperand(1).getReg();
1039 MI.getOperand(2).getImm(),
1312 return static_cast<AArch64CC::CondCode>(Instr.getOperand(Idx - 2).getImm());
1327 return static_cast<AArch64CC::CondCode>(Instr.getOperand(Idx - 1).getImm());
1582 if (MI.getOperand(1).isImm() && MI.getOperand(1).getImm() == 0) {
1582 if (MI.getOperand(1).isImm() && MI.getOperand(1).getImm() == 0) {
1584 MI.getOperand(2).getImm() == 0 && "invalid MOVZi operands");
1589 return MI.getOperand(1).getReg() == AArch64::WZR;
1591 return MI.getOperand(1).getReg() == AArch64::XZR;
1593 return MI.getOperand(1).getReg() == AArch64::WZR;
1606 Register DstReg = MI.getOperand(0).getReg();
1611 if (MI.getOperand(1).getReg() == AArch64::XZR) {
1613 MI.getOperand(3).getImm() == 0 && "invalid ORRrs operands");
1618 if (MI.getOperand(2).getImm() == 0) {
1620 MI.getOperand(3).getImm() == 0 && "invalid ADDXri operands");
1636 Register DstReg = MI.getOperand(0).getReg();
1641 if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) {
1641 if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) {
1642 assert(MI.getDesc().getNumOperands() == 3 && MI.getOperand(0).isReg() &&
1663 if (MI.getOperand(0).getSubReg() == 0 && MI.getOperand(1).isFI() &&
1663 if (MI.getOperand(0).getSubReg() == 0 && MI.getOperand(1).isFI() &&
1664 MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 0) {
1664 MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 0) {
1665 FrameIndex = MI.getOperand(1).getIndex();
1666 return MI.getOperand(0).getReg();
1686 if (MI.getOperand(0).getSubReg() == 0 && MI.getOperand(1).isFI() &&
1686 if (MI.getOperand(0).getSubReg() == 0 && MI.getOperand(1).isFI() &&
1687 MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 0) {
1687 MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 0) {
1688 FrameIndex = MI.getOperand(1).getIndex();
1689 return MI.getOperand(0).getReg();
1933 assert((MI.getOperand(1).isReg() || MI.getOperand(1).isFI()) &&
1933 assert((MI.getOperand(1).isReg() || MI.getOperand(1).isFI()) &&
1935 if (!MI.getOperand(2).isImm())
1941 if (MI.getOperand(1).isReg()) {
1942 Register BaseReg = MI.getOperand(1).getReg();
1995 if ((!LdSt.getOperand(1).isReg() && !LdSt.getOperand(1).isFI()) ||
1995 if ((!LdSt.getOperand(1).isReg() && !LdSt.getOperand(1).isFI()) ||
1996 !LdSt.getOperand(2).isImm())
2000 if (!LdSt.getOperand(1).isReg() ||
2001 (!LdSt.getOperand(2).isReg() && !LdSt.getOperand(2).isFI()) ||
2001 (!LdSt.getOperand(2).isReg() && !LdSt.getOperand(2).isFI()) ||
2002 !LdSt.getOperand(3).isImm())
2020 BaseOp = &LdSt.getOperand(1);
2021 Offset = LdSt.getOperand(2).getImm() * Scale;
2024 BaseOp = &LdSt.getOperand(2);
2025 Offset = LdSt.getOperand(3).getImm() * Scale;
2361 int64_t Offset1 = FirstLdSt.getOperand(2).getImm();
2365 int64_t Offset2 = SecondLdSt.getOperand(2).getImm();
3415 MI.getOperand(AArch64InstrInfo::getLoadStoreImmIdx(MI.getOpcode()));
5712 MI.getOperand(1).getReg() == AArch64::WZR &&
5713 MI.getOperand(3).getImm() == 0x0) {
5714 Destination = &MI.getOperand(0);
5715 Source = &MI.getOperand(2);
5720 MI.getOperand(1).getReg() == AArch64::XZR &&
5721 MI.getOperand(3).getImm() == 0x0) {
5722 Destination = &MI.getOperand(0);
5723 Source = &MI.getOperand(2);
lib/Target/AArch64/AArch64InstructionSelector.cpp 406 LLT Ty = MRI.getType(I.getOperand(0).getReg());
559 const Register DstReg = I.getOperand(0).getReg();
560 const Register SrcReg = I.getOperand(1).getReg();
4639 Optional<int64_t> CstVal = getConstantVRegVal(MI.getOperand(0).getReg(), MRI);
4647 uint64_t CstVal = I.getOperand(1).getCImm()->getZExtValue();
4655 uint64_t CstVal = I.getOperand(1).getCImm()->getZExtValue();
4671 if (MRI.getType(MI.getOperand(0).getReg()).getSizeInBits() != 32)
lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp 606 return MI.getOperand(Idx);
611 return MI.getOperand(Idx);
616 return MI.getOperand(Idx);
lib/Target/AArch64/AArch64MacroFusion.cpp 167 SecondMI.getOperand(3).getImm() == 16))
173 SecondMI.getOperand(3).getImm() == 16))
179 FirstMI->getOperand(3).getImm() == 32)) &&
181 SecondMI.getOperand(3).getImm() == 48))
220 return SecondMI.getOperand(2).getImm() == 0;
lib/Target/AArch64/AArch64PBQPRegAlloc.cpp 362 Register Rd = MI.getOperand(0).getReg();
363 Register Ra = MI.getOperand(3).getReg();
372 Register Rd = MI.getOperand(0).getReg();
lib/Target/AArch64/AArch64RegisterBankInfo.cpp 279 unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, TRI);
300 unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, TRI);
336 unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, TRI);
428 LLT Ty = MRI.getType(MI.getOperand(0).getReg());
444 LLT OpTy = MRI.getType(MI.getOperand(Idx).getReg());
475 return getRegBank(MI.getOperand(0).getReg(), MRI, TRI) ==
547 LLT DstTy = MRI.getType(MI.getOperand(0).getReg());
548 LLT SrcTy = MRI.getType(MI.getOperand(1).getReg());
558 LLT ShiftAmtTy = MRI.getType(MI.getOperand(2).getReg());
559 LLT SrcTy = MRI.getType(MI.getOperand(1).getReg());
566 Register DstReg = MI.getOperand(0).getReg();
567 Register SrcReg = MI.getOperand(1).getReg();
593 LLT DstTy = MRI.getType(MI.getOperand(0).getReg());
594 LLT SrcTy = MRI.getType(MI.getOperand(1).getReg());
618 auto &MO = MI.getOperand(Idx);
639 LLT SrcTy = MRI.getType(MI.getOperand(1).getReg());
646 if (MRI.getType(MI.getOperand(0).getReg()).isVector())
652 if (MRI.getType(MI.getOperand(0).getReg()).isVector())
682 MRI.use_instructions(MI.getOperand(0).getReg())) {
696 Register VReg = MI.getOperand(0).getReg();
712 LLT SrcTy = MRI.getType(MI.getOperand(2).getReg());
730 MRI.use_instructions(MI.getOperand(0).getReg()),
748 Register VReg = MI.getOperand(Idx).getReg();
768 LLT SrcTy = MRI.getType(MI.getOperand(MI.getNumOperands()-1).getReg());
772 any_of(MRI.use_instructions(MI.getOperand(0).getReg()),
794 if (getRegBank(MI.getOperand(2).getReg(), MRI, TRI) == &AArch64::FPRRegBank)
804 LLT SrcTy = MRI.getType(MI.getOperand(1).getReg());
816 Register VReg = MI.getOperand(1).getReg();
840 if (MI.getOperand(Idx).isReg() && MI.getOperand(Idx).getReg()) {
840 if (MI.getOperand(Idx).isReg() && MI.getOperand(Idx).getReg()) {
lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp 1295 const MachineOperand &MO = MI->getOperand(OpNo);
lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp 1477 const MachineInstr *PtrMI = MRI.getUniqueVRegDef(Load.getOperand(1).getReg());
1487 const MachineOperand &GEPOp = PtrMI->getOperand(i);
1494 GEPInfo.Imm = OpDef->getOperand(1).getCImm()->getSExtValue();
1968 getConstantVRegVal(OpDef->getOperand(2).getReg(), *MRI);
1976 Register BasePtr = OpDef->getOperand(1).getReg();
2045 const MachineOperand &LHS = RootDef->getOperand(1);
2046 const MachineOperand &RHS = RootDef->getOperand(2);
2051 RHSDef->getOperand(1).getCImm()->getSExtValue();
2056 FI = LHSDef->getOperand(1).getIndex();
2063 FI = RootDef->getOperand(1).getIndex();
2147 const MachineOperand &LHS = RootDef->getOperand(1);
2148 const MachineOperand &RHS = RootDef->getOperand(2);
2153 RHSDef->getOperand(1).getCImm()->getSExtValue();
2181 Optional<int64_t> CstVal = getConstantVRegVal(MI.getOperand(0).getReg(), MRI);
lib/Target/AMDGPU/AMDGPUMCInstLower.cpp 190 lowerOperand(MI->getOperand(0), Dest);
191 lowerOperand(MI->getOperand(1), Src);
287 const MachineBasicBlock *MBB = MI->getOperand(0).getMBB();
lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp 188 Register Reg = MI.getOperand(RegSrcOpIdx[I]).getReg();
193 unsigned SizeI = getSizeInBits(MI.getOperand(I).getReg(), MRI, *TRI);
348 unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, *TRI);
375 unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, *TRI);
446 unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, *TRI);
447 LLT PtrTy = MRI.getType(MI.getOperand(1).getReg());
450 LLT LoadTy = MRI.getType(MI.getOperand(0).getReg());
479 unsigned Size = getSizeInBits(MI.getOperand(2).getReg(), MRI, *TRI);
515 unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, *TRI);
555 unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, *TRI);
577 assert(MRI.getType(MI.getOperand(0).getReg()).getSizeInBits() == 1);
1907 if (!MI.getOperand(i).isReg())
1909 Register Reg = MI.getOperand(i).getReg();
1928 unsigned Size = getSizeInBits(MI.getOperand(i).getReg(), MRI, *TRI);
1943 unsigned Size0 = getSizeInBits(MI.getOperand(0).getReg(), MRI, *TRI);
1946 if (MI.getOperand(OpdIdx).isIntrinsicID())
1949 Register Reg1 = MI.getOperand(OpdIdx).getReg();
1959 const MachineOperand &MO = MI.getOperand(OpdIdx);
1979 const MachineOperand &Op = MI.getOperand(I);
2005 if (!MI.getOperand(I).isReg())
2008 Register OpReg = MI.getOperand(I).getReg();
2036 unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, *TRI);
2037 LLT LoadTy = MRI.getType(MI.getOperand(0).getReg());
2038 Register PtrReg = MI.getOperand(1).getReg();
2122 auto OpBank = getRegBankID(MI.getOperand(I).getReg(), MRI, *TRI);
2130 unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, *TRI);
2147 Register Reg = MI.getOperand(I).getReg();
2175 unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
2197 unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
2200 = getRegBank(MI.getOperand(0).getReg(), MRI, *TRI);
2216 BankLHS = getRegBankID(MI.getOperand(1).getReg(), MRI, *TRI,
2218 BankRHS = getRegBankID(MI.getOperand(2).getReg(), MRI, *TRI,
2222 BankLHS = getRegBankID(MI.getOperand(1).getReg(), MRI, *TRI,
2224 BankRHS = getRegBankID(MI.getOperand(2).getReg(), MRI, *TRI,
2259 unsigned Bank1 = getRegBankID(MI.getOperand(1).getReg(), MRI, *TRI/*, DefaultBankID*/);
2262 unsigned Bank2 = getRegBankID(MI.getOperand(2).getReg(), MRI, *TRI/*, DefaultBankID*/);
2325 unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
2333 unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
2340 unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
2347 unsigned DstSize = getSizeInBits(MI.getOperand(0).getReg(), MRI, *TRI);
2348 unsigned SrcSize = getSizeInBits(MI.getOperand(1).getReg(), MRI, *TRI);
2349 unsigned EltSize = getSizeInBits(MI.getOperand(2).getReg(), MRI, *TRI);
2357 unsigned BankID = getRegBankID(MI.getOperand(1).getReg(), MRI, *TRI);
2358 unsigned DstSize = getSizeInBits(MI.getOperand(0).getReg(), MRI, *TRI);
2359 unsigned SrcSize = getSizeInBits(MI.getOperand(1).getReg(), MRI, *TRI);
2367 LLT DstTy = MRI.getType(MI.getOperand(0).getReg());
2370 unsigned SrcSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
2371 unsigned Src0BankID = getRegBankID(MI.getOperand(1).getReg(), MRI, *TRI);
2372 unsigned Src1BankID = getRegBankID(MI.getOperand(2).getReg(), MRI, *TRI);
2387 unsigned DstSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
2388 unsigned SrcSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
2408 unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
2409 unsigned BankID = getRegBankID(MI.getOperand(1).getReg(), MRI, *TRI);
2414 Register Dst = MI.getOperand(0).getReg();
2415 Register Src = MI.getOperand(1).getReg();
2426 Register Dst = MI.getOperand(0).getReg();
2427 Register Src = MI.getOperand(1).getReg();
2458 unsigned Size = MRI.getType(MI.getOperand(2).getReg()).getSizeInBits();
2459 unsigned Op2Bank = getRegBankID(MI.getOperand(2).getReg(), MRI, *TRI);
2467 assert(MI.getOperand(0).isReg());
2468 unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
2485 auto Pred = static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate());
2486 unsigned Size = MRI.getType(MI.getOperand(2).getReg()).getSizeInBits();
2487 unsigned Op2Bank = getRegBankID(MI.getOperand(2).getReg(), MRI, *TRI);
2488 unsigned Op3Bank = getRegBankID(MI.getOperand(3).getReg(), MRI, *TRI);
2506 unsigned SrcBankID = getRegBankID(MI.getOperand(1).getReg(), MRI, *TRI);
2507 unsigned DstSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
2508 unsigned SrcSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
2509 unsigned IdxSize = MRI.getType(MI.getOperand(2).getReg()).getSizeInBits();
2510 unsigned IdxBank = getRegBankID(MI.getOperand(2).getReg(), MRI, *TRI);
2524 unsigned VecSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
2525 unsigned InsertSize = MRI.getType(MI.getOperand(2).getReg()).getSizeInBits();
2526 unsigned IdxSize = MRI.getType(MI.getOperand(3).getReg()).getSizeInBits();
2527 unsigned SrcBankID = getRegBankID(MI.getOperand(1).getReg(), MRI, *TRI);
2528 unsigned InsertEltBankID = getRegBankID(MI.getOperand(2).getReg(),
2530 unsigned IdxBankID = getRegBankID(MI.getOperand(3).getReg(), MRI, *TRI);
2548 unsigned Size = getSizeInBits(MI.getOperand(i).getReg(), MRI, *TRI);
2618 unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
2623 unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
2630 Register RSrc = MI.getOperand(2).getReg(); // SGPR
2631 Register Offset = MI.getOperand(3).getReg(); // SGPR/imm
2633 unsigned Size0 = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
2651 unsigned Dst0Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
2652 unsigned Dst1Size = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
2656 unsigned SrcSize = MRI.getType(MI.getOperand(3).getReg()).getSizeInBits();
2658 getRegBankID(MI.getOperand(3).getReg(), MRI, *TRI), SrcSize);
2660 getRegBankID(MI.getOperand(4).getReg(), MRI, *TRI), SrcSize);
2665 Register Src0Reg = MI.getOperand(2).getReg();
2666 Register Src1Reg = MI.getOperand(3).getReg();
2669 unsigned DstSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
2679 unsigned DstSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
2682 unsigned OpSize = MRI.getType(MI.getOperand(2).getReg()).getSizeInBits();
2683 unsigned Op1Bank = getRegBankID(MI.getOperand(2).getReg(), MRI, *TRI);
2684 unsigned Op2Bank = getRegBankID(MI.getOperand(3).getReg(), MRI, *TRI);
2691 Register IdxReg = MI.getOperand(3).getReg();
2698 unsigned DstSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
2699 unsigned SrcSize = MRI.getType(MI.getOperand(2).getReg()).getSizeInBits();
2705 unsigned DstSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
2706 Register SrcReg = MI.getOperand(2).getReg();
2709 Register IdxReg = MI.getOperand(3).getReg();
2722 unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, *TRI);
2738 unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
2752 unsigned DstSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
2754 unsigned M0Bank = getRegBankID(MI.getOperand(2).getReg(), MRI, *TRI,
2780 Register RSrc = MI.getOperand(2).getReg(); // SGPR
2781 Register VIndex = MI.getOperand(3).getReg(); // VGPR
2782 Register Offset = MI.getOperand(4).getReg(); // SGPR/VGPR/imm
2784 unsigned Size0 = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
2807 unsigned Bank = getRegBankID(MI.getOperand(2).getReg(), MRI, *TRI,
2814 unsigned Size = getSizeInBits(MI.getOperand(1).getReg(), MRI, *TRI);
2819 unsigned WaveSize = getSizeInBits(MI.getOperand(1).getReg(), MRI, *TRI);
2833 OpdsMapping[0] = getVGPROpMapping(MI.getOperand(0).getReg(), MRI, *TRI);
2834 OpdsMapping[2] = getSGPROpMapping(MI.getOperand(2).getReg(), MRI, *TRI);
2835 OpdsMapping[3] = getVGPROpMapping(MI.getOperand(3).getReg(), MRI, *TRI);
2836 OpdsMapping[4] = getSGPROpMapping(MI.getOperand(4).getReg(), MRI, *TRI);
2842 OpdsMapping[1] = getVGPROpMapping(MI.getOperand(1).getReg(), MRI, *TRI);
2843 OpdsMapping[2] = getSGPROpMapping(MI.getOperand(2).getReg(), MRI, *TRI);
2844 OpdsMapping[3] = getVGPROpMapping(MI.getOperand(3).getReg(), MRI, *TRI);
2845 OpdsMapping[4] = getSGPROpMapping(MI.getOperand(4).getReg(), MRI, *TRI);
2850 OpdsMapping[0] = getVGPROpMapping(MI.getOperand(0).getReg(), MRI, *TRI);
2851 OpdsMapping[2] = getSGPROpMapping(MI.getOperand(2).getReg(), MRI, *TRI);
2852 OpdsMapping[3] = getVGPROpMapping(MI.getOperand(3).getReg(), MRI, *TRI);
2853 OpdsMapping[4] = getVGPROpMapping(MI.getOperand(4).getReg(), MRI, *TRI);
2854 OpdsMapping[5] = getSGPROpMapping(MI.getOperand(5).getReg(), MRI, *TRI);
2859 OpdsMapping[1] = getVGPROpMapping(MI.getOperand(1).getReg(), MRI, *TRI);
2860 OpdsMapping[2] = getSGPROpMapping(MI.getOperand(2).getReg(), MRI, *TRI);
2861 OpdsMapping[3] = getVGPROpMapping(MI.getOperand(3).getReg(), MRI, *TRI);
2862 OpdsMapping[4] = getVGPROpMapping(MI.getOperand(4).getReg(), MRI, *TRI);
2863 OpdsMapping[5] = getSGPROpMapping(MI.getOperand(5).getReg(), MRI, *TRI);
2867 unsigned Size = getSizeInBits(MI.getOperand(1).getReg(), MRI, *TRI);
2878 unsigned Bank = getRegBankID(MI.getOperand(2).getReg(), MRI, *TRI,
2887 unsigned Bank = getRegBankID(MI.getOperand(1).getReg(), MRI, *TRI,
2907 unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
2908 unsigned Op2Bank = getRegBankID(MI.getOperand(2).getReg(), MRI, *TRI,
2910 unsigned Op3Bank = getRegBankID(MI.getOperand(3).getReg(), MRI, *TRI,
2917 unsigned CondBank = getRegBankID(MI.getOperand(1).getReg(), MRI, *TRI,
2965 unsigned Bank = getRegBankID(MI.getOperand(0).getReg(), MRI, *TRI,
2967 assert(MRI.getType(MI.getOperand(0).getReg()).getSizeInBits() == 1);
lib/Target/AMDGPU/GCNHazardRecognizer.cpp 112 if (MI.getOperand(GDS).getImm())
lib/Target/AMDGPU/GCNNSAReassign.cpp 175 const MachineOperand &Op = MI.getOperand(VAddr0Idx + I);
199 if (Def && Def->isCopy() && Def->getOperand(1).getReg() == PhysReg)
206 if (UseInst->isCopy() && UseInst->getOperand(0).getReg() == PhysReg)
278 const MachineOperand &Op = MI->getOperand(VAddr0Idx + I);
lib/Target/AMDGPU/GCNRegBankReassign.cpp 430 if (Def && Def->isCopy() && Def->getOperand(1).getReg() == PhysReg)
437 if (UseInst->isCopy() && UseInst->getOperand(0).getReg() == PhysReg)
lib/Target/AMDGPU/R600AsmPrinter.cpp 57 const MachineOperand &MO = MI.getOperand(op_idx);
lib/Target/AMDGPU/R600ClauseMergePass.cpp 87 .getOperand(TII->getOperandIdx(MI.getOpcode(), R600::OpName::COUNT))
94 .getOperand(TII->getOperandIdx(MI.getOpcode(), R600::OpName::Enabled))
136 if (LatrCFAlu.getOperand(Mode0Idx).getImm() &&
138 (LatrCFAlu.getOperand(KBank0Idx).getImm() !=
140 LatrCFAlu.getOperand(KBank0LineIdx).getImm() !=
152 if (LatrCFAlu.getOperand(Mode1Idx).getImm() &&
154 (LatrCFAlu.getOperand(KBank1Idx).getImm() !=
156 LatrCFAlu.getOperand(KBank1LineIdx).getImm() !=
161 if (LatrCFAlu.getOperand(Mode0Idx).getImm()) {
163 LatrCFAlu.getOperand(Mode0Idx).getImm());
165 LatrCFAlu.getOperand(KBank0Idx).getImm());
167 .setImm(LatrCFAlu.getOperand(KBank0LineIdx).getImm());
169 if (LatrCFAlu.getOperand(Mode1Idx).getImm()) {
171 LatrCFAlu.getOperand(Mode1Idx).getImm());
173 LatrCFAlu.getOperand(KBank1Idx).getImm());
175 .setImm(LatrCFAlu.getOperand(KBank1LineIdx).getImm());
lib/Target/AMDGPU/R600ExpandSpecialInstrs.cpp 77 uint64_t Val = OldMI->getOperand(OpIdx).getImm();
lib/Target/AMDGPU/R600InstrInfo.cpp 867 Register Reg = MI.getOperand(idx).getReg();
891 return MI.getOperand(3).getImm() == 0 && MI.getOperand(4).getImm() == 0;
891 return MI.getOperand(3).getImm() == 0 && MI.getOperand(4).getImm() == 0;
lib/Target/AMDGPU/R600Packetizer.cpp 63 return TRI.getHWRegChan(MI.getOperand(0).getReg());
lib/Target/AMDGPU/SIFixSGPRCopies.cpp 156 if (!MI.getOperand(i).isReg() ||
157 !Register::isVirtualRegister(MI.getOperand(i).getReg()))
160 if (TRI->hasVectorRegisters(MRI.getRegClass(MI.getOperand(i).getReg())))
170 Register DstReg = Copy.getOperand(0).getReg();
171 Register SrcReg = Copy.getOperand(1).getReg();
339 if (Copy->getOperand(0).getSubReg())
767 unsigned Reg = Instr->getOperand(0).getReg();
771 TRI->isAGPR(*MRI, UseMI->getOperand(0).getReg())) ||
775 UseMI->getOperand(0).getReg().isPhysical() &&
776 !TRI->isSGPRReg(*MRI, UseMI->getOperand(0).getReg())) {
lib/Target/AMDGPU/SIInsertWaitcnts.cpp 464 const MachineOperand &Op = MI->getOperand(OpNo);
508 const MachineOperand &Opnd = MI->getOperand(OpNo);
807 !MI.getOperand(1).isUndef();
lib/Target/AMDGPU/SIInstrInfo.cpp 1367 return MI.getOperand(0).getImm() + 1;
1764 return MI.getOperand(0).getMBB();
2792 if (!RI.isSGPRReg(MRI, MI.getOperand(0).getReg()))
3219 const MachineOperand &Op = MI.getOperand(I);
3235 if (MI.getOperand(i).isFPImm()) {
3245 if (MI.getOperand(i).isImm() || MI.getOperand(i).isGlobal()) {
3245 if (MI.getOperand(i).isImm() || MI.getOperand(i).isGlobal()) {
3263 const MachineOperand &MO = MI.getOperand(i);
3275 if (!MI.getOperand(i).isImm() && !MI.getOperand(i).isFI()) {
3275 if (!MI.getOperand(i).isImm() && !MI.getOperand(i).isFI()) {
3284 if (!MI.getOperand(i).isReg())
3288 Register Reg = MI.getOperand(i).getReg();
3314 const MachineOperand &MO = MI.getOperand(OpIdx);
3345 const MachineOperand &Dst = MI.getOperand(DstIdx);
3370 const MachineOperand &Dst = MI.getOperand(DstIdx);
3377 MI.getOperand(MI.findTiedOperandIdx(DstIdx));
3413 const MachineOperand &Dst = MI.getOperand(DstIdx);
3450 const MachineOperand &MO = MI.getOperand(OpIdx);
3497 const MachineOperand &MO = MI.getOperand(OpIdx);
3516 const MachineOperand &Src0 = MI.getOperand(Src0Idx);
3517 const MachineOperand &Src1 = MI.getOperand(Src1Idx);
3518 const MachineOperand &Src2 = MI.getOperand(Src2Idx);
3529 const MachineOperand &Src0 = MI.getOperand(Src0Idx);
3530 const MachineOperand &Src1 = MI.getOperand(Src1Idx);
3603 const MachineOperand &Src0 = MI.getOperand(Src0Idx);
3605 = MI.getOperand(StaticNumOps + NumImplicitOps - 1);
3739 return MI.getOperand(1).isReg() ||
3740 RI.isAGPR(MRI, MI.getOperand(0).getReg()) ?
3813 Register Reg = MI.getOperand(OpNo).getReg();
3959 MO = &MI.getOperand(OpIdx);
3974 const MachineOperand &Op = MI.getOperand(i);
5808 const MachineOperand &MO = MI.getOperand(Idx);
5997 if (isLiteralConstantLike(MI.getOperand(Src0Idx), Desc.OpInfo[Src0Idx]))
6004 if (isLiteralConstantLike(MI.getOperand(Src1Idx), Desc.OpInfo[Src1Idx]))
6011 if (isLiteralConstantLike(MI.getOperand(Src2Idx), Desc.OpInfo[Src2Idx]))
6038 const char *AsmStr = MI.getOperand(0).getSymbolName();
lib/Target/AMDGPU/SIInstrInfo.h 672 unsigned Dest = MI.getOperand(0).getReg();
719 const MachineOperand &MO = MI.getOperand(OpIdx);
751 const MachineOperand &MO = MI.getOperand(OpIdx);
818 const MachineOperand &MO = MI.getOperand(OpNo);
918 return MI.getOperand(Idx).getImm();
lib/Target/AMDGPU/SILoadStoreOptimizer.cpp 139 const MachineOperand &AddrRegNext = MI.getOperand(AddrIdx[i]);
lib/Target/AMDGPU/SILowerControlFlow.cpp 149 Register SaveExecReg = MI.getOperand(0).getReg();
lib/Target/AMDGPU/SILowerI1Copies.cpp 744 Reg = MI->getOperand(1).getReg();
754 if (!MI->getOperand(1).isImm())
757 int64_t Imm = MI->getOperand(1).getImm();
lib/Target/AMDGPU/SIOptimizeExecMasking.cpp 66 const MachineOperand &Src = MI.getOperand(1);
69 return MI.getOperand(0).getReg();
82 const MachineOperand &Dst = MI.getOperand(0);
85 MI.getOperand(1).isReg())
86 return MI.getOperand(1).getReg();
109 const MachineOperand &Src1 = MI.getOperand(1);
111 return MI.getOperand(0).getReg();
112 const MachineOperand &Src2 = MI.getOperand(2);
114 return MI.getOperand(0).getReg();
125 const MachineOperand &Src1 = MI.getOperand(1);
127 return MI.getOperand(0).getReg();
128 const MachineOperand &Src2 = MI.getOperand(2);
130 return MI.getOperand(0).getReg();
lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp 99 if (MI.isCopy() && MI.getOperand(1).getReg() == Exec) {
lib/Target/AMDGPU/SIPeepholeSDWA.cpp 538 const MachineOperand &Copied = DefInst->getOperand(1);
lib/Target/AMDGPU/SIRegisterInfo.cpp 318 return MI->getOperand(OffIdx).getImm();
lib/Target/AMDGPU/SIShrinkInstructions.cpp 176 const MachineOperand &MO = MI.getOperand(i);
lib/Target/AMDGPU/SIWholeQuadMode.cpp 543 const MachineOperand &Op = MI.getOperand(0);
lib/Target/ARC/ARCInstrInfo.cpp 72 if ((MI.getOperand(1).isFI()) && // is a stack slot
73 (MI.getOperand(2).isImm()) && // the imm is zero
74 (isZeroImm(MI.getOperand(2)))) {
75 FrameIndex = MI.getOperand(1).getIndex();
76 return MI.getOperand(0).getReg();
91 if ((MI.getOperand(1).isFI()) && // is a stack slot
92 (MI.getOperand(2).isImm()) && // the imm is zero
93 (isZeroImm(MI.getOperand(2)))) {
94 FrameIndex = MI.getOperand(1).getIndex();
95 return MI.getOperand(0).getReg();
406 const char *AsmStr = MI.getOperand(0).getSymbolName();
438 if (!MI.getOperand(BasePos).isReg() || !MI.getOperand(OffsetPos).isImm())
438 if (!MI.getOperand(BasePos).isReg() || !MI.getOperand(OffsetPos).isImm())
lib/Target/ARC/ARCMCInstLower.cpp 108 const MachineOperand &MO = MI->getOperand(i);
lib/Target/ARC/ARCOptAddrMode.cpp 129 assert(MI.getOperand(2).isImm() && "Expected immediate operand");
130 Amount = Sign * MI.getOperand(2).getImm();
174 const MachineOperand &MO = MI.getOperand(OffPos);
183 Register R = Add->getOperand(0).getReg();
lib/Target/ARM/ARMAsmPrinter.cpp 201 const MachineOperand &MO = MI->getOperand(OpNum);
277 if (MI->getOperand(OpNum).isReg()) {
278 Register Reg = MI->getOperand(OpNum).getReg();
292 if (!MI->getOperand(OpNum).isImm())
294 O << ~(MI->getOperand(OpNum).getImm());
297 if (!MI->getOperand(OpNum).isImm())
299 O << (MI->getOperand(OpNum).getImm() & 0xffff);
302 if (!MI->getOperand(OpNum).isReg())
304 const MachineOperand &MO = MI->getOperand(OpNum);
323 while (MI->getOperand(RegOps).isReg()) {
325 << ARMInstPrinter::getRegisterName(MI->getOperand(RegOps).getReg());
337 const MachineOperand &FlagsOP = MI->getOperand(OpNum - 1);
348 unsigned OpFlags = MI->getOperand(OpNum).getImm();
351 Flags = MI->getOperand(OpNum).getImm();
377 const MachineOperand &MO = MI->getOperand(OpNum);
391 const MachineOperand &MO = MI->getOperand(RegOp);
401 if (!MI->getOperand(OpNum).isReg())
403 Register Reg = MI->getOperand(OpNum).getReg();
417 const MachineOperand &MO = MI->getOperand(OpNum);
447 if (!MI->getOperand(OpNum).isReg())
449 O << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg());
454 const MachineOperand &MO = MI->getOperand(OpNum);
938 const MachineOperand &MO1 = MI->getOperand(1);
984 const MachineOperand &MO1 = MI->getOperand(1);
1014 const MachineOperand &MO1 = MI->getOperand(1);
1046 MCSymbol *TBInstPC = GetCPISymbol(MI->getOperand(0).getImm());
1087 SrcReg = MI->getOperand(1).getReg();
1088 DstReg = MI->getOperand(0).getReg();
1120 const MachineOperand &MO = MI->getOperand(i);
1148 assert(MI->getOperand(2).getReg() == ARM::SP &&
1173 Offset = -MI->getOperand(2).getImm();
1177 Offset = MI->getOperand(2).getImm();
1180 Offset = MI->getOperand(2).getImm()*4;
1184 Offset = -MI->getOperand(2).getImm()*4;
1189 unsigned CPI = MI->getOperand(1).getIndex();
1274 MCSymbol *CPISymbol = GetCPISymbol(MI->getOperand(1).getIndex());
1279 .addReg(MI->getOperand(0).getReg())
1282 .addImm(MI->getOperand(2).getImm())
1283 .addReg(MI->getOperand(3).getReg()));
1290 GetARMJTIPICJumpTableLabel(MI->getOperand(1).getIndex());
1295 .addReg(MI->getOperand(0).getReg())
1298 .addImm(MI->getOperand(2).getImm())
1299 .addReg(MI->getOperand(3).getReg()));
1316 .addReg(MI->getOperand(0).getReg()));
1329 Register TReg = MI->getOperand(0).getReg();
1362 .addReg(MI->getOperand(0).getReg())
1380 const MachineOperand &Op = MI->getOperand(0);
1396 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
1398 unsigned TF = MI->getOperand(1).getTargetFlags();
1399 const GlobalValue *GV = MI->getOperand(1).getGlobal();
1405 MI->getOperand(2).getImm(), OutContext);
1428 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
1429 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(1).getReg()));
1431 unsigned TF = MI->getOperand(2).getTargetFlags();
1432 const GlobalValue *GV = MI->getOperand(2).getGlobal();
1438 MI->getOperand(3).getImm(), OutContext);
1464 MI->getOperand(0).getIndex(), OutContext),
1468 if (MI->getOperand(1).isReg()) {
1470 MCInst.addReg(MI->getOperand(1).getReg());
1474 if (MI->getOperand(1).isMBB())
1476 MI->getOperand(1).getMBB()->getSymbol(), OutContext);
1477 else if (MI->getOperand(1).isGlobal()) {
1478 const GlobalValue *GV = MI->getOperand(1).getGlobal();
1480 GetARMGVSymbol(GV, MI->getOperand(1).getTargetFlags()), OutContext);
1481 } else if (MI->getOperand(1).isSymbol()) {
1483 GetExternalSymbolSymbol(MI->getOperand(1).getSymbolName()),
1494 MI->getOperand(2).getIndex(), OutContext),
1497 MCInst.addImm(MI->getOperand(3).getImm());
1499 MCInst.addImm(MI->getOperand(2).getImm())
1500 .addReg(MI->getOperand(3).getReg());
1512 MI->getOperand(0).getIndex(), OutContext));
1524 MI->getOperand(2).getImm(), OutContext));
1528 .addReg(MI->getOperand(0).getReg())
1529 .addReg(MI->getOperand(0).getReg())
1545 MI->getOperand(2).getImm(), OutContext));
1549 .addReg(MI->getOperand(0).getReg())
1551 .addReg(MI->getOperand(1).getReg())
1553 .addImm(MI->getOperand(3).getImm())
1554 .addReg(MI->getOperand(4).getReg())
1576 MI->getOperand(2).getImm(), OutContext));
1593 .addReg(MI->getOperand(0).getReg())
1595 .addReg(MI->getOperand(1).getReg())
1598 .addImm(MI->getOperand(3).getImm())
1599 .addReg(MI->getOperand(4).getReg()));
1612 unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
1613 unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
1643 .addReg(MI->getOperand(0).getReg())
1653 OutStreamer->EmitLabel(GetCPISymbol(MI->getOperand(3).getImm()));
1655 .addReg(MI->getOperand(0).getReg())
1656 .addReg(MI->getOperand(1).getReg())
1666 Register Base = MI->getOperand(0).getReg();
1667 Register Idx = MI->getOperand(1).getReg();
1668 assert(MI->getOperand(1).isKill() && "We need the index register as scratch!");
1737 OutStreamer->EmitLabel(GetCPISymbol(MI->getOperand(3).getImm()));
1755 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
1770 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
1771 TmpInst.addOperand(MCOperand::createImm(MI->getOperand(2).getImm()));
1783 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
1784 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(1).getReg()));
1785 TmpInst.addOperand(MCOperand::createImm(MI->getOperand(2).getImm()));
1796 .addReg(MI->getOperand(0).getReg())
1797 .addReg(MI->getOperand(1).getReg())
1806 OutStreamer->EmitZeros(MI->getOperand(1).getImm());
1847 Register SrcReg = MI->getOperand(0).getReg();
1848 Register ValReg = MI->getOperand(1).getReg();
1913 Register SrcReg = MI->getOperand(0).getReg();
1914 Register ValReg = MI->getOperand(1).getReg();
1970 Register SrcReg = MI->getOperand(0).getReg();
1971 Register ScratchReg = MI->getOperand(1).getReg();
2030 Register SrcReg = MI->getOperand(0).getReg();
2031 Register ScratchReg = MI->getOperand(1).getReg();
2098 Register SrcReg = MI->getOperand(0).getReg();
lib/Target/ARM/ARMBaseInstrInfo.cpp 488 if (PIdx != -1 && I->getOperand(PIdx).getImm() != ARMCC::AL)
495 return PIdx != -1 && MI.getOperand(PIdx).getImm() != ARMCC::AL;
569 const MachineOperand &Offset = MI.getOperand(Op + 1);
577 const MachineOperand &Offset = MI.getOperand(Op + 1);
578 const MachineOperand &Opc = MI.getOperand(Op + 2);
589 const MachineOperand &Opc = MI.getOperand(Op + 2);
597 const MachineOperand &Opc = MI.getOperand(Op + 2);
611 unsigned OffImm = MI.getOperand(Op + 2).getImm();
618 unsigned OffImm = MI.getOperand(Op + 2).getImm();
684 const MachineOperand &MO = MI->getOperand(i);
730 return MI.getOperand(2).getImm();
745 return MI.getOperand(1).getImm();
749 unsigned Size = getInlineAsmLength(MI.getOperand(0).getSymbolName(), *MAI);
1008 MI.getOperand(1).getReg() != MI.getOperand(2).getReg()))
1008 MI.getOperand(1).getReg() != MI.getOperand(2).getReg()))
1010 Dest = &MI.getOperand(0);
1011 Src = &MI.getOperand(1);
1211 if (MI.getOperand(1).isFI() && MI.getOperand(2).isReg() &&
1211 if (MI.getOperand(1).isFI() && MI.getOperand(2).isReg() &&
1212 MI.getOperand(3).isImm() && MI.getOperand(2).getReg() == 0 &&
1212 MI.getOperand(3).isImm() && MI.getOperand(2).getReg() == 0 &&
1213 MI.getOperand(3).getImm() == 0) {
1214 FrameIndex = MI.getOperand(1).getIndex();
1215 return MI.getOperand(0).getReg();
1223 if (MI.getOperand(1).isFI() && MI.getOperand(2).isImm() &&
1223 if (MI.getOperand(1).isFI() && MI.getOperand(2).isImm() &&
1224 MI.getOperand(2).getImm() == 0) {
1225 FrameIndex = MI.getOperand(1).getIndex();
1226 return MI.getOperand(0).getReg();
1230 if (MI.getOperand(0).isFI() && MI.getOperand(1).isImm() &&
1230 if (MI.getOperand(0).isFI() && MI.getOperand(1).isImm() &&
1231 MI.getOperand(1).getImm() == 0) {
1232 FrameIndex = MI.getOperand(0).getIndex();
1239 if (MI.getOperand(0).isFI() && MI.getOperand(2).getSubReg() == 0) {
1239 if (MI.getOperand(0).isFI() && MI.getOperand(2).getSubReg() == 0) {
1240 FrameIndex = MI.getOperand(0).getIndex();
1241 return MI.getOperand(2).getReg();
1245 if (MI.getOperand(1).isFI() && MI.getOperand(0).getSubReg() == 0) {
1245 if (MI.getOperand(1).isFI() && MI.getOperand(0).getSubReg() == 0) {
1246 FrameIndex = MI.getOperand(1).getIndex();
1247 return MI.getOperand(0).getReg();
1448 if (MI.getOperand(1).isFI() && MI.getOperand(2).isReg() &&
1448 if (MI.getOperand(1).isFI() && MI.getOperand(2).isReg() &&
1449 MI.getOperand(3).isImm() && MI.getOperand(2).getReg() == 0 &&
1449 MI.getOperand(3).isImm() && MI.getOperand(2).getReg() == 0 &&
1450 MI.getOperand(3).getImm() == 0) {
1451 FrameIndex = MI.getOperand(1).getIndex();
1452 return MI.getOperand(0).getReg();
1460 if (MI.getOperand(1).isFI() && MI.getOperand(2).isImm() &&
1460 if (MI.getOperand(1).isFI() && MI.getOperand(2).isImm() &&
1461 MI.getOperand(2).getImm() == 0) {
1462 FrameIndex = MI.getOperand(1).getIndex();
1463 return MI.getOperand(0).getReg();
1467 if (MI.getOperand(0).isFI() && MI.getOperand(1).isImm() &&
1467 if (MI.getOperand(0).isFI() && MI.getOperand(1).isImm() &&
1468 MI.getOperand(1).getImm() == 0) {
1469 FrameIndex = MI.getOperand(0).getIndex();
1482 if (MI.getOperand(1).isFI() && MI.getOperand(0).getSubReg() == 0) {
1482 if (MI.getOperand(1).isFI() && MI.getOperand(0).getSubReg() == 0) {
1483 FrameIndex = MI.getOperand(1).getIndex();
1484 return MI.getOperand(0).getReg();
1488 if (MI.getOperand(1).isFI() && MI.getOperand(0).getSubReg() == 0) {
1488 if (MI.getOperand(1).isFI() && MI.getOperand(0).getSubReg() == 0) {
1489 FrameIndex = MI.getOperand(1).getIndex();
1490 return MI.getOperand(0).getReg();
1701 MI->substituteRegister(Orig.getOperand(0).getReg(), DestReg, SubIdx, TRI);
1708 unsigned CPI = Orig.getOperand(1).getIndex();
1763 const MachineOperand &MO0 = MI0.getOperand(1);
1764 const MachineOperand &MO1 = MI1.getOperand(1);
1801 Register Addr0 = MI0.getOperand(1).getReg();
1802 Register Addr1 = MI1.getOperand(1).getReg();
1819 const MachineOperand &MO0 = MI0.getOperand(i);
1820 const MachineOperand &MO1 = MI1.getOperand(i);
2133 PredReg = MI.getOperand(PIdx+1).getReg();
2134 return (ARMCC::CondCodes)MI.getOperand(PIdx).getImm();
2226 Cond.push_back(MI.getOperand(3));
2227 Cond.push_back(MI.getOperand(4));
2685 SrcReg = MI.getOperand(0).getReg();
2688 CmpValue = MI.getOperand(1).getImm();
2693 SrcReg = MI.getOperand(0).getReg();
2694 SrcReg2 = MI.getOperand(1).getReg();
2700 SrcReg = MI.getOperand(0).getReg();
2702 CmpMask = MI.getOperand(1).getImm();
2773 ((OI->getOperand(1).getReg() == SrcReg &&
2774 OI->getOperand(2).getReg() == SrcReg2) ||
2775 (OI->getOperand(1).getReg() == SrcReg2 &&
2776 OI->getOperand(2).getReg() == SrcReg))) {
2782 ((OI->getOperand(2).getReg() == SrcReg &&
2783 OI->getOperand(3).getReg() == SrcReg2) ||
2784 (OI->getOperand(2).getReg() == SrcReg2 &&
2785 OI->getOperand(3).getReg() == SrcReg))) {
2792 OI->getOperand(1).getReg() == SrcReg &&
2793 OI->getOperand(2).getImm() == ImmValue) {
2800 OI->getOperand(2).getReg() == SrcReg &&
2801 OI->getOperand(3).getImm() == ImmValue) {
2809 OI->getOperand(0).isReg() && OI->getOperand(1).isReg() &&
2809 OI->getOperand(0).isReg() && OI->getOperand(1).isReg() &&
2810 OI->getOperand(0).getReg() == SrcReg &&
2811 OI->getOperand(1).getReg() == SrcReg2) {
2819 OI->getOperand(0).getReg() == SrcReg &&
2820 OI->getOperand(2).getReg() == SrcReg2) {
3058 const MachineOperand &MO = Instr.getOperand(IO);
3075 CC = (ARMCC::CondCodes)Instr.getOperand(IO - 1).getImm();
3346 unsigned ShOpVal = MI.getOperand(3).getImm();
3359 if (!MI.getOperand(2).getReg())
3362 unsigned ShOpVal = MI.getOperand(3).getImm();
3375 return (ARM_AM::getAM3Op(MI.getOperand(3).getImm()) == ARM_AM::sub) ? 3 : 2;
3379 Register Rt = MI.getOperand(0).getReg();
3380 Register Rm = MI.getOperand(3).getReg();
3386 Register Rt = MI.getOperand(0).getReg();
3387 Register Rm = MI.getOperand(3).getReg();
3390 unsigned ShOpVal = MI.getOperand(4).getImm();
3403 unsigned ShOpVal = MI.getOperand(4).getImm();
3416 Register Rt = MI.getOperand(0).getReg();
3417 Register Rm = MI.getOperand(3).getReg();
3422 return (ARM_AM::getAM3Op(MI.getOperand(4).getImm()) == ARM_AM::sub) ? 3 : 2;
3428 Register Rt = MI.getOperand(0).getReg();
3429 Register Rm = MI.getOperand(3).getReg();
3448 Register Rm = MI.getOperand(3).getReg();
3451 Register Rt = MI.getOperand(0).getReg();
3454 unsigned ShOpVal = MI.getOperand(4).getImm();
3466 Register Rt = MI.getOperand(0).getReg();
3467 Register Rn = MI.getOperand(2).getReg();
3468 Register Rm = MI.getOperand(3).getReg();
3470 return (ARM_AM::getAM3Op(MI.getOperand(4).getImm()) == ARM_AM::sub) ? 4
3476 Register Rm = MI.getOperand(3).getReg();
3478 return (ARM_AM::getAM3Op(MI.getOperand(4).getImm()) == ARM_AM::sub) ? 4
3492 Register Rt = MI.getOperand(0).getReg();
3493 Register Rn = MI.getOperand(3).getReg();
3494 Register Rm = MI.getOperand(4).getReg();
3496 return (ARM_AM::getAM3Op(MI.getOperand(5).getImm()) == ARM_AM::sub) ? 5
3502 Register Rt = MI.getOperand(0).getReg();
3503 Register Rn = MI.getOperand(3).getReg();
3508 Register Rm = MI.getOperand(4).getReg();
3510 return (ARM_AM::getAM3Op(MI.getOperand(5).getImm()) == ARM_AM::sub) ? 5
3539 Register Rt = MI.getOperand(0).getReg();
3540 Register Rn = MI.getOperand(2).getReg();
3789 Register BaseReg = MI.getOperand(0).getReg();
3791 const auto &Op = MI.getOperand(i);
4086 unsigned ShOpVal = DefMI.getOperand(3).getImm();
4098 unsigned ShAmt = DefMI.getOperand(3).getImm();
4111 unsigned ShOpVal = DefMI.getOperand(3).getImm();
4129 unsigned ShAmt = DefMI.getOperand(3).getImm();
4262 const MachineOperand &DefMO = DefMI.getOperand(DefIdx);
4320 if (DefMO.isImplicit() || UseMI.getOperand(UseIdx).isImplicit())
4739 if (!ARM::hGPRRegClass.contains(MI.getOperand(0).getReg()) &&
4740 !ARM::hGPRRegClass.contains(MI.getOperand(1).getReg())) {
4749 if (MI.getOperand(i).isImplicit() ||
4750 !MI.getOperand(i).isReg())
4752 Register Reg = MI.getOperand(i).getReg();
5145 const MachineOperand &MO = MI.getOperand(OpNum);
5174 if (UseOp != -1 && MI.getOperand(UseOp).readsReg())
5238 unsigned ShOpVal = MI->getOperand(3).getImm();
5262 const MachineOperand *MOReg = &MI.getOperand(1);
5267 MOReg = &MI.getOperand(2);
5288 const MachineOperand &MOReg = MI.getOperand(2);
5308 const MachineOperand &MOBaseReg = MI.getOperand(1);
5309 const MachineOperand &MOInsertedReg = MI.getOperand(2);
5312 const MachineOperand &MOIndex = MI.getOperand(3);
lib/Target/ARM/ARMBaseInstrInfo.h 152 return PIdx != -1 ? (ARMCC::CondCodes)MI.getOperand(PIdx).getImm()
456 return MI.getOperand(3).getReg();
lib/Target/ARM/ARMBaseRegisterInfo.cpp 508 InstrOffs = MI->getOperand(Idx+1).getImm();
513 const MachineOperand &OffOp = MI->getOperand(Idx+1);
522 InstrOffs = ARM_AM::getAM2Offset(MI->getOperand(ImmIdx).getImm());
523 if (ARM_AM::getAM2Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
528 InstrOffs = ARM_AM::getAM3Offset(MI->getOperand(ImmIdx).getImm());
529 if (ARM_AM::getAM3Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
534 InstrOffs = MI->getOperand(ImmIdx).getImm();
688 for (; !MI->getOperand(i).isFI(); ++i)
lib/Target/ARM/ARMConstantIslandPass.cpp 1120 if (CPEMI->getOperand(1).isCPI())
1121 return CPEMI->getOperand(1).getIndex();
1123 return JumpTableEntryIndices[CPEMI->getOperand(1).getIndex()];
lib/Target/ARM/ARMFeatures.h 78 return Instr->getOperand(2).getReg() != ARM::PC;
83 return Instr->getOperand(0).getReg() != ARM::PC;
85 return Instr->getOperand(0).getReg() != ARM::PC &&
86 Instr->getOperand(2).getReg() != ARM::PC;
89 return Instr->getOperand(0).getReg() != ARM::PC &&
90 Instr->getOperand(1).getReg() != ARM::PC;
lib/Target/ARM/ARMInstructionSelector.cpp 817 APFloat FPImmValue = OldInst.getOperand(1).getFPImm()->getValueAPF();
829 APFloat FPImmValue = OldInst.getOperand(1).getFPImm()->getValueAPF();
lib/Target/ARM/ARMLoadStoreOptimizer.cpp 220 unsigned OffField = MI.getOperand(NumOperands - 3).getImm();
245 return MI.getOperand(1);
249 return MI.getOperand(0);
1198 if (MI.getOperand(0).getReg() != Reg ||
1199 MI.getOperand(1).getReg() != Reg ||
1206 return MI.getOperand(2).getImm() * Scale;
1586 if (!MI.getOperand(1).isReg())
1610 if (MI.getOperand(0).isReg() && MI.getOperand(0).isUndef())
1610 if (MI.getOperand(0).isReg() && MI.getOperand(0).isUndef())
1614 if (MI.getOperand(1).isUndef())
lib/Target/ARM/ARMRegisterBankInfo.cpp 234 LLT Ty = MRI.getType(MI.getOperand(0).getReg());
269 LLT LargeTy = MRI.getType(MI.getOperand(1).getReg());
279 LLT Ty = MRI.getType(MI.getOperand(0).getReg());
292 LLT Ty = MRI.getType(MI.getOperand(0).getReg());
299 LLT Ty = MRI.getType(MI.getOperand(0).getReg());
313 LLT ToTy = MRI.getType(MI.getOperand(0).getReg());
314 LLT FromTy = MRI.getType(MI.getOperand(1).getReg());
322 LLT ToTy = MRI.getType(MI.getOperand(0).getReg());
323 LLT FromTy = MRI.getType(MI.getOperand(1).getReg());
332 LLT ToTy = MRI.getType(MI.getOperand(0).getReg());
333 LLT FromTy = MRI.getType(MI.getOperand(1).getReg());
346 LLT ToTy = MRI.getType(MI.getOperand(0).getReg());
347 LLT FromTy = MRI.getType(MI.getOperand(1).getReg());
359 LLT Ty = MRI.getType(MI.getOperand(0).getReg());
373 LLT Ty = MRI.getType(MI.getOperand(0).getReg());
375 LLT Ty2 = MRI.getType(MI.getOperand(1).getReg());
387 LLT Ty2 = MRI.getType(MI.getOperand(2).getReg());
397 LLT Ty = MRI.getType(MI.getOperand(0).getReg());
399 LLT Ty1 = MRI.getType(MI.getOperand(2).getReg());
400 LLT Ty2 = MRI.getType(MI.getOperand(3).getReg());
419 LLT Ty = MRI.getType(MI.getOperand(0).getReg());
420 LLT Ty1 = MRI.getType(MI.getOperand(1).getReg());
421 LLT Ty2 = MRI.getType(MI.getOperand(2).getReg());
434 LLT Ty = MRI.getType(MI.getOperand(0).getReg());
435 LLT Ty1 = MRI.getType(MI.getOperand(1).getReg());
436 LLT Ty2 = MRI.getType(MI.getOperand(2).getReg());
455 const MachineOperand &MaybeReg = MI.getOperand(0);
lib/Target/ARM/Thumb2InstrInfo.cpp 726 PredReg = MI.getOperand(PIdx+1).getReg();
727 return (ARMVCC::VPTCodes)MI.getOperand(PIdx).getImm();
lib/Target/AVR/AVRAsmPrinter.cpp 62 const MachineOperand &MO = MI->getOperand(OpNo);
96 const MachineOperand &RegOp = MI->getOperand(OpNum);
104 unsigned OpFlags = MI->getOperand(OpNum - 1).getImm();
118 Reg = MI->getOperand(OpNum + RegIdx).getReg();
143 const MachineOperand &MO = MI->getOperand(OpNum);
151 if (MI->getOperand(OpNum).getReg() == AVR::R31R30) {
154 assert(MI->getOperand(OpNum).getReg() == AVR::R29R28 &&
161 unsigned OpFlags = MI->getOperand(OpNum - 1).getImm();
165 O << '+' << MI->getOperand(OpNum + 1).getImm();
lib/Target/AVR/AVRInstrInfo.cpp 87 if (MI.getOperand(1).isFI() && MI.getOperand(2).isImm() &&
87 if (MI.getOperand(1).isFI() && MI.getOperand(2).isImm() &&
88 MI.getOperand(2).getImm() == 0) {
89 FrameIndex = MI.getOperand(1).getIndex();
90 return MI.getOperand(0).getReg();
106 if (MI.getOperand(0).isFI() && MI.getOperand(1).isImm() &&
106 if (MI.getOperand(0).isFI() && MI.getOperand(1).isImm() &&
107 MI.getOperand(1).getImm() == 0) {
108 FrameIndex = MI.getOperand(0).getIndex();
109 return MI.getOperand(2).getReg();
497 return TII.getInlineAsmLength(MI.getOperand(0).getSymbolName(),
520 return MI.getOperand(0).getMBB();
523 return MI.getOperand(1).getMBB();
lib/Target/BPF/BPFAsmPrinter.cpp 74 const MachineOperand &MO = MI->getOperand(OpNum);
123 const MachineOperand &BaseMO = MI->getOperand(OpNum);
124 const MachineOperand &OffsetMO = MI->getOperand(OpNum + 1);
lib/Target/BPF/BPFMCInstLower.cpp 51 const MachineOperand &MO = MI->getOperand(i);
lib/Target/BPF/BTFDebug.cpp 988 const MachineOperand &MO = MI->getOperand(1);
1013 for (; MI->getOperand(NumDefs).isReg() && MI->getOperand(NumDefs).isDef();
1013 for (; MI->getOperand(NumDefs).isReg() && MI->getOperand(NumDefs).isDef();
1018 const char *AsmStr = MI->getOperand(NumDefs).getSymbolName();
1125 const MachineOperand &MO = MI->getOperand(1);
1133 OutMI.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
lib/Target/Hexagon/BitTracker.cpp 726 RegisterRef RD = MI.getOperand(0);
728 RegisterRef RS = MI.getOperand(1);
729 unsigned SS = MI.getOperand(2).getImm();
730 RegisterRef RT = MI.getOperand(3);
731 unsigned ST = MI.getOperand(4).getImm();
745 RegisterRef RD = MI.getOperand(0);
746 RegisterRef RS = MI.getOperand(1);
803 const MachineOperand &MD = PI.getOperand(0);
815 const MachineBasicBlock *PB = PI.getOperand(i + 1).getMBB();
826 RegisterRef RU = PI.getOperand(i);
855 const MachineOperand &MO = MI.getOperand(i);
lib/Target/Hexagon/HexagonAsmPrinter.cpp 77 const MachineOperand &MO = MI->getOperand(OpNo);
128 const MachineOperand &MO = MI->getOperand(OpNo);
145 if (MI->getOperand(OpNo).isImm())
162 const MachineOperand &Base = MI->getOperand(OpNo);
163 const MachineOperand &Offset = MI->getOperand(OpNo+1);
216 const MachineOperand &MO = MI.getOperand(1);
lib/Target/Hexagon/HexagonBitSimplify.cpp 435 unsigned Sub1 = I.getOperand(2).getImm(), Sub2 = I.getOperand(4).getImm();
435 unsigned Sub1 = I.getOperand(2).getImm(), Sub2 = I.getOperand(4).getImm();
436 auto &DstRC = *MRI.getRegClass(I.getOperand(0).getReg());
443 SL = I.getOperand(1);
444 SH = I.getOperand(3);
448 SH = I.getOperand(1);
449 SL = I.getOperand(3);
1126 assert(MI.getOperand(ImN).isImm());
1127 unsigned S = MI.getOperand(ImN).getImm();
1191 assert(MI.getOperand(ImN).isImm());
1192 unsigned S = MI.getOperand(ImN).getImm();
1258 assert(MI.getOperand(OpN).isReg());
1259 BitTracker::RegisterRef RR = MI.getOperand(OpN);
3011 const MachineOperand &Op = MI->getOperand(i);
3088 const MachineOperand &Op = SI->getOperand(j);
3278 if (!DefPrehR->getOperand(1).isImm())
3280 if (DefPrehR->getOperand(1).getImm() != 0)
lib/Target/Hexagon/HexagonBitTracker.cpp 168 const MachineOperand &MO = MI.getOperand(i);
268 const MachineOperand &Op = MI.getOperand(N);
325 return rr0(eIMM(im(1), W0), Outputs);
331 int FI = op(1).getIndex();
332 int Off = op(2).getImm();
381 return rr0(eADD(rc(1), eIMM(im(2), W0)), Outputs);
383 RegisterCell RC = eADD(eIMM(im(1), W0), eASL(rc(2), im(3)));
383 RegisterCell RC = eADD(eIMM(im(1), W0), eASL(rc(2), im(3)));
387 RegisterCell RC = eADD(eIMM(im(1), W0), eLSR(rc(2), im(3)));
387 RegisterCell RC = eADD(eIMM(im(1), W0), eLSR(rc(2), im(3)));
391 RegisterCell RC = eADD(rc(1), eADD(rc(2), eIMM(im(3), W0)));
395 RegisterCell M = eMLS(rc(2), eIMM(im(3), W0));
396 RegisterCell RC = eADD(eIMM(im(1), W0), lo(M, W0));
401 RegisterCell RC = eADD(eIMM(im(1), W0), lo(M, W0));
405 RegisterCell M = eMLS(eIMM(im(2), W0), rc(3));
410 RegisterCell M = eMLS(rc(2), eIMM(im(3), W0));
420 RegisterCell RC = eADD(rc(1), eSUB(eIMM(im(2), W0), rc(3)));
424 RegisterCell RC = eADD(rc(1), eADD(rc(2), eIMM(im(3), W0)));
436 RegisterCell RC = eADD(rc(1), eASL(rc(2), im(3)));
442 return rr0(eADD(RPC, eIMM(im(2), W0)), Outputs);
448 return rr0(eSUB(eIMM(im(1), W0), rc(2)), Outputs);
450 RegisterCell RC = eSUB(eIMM(im(1), W0), eASL(rc(2), im(3)));
450 RegisterCell RC = eSUB(eIMM(im(1), W0), eASL(rc(2), im(3)));
454 RegisterCell RC = eSUB(eIMM(im(1), W0), eLSR(rc(2), im(3)));
454 RegisterCell RC = eSUB(eIMM(im(1), W0), eLSR(rc(2), im(3)));
458 RegisterCell RC = eSUB(rc(1), eADD(rc(2), eIMM(im(3), W0)));
484 RegisterCell M = eMLS(rc(2), eIMM(im(3), W0));
489 RegisterCell M = eMLS(rc(2), eIMM(im(3), W0));
499 RegisterCell M = eMLS(rc(1), eIMM(im(2), W0));
503 RegisterCell M = eMLS(rc(1), eIMM(-im(2), W0));
507 RegisterCell M = eMLS(rc(1), eIMM(im(2), W0));
525 return rr0(eAND(rc(1), eIMM(im(2), W0)), Outputs);
533 RegisterCell RC = eAND(eIMM(im(1), W0), eASL(rc(2), im(3)));
533 RegisterCell RC = eAND(eIMM(im(1), W0), eASL(rc(2), im(3)));
537 RegisterCell RC = eAND(eIMM(im(1), W0), eLSR(rc(2), im(3)));
537 RegisterCell RC = eAND(eIMM(im(1), W0), eLSR(rc(2), im(3)));
549 return rr0(eORL(rc(1), eIMM(im(2), W0)), Outputs);
557 RegisterCell RC = eORL(eIMM(im(1), W0), eASL(rc(2), im(3)));
557 RegisterCell RC = eORL(eIMM(im(1), W0), eASL(rc(2), im(3)));
561 RegisterCell RC = eORL(eIMM(im(1), W0), eLSR(rc(2), im(3)));
561 RegisterCell RC = eORL(eIMM(im(1), W0), eLSR(rc(2), im(3)));
570 RegisterCell RC = eORL(rc(1), eAND(rc(2), eIMM(im(3), W0)));
574 RegisterCell RC = eORL(rc(1), eORL(rc(2), eIMM(im(3), W0)));
598 return rr0(eASL(rc(1), im(2)), Outputs);
603 return rr0(eADD(rc(1), eASL(rc(2), im(3))), Outputs);
606 return rr0(eSUB(rc(1), eASL(rc(2), im(3))), Outputs);
609 return rr0(eAND(rc(1), eASL(rc(2), im(3))), Outputs);
612 return rr0(eORL(rc(1), eASL(rc(2), im(3))), Outputs);
615 return rr0(eXOR(rc(1), eASL(rc(2), im(3))), Outputs);
623 return rr0(eASR(rc(1), im(2)), Outputs);
628 return rr0(eADD(rc(1), eASR(rc(2), im(3))), Outputs);
631 return rr0(eSUB(rc(1), eASR(rc(2), im(3))), Outputs);
634 return rr0(eAND(rc(1), eASR(rc(2), im(3))), Outputs);
637 return rr0(eORL(rc(1), eASR(rc(2), im(3))), Outputs);
643 RegisterCell RC = eASR(eADD(eASR(XC, im(2)), eIMM(1, 2*W0)), 1);
647 int64_t S = im(2);
663 return rr0(eLSR(rc(1), im(2)), Outputs);
666 return rr0(eADD(rc(1), eLSR(rc(2), im(3))), Outputs);
669 return rr0(eSUB(rc(1), eLSR(rc(2), im(3))), Outputs);
672 return rr0(eAND(rc(1), eLSR(rc(2), im(3))), Outputs);
675 return rr0(eORL(rc(1), eLSR(rc(2), im(3))), Outputs);
678 return rr0(eXOR(rc(1), eLSR(rc(2), im(3))), Outputs);
682 RC[im(2)] = BT::BitValue::Zero;
687 RC[im(2)] = BT::BitValue::One;
692 uint16_t BX = im(2);
701 uint16_t BX = im(2);
714 uint16_t Wd = im(2), Of = im(3);
714 uint16_t Wd = im(2), Of = im(3);
730 uint16_t Wd = im(3), Of = im(4);
730 uint16_t Wd = im(3), Of = im(4);
950 BT::BitValue V = rc(1)[im(2)];
1007 Targets.insert(BI.getOperand(0).getMBB());
1020 RegisterRef PR = BI.getOperand(0);
1035 Targets.insert(BI.getOperand(1).getMBB());
1189 const MachineOperand &MD = MI.getOperand(0);
1220 RegisterRef RD = MI.getOperand(0);
1221 RegisterRef RS = MI.getOperand(1);
lib/Target/Hexagon/HexagonConstExtenders.cpp 1055 const MachineOperand &Op1 = MI.getOperand(1), &Op2 = MI.getOperand(2);
1055 const MachineOperand &Op1 = MI.getOperand(1), &Op2 = MI.getOperand(2);
1071 Rb != Register(MI.getOperand(BaseP)) ||
1072 !MI.getOperand(OffP).isImm())
1084 int32_t Off = MI.getOperand(OffP).getImm();
1917 if (&MI.getOperand(i) == &Op)
1936 return MI.getOperand(0);
1941 return MI.getOperand(MI.getNumExplicitOperands()-1);
lib/Target/Hexagon/HexagonConstPropagation.cpp 624 const MachineOperand &MD = PN.getOperand(0);
644 const MachineBasicBlock *PB = PN.getOperand(i+1).getMBB();
651 const MachineOperand &SO = PN.getOperand(i);
1920 if (MI.getNumOperands() == 0 || !MI.getOperand(0).isReg())
1922 const MachineOperand &MD = MI.getOperand(0);
1934 RegisterSubReg SrcR(MI.getOperand(1));
1942 unsigned Sub1 = MI.getOperand(2).getImm();
1943 unsigned Sub2 = MI.getOperand(4).getImm();
1953 const MachineOperand &OpLo = LoIs1 ? MI.getOperand(1) : MI.getOperand(3);
1953 const MachineOperand &OpLo = LoIs1 ? MI.getOperand(1) : MI.getOperand(3);
1954 const MachineOperand &OpHi = LoIs1 ? MI.getOperand(3) : MI.getOperand(1);
1954 const MachineOperand &OpHi = LoIs1 ? MI.getOperand(3) : MI.getOperand(1);
1976 const MachineOperand &VO = MI.getOperand(1);
1982 int64_t V = MI.getOperand(1).getImm();
2025 if (!MI.getOperand(1).isImm() || !MI.getOperand(2).isImm())
2025 if (!MI.getOperand(1).isImm() || !MI.getOperand(2).isImm())
2027 uint64_t Hi = MI.getOperand(1).getImm();
2028 uint64_t Lo = MI.getOperand(2).getImm();
2040 int64_t B = MI.getOperand(2).getImm();
2043 RegisterSubReg R(MI.getOperand(1));
2083 RegisterSubReg R1(MI.getOperand(1));
2115 RegisterSubReg R1(MI.getOperand(1));
2143 RegisterSubReg R1(MI.getOperand(1));
2145 unsigned Bits = MI.getOperand(2).getImm();
2146 unsigned Offset = MI.getOperand(3).getImm();
2272 Targets.insert(BrI.getOperand(0).getMBB());
2284 const MachineOperand &MD = BrI.getOperand(0);
2305 const MachineBasicBlock *BranchTarget = BrI.getOperand(1).getMBB();
2567 const MachineOperand &Src1 = MI.getOperand(1);
2568 const MachineOperand &Src2 = MI.getOperand(2);
2576 RegisterSubReg DefR(MI.getOperand(0));
2624 const MachineOperand &Src1 = MI.getOperand(1);
2625 const MachineOperand &Src2 = MI.getOperand(2);
2660 RegisterSubReg DefR(MI.getOperand(0));
2669 RegisterSubReg CR(MI.getOperand(1));
2683 const MachineOperand &ValOp = MI.getOperand(TakeOp);
2684 RegisterSubReg DefR(MI.getOperand(0));
2712 RegisterSubReg R1(MI.getOperand(1));
2742 RegisterSubReg DefR(MI.getOperand(0));
2756 RegisterSubReg DefR(MI.getOperand(0));
2757 RegisterSubReg R1(MI.getOperand(1));
lib/Target/Hexagon/HexagonCopyToCombine.cpp 175 const MachineOperand &Op = I.getOperand(1);
lib/Target/Hexagon/HexagonEarlyIfConv.cpp 253 Register PredR = T1I->getOperand(0).getReg();
259 MachineBasicBlock *T1B = T1I->getOperand(1).getMBB();
264 : T2I->getOperand(0).getMBB();
440 Register DefR = MI.getOperand(0).getReg();
463 const MachineBasicBlock *BB = MI.getOperand(i+1).getMBB();
471 const MachineOperand &RA = MI.getOperand(1);
472 const MachineOperand &RB = MI.getOperand(3);
lib/Target/Hexagon/HexagonFrameLowering.cpp 1389 AP = AI->getOperand(0).getReg();
2518 if (MI.getOperand(0).isFI())
lib/Target/Hexagon/HexagonGenInsert.cpp 607 const MachineOperand &MO = MI->getOperand(i);
724 const MachineOperand &MO = MI->getOperand(i);
737 const MachineOperand &MO = MI->getOperand(i);
lib/Target/Hexagon/HexagonGenPredicate.cpp 198 if (MI->getOperand(2).isImm() && MI->getOperand(2).getImm() == 0)
198 if (MI->getOperand(2).isImm() && MI->getOperand(2).getImm() == 0)
lib/Target/Hexagon/HexagonHardwareLoops.cpp 740 Start = &StartValInstr->getOperand(1);
746 End = &EndValInstr->getOperand(1);
930 EndValInstr->getOperand(1).getSubReg() == 0 &&
931 EndValInstr->getOperand(2).getImm() == StartV) {
932 DistR = EndValInstr->getOperand(1).getReg();
1037 const MachineOperand &MO = MI->getOperand(i);
lib/Target/Hexagon/HexagonInstrInfo.cpp 191 const MachineOperand &MO = MI.getOperand(i);
254 const MachineOperand OpFI = MI.getOperand(1);
257 const MachineOperand OpOff = MI.getOperand(2);
261 return MI.getOperand(0).getReg();
268 const MachineOperand OpFI = MI.getOperand(2);
271 const MachineOperand OpOff = MI.getOperand(3);
275 return MI.getOperand(0).getReg();
302 const MachineOperand &OpFI = MI.getOperand(0);
305 const MachineOperand &OpOff = MI.getOperand(1);
309 return MI.getOperand(2).getReg();
320 const MachineOperand &OpFI = MI.getOperand(1);
323 const MachineOperand &OpOff = MI.getOperand(2);
327 return MI.getOperand(3).getReg();
1785 SrcReg = MI.getOperand(1).getReg();
1794 SrcReg = MI.getOperand(1).getReg();
1803 SrcReg = MI.getOperand(1).getReg();
1825 SrcReg2 = MI.getOperand(2).getReg();
1841 const MachineOperand &Op2 = MI.getOperand(2);
1844 Value = MI.getOperand(2).getImm();
1883 const MachineOperand &BaseA = MIa.getOperand(BasePosA);
1891 const MachineOperand &BaseB = MIb.getOperand(BasePosB);
1903 const MachineOperand &OffA = MIa.getOperand(OffsetPosA);
1904 const MachineOperand &OffB = MIb.getOperand(OffsetPosB);
1905 if (!MIa.getOperand(OffsetPosA).isImm() ||
1906 !MIb.getOperand(OffsetPosB).isImm())
1932 const MachineOperand &OffsetOp = MI.getOperand(OffsetPos);
1938 const MachineOperand &AddOp = MI.getOperand(2);
2043 const MachineOperand &MO = MI.getOperand(ExtOpNum);
2617 Register DstReg = MI1.getOperand(0).getReg();
2620 if (MI2.getOperand(I).isReg() && DstReg == MI2.getOperand(I).getReg())
2620 if (MI2.getOperand(I).isReg() && DstReg == MI2.getOperand(I).getReg())
2625 if (MI1.getOperand(0).isReg() && MI2.getOperand(3).isReg() &&
2625 if (MI1.getOperand(0).isReg() && MI2.getOperand(3).isReg() &&
2626 MI1.getOperand(0).getReg() == MI2.getOperand(3).getReg())
2626 MI1.getOperand(0).getReg() == MI2.getOperand(3).getReg())
2954 const MachineOperand &Op = Second.getOperand(0);
2964 Second.getOperand(Second.getNumOperands() - 1);
2968 const MachineOperand &Op = First.getOperand(i);
3176 const MachineOperand &OffsetOp = MI.getOperand(OffsetPos);
3182 const MachineOperand &BaseOp = MI.getOperand(BasePos);
3216 if (!MI.getOperand(BasePos).isReg() || !MI.getOperand(OffsetPos).isImm())
3216 if (!MI.getOperand(BasePos).isReg() || !MI.getOperand(OffsetPos).isImm())
3307 DstReg = MI.getOperand(0).getReg();
3308 Src1Reg = MI.getOperand(1).getReg();
3309 Src2Reg = MI.getOperand(2).getReg();
3319 DstReg = MI.getOperand(0).getReg();
3320 SrcReg = MI.getOperand(1).getReg();
3323 isIntRegForSubInst(SrcReg) && MI.getOperand(2).isImm() &&
3324 ((isUInt<5>(MI.getOperand(2).getImm())) ||
3325 (MI.getOperand(2).getImm() == -1)))
3330 DstReg = MI.getOperand(0).getReg();
3331 SrcReg = MI.getOperand(1).getReg();
3339 DstReg = MI.getOperand(0).getReg();
3344 DstReg = MI.getOperand(0).getReg();
3345 Src1Reg = MI.getOperand(1).getReg();
3348 MI.getOperand(2).isImm() &&
3349 isIntRegForSubInst(Src1Reg) && (MI.getOperand(2).getImm() == 0))
3360 Src1Reg = MI.getOperand(0).getReg();
3386 Register DestReg = GA.getOperand(0).getReg();
3392 const MachineOperand &CmpOp = GA.getOperand(2);
3575 const MachineOperand &BrTarget = MI.getOperand(1);
3737 DstReg = MI.getOperand(0).getReg();
3738 SrcReg = MI.getOperand(1).getReg();
3744 MI.getOperand(2).isImm() &&
3745 isShiftedUInt<5,2>(MI.getOperand(2).getImm()))
3749 (MI.getOperand(2).isImm() &&
3750 isShiftedUInt<4,2>(MI.getOperand(2).getImm())))
3756 DstReg = MI.getOperand(0).getReg();
3757 SrcReg = MI.getOperand(1).getReg();
3759 MI.getOperand(2).isImm() && isUInt<4>(MI.getOperand(2).getImm()))
3759 MI.getOperand(2).isImm() && isUInt<4>(MI.getOperand(2).getImm()))
3775 DstReg = MI.getOperand(0).getReg();
3776 SrcReg = MI.getOperand(1).getReg();
3778 MI.getOperand(2).isImm() &&
3779 isShiftedUInt<3,1>(MI.getOperand(2).getImm()))
3784 DstReg = MI.getOperand(0).getReg();
3785 SrcReg = MI.getOperand(1).getReg();
3787 MI.getOperand(2).isImm() &&
3788 isUInt<3>(MI.getOperand(2).getImm()))
3793 DstReg = MI.getOperand(0).getReg();
3794 SrcReg = MI.getOperand(1).getReg();
3798 MI.getOperand(2).isImm() &&
3799 isShiftedUInt<5,3>(MI.getOperand(2).getImm()))
3814 DstReg = MI.getOperand(0).getReg();
3827 DstReg = MI.getOperand(1).getReg();
3828 SrcReg = MI.getOperand(0).getReg();
3842 SrcReg = MI.getOperand(0).getReg();
3854 Src1Reg = MI.getOperand(0).getReg();
3855 Src2Reg = MI.getOperand(2).getReg();
3858 HRI.getStackRegister() == Src1Reg && MI.getOperand(1).isImm() &&
3859 isShiftedUInt<5,2>(MI.getOperand(1).getImm()))
3863 MI.getOperand(1).isImm() &&
3864 isShiftedUInt<4,2>(MI.getOperand(1).getImm()))
3869 Src1Reg = MI.getOperand(0).getReg();
3870 Src2Reg = MI.getOperand(2).getReg();
3872 MI.getOperand(1).isImm() && isUInt<4>(MI.getOperand(1).getImm()))
3872 MI.getOperand(1).isImm() && isUInt<4>(MI.getOperand(1).getImm()))
3886 Src1Reg = MI.getOperand(0).getReg();
3887 Src2Reg = MI.getOperand(2).getReg();
3889 MI.getOperand(1).isImm() &&
3890 isShiftedUInt<3,1>(MI.getOperand(1).getImm()))
3895 Src1Reg = MI.getOperand(0).getReg();
3896 Src2Reg = MI.getOperand(2).getReg();
3899 HRI.getStackRegister() == Src1Reg && MI.getOperand(1).isImm() &&
3900 isShiftedInt<6,3>(MI.getOperand(1).getImm()))
3905 Src1Reg = MI.getOperand(0).getReg();
3906 if (isIntRegForSubInst(Src1Reg) && MI.getOperand(1).isImm() &&
3907 isShiftedUInt<4,2>(MI.getOperand(1).getImm()) &&
3908 MI.getOperand(2).isImm() && isUInt<1>(MI.getOperand(2).getImm()))
3908 MI.getOperand(2).isImm() && isUInt<1>(MI.getOperand(2).getImm()))
3913 Src1Reg = MI.getOperand(0).getReg();
3915 MI.getOperand(1).isImm() && isUInt<4>(MI.getOperand(1).getImm()) &&
3915 MI.getOperand(1).isImm() && isUInt<4>(MI.getOperand(1).getImm()) &&
3916 MI.getOperand(2).isImm() && isUInt<1>(MI.getOperand(2).getImm()))
3916 MI.getOperand(2).isImm() && isUInt<1>(MI.getOperand(2).getImm()))
3920 if (MI.getOperand(2).isImm() &&
3921 isShiftedUInt<5,3>(MI.getOperand(2).getImm()))
3943 DstReg = MI.getOperand(0).getReg();
3944 SrcReg = MI.getOperand(1).getReg();
3948 HRI.getStackRegister() == SrcReg && MI.getOperand(2).isImm() &&
3949 isShiftedUInt<6,2>(MI.getOperand(2).getImm()))
3952 if ((DstReg == SrcReg) && MI.getOperand(2).isImm() &&
3953 isInt<7>(MI.getOperand(2).getImm()))
3957 if (isIntRegForSubInst(SrcReg) && MI.getOperand(2).isImm() &&
3958 ((MI.getOperand(2).getImm() == 1) ||
3959 (MI.getOperand(2).getImm() == -1)))
3965 DstReg = MI.getOperand(0).getReg();
3966 Src1Reg = MI.getOperand(1).getReg();
3967 Src2Reg = MI.getOperand(2).getReg();
3976 DstReg = MI.getOperand(0).getReg();
3977 SrcReg = MI.getOperand(1).getReg();
3979 MI.getOperand(2).isImm() &&
3980 ((MI.getOperand(2).getImm() == 1) ||
3981 (MI.getOperand(2).getImm() == 255)))
3986 DstReg = MI.getOperand(0).getReg();
3987 SrcReg = MI.getOperand(1).getReg();
3996 DstReg = MI.getOperand(0).getReg();
4007 DstReg = MI.getOperand(0).getReg();
4008 SrcReg = MI.getOperand(1).getReg();
4011 MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 0)
4011 MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 0)
4016 DstReg = MI.getOperand(0).getReg();
4017 SrcReg = MI.getOperand(1).getReg();
4020 MI.getOperand(2).isImm() && isUInt<2>(MI.getOperand(2).getImm()))
4020 MI.getOperand(2).isImm() && isUInt<2>(MI.getOperand(2).getImm()))
4026 DstReg = MI.getOperand(0).getReg();
4028 ((MI.getOperand(1).isImm() && isUInt<2>(MI.getOperand(1).getImm())) ||
4028 ((MI.getOperand(1).isImm() && isUInt<2>(MI.getOperand(1).getImm())) ||
4029 (MI.getOperand(1).isGlobal() &&
4030 isUInt<2>(MI.getOperand(1).getOffset()))) &&
4031 ((MI.getOperand(2).isImm() && isUInt<2>(MI.getOperand(2).getImm())) ||
4031 ((MI.getOperand(2).isImm() && isUInt<2>(MI.getOperand(2).getImm())) ||
4032 (MI.getOperand(2).isGlobal() &&
4033 isUInt<2>(MI.getOperand(2).getOffset()))))
4038 DstReg = MI.getOperand(0).getReg();
4039 SrcReg = MI.getOperand(1).getReg();
4041 ((MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 0) ||
4041 ((MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 0) ||
4042 (MI.getOperand(2).isGlobal() && MI.getOperand(2).getOffset() == 0)))
4042 (MI.getOperand(2).isGlobal() && MI.getOperand(2).getOffset() == 0)))
4047 DstReg = MI.getOperand(0).getReg();
4048 SrcReg = MI.getOperand(2).getReg();
4050 ((MI.getOperand(1).isImm() && MI.getOperand(1).getImm() == 0) ||
4050 ((MI.getOperand(1).isImm() && MI.getOperand(1).getImm() == 0) ||
4051 (MI.getOperand(1).isGlobal() && MI.getOperand(1).getOffset() == 0)))
4051 (MI.getOperand(1).isGlobal() && MI.getOperand(1).getOffset() == 0)))
4059 DstReg = MI.getOperand(0).getReg();
4060 SrcReg = MI.getOperand(1).getReg();
4101 const MachineOperand &DefMO = DefMI.getOperand(DefIdx);
4114 const MachineOperand &UseMO = UseMI.getOperand(UseIdx);
4312 for (; MI.getOperand(NumDefs).isReg() && MI.getOperand(NumDefs).isDef();
4312 for (; MI.getOperand(NumDefs).isReg() && MI.getOperand(NumDefs).isDef();
4316 assert(MI.getOperand(NumDefs).isSymbol() && "No asm string?");
4318 const char *AsmStr = MI.getOperand(NumDefs).getSymbolName();
4443 const MachineOperand &Operand = MIB.getOperand(0);
lib/Target/Hexagon/HexagonMCInstLower.cpp 113 const MachineOperand &MO = MI->getOperand(i);
lib/Target/Hexagon/HexagonRDFOpt.cpp 120 const MachineOperand &DstOp = MI->getOperand(0);
121 const MachineOperand &HiOp = MI->getOperand(1);
122 const MachineOperand &LoOp = MI->getOperand(2);
131 const MachineOperand &A = MI->getOperand(2);
137 const MachineOperand &DstOp = MI->getOperand(0);
138 const MachineOperand &SrcOp = MI->getOperand(1);
lib/Target/Hexagon/HexagonSplitDouble.cpp 179 if (MI->getOperand(1).isReg())
184 if (MI->getOperand(0).isReg())
325 if (MI->getOperand(1).getSubReg() != 0)
338 uint64_t D = MI->getOperand(1).getImm();
345 const MachineOperand &Op1 = MI->getOperand(1);
346 const MachineOperand &Op2 = MI->getOperand(2);
357 const MachineOperand &OpX = MI->getOperand(ImmX);
375 Register Rs = MI->getOperand(1).getReg();
376 Register Rt = MI->getOperand(2).getReg();
381 unsigned S = MI->getOperand(3).getImm();
389 unsigned S = MI->getOperand(2).getImm();
510 CmpI = MRI->getVRegDef(CmpI->getOperand(1).getReg());
537 const MachineOperand &MD = MI.getOperand(0);
554 Register T = UseI->getOperand(0).getReg();
lib/Target/Hexagon/HexagonStoreWidening.cpp 122 const MachineOperand &MO = MI->getOperand(0);
135 const MachineOperand &MO = MI->getOperand(1);
161 return MI->getOperand(0).isReg();
291 int Off1 = S1->getOperand(1).getImm();
292 int Off2 = S2->getOperand(1).getImm();
lib/Target/Hexagon/HexagonSubtarget.cpp 233 Register::isPhysicalRegister(MI->getOperand(1).getReg())) {
235 VRegHoldingReg[MI->getOperand(0).getReg()] = MI->getOperand(1).getReg();
235 VRegHoldingReg[MI->getOperand(0).getReg()] = MI->getOperand(1).getReg();
236 LastVRegUse.erase(MI->getOperand(1).getReg());
239 const MachineOperand &MO = MI->getOperand(i);
lib/Target/Hexagon/HexagonVLIWPacketizer.cpp 426 Register DestReg = MI.getOperand(0).getReg();
604 return MI.getOperand(MI.getNumOperands()-1);
623 return MI.getOperand(1);
777 const MachineOperand &MO = MI.getOperand(opNum);
lib/Target/Hexagon/HexagonVectorPrint.cpp 110 if (MI.getOperand(0).isReg() && MI.getOperand(0).isDef()) {
110 if (MI.getOperand(0).isReg() && MI.getOperand(0).isDef()) {
111 Reg = MI.getOperand(0).getReg();
116 if (MI.mayStore() && MI.getNumOperands() >= 3 && MI.getOperand(2).isReg()) {
117 Reg = MI.getOperand(2).getReg();
122 if (MI.mayStore() && MI.getNumOperands() >= 4 && MI.getOperand(3).isReg()) {
123 Reg = MI.getOperand(3).getReg();
lib/Target/Hexagon/RDFCopy.cpp 44 const MachineOperand &Dst = MI->getOperand(0);
45 const MachineOperand &Src = MI->getOperand(1);
lib/Target/Hexagon/RDFGraph.cpp 606 const MachineOperand &Op = In.getOperand(OpNum);
630 const MachineOperand &Op = In.getOperand(OpNum);
lib/Target/Lanai/LanaiAsmPrinter.cpp 66 const MachineOperand &MO = MI->getOperand(OpNum);
123 const MachineOperand &FlagsOP = MI->getOperand(OpNo - 1);
133 const MachineOperand &MO = MI->getOperand(RegOp);
182 .addReg(MI->getOperand(0).getReg())
lib/Target/Lanai/LanaiInstrInfo.cpp 185 SrcReg = MI.getOperand(0).getReg();
188 CmpValue = MI.getOperand(1).getImm();
191 SrcReg = MI.getOperand(0).getReg();
192 SrcReg2 = MI.getOperand(1).getReg();
359 const MachineOperand &MO = Instr.getOperand(IO);
372 CC = (LPCC::CondCode)Instr.getOperand(IO - 1).getImm();
450 Cond.push_back(MI.getOperand(3));
720 if (MI.getOperand(1).isFI() && MI.getOperand(2).isImm() &&
720 if (MI.getOperand(1).isFI() && MI.getOperand(2).isImm() &&
721 MI.getOperand(2).getImm() == 0) {
722 FrameIndex = MI.getOperand(1).getIndex();
723 return MI.getOperand(0).getReg();
749 if (MI.getOperand(0).isFI() && MI.getOperand(1).isImm() &&
749 if (MI.getOperand(0).isFI() && MI.getOperand(1).isImm() &&
750 MI.getOperand(1).getImm() == 0) {
751 FrameIndex = MI.getOperand(0).getIndex();
752 return MI.getOperand(2).getReg();
764 if (!LdSt.getOperand(1).isReg() || !LdSt.getOperand(2).isImm() ||
764 if (!LdSt.getOperand(1).isReg() || !LdSt.getOperand(2).isImm() ||
765 !(LdSt.getOperand(3).isImm() && LdSt.getOperand(3).getImm() == LPAC::ADD))
765 !(LdSt.getOperand(3).isImm() && LdSt.getOperand(3).getImm() == LPAC::ADD))
789 BaseOp = &LdSt.getOperand(1);
790 Offset = LdSt.getOperand(2).getImm();
lib/Target/Lanai/LanaiMCInstLower.cpp 97 const MachineOperand &MO = MI->getOperand(I);
lib/Target/MSP430/MSP430AsmPrinter.cpp 80 const MachineOperand &MO = MI->getOperand(OpNum);
109 const MachineOperand &Base = MI->getOperand(OpNum);
110 const MachineOperand &Disp = MI->getOperand(OpNum+1);
lib/Target/MSP430/MSP430InstrInfo.cpp 314 return TII.getInlineAsmLength(MI.getOperand(0).getSymbolName(),
lib/Target/MSP430/MSP430InstrInfo.h 74 assert(I.getOperand(1).getImm() >= 0 && "Size must not be negative");
75 return I.getOperand(1).getImm();
lib/Target/MSP430/MSP430MCInstLower.cpp 119 const MachineOperand &MO = MI->getOperand(i);
lib/Target/Mips/Mips16InstrInfo.cpp 103 Dest = &MI.getOperand(0);
104 Src = &MI.getOperand(1);
lib/Target/Mips/MipsAsmPrinter.cpp 148 lowerOperand(MI->getOperand(0), MCOp);
168 MachineOperand MO = MI.getOperand(I);
216 unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
217 unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
520 const MachineOperand &MO = MI->getOperand(OpNum);
566 const MachineOperand &FlagsOP = MI->getOperand(OpNum - 1);
598 const MachineOperand &MO = MI->getOperand(RegOp);
624 const MachineOperand &BaseMO = MI->getOperand(OpNum);
625 const MachineOperand &OffsetMO = MI->getOperand(OpNum + 1);
657 const MachineOperand &MO = MI->getOperand(opNum);
755 const MachineOperand &MO = MI->getOperand(opNum);
lib/Target/Mips/MipsBranchExpansion.cpp 227 const MachineOperand &MO = Br.getOperand(I);
lib/Target/Mips/MipsConstantIslandPass.cpp 629 unsigned CPI = CPEMI.getOperand(1).getIndex();
lib/Target/Mips/MipsDelaySlotFiller.cpp 418 const MachineOperand &MO = MI.getOperand(I);
lib/Target/Mips/MipsInstrInfo.cpp 87 BB = Inst->getOperand(NumOp-1).getMBB();
91 Cond.push_back(Inst->getOperand(i));
583 const char *AsmStr = MI.getOperand(0).getSymbolName();
589 return MI.getOperand(2).getImm();
701 if (!MI.getOperand(SrcOpIdx1).isReg() || !MI.getOperand(SrcOpIdx2).isReg())
701 if (!MI.getOperand(SrcOpIdx1).isReg() || !MI.getOperand(SrcOpIdx2).isReg())
728 MachineOperand MOPos = MI.getOperand(2);
739 MachineOperand MOSize = MI.getOperand(3);
lib/Target/Mips/MipsMCInstLower.cpp 221 OutMI.addOperand(LowerOperand(MI->getOperand(0)));
224 unsigned TargetFlags = MI->getOperand(1).getTargetFlags();
244 MCSymbolRefExpr::create(MI->getOperand(1).getMBB()->getSymbol(), *Ctx);
249 OutMI.addOperand(createSub(MI->getOperand(1).getMBB(),
250 MI->getOperand(2).getMBB(), Kind));
259 unsigned TargetFlags = MI->getOperand(2).getTargetFlags();
279 const MachineOperand &MO = MI->getOperand(I);
286 MCSymbolRefExpr::create(MI->getOperand(2).getMBB()->getSymbol(), *Ctx);
291 OutMI.addOperand(createSub(MI->getOperand(2).getMBB(),
292 MI->getOperand(3).getMBB(), Kind));
324 const MachineOperand &MO = MI->getOperand(i);
lib/Target/Mips/MipsRegisterBankInfo.cpp 228 addDefUses(MI->getOperand(0).getReg(), MRI);
231 addUseDef(MI->getOperand(0).getReg(), MRI);
234 addDefUses(MI->getOperand(0).getReg(), MRI);
237 addUseDef(MI->getOperand(i).getReg(), MRI);
241 addDefUses(MI->getOperand(0).getReg(), MRI);
243 addUseDef(MI->getOperand(2).getReg(), MRI);
244 addUseDef(MI->getOperand(3).getReg(), MRI);
248 addDefUses(MI->getOperand(0).getReg(), MRI);
336 assert((Register::isPhysicalRegister(CopyInst->getOperand(Op).getReg())) &&
345 RBI.getRegBank(CopyInst->getOperand(Op).getReg(), MRI, TRI);
434 const LLT Op0Ty = MRI.getType(MI.getOperand(0).getReg());
556 unsigned Op2Size = MRI.getType(MI.getOperand(2).getReg()).getSizeInBits();
572 unsigned SizeFP = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
578 assert((MRI.getType(MI.getOperand(1).getReg()).getSizeInBits() == 32) &&
lib/Target/Mips/MipsSEISelDAGToDAG.cpp 88 (MI.getOperand(1).getReg() == Mips::ZERO) &&
89 (MI.getOperand(2).isImm()) &&
90 (MI.getOperand(2).getImm() == 0)) {
91 DstReg = MI.getOperand(0).getReg();
94 (MI.getOperand(1).getReg() == Mips::ZERO_64) &&
95 (MI.getOperand(2).isImm()) &&
96 (MI.getOperand(2).getImm() == 0)) {
97 DstReg = MI.getOperand(0).getReg();
lib/Target/Mips/MipsSEInstrInfo.cpp 51 if ((MI.getOperand(1).isFI()) && // is a stack slot
52 (MI.getOperand(2).isImm()) && // the imm is zero
53 (isZeroImm(MI.getOperand(2)))) {
54 FrameIndex = MI.getOperand(1).getIndex();
55 return MI.getOperand(0).getReg();
73 if ((MI.getOperand(1).isFI()) && // is a stack slot
74 (MI.getOperand(2).isImm()) && // the imm is zero
75 (isZeroImm(MI.getOperand(2)))) {
76 FrameIndex = MI.getOperand(1).getIndex();
77 return MI.getOperand(0).getReg();
192 if (MI.getOperand(2).getReg() == Mips::ZERO)
196 if (MI.getOperand(2).getReg() == Mips::ZERO_64)
231 if (!MI.getOperand(1).isImm() || MI.getOperand(1).getImm() != (1<<4))
231 if (!MI.getOperand(1).isImm() || MI.getOperand(1).getImm() != (1<<4))
234 Src = &MI.getOperand(0);
235 Dest = &MI.getOperand(2);
237 Dest = &MI.getOperand(0);
238 Src = &MI.getOperand(2);
242 Dest = &MI.getOperand(0);
243 Src = &MI.getOperand(1);
lib/Target/NVPTX/NVPTXAsmPrinter.cpp 153 const MachineOperand &MO = MI->getOperand(OpNo);
216 const MachineOperand &MO = MI->getOperand(0);
224 const MachineOperand &MO = MI->getOperand(i);
510 Register RegNo = MI->getOperand(0).getReg();
2210 const MachineOperand &MO = MI->getOperand(opNum);
2252 if (MI->getOperand(opNum + 1).isImm() &&
2253 MI->getOperand(opNum + 1).getImm() == 0)
lib/Target/PowerPC/PPCAsmPrinter.cpp 208 const MachineOperand &MO = MI->getOperand(OpNo);
261 if (!MI->getOperand(OpNo).isReg() ||
263 !MI->getOperand(OpNo+1).isReg())
270 if (MI->getOperand(OpNo).isImm())
274 if(!MI->getOperand(OpNo).isReg())
278 Register Reg = MI->getOperand(OpNo).getReg();
325 assert(MI->getOperand(OpNo).isReg());
331 assert(MI->getOperand(OpNo).isReg());
353 unsigned NumNOPBytes = MI.getOperand(1).getImm();
391 Register ScratchReg = MI.getOperand(Opers.getNextScratchIdx()).getReg();
484 assert(MI->getOperand(0).isReg() &&
485 ((Subtarget->isPPC64() && MI->getOperand(0).getReg() == PPC::X3) ||
486 (!Subtarget->isPPC64() && MI->getOperand(0).getReg() == PPC::R3)) &&
488 assert(MI->getOperand(1).isReg() &&
489 ((Subtarget->isPPC64() && MI->getOperand(1).getReg() == PPC::X3) ||
490 (!Subtarget->isPPC64() && MI->getOperand(1).getReg() == PPC::R3)) &&
504 const MachineOperand &MO = MI->getOperand(2);
686 const MachineOperand &MO = MI->getOperand(1);
744 const MachineOperand &MO = MI->getOperand(1);
773 const MachineOperand &MO = MI->getOperand(2);
803 const MachineOperand &MO = MI->getOperand(1);
834 const MachineOperand &MO = MI->getOperand(2);
874 const MachineOperand &MO = MI->getOperand(1);
906 const MachineOperand &MO = MI->getOperand(2);
924 const MachineOperand &MO = MI->getOperand(2);
931 .addReg(MI->getOperand(0).getReg())
932 .addReg(MI->getOperand(1).getReg())
943 const MachineOperand &MO = MI->getOperand(1);
972 .addReg(MI->getOperand(0).getReg()));
974 .addReg(MI->getOperand(1).getReg())
976 .addReg(MI->getOperand(0).getReg()));
978 .addReg(MI->getOperand(0).getReg())
979 .addReg(MI->getOperand(1).getReg())
980 .addReg(MI->getOperand(0).getReg()));
991 .addReg(MI->getOperand(0).getReg())
994 .addReg(MI->getOperand(0).getReg())
995 .addReg(MI->getOperand(0).getReg())
1003 const MachineOperand &MO = MI->getOperand(2);
1010 .addReg(MI->getOperand(0).getReg())
1011 .addReg(MI->getOperand(1).getReg())
1021 const MachineOperand &MO = MI->getOperand(2);
1030 .addReg(MI->getOperand(0).getReg())
1031 .addReg(MI->getOperand(1).getReg())
1048 const MachineOperand &MO = MI->getOperand(2);
1055 .addReg(MI->getOperand(0).getReg())
1056 .addReg(MI->getOperand(1).getReg())
1066 const MachineOperand &MO = MI->getOperand(2);
1075 .addReg(MI->getOperand(0).getReg())
1076 .addReg(MI->getOperand(1).getReg())
1095 const MachineOperand &MO = MI->getOperand(2);
1104 .addReg(MI->getOperand(0).getReg())
1105 .addReg(MI->getOperand(1).getReg())
1115 const MachineOperand &MO = MI->getOperand(2);
1123 .addReg(MI->getOperand(0).getReg())
1124 .addReg(MI->getOperand(1).getReg())
1136 getRegisterName(MI->getOperand(1).getReg()));
1138 .addReg(MI->getOperand(0).getReg()));
1150 ->getEncodingValue(MI->getOperand(0).getReg());
1152 getRegisterName(MI->getOperand(0).getReg()));
1155 .addReg(MI->getOperand(1).getReg()));
1171 const MachineOperand &MO = MI->getOperand(OpNum);
1225 unsigned RetOpcode = MI->getOperand(0).getImm();
1273 static_cast<PPC::Predicate>(MI->getOperand(1).getImm())))
1274 .addReg(MI->getOperand(2).getReg())
lib/Target/PowerPC/PPCCTRLoops.cpp 115 const MachineOperand &MO = MI.getOperand(i);
lib/Target/PowerPC/PPCFrameLowering.cpp 366 const MachineOperand &MO = Ret.getOperand(I);
lib/Target/PowerPC/PPCInstrInfo.cpp 161 const MachineOperand &MO = MI.getOperand(i);
185 const MachineOperand &DefMO = DefMI.getOperand(DefIdx);
291 SrcReg = MI.getOperand(1).getReg();
292 DstReg = MI.getOperand(0).getReg();
307 if (MI.getOperand(1).isImm() && !MI.getOperand(1).getImm() &&
307 if (MI.getOperand(1).isImm() && !MI.getOperand(1).getImm() &&
308 MI.getOperand(2).isFI()) {
309 FrameIndex = MI.getOperand(2).getIndex();
310 return MI.getOperand(0).getReg();
359 if (MI.getOperand(1).isImm() && !MI.getOperand(1).getImm() &&
359 if (MI.getOperand(1).isImm() && !MI.getOperand(1).getImm() &&
360 MI.getOperand(2).isFI()) {
361 FrameIndex = MI.getOperand(2).getIndex();
362 return MI.getOperand(0).getReg();
1617 SrcReg = MI.getOperand(1).getReg();
1619 Value = MI.getOperand(2).getImm();
1628 SrcReg = MI.getOperand(1).getReg();
1629 SrcReg2 = MI.getOperand(2).getReg();
1817 ((Instr.getOperand(1).getReg() == SrcReg &&
1818 Instr.getOperand(2).getReg() == SrcReg2) ||
1819 (Instr.getOperand(1).getReg() == SrcReg2 &&
1820 Instr.getOperand(2).getReg() == SrcReg))) {
2015 const char *AsmStr = MI.getOperand(0).getSymbolName();
3896 if (Opcode == PPC::RLDICL && MI.getOperand(3).getImm() >= 33)
3901 MI.getOperand(3).getImm() > 0 &&
3902 MI.getOperand(3).getImm() <= MI.getOperand(4).getImm())
3902 MI.getOperand(3).getImm() <= MI.getOperand(4).getImm())
3916 int64_t Imm = MI.getOperand(1).getImm();
3926 MI.getOperand(3).getImm() >= 32)
3930 MI.getOperand(3).getImm() >= 32 &&
3931 MI.getOperand(3).getImm() <= 63 - MI.getOperand(2).getImm())
3931 MI.getOperand(3).getImm() <= 63 - MI.getOperand(2).getImm())
3937 MI.getOperand(3).getImm() <= MI.getOperand(4).getImm())
3937 MI.getOperand(3).getImm() <= MI.getOperand(4).getImm())
3978 if (!MI.getOperand(1).isImm() || !MI.getOperand(2).isReg())
3978 if (!MI.getOperand(1).isImm() || !MI.getOperand(2).isReg())
3981 unsigned StackOffset = MI.getOperand(1).getImm();
3982 Register StackReg = MI.getOperand(2).getReg();
4007 Register SrcReg = MI.getOperand(1).getReg();
4016 Register VReg = MI.getOperand(0).getReg();
4035 if (CallMI.isCall() && CallMI.getOperand(0).isGlobal()) {
4037 dyn_cast<Function>(CallMI.getOperand(0).getGlobal());
4076 Register SrcReg = MI.getOperand(1).getReg();
4104 if (MI.getOperand(I).isReg()) {
4105 Register SrcReg = MI.getOperand(I).getReg();
4126 assert(MI.getOperand(1).isReg() && MI.getOperand(2).isReg());
4126 assert(MI.getOperand(1).isReg() && MI.getOperand(2).isReg());
4128 Register SrcReg1 = MI.getOperand(1).getReg();
4129 Register SrcReg2 = MI.getOperand(2).getReg();
4274 if (!LdSt.getOperand(1).isImm() || !LdSt.getOperand(2).isReg())
4274 if (!LdSt.getOperand(1).isImm() || !LdSt.getOperand(2).isReg())
4281 Offset = LdSt.getOperand(1).getImm();
4282 BaseReg = &LdSt.getOperand(2);
lib/Target/PowerPC/PPCMCInstLower.cpp 156 if (LowerPPCMachineOperandToMCOperand(MI->getOperand(i), MCOp, AP,
lib/Target/PowerPC/PPCRegisterInfo.cpp 1269 while (!MI->getOperand(FIOperandNum).isFI()) {
1276 Offset += MI->getOperand(OffsetOperandNo).getImm();
lib/Target/RISCV/RISCVAsmPrinter.cpp 90 const MachineOperand &MO = MI->getOperand(OpNo);
130 const MachineOperand &MO = MI->getOperand(OpNo);
lib/Target/RISCV/RISCVInstrInfo.cpp 53 if (MI.getOperand(1).isFI() && MI.getOperand(2).isImm() &&
53 if (MI.getOperand(1).isFI() && MI.getOperand(2).isImm() &&
54 MI.getOperand(2).getImm() == 0) {
55 FrameIndex = MI.getOperand(1).getIndex();
56 return MI.getOperand(0).getReg();
76 if (MI.getOperand(0).isFI() && MI.getOperand(1).isImm() &&
76 if (MI.getOperand(0).isFI() && MI.getOperand(1).isImm() &&
77 MI.getOperand(1).getImm() == 0) {
78 FrameIndex = MI.getOperand(0).getIndex();
79 return MI.getOperand(2).getReg();
426 return MI.getOperand(NumOp - 1).getMBB();
472 return getInlineAsmLength(MI.getOperand(0).getSymbolName(),
486 return (MI.getOperand(1).isReg() && MI.getOperand(1).getReg() == RISCV::X0);
486 return (MI.getOperand(1).isReg() && MI.getOperand(1).getReg() == RISCV::X0);
500 const MachineOperand &MO = MI.getOperand(OI.index());
lib/Target/Sparc/SparcAsmPrinter.cpp 175 const MachineOperand &MO = MI->getOperand(0);
294 const MachineOperand &MO = MI->getOperand (opNum);
393 if (MI->getOperand(opNum+1).isReg() &&
394 MI->getOperand(opNum+1).getReg() == SP::G0)
396 if (MI->getOperand(opNum+1).isImm() &&
397 MI->getOperand(opNum+1).getImm() == 0)
lib/Target/Sparc/SparcInstrInfo.cpp 48 if (MI.getOperand(1).isFI() && MI.getOperand(2).isImm() &&
48 if (MI.getOperand(1).isFI() && MI.getOperand(2).isImm() &&
49 MI.getOperand(2).getImm() == 0) {
50 FrameIndex = MI.getOperand(1).getIndex();
51 return MI.getOperand(0).getReg();
67 if (MI.getOperand(0).isFI() && MI.getOperand(1).isImm() &&
67 if (MI.getOperand(0).isFI() && MI.getOperand(1).isImm() &&
68 MI.getOperand(1).getImm() == 0) {
69 FrameIndex = MI.getOperand(0).getIndex();
70 return MI.getOperand(2).getReg();
lib/Target/Sparc/SparcMCInstLower.cpp 101 const MachineOperand &MO = MI->getOperand(i);
lib/Target/SystemZ/SystemZAsmPrinter.cpp 34 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg()))
35 .addImm(MI->getOperand(1).getImm());
38 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg()))
39 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(1).getReg()))
40 .addImm(MI->getOperand(2).getImm());
48 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg()))
49 .addImm(MI->getOperand(1).getImm());
52 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg()))
53 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(1).getReg()))
54 .addImm(MI->getOperand(2).getImm());
61 .addReg(MI->getOperand(0).getReg())
62 .addReg(MI->getOperand(1).getReg())
63 .addReg(SystemZMC::getRegAsGR64(MI->getOperand(2).getReg()))
64 .addImm(MI->getOperand(3).getImm())
65 .addImm(MI->getOperand(4).getImm())
66 .addImm(MI->getOperand(5).getImm());
108 .addReg(SystemZMC::getRegAsVR128(MI->getOperand(0).getReg()))
109 .addReg(MI->getOperand(1).getReg())
110 .addImm(MI->getOperand(2).getImm())
111 .addReg(MI->getOperand(3).getReg());
118 .addReg(SystemZMC::getRegAsVR128(MI->getOperand(0).getReg()))
119 .addReg(MI->getOperand(1).getReg())
120 .addImm(MI->getOperand(2).getImm())
121 .addReg(MI->getOperand(3).getReg())
135 .addImm(MI->getOperand(0).getImm())
136 .addImm(MI->getOperand(1).getImm())
142 .addReg(MI->getOperand(0).getReg())
143 .addReg(MI->getOperand(1).getReg())
144 .addImm(MI->getOperand(2).getImm())
151 .addReg(MI->getOperand(0).getReg())
152 .addReg(MI->getOperand(1).getReg())
153 .addImm(MI->getOperand(2).getImm())
160 .addReg(MI->getOperand(0).getReg())
161 .addImm(MI->getOperand(1).getImm())
162 .addImm(MI->getOperand(2).getImm())
169 .addReg(MI->getOperand(0).getReg())
170 .addImm(MI->getOperand(1).getImm())
171 .addImm(MI->getOperand(2).getImm())
178 .addReg(MI->getOperand(0).getReg())
179 .addReg(MI->getOperand(1).getReg())
180 .addImm(MI->getOperand(2).getImm())
187 .addReg(MI->getOperand(0).getReg())
188 .addReg(MI->getOperand(1).getReg())
189 .addImm(MI->getOperand(2).getImm())
196 .addReg(MI->getOperand(0).getReg())
197 .addImm(MI->getOperand(1).getImm())
198 .addImm(MI->getOperand(2).getImm())
205 .addReg(MI->getOperand(0).getReg())
206 .addImm(MI->getOperand(1).getImm())
207 .addImm(MI->getOperand(2).getImm())
215 .addExpr(Lower.getExpr(MI->getOperand(0), MCSymbolRefExpr::VK_PLT));
221 .addReg(MI->getOperand(0).getReg());
226 .addExpr(Lower.getExpr(MI->getOperand(0), MCSymbolRefExpr::VK_PLT));
231 .addImm(MI->getOperand(0).getImm())
232 .addImm(MI->getOperand(1).getImm())
233 .addExpr(Lower.getExpr(MI->getOperand(2), MCSymbolRefExpr::VK_PLT));
242 .addImm(MI->getOperand(0).getImm())
243 .addImm(MI->getOperand(1).getImm())
249 .addReg(MI->getOperand(0).getReg())
250 .addReg(MI->getOperand(1).getReg())
251 .addImm(MI->getOperand(2).getImm())
258 .addReg(MI->getOperand(0).getReg())
259 .addReg(MI->getOperand(1).getReg())
260 .addImm(MI->getOperand(2).getImm())
267 .addReg(MI->getOperand(0).getReg())
268 .addImm(MI->getOperand(1).getImm())
269 .addImm(MI->getOperand(2).getImm())
276 .addReg(MI->getOperand(0).getReg())
277 .addImm(MI->getOperand(1).getImm())
278 .addImm(MI->getOperand(2).getImm())
285 .addReg(MI->getOperand(0).getReg())
286 .addReg(MI->getOperand(1).getReg())
287 .addImm(MI->getOperand(2).getImm())
294 .addReg(MI->getOperand(0).getReg())
295 .addReg(MI->getOperand(1).getReg())
296 .addImm(MI->getOperand(2).getImm())
303 .addReg(MI->getOperand(0).getReg())
304 .addImm(MI->getOperand(1).getImm())
305 .addImm(MI->getOperand(2).getImm())
312 .addReg(MI->getOperand(0).getReg())
313 .addImm(MI->getOperand(1).getImm())
314 .addImm(MI->getOperand(2).getImm())
323 .addExpr(Lower.getExpr(MI->getOperand(0), MCSymbolRefExpr::VK_TLSGD));
330 .addExpr(Lower.getExpr(MI->getOperand(0), MCSymbolRefExpr::VK_TLSLDM));
335 .addReg(MI->getOperand(0).getReg())
341 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg()))
342 .addImm(MI->getOperand(2).getImm());
347 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg()))
348 .addImm(MI->getOperand(2).getImm());
363 .addReg(MI->getOperand(0).getReg())
364 .addReg(SystemZMC::getRegAsGR64(MI->getOperand(1).getReg()))
365 .addReg(SystemZMC::getRegAsGR64(MI->getOperand(2).getReg()));
371 .addReg(SystemZMC::getRegAsVR128(MI->getOperand(0).getReg()))
372 .addReg(SystemZMC::getRegAsVR128(MI->getOperand(1).getReg()));
413 .addReg(SystemZMC::getRegAsGR64(MI->getOperand(0).getReg()))
414 .addReg(SystemZMC::getRegAsVR128(MI->getOperand(1).getReg()))
420 .addReg(SystemZMC::getRegAsVR128(MI->getOperand(0).getReg()))
421 .addReg(SystemZMC::getRegAsVR128(MI->getOperand(0).getReg()))
422 .addReg(MI->getOperand(1).getReg())
498 .addImm(MI->getOperand(0).getImm())
499 .addImm(MI->getOperand(1).getImm())
573 unsigned NumNOPBytes = MI.getOperand(1).getImm();
617 ScratchReg = MI.getOperand(ScratchIdx).getReg();
688 MCOperand MO(Lower.lowerOperand(MI->getOperand(OpNo)));
697 SystemZInstPrinter::printAddress(MI->getOperand(OpNo).getReg(),
698 MI->getOperand(OpNo + 1).getImm(),
699 MI->getOperand(OpNo + 2).getReg(), OS);
lib/Target/SystemZ/SystemZInstrInfo.cpp 312 if ((MCID.TSFlags & Flag) && MI.getOperand(1).isFI() &&
313 MI.getOperand(2).getImm() == 0 && MI.getOperand(3).getReg() == 0) {
313 MI.getOperand(2).getImm() == 0 && MI.getOperand(3).getReg() == 0) {
314 FrameIndex = MI.getOperand(1).getIndex();
315 return MI.getOperand(0).getReg();
335 if (MI.getOpcode() != SystemZ::MVC || !MI.getOperand(0).isFI() ||
336 MI.getOperand(1).getImm() != 0 || !MI.getOperand(3).isFI() ||
336 MI.getOperand(1).getImm() != 0 || !MI.getOperand(3).isFI() ||
337 MI.getOperand(4).getImm() != 0)
341 int64_t Length = MI.getOperand(2).getImm();
342 unsigned FI1 = MI.getOperand(0).getIndex();
343 unsigned FI2 = MI.getOperand(3).getIndex();
521 if (MI.getNumExplicitOperands() == 2 && MI.getOperand(0).isReg() &&
522 MI.getOperand(1).isImm()) {
523 SrcReg = MI.getOperand(0).getReg();
525 Value = MI.getOperand(1).getImm();
905 isUInt<12>(MI->getOperand(2).getImm()) &&
906 MI->getOperand(3).getReg() == 0);
1399 const char *AsmStr = MI.getOperand(0).getSymbolName();
1413 SystemZ::CCMASK_ANY, &MI.getOperand(0));
1417 return SystemZII::Branch(SystemZII::BranchNormal, MI.getOperand(0).getImm(),
1418 MI.getOperand(1).getImm(), &MI.getOperand(2));
1418 MI.getOperand(1).getImm(), &MI.getOperand(2));
1423 SystemZ::CCMASK_CMP_NE, &MI.getOperand(2));
1427 SystemZ::CCMASK_CMP_NE, &MI.getOperand(2));
1432 MI.getOperand(2).getImm(), &MI.getOperand(3));
1432 MI.getOperand(2).getImm(), &MI.getOperand(3));
1437 MI.getOperand(2).getImm(), &MI.getOperand(3));
1437 MI.getOperand(2).getImm(), &MI.getOperand(3));
1442 MI.getOperand(2).getImm(), &MI.getOperand(3));
1442 MI.getOperand(2).getImm(), &MI.getOperand(3));
1447 MI.getOperand(2).getImm(), &MI.getOperand(3));
1447 MI.getOperand(2).getImm(), &MI.getOperand(3));
1604 if (!(MI && isInt<8>(MI->getOperand(1).getImm())))
1609 if (!(MI && isUInt<8>(MI->getOperand(1).getImm())))
1616 if (!(MI && MI->getOperand(3).getReg() == 0))
lib/Target/SystemZ/SystemZMCInstLower.cpp 97 const MachineOperand &MO = MI->getOperand(I);
lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp 375 const MachineOperand &MO = MI->getOperand(OpNo);
lib/Target/WebAssembly/WebAssemblyMCInstLower.cpp 212 const MachineOperand &MO = MI->getOperand(I);
lib/Target/WebAssembly/WebAssemblyRegStackify.cpp 143 const MachineOperand &MO = MI.getOperand(CalleeOpNo);
250 strcmp(MI.getOperand(0).getSymbolName(), "__stack_pointer") == 0)
436 const MachineOperand &MO = UseInst->getOperand(0);
lib/Target/WebAssembly/WebAssemblyUtilities.cpp 32 const MachineOperand &MO = MI.getOperand(0);
52 const MachineOperand &MO = MI.getOperand(getCalleeOpNo(MI.getOpcode()));
lib/Target/X86/X86AsmPrinter.cpp 204 const MachineOperand &MO = MI->getOperand(OpNo);
240 const MachineOperand &MO = MI->getOperand(OpNo);
260 const MachineOperand &MO = MI->getOperand(OpNo);
278 const MachineOperand &BaseReg = MI->getOperand(OpNo + X86::AddrBaseReg);
279 const MachineOperand &IndexReg = MI->getOperand(OpNo + X86::AddrIndexReg);
280 const MachineOperand &DispSpec = MI->getOperand(OpNo + X86::AddrDisp);
320 unsigned ScaleVal = MI->getOperand(OpNo + X86::AddrScaleAmt).getImm();
331 const MachineOperand &Segment = MI->getOperand(OpNo + X86::AddrSegmentReg);
341 const MachineOperand &BaseReg = MI->getOperand(OpNo + X86::AddrBaseReg);
342 unsigned ScaleVal = MI->getOperand(OpNo + X86::AddrScaleAmt).getImm();
343 const MachineOperand &IndexReg = MI->getOperand(OpNo + X86::AddrIndexReg);
344 const MachineOperand &DispSpec = MI->getOperand(OpNo + X86::AddrDisp);
345 const MachineOperand &SegReg = MI->getOperand(OpNo + X86::AddrSegmentReg);
439 const MachineOperand &MO = MI->getOperand(OpNo);
lib/Target/X86/X86CondBrFolding.cpp 466 SrcReg = MI.getOperand(SrcRegIndex).getReg();
467 if (!MI.getOperand(ValueIndex).isImm())
469 CmpValue = MI.getOperand(ValueIndex).getImm();
lib/Target/X86/X86DomainReassignment.cpp 222 Register DstReg = MI->getOperand(0).getReg();
227 Register SrcReg = MI->getOperand(1).getReg();
540 auto &Op = MI.getOperand(MemOpIdx);
lib/Target/X86/X86ISelLowering.cpp30956 Sym = MI.getOperand(0).getMCSymbol();
lib/Target/X86/X86InsertPrefetch.cpp 82 Register BaseReg = MI.getOperand(Op + X86::AddrBaseReg).getReg();
83 Register IndexReg = MI.getOperand(Op + X86::AddrIndexReg).getReg();
lib/Target/X86/X86InstrBuilder.h 95 const MachineOperand &Op0 = MI->getOperand(Operand);
104 const MachineOperand &Op1 = MI->getOperand(Operand + 1);
107 const MachineOperand &Op2 = MI->getOperand(Operand + 2);
110 const MachineOperand &Op3 = MI->getOperand(Operand + 3);
lib/Target/X86/X86InstrInfo.cpp 109 if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
109 if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
112 SrcReg = MI.getOperand(1).getReg();
113 DstReg = MI.getOperand(0).getReg();
168 return -(I->getOperand(1).getImm());
195 if (MI.getOperand(Op + X86::AddrBaseReg).isFI() &&
196 MI.getOperand(Op + X86::AddrScaleAmt).isImm() &&
197 MI.getOperand(Op + X86::AddrIndexReg).isReg() &&
198 MI.getOperand(Op + X86::AddrDisp).isImm() &&
199 MI.getOperand(Op + X86::AddrScaleAmt).getImm() == 1 &&
200 MI.getOperand(Op + X86::AddrIndexReg).getReg() == 0 &&
201 MI.getOperand(Op + X86::AddrDisp).getImm() == 0) {
202 FrameIndex = MI.getOperand(Op + X86::AddrBaseReg).getIndex();
406 if (MI.getOperand(0).getSubReg() == 0 && isFrameOperand(MI, 1, FrameIndex))
407 return MI.getOperand(0).getReg();
440 if (MI.getOperand(X86::AddrNumOperands).getSubReg() == 0 &&
442 return MI.getOperand(X86::AddrNumOperands).getReg();
600 if (MI.getOperand(1 + X86::AddrBaseReg).isReg() &&
601 MI.getOperand(1 + X86::AddrScaleAmt).isImm() &&
602 MI.getOperand(1 + X86::AddrIndexReg).isReg() &&
603 MI.getOperand(1 + X86::AddrIndexReg).getReg() == 0 &&
605 Register BaseReg = MI.getOperand(1 + X86::AddrBaseReg).getReg();
609 if (!ReMatPICStubLoad && MI.getOperand(1 + X86::AddrDisp).isGlobal())
620 if (MI.getOperand(1 + X86::AddrScaleAmt).isImm() &&
621 MI.getOperand(1 + X86::AddrIndexReg).isReg() &&
622 MI.getOperand(1 + X86::AddrIndexReg).getReg() == 0 &&
623 !MI.getOperand(1 + X86::AddrDisp).isReg()) {
625 if (!MI.getOperand(1 + X86::AddrBaseReg).isReg())
627 Register BaseReg = MI.getOperand(1 + X86::AddrBaseReg).getReg();
660 .add(Orig.getOperand(0))
668 NewMI.substituteRegister(Orig.getOperand(0).getReg(), DestReg, SubIdx, TRI);
688 unsigned Imm = MI.getOperand(ShiftAmtOperandIdx).getImm();
1947 Register Op2Reg = MI.getOperand(CommutableOpIdx2).getReg();
1959 if (Op2Reg != MI.getOperand(CommutableOpIdx1).getReg())
2013 unsigned Imm = MI.getOperand(3 + OpOffset).getImm() & 0x7;
2042 if (MI.getOperand(3).getImm() == 0x02)
2131 if (!MI.getOperand(SrcOpIdx1).isReg() ||
2132 !MI.getOperand(SrcOpIdx2).isReg())
2172 if (!MI.getOperand(SrcOpIdx1).isReg() ||
2173 !MI.getOperand(SrcOpIdx2).isReg())
2189 MI.getOperand(MI.getDesc().getNumOperands() - 1).getImm());
2199 MI.getOperand(MI.getDesc().getNumOperands() - 1).getImm());
2210 MI.getOperand(MI.getDesc().getNumOperands() - 1).getImm());
2429 TailCall.getOperand(1).getImm() != 0) {
2462 MIB->addOperand(TailCall.getOperand(0)); // Destination.
3053 Dest = &MI.getOperand(0);
3054 Src = &MI.getOperand(1);
3205 BaseOp = &MemOp.getOperand(MemRefBegin + X86::AddrBaseReg);
3209 if (MemOp.getOperand(MemRefBegin + X86::AddrScaleAmt).getImm() != 1)
3212 if (MemOp.getOperand(MemRefBegin + X86::AddrIndexReg).getReg() !=
3216 const MachineOperand &DispMO = MemOp.getOperand(MemRefBegin + X86::AddrDisp);
3287 SrcReg = MI.getOperand(0).getReg();
3289 if (MI.getOperand(1).isImm()) {
3291 CmpValue = MI.getOperand(1).getImm();
3301 SrcReg = MI.getOperand(1).getReg();
3310 SrcReg = MI.getOperand(1).getReg();
3311 SrcReg2 = MI.getOperand(2).getReg();
3322 SrcReg = MI.getOperand(1).getReg();
3324 if (MI.getOperand(2).isImm()) {
3326 CmpValue = MI.getOperand(2).getImm();
3335 SrcReg = MI.getOperand(0).getReg();
3336 SrcReg2 = MI.getOperand(1).getReg();
3344 SrcReg = MI.getOperand(0).getReg();
3345 if (MI.getOperand(1).getReg() != SrcReg)
3370 ((OI.getOperand(1).getReg() == SrcReg &&
3371 OI.getOperand(2).getReg() == SrcReg2) ||
3372 (OI.getOperand(1).getReg() == SrcReg2 &&
3373 OI.getOperand(2).getReg() == SrcReg)))
3388 OI.getOperand(1).getReg() == SrcReg &&
3389 OI.getOperand(2).getImm() == ImmValue)
4347 const MachineOperand &MO = MI.getOperand(0);
4560 const MachineOperand &MO = MI.getOperand(OpNum);
5077 MF.getRegInfo().getRegClass(LoadMI.getOperand(0).getReg());
6595 if (MI.getOperand(NumOperands - 1).isImm()) {
6596 unsigned Imm = MI.getOperand(NumOperands - 1).getImm();
6657 if (RI.getEncodingValue(MI.getOperand(0).getReg()) >= 16)
6659 if (RI.getEncodingValue(MI.getOperand(1).getReg()) >= 16)
6663 RI.getEncodingValue(MI.getOperand(2).getReg()) >= 16)
6675 if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg() &&
6675 if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg() &&
6676 MI.getOperand(0).getSubReg() == 0 &&
6677 MI.getOperand(1).getSubReg() == 0 &&
6678 MI.getOperand(2).getSubReg() == 0)
7246 assert(Inst.getOperand(3).isReg() &&
7247 Inst.getOperand(3).getReg() == X86::EFLAGS &&
7249 if (!Inst.getOperand(3).isDead())
7572 if (!MI.getOperand(4).isImm() || !MI.getOperand(2).isImm())
7572 if (!MI.getOperand(4).isImm() || !MI.getOperand(2).isImm())
7575 const MachineOperand &Op1 = MI.getOperand(1);
7576 const MachineOperand &Op2 = MI.getOperand(3);
7583 if ((Op1.isReg() && Op1.getReg() == MI.getOperand(0).getReg()) ||
7584 Op2.getReg() == MI.getOperand(0).getReg())
7587 TRI->regsOverlap(Op1.getReg(), MI.getOperand(0).getReg())) ||
7589 TRI->regsOverlap(Op2.getReg(), MI.getOperand(0).getReg())))
7592 int64_t Coef = MI.getOperand(2).getImm();
7593 int64_t Offset = MI.getOperand(4).getImm();
7644 return ParamLoadedValue(MI.getOperand(1), Expr);
7646 if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg())
7646 if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg())
lib/Target/X86/X86InstrInfo.h 113 if (MI.getOperand(Op).isFI())
116 MI.getOperand(Op + X86::AddrBaseReg).isReg() &&
117 isScale(MI.getOperand(Op + X86::AddrScaleAmt)) &&
118 MI.getOperand(Op + X86::AddrIndexReg).isReg() &&
119 (MI.getOperand(Op + X86::AddrDisp).isImm() ||
120 MI.getOperand(Op + X86::AddrDisp).isGlobal() ||
121 MI.getOperand(Op + X86::AddrDisp).isCPI() ||
122 MI.getOperand(Op + X86::AddrDisp).isJTI());
126 if (MI.getOperand(Op).isFI())
129 MI.getOperand(Op + X86::AddrSegmentReg).isReg() && isLeaMem(MI, Op);
158 return I.getOperand(2).getImm();
159 return I.getOperand(1).getImm();
lib/Target/X86/X86InstructionSelector.cpp 475 assert(I.getOperand(0).isReg() && "unsupported opperand.");
476 assert(MRI.getType(I.getOperand(0).getReg()).isPointer() &&
480 if (auto COff = getConstantVRegVal(I.getOperand(2).getReg(), MRI)) {
484 AM.Base.Reg = I.getOperand(1).getReg();
489 AM.Base.FrameIndex = I.getOperand(1).getIndex();
495 AM.Base.Reg = I.getOperand(0).getReg();
lib/Target/X86/X86MCInstLower.cpp 905 MCInstLowering.GetSymbolFromOperand(MI.getOperand(3)), SRVK, Ctx);
1159 Register DefRegister = FaultingMI.getOperand(0).getReg();
1161 static_cast<FaultMaps::FaultKind>(FaultingMI.getOperand(1).getImm());
1162 MCSymbol *HandlerLabel = FaultingMI.getOperand(2).getMBB()->getSymbol();
1163 unsigned Opcode = FaultingMI.getOperand(3).getImm();
1202 unsigned MinSize = MI.getOperand(0).getImm();
1203 unsigned Opcode = MI.getOperand(1).getImm();
1240 unsigned NumShadowBytes = MI.getOperand(1).getImm();
1280 Register ScratchReg = MI.getOperand(ScratchIdx).getReg();
1351 if (auto Op = MCIL.LowerMachineOperand(&MI, MI.getOperand(I))) {
1446 if (auto Op = MCIL.LowerMachineOperand(&MI, MI.getOperand(I))) {
1543 unsigned OpCode = MI.getOperand(0).getImm();
1575 unsigned OpCode = MI.getOperand(0).getImm();
1637 const MachineOperand &DstOp = MI->getOperand(0);
1638 const MachineOperand &SrcOp1 = MI->getOperand(SrcOp1Idx);
1639 const MachineOperand &SrcOp2 = MI->getOperand(SrcOp2Idx);
1663 const MachineOperand &WriteMaskOp = MI->getOperand(SrcOp1Idx - 1);
1753 XTS->emitFPOPushReg(MI->getOperand(0).getImm());
1756 XTS->emitFPOStackAlloc(MI->getOperand(0).getImm());
1759 XTS->emitFPOStackAlign(MI->getOperand(0).getImm());
1762 assert(MI->getOperand(1).getImm() == 0 &&
1764 XTS->emitFPOSetFrame(MI->getOperand(0).getImm());
1783 OutStreamer->EmitWinCFIPushReg(MI->getOperand(0).getImm());
1787 OutStreamer->EmitWinCFISaveReg(MI->getOperand(0).getImm(),
1788 MI->getOperand(1).getImm());
1792 OutStreamer->EmitWinCFISaveXMM(MI->getOperand(0).getImm(),
1793 MI->getOperand(1).getImm());
1797 OutStreamer->EmitWinCFIAllocStack(MI->getOperand(0).getImm());
1801 OutStreamer->EmitWinCFISetFrame(MI->getOperand(0).getImm(),
1802 MI->getOperand(1).getImm());
1806 OutStreamer->EmitWinCFIPushFrame(MI->getOperand(0).getImm());
1854 Register Reg = MI->getOperand(0).getReg();
1899 int64_t Disp = MI->getOperand(1 + X86::AddrDisp).getImm();
1901 Register Reg = MI->getOperand(0).getReg();
1909 auto Op = MCInstLowering.LowerMachineOperand(MI, MI->getOperand(1 + i));
1921 auto Op = MCInstLowering.LowerMachineOperand(MI, MI->getOperand(1 + i));
1930 int64_t Disp = MI->getOperand(X86::AddrDisp).getImm();
1932 Register Reg = MI->getOperand(X86::AddrNumOperands).getReg();
1939 MIB.addOperand(MCInstLowering.LowerMachineOperand(MI, MI->getOperand(i)).getValue());
1949 auto Op = MCInstLowering.LowerMachineOperand(MI, MI->getOperand(0 + i));
1992 MCInstBuilder(X86::POP32r).addReg(MI->getOperand(0).getReg()));
2002 if (MI->getOperand(2).getTargetFlags() != X86II::MO_GOT_ABSOLUTE_ADDRESS)
2016 MCSymbol *OpSym = MCInstLowering.GetSymbolFromOperand(MI->getOperand(2));
2027 .addReg(MI->getOperand(0).getReg())
2028 .addReg(MI->getOperand(1).getReg())
2145 const MachineOperand &MaskOp = MI->getOperand(MaskIdx);
2217 const MachineOperand &MaskOp = MI->getOperand(MaskIdx);
2237 const MachineOperand &CtrlOp = MI->getOperand(MI->getNumOperands() - 1);
2248 const MachineOperand &MaskOp = MI->getOperand(6);
2265 const MachineOperand &MaskOp = MI->getOperand(6);
2281 if (auto *C = getConstantFromPool(*MI, MI->getOperand(4))) {
2284 const MachineOperand &DstOp = MI->getOperand(0);
2343 if (auto *C = getConstantFromPool(*MI, MI->getOperand(4))) {
2365 const MachineOperand &DstOp = MI->getOperand(0);
2436 if (auto *C = getConstantFromPool(*MI, MI->getOperand(4))) {
2475 const MachineOperand &DstOp = MI->getOperand(0);
lib/Target/X86/X86OptimizeLEAs.cpp 191 return MemOpKey(&MI.getOperand(N + X86::AddrBaseReg),
192 &MI.getOperand(N + X86::AddrScaleAmt),
193 &MI.getOperand(N + X86::AddrIndexReg),
194 &MI.getOperand(N + X86::AddrSegmentReg),
195 &MI.getOperand(N + X86::AddrDisp));
394 const MachineOperand &Op1 = MI1.getOperand(N1 + X86::AddrDisp);
395 const MachineOperand &Op2 = MI2.getOperand(N2 + X86::AddrDisp);
425 if (MRI->getRegClass(First.getOperand(0).getReg()) !=
426 MRI->getRegClass(Last.getOperand(0).getReg()))
435 for (auto &MO : MRI->use_nodbg_operands(Last.getOperand(0).getReg())) {
lib/Target/X86/X86RegisterBankInfo.cpp 116 auto &MO = MI.getOperand(Idx);
131 if (!MI.getOperand(Idx).isReg())
150 LLT Ty = MRI.getType(MI.getOperand(0).getReg());
152 if (NumOperands != 3 || (Ty != MRI.getType(MI.getOperand(1).getReg())) ||
153 (Ty != MRI.getType(MI.getOperand(2).getReg())))
188 LLT Ty = MRI.getType(MI.getOperand(0).getReg());
212 auto &Op0 = MI.getOperand(0);
213 auto &Op1 = MI.getOperand(1);
224 LLT Ty1 = MRI.getType(MI.getOperand(2).getReg());
225 LLT Ty2 = MRI.getType(MI.getOperand(3).getReg());
241 auto &Op0 = MI.getOperand(0);
242 auto &Op1 = MI.getOperand(1);
289 unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, TRI);
lib/Target/XCore/XCoreAsmPrinter.cpp 188 unsigned JTI = MI->getOperand(opNum).getIndex();
205 const MachineOperand &MO = MI->getOperand(opNum);
267 if (MI->getOperand(2).getImm() == 0) {
269 << XCoreInstPrinter::getRegisterName(MI->getOperand(0).getReg()) << ", "
270 << XCoreInstPrinter::getRegisterName(MI->getOperand(1).getReg());
278 << XCoreInstPrinter::getRegisterName(MI->getOperand(1).getReg()) << '\n';
lib/Target/XCore/XCoreInstrInfo.cpp 67 if ((MI.getOperand(1).isFI()) && // is a stack slot
68 (MI.getOperand(2).isImm()) && // the imm is zero
69 (isZeroImm(MI.getOperand(2)))) {
70 FrameIndex = MI.getOperand(1).getIndex();
71 return MI.getOperand(0).getReg();
87 if ((MI.getOperand(1).isFI()) && // is a stack slot
88 (MI.getOperand(2).isImm()) && // the imm is zero
89 (isZeroImm(MI.getOperand(2)))) {
90 FrameIndex = MI.getOperand(1).getIndex();
91 return MI.getOperand(0).getReg();
lib/Target/XCore/XCoreMCInstLower.cpp 107 const MachineOperand &MO = MI->getOperand(i);