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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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Declarations
include/llvm/CodeGen/MachineOperand.h 462 void setReg(Register Reg);
References
include/llvm/CodeGen/MachineRegisterInfo.h 828 MI->getOperand(0).setReg(Reg);
lib/CodeGen/AggressiveAntiDepBreaker.cpp 976 Q.second.Operand->setReg(NewReg);
lib/CodeGen/AntiDepBreaker.h 62 MI.getOperand(0).setReg(NewReg);
lib/CodeGen/BreakFalseDeps.cpp 136 MO.setReg(CurrMO.getReg());
158 MO.setReg(MaxClearanceReg);
lib/CodeGen/CriticalAntiDepBreaker.cpp 657 Q->second->setReg(NewReg);
lib/CodeGen/EarlyIfConversion.cpp 608 PI.PHI->getOperand(i-2).setReg(DstReg);
lib/CodeGen/GlobalISel/CombinerHelper.cpp 60 FromRegOp.setReg(ToReg);
437 UseMO.setReg(PreviouslyEmitted->getOperand(0).getReg());
529 MI.getOperand(0).setReg(ChosenDstReg);
lib/CodeGen/GlobalISel/LegalizerHelper.cpp 1002 MO1.setReg(TruncMIB->getOperand(0).getReg());
1008 MO2.setReg(DstExt);
1085 MO.setReg(ExtB->getOperand(0).getReg());
1093 MO.setReg(ExtB->getOperand(0).getReg());
1102 MO.setReg(DstExt);
1111 MO.setReg(DstTrunc);
1120 MO.setReg(DstExt);
1143 MO.setReg(Concat.getReg(0));
1150 MO.setReg(MoreReg);
1306 MI.getOperand(NumDst).setReg(WideSrc->getOperand(0).getReg());
1499 MI.getOperand(0).setReg(DstExt);
1524 MI.getOperand(0).setReg(DstExt);
3781 MI.getOperand(1).setReg(MIBTmp->getOperand(0).getReg());
lib/CodeGen/GlobalISel/Localizer.cpp 156 LocalizedMI->getOperand(0).setReg(NewReg);
164 MOUse.setReg(NewVRegIt->second);
lib/CodeGen/GlobalISel/RegisterBankInfo.cpp 465 MO.setReg(NewReg);
lib/CodeGen/GlobalISel/Utils.cpp 144 MO.setReg(constrainOperandRegClass(MF, TRI, MRI, TII, RBI, I, I.getDesc(),
lib/CodeGen/InlineSpiller.cpp 625 MO.setReg(NewVReg);
1044 MO.setReg(NewVReg);
lib/CodeGen/LiveDebugVariables.cpp 1194 Loc.setReg(0);
lib/CodeGen/LiveInterval.cpp 1376 MO.setReg(LIV[EqClass-1]->reg);
lib/CodeGen/MIRCanonicalizerPass.cpp 344 MO->setReg(Src);
438 MO->setReg(Rename);
lib/CodeGen/MIRVRegNamerUtils.cpp 243 MO->setReg(Rename);
lib/CodeGen/MachineCSE.cpp 202 MO.setReg(SrcReg);
833 NewMI.getOperand(0).setReg(NewReg);
lib/CodeGen/MachineCopyPropagation.cpp 445 MOUse.setReg(CopySrcReg);
lib/CodeGen/MachineInstr.cpp 2142 DBI->getOperand(0).setReg(Reg);
lib/CodeGen/MachineLoopUtils.cpp 56 MO.setReg(R);
68 Use->setReg(R);
77 MO.setReg(Remaps[MO.getReg()]);
92 OrigPhi.getOperand(InitRegIdx).setReg(R);
99 MI.getOperand(LoopRegIdx).setReg(LoopReg);
lib/CodeGen/MachineOperand.cpp 79 setReg(Reg);
94 setReg(Reg);
lib/CodeGen/MachinePipeliner.cpp 372 RegOp.setReg(NewReg);
2169 NewMI->getOperand(BasePos).setReg(RegAndOffset.first);
2779 NewMI->getOperand(BasePos).setReg(NewBaseReg);
lib/CodeGen/MachineRegisterInfo.cpp 392 O.setReg(ToReg);
553 UseMI->getOperand(0).setReg(0U);
lib/CodeGen/MachineSSAUpdater.cpp 233 U.setReg(NewVR);
lib/CodeGen/MachineSink.cpp 800 DbgMI->getOperand(0).setReg(0);
831 DbgMI->getOperand(0).setReg(SrcMO->getReg());
1013 User->getOperand(0).setReg(MI.getOperand(1).getReg());
lib/CodeGen/ModuloSchedule.cpp 343 O.setReg(ToReg);
1034 MO.setReg(NewReg);
1050 MO.setReg(VRMap[StageNum][reg]);
1184 UseOp.setReg(ReplaceReg);
1323 MO.setReg(Reg);
1473 MI->getOperand(1).setReg(InitReg.getValue());
lib/CodeGen/PeepholeOptimizer.cpp 593 UseMO->setReg(NewVR);
856 MOSrc.setReg(NewReg);
946 MO.setReg(NewReg);
993 CopyLike.getOperand(CurrentSrcIdx).setReg(NewReg);
1073 MO.setReg(NewReg);
lib/CodeGen/RegAllocFast.cpp 772 MO.setReg(PhysReg);
859 MO.setReg(PhysReg);
865 MO.setReg(PhysReg ? TRI->getSubReg(PhysReg, MO.getSubReg()) : Register());
1237 MO.setReg(0);
lib/CodeGen/RegisterCoalescer.cpp 870 UseMO.setReg(NewReg);
883 UseMO.setReg(NewReg);
1486 UseMO.setReg(DstReg);
lib/CodeGen/RenameIndependentSubregs.cpp 245 MO.setReg(VReg);
253 MI->getOperand(TiedIdx).setReg(VReg);
lib/CodeGen/SplitKit.cpp 1323 MO.setReg(0);
1337 MO.setReg(LI.reg);
lib/CodeGen/TailDuplicator.cpp 393 MO.setReg(NewReg);
424 MO.setReg(VI->second.Reg);
442 MO.setReg(NewReg);
513 MI.getOperand(Idx).setReg(SrcReg);
525 MI.getOperand(Idx).setReg(Reg);
lib/CodeGen/TargetInstrInfo.cpp 217 CommutedMI->getOperand(0).setReg(Reg0);
220 CommutedMI->getOperand(Idx2).setReg(Reg1);
221 CommutedMI->getOperand(Idx1).setReg(Reg2);
335 MO.setReg(Pred[j].getReg());
lib/CodeGen/TwoAddressInstructionPass.cpp 1489 SrcMO.setReg(DstReg);
1602 MO.setReg(RegA);
1623 MO.setReg(LastCopiedReg);
lib/CodeGen/VirtRegMap.cpp 569 MO.setReg(PhysReg);
lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp 556 U.setReg(Substs[OrigReg]);
582 MO.setReg(Reg);
lib/Target/AArch64/AArch64CallLowering.cpp 911 MIB->getOperand(0).setReg(constrainOperandRegClass(
997 MIB->getOperand(0).setReg(constrainOperandRegClass(
lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp 174 MO.setReg(NewReg);
lib/Target/AArch64/AArch64FalkorHWPFFix.cpp 775 BaseOpnd.setReg(ScratchReg);
782 MI.getOperand(0).setReg(
lib/Target/AArch64/AArch64InstructionSelector.cpp 602 RegOp.setReg(SubRegCopy.getReg(0));
731 RegOp.setReg(PromoteReg);
1186 I.getOperand(2).setReg(Trunc.getReg(0));
1272 I.getOperand(0).setReg(DefDstReg);
1554 RegOp.setReg(DefGPRReg);
1634 I.getOperand(0).setReg(DstReg);
1669 I.getOperand(2).setReg(SrcReg);
1775 I.getOperand(1).setReg(Ptr2Reg);
1793 I.getOperand(0).setReg(AArch64::WZR);
1795 I.getOperand(0).setReg(AArch64::XZR);
1807 I.getOperand(0).setReg(LdReg);
2052 I.getOperand(1).setReg(ExtSrc);
3841 InsMI->getOperand(0).setReg(DstReg);
3911 RegOp.setReg(Reg);
3917 PrevMI->getOperand(0).setReg(I.getOperand(0).getReg());
lib/Target/AArch64/AArch64LegalizerInfo.cpp 679 MI.getOperand(2).setReg(ExtCst.getReg(0));
lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp 908 DstMO.setReg(DstRegW);
lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp 1711 MI.getOperand(1).setReg(Cast.getReg(0));
2090 MI.getOperand(1).setReg(AnyExt);
2097 MI.getOperand(1).setReg(handleD16VData(B, MRI, VData));
lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp 963 O.setReg(NewRegister);
2249 O.setReg(NewRegister);
lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp 796 Op.setReg(CurrentLaneOpReg);
907 Op.setReg(Merge.getReg(0));
910 Op.setReg(Merge.getReg(0));
1017 MI.getOperand(OpIdx).setReg(SGPR);
1096 LegalizedInst->getOperand(0).setReg(TmpReg);
1144 OpdMapper.getMI().getOperand(OpIdx).setReg(SrcReg[0]);
lib/Target/AMDGPU/R600ControlFlowFinalizer.cpp 384 Src.first->setReg(LiteralRegs[Index]);
388 Src.first->setReg(LiteralRegs[Lits.size()]);
lib/Target/AMDGPU/R600EmitClauseMarkers.cpp 178 Consts[i].first->setReg(
182 Consts[i].first->setReg(
lib/Target/AMDGPU/R600ExpandSpecialInstrs.cpp 103 DstOp.setReg(R600::OQAP);
109 Mov->getOperand(MovPredSelIdx).setReg(
lib/Target/AMDGPU/R600InstrInfo.cpp 955 MO2.setReg(R600::PRED_SEL_ONE);
958 MO2.setReg(R600::PRED_SEL_ZERO);
982 .setReg(Pred[2].getReg());
984 .setReg(Pred[2].getReg());
986 .setReg(Pred[2].getReg());
988 .setReg(Pred[2].getReg());
996 PMO.setReg(Pred[2].getReg());
1352 .setReg(MO.getReg());
lib/Target/AMDGPU/R600Packetizer.cpp 142 MI.getOperand(OperandIdx).setReg(It->second);
lib/Target/AMDGPU/SIFixSGPRCopies.cpp 284 MI.getOperand(0).setReg(CopyUse.getOperand(0).getReg());
315 MI.getOperand(I).setReg(TmpReg);
628 MI.getOperand(1).setReg(TmpReg);
lib/Target/AMDGPU/SIFoldOperands.cpp 273 Dst0.setReg(NewReg0);
605 SOff->setReg(MFI->getStackPtrOffsetReg());
676 UseMI->getOperand(1).setReg(UseReg);
812 UseMI->getOperand(1).setReg(OpToFold.getReg());
lib/Target/AMDGPU/SIInstrInfo.cpp 2401 Src0->setReg(Src1Reg);
4263 SBase->setReg(SGPR);
4268 SOff->setReg(SGPR);
4292 Op.setReg(DstReg);
4370 Rsrc.setReg(SRsrc);
4639 Src.setReg(readlaneVGPRToSGPR(Src.getReg(), MI, MRI));
4654 SRsrc->setReg(SGPR);
4660 SSamp->setReg(SGPR);
4732 VAddr->setReg(NewVAddr);
4733 Rsrc->setReg(NewSRsrc);
5077 Inst.getOperand(0).setReg(DstReg);
6252 Op.setReg(AMDGPU::VCC_LO);
lib/Target/AMDGPU/SILoadStoreOptimizer.cpp 1432 TII->getNamedOperand(MI, AMDGPU::OpName::vaddr)->setReg(NewBase);
lib/Target/AMDGPU/SILowerI1Copies.cpp 707 MI.getOperand(1).setReg(TmpReg);
lib/Target/AMDGPU/SIOptimizeExecMasking.cpp 309 PrepareExecInst->getOperand(0).setReg(Exec);
lib/Target/AMDGPU/SIPeepholeSDWA.cpp 277 To.setReg(From.getReg());
lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp 141 MO.setReg(PhysReg);
lib/Target/AMDGPU/SIRegisterInfo.cpp 1209 TII->getNamedOperand(*MI, AMDGPU::OpName::soffset)->setReg(FrameReg);
lib/Target/AMDGPU/SIShrinkInstructions.cpp 296 MI.getOperand(VAddr0Idx).setReg(RC->getRegister(VgprBase));
lib/Target/ARC/ARCOptAddrMode.cpp 383 MI->getOperand(BasePos).setReg(NewBase);
lib/Target/ARM/ARMBaseInstrInfo.cpp 513 MI.getOperand(PIdx+1).setReg(Pred[1].getReg());
1625 MI.getOperand(0).setReg(DstRegD);
1626 MI.getOperand(1).setReg(SrcRegD);
3166 MI->getOperand(5).setReg(ARM::CPSR);
3325 UseMI.getOperand(1).setReg(NewReg);
lib/Target/ARM/ARMCallLowering.cpp 534 MIB->getOperand(CalleeIdx).setReg(constrainOperandRegClass(
lib/Target/ARM/ARMConstantIslandPass.cpp 2308 NewJTMI->getOperand(0).setReg(ARM::PC);
lib/Target/ARM/ARMISelLowering.cpp10219 MIB->getOperand(5).setReg(ARM::CPSR);
10809 MO.setReg(ARM::CPSR);
lib/Target/ARM/ARMInstructionSelector.cpp 690 MIB->getOperand(0).setReg(AddressReg);
880 I.getOperand(0).setReg(AndResult);
1102 I.getOperand(0).setReg(ValueToStore);
lib/Target/ARM/ARMLoadStoreOptimizer.cpp 1950 MO.setReg(ARM::PC);
lib/Target/AVR/AVRFrameLowering.cpp 355 MI.getOperand(0).setReg(AVR::R29R28);
lib/Target/BPF/BPFMISimplifyPatchable.cpp 135 I->setReg(SrcReg);
lib/Target/Hexagon/HexagonBitSimplify.cpp 362 I->setReg(NewR);
377 I->setReg(NewR);
395 I->setReg(NewR);
1929 ValOp.setReg(H.Reg);
lib/Target/Hexagon/HexagonConstPropagation.cpp 3119 O.setReg(ToReg);
lib/Target/Hexagon/HexagonExpandCondsets.cpp 923 Op.setReg(RN.Reg);
lib/Target/Hexagon/HexagonFrameLowering.cpp 2284 SrcOp.setReg(HRI.getSubReg(FoundR, SR));
2286 SrcOp.setReg(FoundR);
lib/Target/Hexagon/HexagonHardwareLoops.cpp 1105 UseMI->getOperand(0).setReg(0U);
1593 MO.setReg(NewR);
1793 IndMO->setReg(I->first);
1794 nonIndMO->setReg(nonIndI->getOperand(1).getReg());
1837 MO.setReg(I->first);
lib/Target/Hexagon/HexagonInstrInfo.cpp 747 Loop->getOperand(1).setReg(NewLoopCount);
lib/Target/Hexagon/HexagonOptAddrMode.cpp 421 BaseOp.setReg(newReg);
lib/Target/Hexagon/HexagonPeephole.cpp 249 MI.getOperand(0).setReg(PeepholeSrc);
lib/Target/Hexagon/HexagonSplitDouble.cpp 1089 Op.setReg(P.first);
1092 Op.setReg(P.second);
1122 Op.setReg(NewDR);
lib/Target/Hexagon/RDFCopy.cpp 180 Op.setReg(NewReg);
lib/Target/Mips/MipsInstructionSelector.cpp 346 LW->getOperand(0).setReg(DestTmp);
575 LWGOT->getOperand(0).setReg(LWGOTDef);
lib/Target/Mips/MipsOptimizePICCall.cpp 158 I->getOperand(0).setReg(DstReg);
249 getCallTargetRegOpnd(*I)->setReg(getReg(Entry));
lib/Target/Mips/MipsSEISelDAGToDAG.cpp 121 MO.setReg(ZeroReg);
lib/Target/NVPTX/NVPTXProxyRegErasure.cpp 114 Op.setReg(To.getReg());
lib/Target/PowerPC/PPCFrameLowering.cpp 579 MO.setReg(FPReg);
582 MO.setReg(FP8Reg);
585 MO.setReg(BPReg);
588 MO.setReg(BP8Reg);
lib/Target/PowerPC/PPCInstrInfo.cpp 436 MI.getOperand(0).setReg(Reg2);
439 MI.getOperand(2).setReg(Reg1);
440 MI.getOperand(1).setReg(Reg2);
1384 UseMI.getOperand(UseIdx).setReg(ZeroReg);
lib/Target/PowerPC/PPCMIPeephole.cpp 407 MI.getOperand(1).setReg(DefMI->getOperand(1).getReg());
408 MI.getOperand(2).setReg(DefMI->getOperand(2).getReg());
429 DefMI->getOperand(0).setReg(MI.getOperand(0).getReg());
499 MI.getOperand(1).setReg(ShiftOp1);
541 Use.getOperand(i).setReg(ConvReg1);
601 SrcMI->getOperand(0).setReg(MI.getOperand(0).getReg());
645 SrcMI->getOperand(0).setReg(MI.getOperand(0).getReg());
1274 CMPI2->getOperand(1).setReg(Op2);
1275 CMPI2->getOperand(2).setReg(Op1);
1289 CMPI2->getOperand(I).setReg(SrcReg);
1301 BI2->getOperand(1).setReg(NewVReg);
1305 BI2->getOperand(1).setReg(BI1->getOperand(1).getReg());
1374 MI.getOperand(1).setReg(SrcMI->getOperand(1).getReg());
lib/Target/PowerPC/PPCQPXLoadSplat.cpp 109 MI->getOperand(0).setReg(SplatSubReg);
lib/Target/PowerPC/PPCReduceCRLogicals.cpp 234 FirstTerminator->getOperand(0).setReg(BSI.NewCond->getOperand(0).getReg());
lib/Target/PowerPC/PPCVSXCopy.cpp 114 SrcMO.setReg(NewVReg);
133 SrcMO.setReg(NewVReg);
lib/Target/PowerPC/PPCVSXFMAMutate.cpp 245 MI.getOperand(0).setReg(KilledProdReg);
246 MI.getOperand(1).setReg(KilledProdReg);
247 MI.getOperand(3).setReg(AddendSrcReg);
264 MI.getOperand(2).setReg(AddendSrcReg);
269 MI.getOperand(2).setReg(OtherProdReg);
lib/Target/PowerPC/PPCVSXSwapRemoval.cpp 874 MI->getOperand(1).setReg(Reg2);
875 MI->getOperand(2).setReg(Reg1);
901 MI->getOperand(0).setReg(NewVReg);
lib/Target/RISCV/RISCVMergeBaseOffset.cpp 250 Tail.getOperand(1).setReg(HiLUI.getOperand(0).getReg());
lib/Target/Sparc/DelaySlotFiller.cpp 396 AddMI->getOperand(0).setReg(reg - SP::I0 + SP::O0);
435 OrMI->getOperand(0).setReg(reg - SP::I0 + SP::O0);
469 RestoreMI->getOperand(0).setReg(reg - SP::I0 + SP::O0);
470 RestoreMI->getOperand(1).setReg(SP::G0);
lib/Target/Sparc/SparcRegisterInfo.cpp 193 MI.getOperand(2).setReg(SrcOddReg);
206 MI.getOperand(0).setReg(DestOddReg);
lib/Target/SystemZ/SystemZInstrInfo.cpp 81 HighRegOp.setReg(RI.getSubReg(HighRegOp.getReg(), SystemZ::subreg_h64));
82 LowRegOp.setReg(RI.getSubReg(LowRegOp.getReg(), SystemZ::subreg_l64));
165 MI.getOperand(1).setReg(DestReg);
lib/Target/SystemZ/SystemZPostRewrite.cpp 125 MBBI->getOperand(1).setReg(DestReg);
132 MBBI->getOperand(2).setReg(DestReg);
230 SrcMO.setReg(DstReg);
lib/Target/SystemZ/SystemZShortenInst.cpp 96 MI.getOperand(0).setReg(SystemZMC::getRegAsGR64(Reg));
101 MI.getOperand(0).setReg(SystemZMC::getRegAsGR64(Reg));
lib/Target/WebAssembly/WebAssemblyDebugValueManager.cpp 33 DBI->getOperand(0).setReg(Reg);
42 Clone->getOperand(0).setReg(NewReg);
lib/Target/WebAssembly/WebAssemblyExplicitLocals.cpp 251 MI.getOperand(2).setReg(NewReg);
297 MI.getOperand(0).setReg(NewReg);
353 MO.setReg(NewReg);
lib/Target/WebAssembly/WebAssemblyMemIntrinsicResults.cpp 122 O.setReg(ToReg);
lib/Target/WebAssembly/WebAssemblyPeephole.cpp 67 MO.setReg(NewReg);
123 MO.setReg(NewReg);
lib/Target/WebAssembly/WebAssemblyRegStackify.cpp 503 Def->getOperand(0).setReg(NewReg);
504 Op.setReg(NewReg);
540 Op.setReg(NewReg);
617 Op.setReg(TeeReg);
618 DefMO.setReg(DefReg);
lib/Target/WebAssembly/WebAssemblyReplacePhysRegs.cpp 93 MO.setReg(VReg);
lib/Target/X86/X86CallLowering.cpp 451 MIB->getOperand(0).setReg(constrainOperandRegClass(
lib/Target/X86/X86CmovConversion.cpp 788 MOp.setReg(It->second);
lib/Target/X86/X86FastISel.cpp 3964 MO.setReg(IndexReg);
lib/Target/X86/X86FloatingPoint.cpp 1395 MI.getOperand(0).setReg(getSTReg(Op1));
1422 MI.getOperand(0).setReg(getSTReg(Op1));
1640 Op.setReg(getSTReg(FPReg));
1643 Op.setReg(X86::ST0 + FPReg);
lib/Target/X86/X86InstrBuilder.h 137 MI->getOperand(Operand + 2).setReg(0);
139 MI->getOperand(Operand + 4).setReg(0);
lib/Target/X86/X86InstrInfo.cpp 3954 .setReg(getX86SubSuperRegister(MIB->getOperand(0).getReg(), 64));
4034 MIB->getOperand(0).setReg(DestReg);
4057 MIB->getOperand(X86::AddrNumOperands).setReg(SrcReg);
4110 MIB->getOperand(0).setReg(XReg);
4128 MIB->getOperand(0).setReg(SrcReg);
4138 MIB->getOperand(0).setReg(XReg);
4148 MIB->getOperand(0).setReg(ZReg);
4215 MIB->getOperand(0).setReg(Reg32);
4930 NewMI->getOperand(0).setReg(RI.getSubReg(DstReg, X86::sub_32bit));
lib/Target/X86/X86InstructionSelector.cpp 260 I.getOperand(1).setReg(ExtSrc);
lib/Target/X86/X86OptimizeLEAs.cpp 640 MO.setReg(FirstVReg);
lib/Target/X86/X86SpeculativeLoadHardening.cpp 2012 Op->setReg(It->second);
2139 Op->setReg(TmpReg);
2342 DefOp.setReg(UnhardenedReg);
2636 TargetOp.setReg(HardenedTargetReg);