|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/AArch64/AArch64GenGlobalISel.inc 9461 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
9470 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
9485 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
9496 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
9507 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
9518 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
9529 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
9540 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
9552 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
9571 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
9590 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
9609 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
9628 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
9645 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
9655 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
9665 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
9675 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
9685 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
9695 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
9706 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9720 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9734 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9748 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9762 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9830 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9843 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9857 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9871 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9885 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9899 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9913 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9981 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9994 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10008 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10022 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10036 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10050 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10064 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10132 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10145 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10161 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10175 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10189 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10203 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10217 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10231 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10245 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10423 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
10434 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
10446 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
10465 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
10483 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10497 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10511 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10525 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10539 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10553 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10632 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10646 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10660 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10674 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10688 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10702 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10716 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10795 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10811 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10825 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10839 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10853 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10867 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10881 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10965 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10979 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10993 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11007 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11021 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11035 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11049 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11133 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11147 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11161 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11175 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11189 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11203 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11217 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11231 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11245 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11259 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11273 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11287 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11301 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11317 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
11328 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
11340 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
11359 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
11377 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11391 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11405 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11419 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11433 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11447 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11526 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11540 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11554 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11568 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11582 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11596 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11610 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11689 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11705 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11719 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11733 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11747 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11761 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11775 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11869 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11883 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11897 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11911 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11925 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11939 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11953 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12047 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12061 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12075 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12089 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12103 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12117 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12131 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12145 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12159 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12173 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12187 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12201 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12215 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12231 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
12243 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
12261 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12275 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12289 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12303 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12317 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12331 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12345 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12438 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12452 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12466 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12480 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12494 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12508 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12602 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12616 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12630 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12644 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12658 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12672 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12686 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12780 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12794 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12808 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12822 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12836 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12850 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12864 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12878 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12892 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12906 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12920 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12934 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12948 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12964 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12978 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12992 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
13006 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
13020 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
13034 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
13048 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
13154 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
13168 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
13182 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
13196 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
13210 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
13224 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
25861 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
27538 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
27567 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
27596 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
27625 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
36438 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
36471 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
36504 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
36537 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
36570 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
36603 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
36702 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
36725 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
36749 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
36776 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
36803 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
36851 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
36878 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
36905 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
37055 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
38052 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
38057 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
38094 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
38099 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
38136 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
38141 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
38200 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
38205 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
38242 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
38247 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
38284 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
38289 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
38358 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
38388 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
gen/lib/Target/AMDGPU/AMDGPUGenDAGISel.inc34034 /* 72275*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::COPY), 0,
34039 /* 72284*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::COPY), 0,
57413 /*125562*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::COPY), 0,
63150 /*137845*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::COPY), 0,
63191 /*137947*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::COPY), 0,
63332 /*138238*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::COPY), 0,
77146 /*171529*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::COPY), 0,
77158 /*171549*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::COPY), 0,
77173 /*171581*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::COPY), 0,
77286 /*171842*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::COPY), 0,
77303 /*171876*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::COPY), 0,
78429 /*174366*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::COPY), 0,
78445 /*174400*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::COPY), 0,
gen/lib/Target/AMDGPU/AMDGPUGenGlobalISel.inc 1545 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1557 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1569 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1581 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1598 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1611 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1624 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1637 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1650 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1663 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1676 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1689 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1704 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1717 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1730 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1743 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1756 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1769 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1782 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1795 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1808 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1821 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1836 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1849 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1862 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1875 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1888 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1901 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1916 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1929 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1942 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1955 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1968 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1981 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
1994 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
2007 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
2020 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
2033 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
2046 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
2061 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
2074 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
2087 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
2100 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
2113 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
2129 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
2139 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
2156 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
2169 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
2182 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
2195 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
2208 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
2221 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
2234 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
2247 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
2260 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
2273 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
2288 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
2301 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
2314 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
2327 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
2340 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
2356 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
2366 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
2384 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
2396 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
2408 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
2420 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
2438 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
2448 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
2466 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
2476 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
14575 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
14601 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
14627 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
14656 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
15460 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
15477 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
17914 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
17924 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
17951 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
17961 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
18750 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
18760 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
gen/lib/Target/ARM/ARMGenGlobalISel.inc 5499 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
5503 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
5515 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
5581 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
5585 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
5597 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
5643 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
5647 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
5659 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
7243 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
7247 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
7259 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
7325 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
7329 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
7341 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
7387 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
7391 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
7403 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
7675 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
7679 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
7691 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
7757 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
7761 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
7773 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
7819 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
7823 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
7835 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8055 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8069 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8083 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8097 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8111 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8125 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8139 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8153 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8167 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8181 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8195 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8209 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8385 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8399 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8413 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8427 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8441 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8455 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8469 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8483 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8497 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8511 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8525 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8539 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8715 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8729 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8743 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8757 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8771 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8785 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8799 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8813 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8827 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8841 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8855 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
8869 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9043 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9057 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9071 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9085 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9099 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9113 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9127 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9141 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9155 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9169 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9183 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9197 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9413 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9427 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9441 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9455 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9469 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9483 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9497 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9511 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9525 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9539 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9553 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9567 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9743 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9757 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9771 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9785 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9799 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9813 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9827 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9841 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9855 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9869 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9883 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
9897 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10071 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10085 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10099 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10113 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10127 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10141 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10155 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10169 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10183 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10197 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10211 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10225 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10441 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10455 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10469 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10483 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10497 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10511 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10623 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10637 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10651 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10665 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10679 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10693 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10707 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10721 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10735 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10749 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10763 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10777 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10951 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10965 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10979 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10993 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11007 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11021 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11035 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11049 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11063 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11077 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11091 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11105 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11321 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11335 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11349 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11363 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11377 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11391 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11501 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11515 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11529 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11543 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11557 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11571 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
22843 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
22875 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
22907 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
27059 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
27098 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
27133 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
27154 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
27208 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
27231 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
27254 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
27277 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
27300 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
27323 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
27344 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
27365 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
27386 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
27578 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
27601 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
27624 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
27647 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
27670 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
27693 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
27714 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
27735 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
27756 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
27940 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
27963 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
27986 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
28136 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
28159 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
28182 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
gen/lib/Target/Mips/MipsGenGlobalISel.inc 2911 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
2922 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
2933 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
2944 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
2984 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
2993 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3007 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3017 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3027 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3037 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3047 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3057 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3067 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3077 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3087 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3097 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3107 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3117 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3131 GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::COPY,
3140 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3149 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3166 GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::COPY,
3175 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3184 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3199 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3208 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3223 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3232 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3247 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3256 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3271 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3280 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3295 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3304 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3319 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3328 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3343 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3352 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3367 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3376 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3393 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3402 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3416 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3426 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3436 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3446 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3456 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3466 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3476 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3486 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3496 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3506 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3516 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3526 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3538 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3547 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3562 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3571 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3586 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3595 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3610 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3619 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3634 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3643 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3658 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3667 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3682 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3691 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3706 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3715 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3730 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3739 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3754 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3763 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3778 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3788 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3798 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3808 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3818 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3828 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3838 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
3850 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3859 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3874 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3883 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3898 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3907 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3922 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3931 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3946 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3955 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3970 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3979 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3994 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
4003 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
4018 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
4027 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
4042 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
4051 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
4066 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
4075 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
4090 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
4100 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
4110 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
4120 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
4130 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
4140 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
4152 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
4161 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
4176 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
4185 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
4200 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
4209 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
4224 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
4233 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
4250 GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::COPY,
4259 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
4268 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
4285 GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::COPY,
4294 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
4303 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
12283 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
13019 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
13268 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
13497 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
gen/lib/Target/X86/X86GenFastISel.inc 6952 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TargetOpcode::COPY), X86::AL).addReg(Op0);
7435 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TargetOpcode::COPY), X86::CL).addReg(Op1);
7537 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TargetOpcode::COPY), X86::CL).addReg(Op1);
7699 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TargetOpcode::COPY), X86::CL).addReg(Op1);
8025 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TargetOpcode::COPY), X86::CL).addReg(Op1);
8041 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TargetOpcode::COPY), X86::CL).addReg(Op1);
gen/lib/Target/X86/X86GenGlobalISel.inc 2582 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
2586 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
2595 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
2616 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
2620 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
2629 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
2644 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
2648 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
2657 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
2997 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
3017 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
3475 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
3479 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3488 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3548 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
3552 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3561 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
3671 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
3675 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
3684 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
4038 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
4042 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
4051 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
5049 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
5053 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
5062 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
5122 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
5126 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
5135 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
5245 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
5249 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
5258 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
5619 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
5623 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
5632 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
5653 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
5657 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
5666 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
5687 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
5691 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
5700 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
5715 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
5719 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
5728 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
6371 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
6375 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
6384 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
6444 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
6448 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
6457 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
6567 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
6571 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
6580 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
7046 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
7124 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
7149 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
7177 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
7192 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
7204 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
9417 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
10010 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
10013 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
10077 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
10080 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
10083 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
10103 GIR_BuildMI, /*InsnID*/3, /*Opcode*/TargetOpcode::COPY,
10106 GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
10109 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
10130 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
10153 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
10176 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
10199 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
10240 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10257 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10594 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10609 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
10625 GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
11749 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
11800 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
11877 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
11954 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
12012 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
12062 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
12138 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
12214 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
12272 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
12322 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
12398 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
12474 GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
13959 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
14010 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
14021 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
14092 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
14103 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
14154 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h 464 case TargetOpcode::COPY:
503 assert((TmpDef->getOpcode() == TargetOpcode::COPY ||
include/llvm/CodeGen/GlobalISel/MIPatternMatch.h 319 inline UnaryOp_match<SrcTy, TargetOpcode::COPY> m_Copy(SrcTy &&Src) {
320 return UnaryOp_match<SrcTy, TargetOpcode::COPY>(std::forward<SrcTy>(Src));
include/llvm/CodeGen/MachineInstr.h 1116 return getOpcode() == TargetOpcode::COPY;
1168 case TargetOpcode::COPY:
include/llvm/CodeGen/TargetInstrInfo.h 1421 return Opcode <= TargetOpcode::COPY;
1706 return BuildMI(MBB, InsPt, DL, get(TargetOpcode::COPY), Dst)
1718 return BuildMI(MBB, InsPt, DL, get(TargetOpcode::COPY), Dst)
lib/CodeGen/DetectDeadLanes.cpp 142 case TargetOpcode::COPY:
237 case TargetOpcode::COPY:
339 case TargetOpcode::COPY:
lib/CodeGen/ExpandPostRAPseudos.cpp 213 case TargetOpcode::COPY:
lib/CodeGen/GlobalISel/CombinerHelper.cpp 73 if (MI.getOpcode() != TargetOpcode::COPY)
lib/CodeGen/GlobalISel/GISelKnownBits.cpp 125 case TargetOpcode::COPY: {
lib/CodeGen/GlobalISel/InstructionSelect.cpp 168 if (MI.getOpcode() != TargetOpcode::COPY)
lib/CodeGen/GlobalISel/MachineIRBuilder.cpp 283 return buildInstr(TargetOpcode::COPY, Res, Op);
462 unsigned Opcode = TargetOpcode::COPY;
1016 case TargetOpcode::COPY:
lib/CodeGen/GlobalISel/RegBankSelect.cpp 163 MI = MIRBuilder.buildInstrNoInsert(TargetOpcode::COPY)
lib/CodeGen/GlobalISel/Utils.cpp 58 TII.get(TargetOpcode::COPY), ConstrainedReg)
63 TII.get(TargetOpcode::COPY), Reg)
255 case TargetOpcode::COPY:
309 while (DefMI->getOpcode() == TargetOpcode::COPY) {
lib/CodeGen/MachineBasicBlock.cpp 517 BuildMI(*this, I, DebugLoc(), TII.get(TargetOpcode::COPY), VirtReg)
lib/CodeGen/MachinePipeliner.cpp 368 auto Copy = BuildMI(PredB, At, DL, TII->get(TargetOpcode::COPY), NewReg)
lib/CodeGen/MachineRegisterInfo.cpp 487 TII.get(TargetOpcode::COPY), LiveIns[i].second)
lib/CodeGen/MachineVerifier.cpp 1539 case TargetOpcode::COPY: {
lib/CodeGen/ModuloSchedule.cpp 813 TII->get(TargetOpcode::COPY), SplitReg)
lib/CodeGen/PeepholeOptimizer.cpp 586 TII->get(TargetOpcode::COPY), NewVR)
1006 CopyLike.setDesc(TII.get(TargetOpcode::COPY));
1093 case TargetOpcode::COPY:
1236 TII->get(TargetOpcode::COPY), NewVReg)
lib/CodeGen/PrologEpilogInserter.cpp 548 TII.get(TargetOpcode::COPY), CS.getDstReg())
575 BuildMI(RestoreBlock, I, DebugLoc(), TII.get(TargetOpcode::COPY), Reg)
lib/CodeGen/RegisterCoalescer.cpp 1124 TII->get(TargetOpcode::COPY), IntB.reg)
lib/CodeGen/SelectionDAG/FastISel.cpp 1556 TII.get(TargetOpcode::COPY), ResultReg).addReg(Op0);
2030 TII.get(TargetOpcode::COPY), NewOp).addReg(Op);
2061 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
2086 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
2114 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
2136 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
2161 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
2180 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
2206 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
2222 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
2234 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TargetOpcode::COPY),
lib/CodeGen/SelectionDAG/InstrEmitter.cpp 177 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
324 TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg);
391 TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg);
468 BuildMI(*MBB, InsertPos, DL, TII->get(TargetOpcode::COPY), NewReg)
525 TII->get(TargetOpcode::COPY), VRBase).addReg(SrcReg);
542 TII->get(TargetOpcode::COPY), VRBase);
617 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
1013 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp 806 BuildMI(*BB, InsertPos, DebugLoc(), TII->get(TargetOpcode::COPY), Reg)
815 BuildMI(*BB, InsertPos, DebugLoc(), TII->get(TargetOpcode::COPY), VRBase)
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp 1247 TII->get(TargetOpcode::COPY), VReg)
lib/CodeGen/SplitKit.cpp 515 const MCInstrDesc &Desc = TII.get(TargetOpcode::COPY);
541 const MCInstrDesc &Desc = TII.get(TargetOpcode::COPY);
lib/CodeGen/SwiftErrorValueTracking.cpp 232 BuildMI(*MBB, MBB->getFirstNonPHI(), DLoc, TII->get(TargetOpcode::COPY),
lib/CodeGen/TailDuplicator.cpp 438 TII->get(TargetOpcode::COPY), NewReg)
982 const MCInstrDesc &CopyD = TII->get(TargetOpcode::COPY);
lib/CodeGen/TwoAddressInstructionPass.cpp 1553 TII->get(TargetOpcode::COPY), RegA);
1771 mi->setDesc(TII->get(TargetOpcode::COPY));
1838 TII->get(TargetOpcode::COPY))
lib/CodeGen/UnreachableBlockElim.cpp 196 TII->get(TargetOpcode::COPY), OutputReg)
lib/Target/AArch64/AArch64CallLowering.cpp 641 if (!RegDef || RegDef->getOpcode() != TargetOpcode::COPY) {
lib/Target/AArch64/AArch64CleanupLocalDynamicTLSPass.cpp 105 TII->get(TargetOpcode::COPY), AArch64::X0)
127 TII->get(TargetOpcode::COPY), *TLSBaseAddrReg)
lib/Target/AArch64/AArch64FastISel.cpp 392 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TargetOpcode::COPY),
429 TII.get(TargetOpcode::COPY), ResultReg)
2584 TII.get(TargetOpcode::COPY), ResultReg)
3055 TII.get(TargetOpcode::COPY), ResultReg)
3116 TII.get(TargetOpcode::COPY), VA.getLocReg()).addReg(ArgReg);
3180 TII.get(TargetOpcode::COPY), ResultReg)
3482 TII.get(TargetOpcode::COPY), SrcReg).addReg(FramePtr);
3815 TII.get(TargetOpcode::COPY), ResultReg1).addReg(MulReg);
3927 TII.get(TargetOpcode::COPY), DestReg).addReg(SrcReg);
3998 TII.get(TargetOpcode::COPY), ResultReg)
4128 TII.get(TargetOpcode::COPY), ResultReg)
4235 TII.get(TargetOpcode::COPY), ResultReg)
4356 TII.get(TargetOpcode::COPY), ResultReg)
4543 if (LoadMI->getOpcode() == TargetOpcode::COPY &&
4567 assert((MI->getOpcode() == TargetOpcode::COPY &&
lib/Target/AArch64/AArch64FrameLowering.cpp 991 BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::COPY), AArch64::FP)
lib/Target/AArch64/AArch64ISelLowering.cpp12404 BuildMI(*Entry, MBBI, DebugLoc(), TII->get(TargetOpcode::COPY), NewVR)
12410 TII->get(TargetOpcode::COPY), *I)
lib/Target/AArch64/AArch64InstrInfo.cpp 700 if (Opcode == TargetOpcode::COPY &&
1592 case TargetOpcode::COPY:
1604 case TargetOpcode::COPY: {
1634 case TargetOpcode::COPY: {
lib/Target/AArch64/AArch64InstructionSelector.cpp 599 auto SubRegCopy = MIB.buildInstr(TargetOpcode::COPY, {To}, {})
1183 auto Trunc = MIB.buildInstr(TargetOpcode::COPY, {SrcTy}, {})
1308 I.setDesc(TII.get(TargetOpcode::COPY));
1630 MIB.buildInstr(TargetOpcode::COPY, {I.getOperand(0).getReg()}, {})
1990 I.setDesc(TII.get(TargetOpcode::COPY));
2838 auto Copy = MIRBuilder.buildInstr(TargetOpcode::COPY, {*DstReg}, {})
3018 auto FirstCopy = MIB.buildInstr(TargetOpcode::COPY, {CopyTo}, {})
3410 if (Opc != TargetOpcode::COPY && Opc != TargetOpcode::G_TRUNC)
3414 if (Opc == TargetOpcode::COPY &&
3717 .buildInstr(TargetOpcode::COPY, {I.getOperand(0).getReg()}, {})
3836 MIRBuilder.buildInstr(TargetOpcode::COPY, {DstReg}, {})
3908 MIRBuilder.buildInstr(TargetOpcode::COPY, {DstReg}, {})
4681 case TargetOpcode::COPY:
lib/Target/AArch64/AArch64RegisterBankInfo.cpp 471 if (Op != TargetOpcode::COPY && !MI.isPHI())
514 if ((Opc != TargetOpcode::COPY && !isPreISelGenericOpcode(Opc)) ||
565 case TargetOpcode::COPY: {
lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp 115 I.setDesc(TII.get(TargetOpcode::COPY));
445 MachineInstr *Copy = BuildMI(*BB, &I, DL, TII.get(TargetOpcode::COPY),
528 BuildMI(*BB, &MI, DL, TII.get(TargetOpcode::COPY), Dst.getReg())
1206 I.setDesc(TII.get(TargetOpcode::COPY));
lib/Target/AMDGPU/SIISelLowering.cpp 2006 BuildMI(*Entry, MBBI, DebugLoc(), TII->get(TargetOpcode::COPY), NewVR)
2012 TII->get(TargetOpcode::COPY), *I)
3684 if (I->getOpcode() != TargetOpcode::COPY ||
10204 SDNode *Copy = DAG.getMachineNode(TargetOpcode::COPY,
lib/Target/AMDGPU/SIInstrInfo.cpp 714 if (Opcode == TargetOpcode::COPY) {
3864 BuildMI(*MBB, MI, DL, get(TargetOpcode::COPY), SubReg)
3875 BuildMI(*MBB, MI, DL, get(TargetOpcode::COPY), NewSuperReg)
3878 BuildMI(*MBB, MI, DL, get(TargetOpcode::COPY), SubReg)
4222 get(TargetOpcode::COPY), NewSrcReg)
6532 return BuildMI(MBB, Cur, DL, get(TargetOpcode::COPY), Dst).addReg(Src);
lib/Target/AMDGPU/SILoadStoreOptimizer.cpp 935 const MCInstrDesc &CopyDesc = TII->get(TargetOpcode::COPY);
1073 const MCInstrDesc &CopyDesc = TII->get(TargetOpcode::COPY);
1123 const MCInstrDesc &CopyDesc = TII->get(TargetOpcode::COPY);
1185 const MCInstrDesc &CopyDesc = TII->get(TargetOpcode::COPY);
lib/Target/ARM/A15SDOptimizer.cpp 441 TII->get(TargetOpcode::COPY), Out)
lib/Target/ARM/ARMFastISel.cpp 317 TII.get(TargetOpcode::COPY), ResultReg)
345 TII.get(TargetOpcode::COPY), ResultReg)
371 TII.get(TargetOpcode::COPY), ResultReg)
390 TII.get(TargetOpcode::COPY), ResultReg)
1994 TII.get(TargetOpcode::COPY), VA.getLocReg()).addReg(Arg);
2078 TII.get(TargetOpcode::COPY),
2163 TII.get(TargetOpcode::COPY), DstReg).addReg(SrcReg);
3065 TII.get(TargetOpcode::COPY),
lib/Target/ARM/ARMISelLowering.cpp17125 BuildMI(*Entry, MBBI, DebugLoc(), TII->get(TargetOpcode::COPY), NewVR)
17131 TII->get(TargetOpcode::COPY), *I)
lib/Target/ARM/ARMInstructionSelector.cpp 956 I.setDesc(TII.get(COPY));
1028 I.setDesc(TII.get(COPY));
lib/Target/Hexagon/BitTracker.cpp 742 case TargetOpcode::COPY: {
lib/Target/Hexagon/HexagonBitSimplify.cpp 1310 if (MI->getOpcode() == TargetOpcode::COPY)
1347 BuildMI(B, At, DL, HII.get(TargetOpcode::COPY), NewR)
1610 BuildMI(B, At, DL, HII.get(TargetOpcode::COPY), NewR)
1647 case TargetOpcode::COPY:
1670 case TargetOpcode::COPY:
2710 if (Opc == TargetOpcode::COPY || Opc == TargetOpcode::REG_SEQUENCE)
2982 case TargetOpcode::COPY:
lib/Target/Hexagon/HexagonConstExtenders.cpp 973 case Hexagon::A2_tfrsi: return TargetOpcode::COPY;
1764 BuildMI(MBB, At, dl, HII->get(TargetOpcode::COPY))
lib/Target/Hexagon/HexagonConstPropagation.cpp 2984 NewMI = BuildMI(B, At, DL, HII.get(TargetOpcode::COPY), NewR)
3050 NewMI = BuildMI(B, At, DL, HII.get(TargetOpcode::COPY), NewR)
3082 NewMI = BuildMI(B, At, DL, HII.get(TargetOpcode::COPY), NewR)
lib/Target/Hexagon/HexagonEarlyIfConv.cpp 1001 NonPHI = BuildMI(*B, NonPHI, DL, HII->get(TargetOpcode::COPY), NewR)
lib/Target/Hexagon/HexagonExpandCondsets.cpp 694 MI.setDesc(HII->get(TargetOpcode::COPY));
lib/Target/Hexagon/HexagonFrameLowering.cpp 1580 BuildMI(B, It, DL, HII.get(TargetOpcode::COPY), TmpR).add(MI->getOperand(1));
1581 BuildMI(B, It, DL, HII.get(TargetOpcode::COPY), DstR)
1897 case TargetOpcode::COPY:
2275 CopyIn = BuildMI(B, StartIt, DL, HII.get(TargetOpcode::COPY), FoundR)
2309 unsigned CopyOpc = TargetOpcode::COPY;
2377 BuildMI(MB, AI, DL, HII.get(TargetOpcode::COPY), SP)
lib/Target/Hexagon/HexagonGenPredicate.cpp 213 case TargetOpcode::COPY:
257 if (Opc == Hexagon::C2_tfrpr || Opc == TargetOpcode::COPY) {
274 BuildMI(B, std::next(DefIt), DL, TII->get(TargetOpcode::COPY), NewPR)
333 case TargetOpcode::COPY: {
395 NewOpc = TargetOpcode::COPY;
436 BuildMI(B, MI, DL, TII->get(TargetOpcode::COPY), NewOutR)
470 if (MI.getOpcode() != TargetOpcode::COPY)
lib/Target/Hexagon/HexagonHardwareLoops.cpp 1248 BuildMI(*Preheader, InsertPos, DL, TII->get(TargetOpcode::COPY), CountReg)
1517 case TargetOpcode::COPY:
lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp 1021 SDNode *ResN = (Node.Opc == TargetOpcode::COPY)
2050 Results.push(TargetOpcode::COPY, ResTy, {Vec0});
2051 Results.push(TargetOpcode::COPY, ResTy, {Vec1});
2061 Results.push(TargetOpcode::COPY, ResTy, {Res});
lib/Target/Hexagon/HexagonInstrInfo.cpp 1044 case TargetOpcode::COPY: {
2336 case TargetOpcode::COPY:
lib/Target/Hexagon/HexagonMachineScheduler.cpp 113 case TargetOpcode::COPY:
169 case TargetOpcode::COPY:
lib/Target/Hexagon/HexagonNewValueJump.cpp 222 MII->getOpcode() == TargetOpcode::COPY)
295 if (def->getOpcode() == TargetOpcode::COPY)
lib/Target/Hexagon/HexagonSplitDouble.cpp 174 case TargetOpcode::COPY:
324 case TargetOpcode::COPY:
744 BuildMI(B, MI, DL, TII->get(TargetOpcode::COPY), P.second)
752 BuildMI(B, MI, DL, TII->get(TargetOpcode::COPY), P.first)
770 BuildMI(B, MI, DL, TII->get(TargetOpcode::COPY), P.first)
810 BuildMI(B, MI, DL, TII->get(TargetOpcode::COPY), LoR)
812 BuildMI(B, MI, DL, TII->get(TargetOpcode::COPY), HiR)
869 BuildMI(B, MI, DL, TII->get(TargetOpcode::COPY), (Left ? HiR : LoR))
974 BuildMI(B, MI, DL, TII->get(TargetOpcode::COPY), LoR)
985 BuildMI(B, MI, DL, TII->get(TargetOpcode::COPY), LoR)
1004 case TargetOpcode::COPY: {
lib/Target/Hexagon/RDFCopy.cpp 43 case TargetOpcode::COPY: {
lib/Target/Mips/MipsFastISel.cpp 1067 emitInst(TargetOpcode::COPY, TempReg).addReg(Src2Reg);
1234 TII.get(TargetOpcode::COPY), VA.getLocReg()).addReg(ArgReg);
1304 TII.get(TargetOpcode::COPY),
1474 TII.get(TargetOpcode::COPY), ResultReg)
1560 emitInst(TargetOpcode::COPY, Mips::T9).addReg(DestAddress);
1769 TII.get(TargetOpcode::COPY), DestReg).addReg(SrcReg);
lib/Target/Mips/MipsInstructionSelector.cpp 294 I.setDesc(TII.get(COPY));
lib/Target/Mips/MipsOptimizePICCall.cpp 156 BuildMI(*MBB, I, I->getDebugLoc(), TII.get(TargetOpcode::COPY), DstReg)
lib/Target/Mips/MipsRegisterBankInfo.cpp 178 if (NonCopyInstr->getOpcode() == TargetOpcode::COPY &&
200 while (Ret->getOpcode() == TargetOpcode::COPY &&
214 while (Ret->getOpcode() == TargetOpcode::COPY &&
300 if (AdjMI->getOpcode() == TargetOpcode::COPY) {
lib/Target/Mips/MipsSEFrameLowering.cpp 155 case TargetOpcode::COPY:
178 BuildMI(MBB, I, I->getDebugLoc(), TII.get(TargetOpcode::COPY), Dst)
192 BuildMI(MBB, I, I->getDebugLoc(), TII.get(TargetOpcode::COPY), VR)
213 const MCInstrDesc &Desc = TII.get(TargetOpcode::COPY);
273 BuildMI(MBB, I, DL, TII.get(TargetOpcode::COPY), DstLo)
276 BuildMI(MBB, I, DL, TII.get(TargetOpcode::COPY), DstHi)
lib/Target/NVPTX/NVPTXReplaceImageHandles.cpp 177 case TargetOpcode::COPY: {
lib/Target/PowerPC/PPCFastISel.cpp 159 TII.get(TargetOpcode::COPY), TmpReg).addReg(SrcReg, Flag, SubReg);
1481 TII.get(TargetOpcode::COPY), ArgReg).addReg(Arg);
1729 TII.get(TargetOpcode::COPY), RetReg).addReg(SrcReg);
1786 TII.get(TargetOpcode::COPY), RetRegs[i])
lib/Target/PowerPC/PPCISelLowering.cpp11473 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY),
11481 BuildMI(*BB, MI, Dl, TII->get(TargetOpcode::COPY),
11488 BuildMI(*BB, MI, Dl, TII->get(TargetOpcode::COPY),
11523 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), DestReg)
15057 BuildMI(*Entry, MBBI, DebugLoc(), TII->get(TargetOpcode::COPY), NewVR)
15063 TII->get(TargetOpcode::COPY), *I)
lib/Target/PowerPC/PPCInstrInfo.cpp 868 BuildMI(MBB, MI, dl, get(TargetOpcode::COPY), FirstReg)
1914 get(TargetOpcode::COPY), CRReg)
lib/Target/PowerPC/PPCTLSDynamicCall.cpp 132 BuildMI(MBB, I, DL, TII->get(TargetOpcode::COPY), OutReg)
lib/Target/PowerPC/PPCVSXCopy.cpp 128 BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(TargetOpcode::COPY),
lib/Target/PowerPC/PPCVSXSwapRemoval.cpp 951 BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(TargetOpcode::COPY),
lib/Target/SystemZ/SystemZISelLowering.cpp 7445 BuildMI(MBB, DL, TII->get(TargetOpcode::COPY), SystemZ::R0L).addReg(CharReg);
lib/Target/SystemZ/SystemZInstrInfo.cpp 590 BuildMI(MBB, I, DL, get(TargetOpcode::COPY), TReg).addReg(TrueReg);
591 BuildMI(MBB, I, DL, get(TargetOpcode::COPY), FReg).addReg(FalseReg);
lib/Target/SystemZ/SystemZLDCleanup.cpp 120 TII->get(TargetOpcode::COPY), SystemZ::R2D)
140 TII->get(TargetOpcode::COPY), *TLSBaseAddrReg)
lib/Target/X86/X86DomainReassignment.cpp 192 BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::COPY))
238 assert(MI->getOpcode() == TargetOpcode::COPY && "Expected a COPY");
271 TII->get(TargetOpcode::COPY))
617 Converters[{MaskDomain, TargetOpcode::COPY}] =
618 new InstrCOPYReplacer(TargetOpcode::COPY, MaskDomain, TargetOpcode::COPY);
618 new InstrCOPYReplacer(TargetOpcode::COPY, MaskDomain, TargetOpcode::COPY);
lib/Target/X86/X86FastISel.cpp 1252 TII.get(TargetOpcode::COPY), DstReg).addReg(SrcReg);
1271 TII.get(TargetOpcode::COPY), RetReg).addReg(Reg);
1765 TII.get(TargetOpcode::COPY), OpReg)
1831 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TargetOpcode::COPY),
1853 const static unsigned Copy = TargetOpcode::COPY;
2111 TII.get(TargetOpcode::COPY), CondReg)
2228 TII.get(TargetOpcode::COPY), ResultReg).addReg(MovReg);
2249 TII.get(TargetOpcode::COPY), ResultReg).addReg(VBlendReg);
2275 TII.get(TargetOpcode::COPY), ResultReg).addReg(OrReg);
2329 TII.get(TargetOpcode::COPY), CondReg)
2382 TII.get(TargetOpcode::COPY), ResultReg)
2661 TII.get(TargetOpcode::COPY), ResultReg)
2704 TII.get(TargetOpcode::COPY), SrcReg).addReg(FrameReg);
2951 TII.get(TargetOpcode::COPY), Reg[VT.SimpleTy-MVT::i8])
2962 TII.get(TargetOpcode::COPY), X86::AL)
3147 TII.get(TargetOpcode::COPY), ResultReg)
3405 TII.get(TargetOpcode::COPY), VA.getLocReg()).addReg(ArgReg);
3447 TII.get(TargetOpcode::COPY), X86::EBX).addReg(Base);
3574 TII.get(TargetOpcode::COPY), CopyReg).addReg(SrcReg);
4001 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
lib/Target/X86/X86FlagsCopyLowering.cpp 360 if (MI.getOpcode() == TargetOpcode::COPY &&
371 if (CopyDefI.getOpcode() != TargetOpcode::COPY) {
598 } else if (MI.getOpcode() == TargetOpcode::COPY) {
702 if (MI.getOpcode() == TargetOpcode::COPY &&
956 BuildMI(MBB, SetPos, SetLoc, TII->get(TargetOpcode::COPY),
960 BuildMI(MBB, SetPos, SetLoc, TII->get(TargetOpcode::COPY), NewReg)
lib/Target/X86/X86FloatingPoint.cpp 1452 case TargetOpcode::COPY: {
lib/Target/X86/X86ISelLowering.cpp29236 BuildMI(fallMBB, DL, TII->get(TargetOpcode::COPY), fallDstReg)
29477 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
29859 TII->get(TargetOpcode::COPY),
30072 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
30082 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
30084 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
30121 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
30401 BuildMI(*BB, MI, DL, TII->get(TargetOpcode::COPY), AvailableReg)
31276 BuildMI(*BB, MI, DL, TII->get(TargetOpcode::COPY), NewCW16)
46202 BuildMI(*Entry, MBBI, DebugLoc(), TII->get(TargetOpcode::COPY), NewVR)
46208 TII->get(TargetOpcode::COPY), *I)
lib/Target/X86/X86InstrInfo.cpp 745 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(TargetOpcode::COPY))
799 BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(TargetOpcode::COPY))
851 InsMI2 = BuildMI(*MFI, &*MIB, MI.getDebugLoc(), get(TargetOpcode::COPY))
864 BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(TargetOpcode::COPY))
7908 TII->get(TargetOpcode::COPY), is64Bit ? X86::RAX : X86::EAX)
7935 TII->get(TargetOpcode::COPY), *TLSBaseAddrReg)
lib/Target/X86/X86InstructionSelector.cpp 1392 TII.get(TargetOpcode::COPY), DstReg)
1542 const static unsigned Copy = TargetOpcode::COPY;
1709 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(TargetOpcode::COPY),
lib/Target/X86/X86SpeculativeLoadHardening.cpp 1214 case TargetOpcode::COPY:
1934 BuildMI(MBB, InsertPt, Loc, TII->get(TargetOpcode::COPY), TmpReg)
2296 BuildMI(MBB, InsertPt, Loc, TII->get(TargetOpcode::COPY), NarrowStateReg)
lib/Target/X86/X86WinAllocaExpander.cpp 248 BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::COPY), RegA)
unittests/CodeGen/GlobalISel/CSETest.cpp 34 EXPECT_EQ(MIBAddCopy->getOpcode(), TargetOpcode::COPY);
95 EXPECT_TRUE(MIBAdd1->getOpcode() != TargetOpcode::COPY);
unittests/CodeGen/GlobalISel/GISelMITest.h 131 if (MI.getOpcode() == TargetOpcode::COPY)