|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
lib/CodeGen/AggressiveAntiDepBreaker.cpp 144 << " " << printReg(r, TRI));
219 << " " << printReg(Reg, TRI) << "=g" << State->GetGroup(Reg)
326 dbgs() << header << printReg(Reg, TRI);
342 dbgs() << header << printReg(Reg, TRI);
345 LLVM_DEBUG(dbgs() << " " << printReg(SubregReg, TRI) << "->g"
381 LLVM_DEBUG(dbgs() << " " << printReg(Reg, TRI) << "=g"
402 << printReg(AliasReg, TRI) << ")");
477 LLVM_DEBUG(dbgs() << " " << printReg(Reg, TRI) << "=g"
513 LLVM_DEBUG(dbgs() << "=" << printReg(Reg, TRI));
516 LLVM_DEBUG(dbgs() << " " << printReg(Reg, TRI));
582 LLVM_DEBUG(dbgs() << "\t\t" << printReg(Reg, TRI) << ":");
591 dbgs() << " " << printReg(r, TRI);
616 dbgs() << "*** Performing rename " << printReg(SuperReg, TRI)
654 LLVM_DEBUG(dbgs() << " [" << printReg(NewSuperReg, TRI) << ':');
671 LLVM_DEBUG(dbgs() << " " << printReg(NewReg, TRI));
693 << "(alias " << printReg(AliasReg, TRI) << " live)");
802 LLVM_DEBUG(dbgs() << " " << printReg(Reg, TRI));
858 LLVM_DEBUG(dbgs() << "\tAntidep reg: " << printReg(AntiDepReg, TRI));
961 << printReg(AntiDepReg, TRI) << ":");
969 LLVM_DEBUG(dbgs() << " " << printReg(CurrReg, TRI) << "->"
970 << printReg(NewReg, TRI) << "("
lib/CodeGen/AllocationOrder.cpp 45 dbgs() << ' ' << printReg(Hints[I], TRI);
lib/CodeGen/AsmPrinter/AsmPrinter.cpp 798 << printReg(RegNo, MF->getSubtarget().getRegisterInfo());
812 << printReg(Op.getReg(), AP.MF->getSubtarget().getRegisterInfo());
897 OS << printReg(Reg, AP.MF->getSubtarget().getRegisterInfo());
lib/CodeGen/BranchFolding.cpp 658 LLVM_DEBUG(dbgs() << "Common tail length of " << printMBBReference(*MBB1)
659 << " and " << printMBBReference(*MBB2) << " is "
815 LLVM_DEBUG(dbgs() << "\nSplitting " << printMBBReference(*MBB) << ", size "
968 << printMBBReference(*MergePotentials[i].getBlock())
971 dbgs() << " with successor " << printMBBReference(*SuccBB) << '\n';
974 << printMBBReference(*PredBB) << "\n";
1057 LLVM_DEBUG(dbgs() << "\nUsing common tail in " << printMBBReference(*MBB)
1062 LLVM_DEBUG(dbgs() << printMBBReference(*SameTails[i].getBlock())
lib/CodeGen/BranchRelaxation.cpp 289 << printMBBReference(DestBB) << " from "
290 << printMBBReference(*MI.getParent()) << " to "
386 LLVM_DEBUG(dbgs() << " Insert B to " << printMBBReference(*TBB)
388 << printMBBReference(NextBB) << '\n');
420 << printMBBReference(*NewBB)
422 << " Insert B to " << printMBBReference(*FBB) << ".\n"
424 << printMBBReference(*TBB) << ".\n");
lib/CodeGen/CriticalAntiDepBreaker.cpp 469 LLVM_DEBUG(dbgs() << " " << printReg(Reg, TRI));
649 << printReg(AntiDepReg, TRI) << " with "
651 << " using " << printReg(NewReg, TRI) << "!\n");
lib/CodeGen/DetectDeadLanes.cpp 527 dbgs() << printReg(Reg, nullptr)
528 << " Used: " << PrintLaneMask(Info.UsedLanes)
529 << " Def: " << PrintLaneMask(Info.DefinedLanes) << '\n';
lib/CodeGen/EarlyIfConversion.cpp 203 LLVM_DEBUG(dbgs() << printMBBReference(*MBB) << " has live-ins.\n");
217 LLVM_DEBUG(dbgs() << printMBBReference(*MBB) << " has more than "
275 LLVM_DEBUG(dbgs() << printMBBReference(*I->getParent()) << " depends on "
297 LLVM_DEBUG(dbgs() << printMBBReference(*MBB) << " has live-ins.\n");
312 LLVM_DEBUG(dbgs() << printMBBReference(*MBB) << " has more than "
411 dbgs() << ' ' << printRegUnit(*i, TRI);
455 LLVM_DEBUG(dbgs() << "\nDiamond: " << printMBBReference(*Head) << " -> "
456 << printMBBReference(*Succ0) << "/"
457 << printMBBReference(*Succ1) << " -> "
458 << printMBBReference(*Tail) << '\n');
466 LLVM_DEBUG(dbgs() << "\nTriangle: " << printMBBReference(*Head) << " -> "
467 << printMBBReference(*Succ0) << " -> "
468 << printMBBReference(*Tail) << '\n');
678 LLVM_DEBUG(dbgs() << "Joining tail " << printMBBReference(*Tail)
679 << " into head " << printMBBReference(*Head) << '\n');
lib/CodeGen/EdgeBundles.cpp 82 O << "\t\"" << printMBBReference(MBB) << "\" [ shape=box ]\n"
83 << '\t' << G.getBundle(BB, false) << " -> \"" << printMBBReference(MBB)
85 << "\t\"" << printMBBReference(MBB) << "\" -> " << G.getBundle(BB, true)
89 O << "\t\"" << printMBBReference(MBB) << "\" -> \""
90 << printMBBReference(**SI) << "\" [ color=lightgray ]\n";
lib/CodeGen/ExecutionDomainFix.cpp 164 LLVM_DEBUG(dbgs() << printMBBReference(*MBB) << ": entry\n");
203 LLVM_DEBUG(dbgs() << printMBBReference(*MBB)
248 LLVM_DEBUG(dbgs() << printReg(RC->getRegister(rx), TRI) << ":\t" << *MI);
lib/CodeGen/GlobalISel/Localizer.cpp 161 LLVM_DEBUG(dbgs() << "Update use with: " << printReg(NewVRegIt->second)
lib/CodeGen/GlobalISel/RegBankSelect.cpp 166 LLVM_DEBUG(dbgs() << "Copy: " << printReg(Src) << " to: " << printReg(Dst)
166 LLVM_DEBUG(dbgs() << "Copy: " << printReg(Src) << " to: " << printReg(Dst)
lib/CodeGen/GlobalISel/RegisterBankInfo.cpp 464 LLVM_DEBUG(dbgs() << " changed, replace " << printReg(OrigReg, nullptr));
466 LLVM_DEBUG(dbgs() << " with " << printReg(NewReg, nullptr));
790 OS << '(' << printReg(getMI().getOperand(Idx).getReg(), TRI) << ", [";
796 OS << printReg(VReg, TRI);
lib/CodeGen/IfConversion.cpp 511 << "): " << printMBBReference(*BBI.BB) << " ("
538 LLVM_DEBUG(dbgs() << "): " << printMBBReference(*BBI.BB)
556 LLVM_DEBUG(dbgs() << "Ifcvt (Diamond): " << printMBBReference(*BBI.BB)
568 << printMBBReference(*BBI.BB)
lib/CodeGen/InlineSpiller.cpp 963 LLVM_DEBUG(dbgs() << "spillAroundUses " << printReg(Reg) << '\n');
1122 << printReg(Original) << '\n');
lib/CodeGen/LiveDebugValues.cpp 339 dbgs() << printReg(Loc.RegNo, TRI);
342 dbgs() << printReg(Loc.SpillLocation.SpillBase, TRI);
964 LLVM_DEBUG(dbgs() << "Register: " << Reg << " " << printReg(Reg, TRI)
971 LLVM_DEBUG(dbgs() << "Register: " << Reg << " " << printReg(Reg, TRI)
978 LLVM_DEBUG(dbgs() << "Spilling Register " << printReg(Reg, TRI) << '('
983 LLVM_DEBUG(dbgs() << "Restoring Register " << printReg(Reg, TRI) << '('
lib/CodeGen/LiveDebugVariables.cpp 1356 LLVM_DEBUG(dbgs() << ' ' << printMBBReference(*MBB) << '-' << MBBEnd);
1367 LLVM_DEBUG(dbgs() << ' ' << printMBBReference(*MBB) << '-' << MBBEnd);
1383 LLVM_DEBUG(dbgs() << ' ' << printMBBReference(*MBB));
lib/CodeGen/LiveInterval.cpp 1032 OS << " L" << PrintLaneMask(LaneMask) << ' '
1037 OS << printReg(reg) << ' ';
lib/CodeGen/LiveIntervalUnion.cpp 89 << printReg(SI.value()->reg, TRI);
lib/CodeGen/LiveIntervals.cpp 160 OS << printRegUnit(Unit, TRI) << ' ' << *LR << '\n';
326 LLVM_DEBUG(dbgs() << Begin << "\t" << printMBBReference(MBB));
338 LLVM_DEBUG(dbgs() << ' ' << printRegUnit(Unit, TRI) << '#' << VNI->id);
1027 dbgs() << printReg(Reg);
1029 dbgs() << " L" << PrintLaneMask(LaneMask);
1031 dbgs() << printRegUnit(Reg, &TRI);
lib/CodeGen/LivePhysRegs.cpp 133 OS << " " << printReg(*I, TRI);
lib/CodeGen/LiveRangeCalc.cpp 367 errs() << "Use of " << printReg(PhysReg, MRI->getTargetRegisterInfo())
378 errs() << "The register " << printReg(PhysReg, TRI)
379 << " needs to be live in to " << printMBBReference(*MBB)
lib/CodeGen/LiveRangeEdit.cpp 471 dbgs() << "Inflated " << printReg(LI.reg) << " to "
lib/CodeGen/LiveRegMatrix.cpp 104 LLVM_DEBUG(dbgs() << "assigning " << printReg(VirtReg.reg, TRI) << " to "
105 << printReg(PhysReg, TRI) << ':');
111 LLVM_DEBUG(dbgs() << ' ' << printRegUnit(Unit, TRI) << ' ' << Range);
122 LLVM_DEBUG(dbgs() << "unassigning " << printReg(VirtReg.reg, TRI) << " from "
123 << printReg(PhysReg, TRI) << ':');
128 LLVM_DEBUG(dbgs() << ' ' << printRegUnit(Unit, TRI));
lib/CodeGen/MIRPrinter.cpp 192 OS << printReg(Reg, TRI);
255 OS << printReg(I, TRI);
267 OS << printRegClassOrBank(Reg, RegInfo, TRI);
349 StrOS << printMBBReference(*MFI.getSavePoint());
353 StrOS << printMBBReference(*MFI.getRestorePoint());
534 StrOS << printMBBReference(*MBB);
656 OS << printMBBReference(**I);
676 OS << printReg(LI.PhysReg, &TRI);
678 OS << ":0x" << PrintLaneMask(LI.LaneMask);
lib/CodeGen/MachineBasicBlock.cpp 351 OS << printMBBReference(**I);
364 OS << printMBBReference(**I);
377 OS << printMBBReference(**I) << '('
399 OS << printReg(LI.PhysReg, TRI);
401 OS << ":0x" << PrintLaneMask(LI.LaneMask);
884 LLVM_DEBUG(dbgs() << "Splitting critical edge: " << printMBBReference(*this)
885 << " -- " << printMBBReference(*NMBB) << " -- "
886 << printMBBReference(*Succ) << '\n');
1135 << printMBBReference(*this) << '\n');
lib/CodeGen/MachineBlockPlacement.cpp 567 OS << printMBBReference(*BB);
lib/CodeGen/MachineBranchProbabilityInfo.cpp 86 OS << "edge " << printMBBReference(*Src) << " -> " << printMBBReference(*Dst)
86 OS << "edge " << printMBBReference(*Src) << " -> " << printMBBReference(*Dst)
lib/CodeGen/MachineCopyPropagation.cpp 441 LLVM_DEBUG(dbgs() << "MCP: Replacing " << printReg(MOUse.getReg(), TRI)
442 << "\n with " << printReg(CopySrcReg, TRI)
lib/CodeGen/MachineFunction.cpp 503 OS << printReg(I->first, TRI);
505 OS << " in " << printReg(I->second, TRI);
540 OSS << printMBBReference(*Node);
944 OS << printJumpTableEntryReference(i) << ':';
946 OS << ' ' << printMBBReference(*JumpTables[i].MBBs[j]);
lib/CodeGen/MachineLICM.cpp 594 LLVM_DEBUG(dbgs() << "Hoisting to " << printMBBReference(*Preheader)
595 << " from " << printMBBReference(*MI->getParent()) << ": "
633 LLVM_DEBUG(dbgs() << "Entering " << printMBBReference(*MBB) << '\n');
640 LLVM_DEBUG(dbgs() << "Exiting " << printMBBReference(*MBB) << '\n');
1453 dbgs() << " from " << printMBBReference(*MI->getParent());
1455 dbgs() << " to " << printMBBReference(*Preheader);
lib/CodeGen/MachineOperand.cpp 433 OS << printReg(*Reg, TRI);
779 OS << printReg(Reg, TRI, 0, MRI);
793 OS << printRegClassOrBank(Reg, MRI, TRI);
815 OS << printMBBReference(*getMBB());
841 OS << printJumpTableEntryReference(getIndex());
879 OS << " " << printReg(i, TRI);
904 OS << printReg(Reg, TRI);
lib/CodeGen/MachineRegisterInfo.cpp 224 errs() << printReg(Reg, getTargetRegisterInfo())
233 errs() << printReg(Reg, getTargetRegisterInfo())
239 errs() << printReg(Reg, getTargetRegisterInfo())
245 errs() << printReg(Reg, getTargetRegisterInfo())
lib/CodeGen/MachineScheduler.cpp 562 LLVM_DEBUG(dbgs() << MF->getName() << ":" << printMBBReference(*MBB)
813 << printMBBReference(*begin()->getParent()) << " ***\n";
1119 << printReg(Reg, TRI) << ':'
1120 << PrintLaneMask(P.LaneMask) << ' ' << *SU.getInstr();
1125 LLVM_DEBUG(dbgs() << " LiveReg: " << printVRegOrUnit(Reg, TRI) << "\n");
1249 << printMBBReference(*begin()->getParent()) << " ***\n";
lib/CodeGen/MachineSink.cpp 332 << printMBBReference(*Pair.first) << " -- "
333 << printMBBReference(*NewSucc) << " -- "
334 << printMBBReference(*Pair.second) << '\n');
lib/CodeGen/MachineTraceMetrics.cpp 397 LLVM_DEBUG(dbgs() << "Invalidate traces through " << printMBBReference(*MBB)
479 << printMBBReference(*MBB) << '\n');
487 LLVM_DEBUG(dbgs() << " pred for " << printMBBReference(*I) << ": ");
493 dbgs() << printMBBReference(*TBI.Pred) << '\n';
505 LLVM_DEBUG(dbgs() << " succ for " << printMBBReference(*I) << ": ");
511 dbgs() << printMBBReference(*TBI.Succ) << '\n';
532 LLVM_DEBUG(dbgs() << "Invalidate " << printMBBReference(*MBB) << ' '
557 LLVM_DEBUG(dbgs() << "Invalidate " << printMBBReference(*MBB) << ' '
861 LLVM_DEBUG(dbgs() << "\nDepths for " << printMBBReference(*MBB) << ":\n");
1046 LLVM_DEBUG(dbgs() << "Heights for " << printMBBReference(*MBB) << ":\n");
1133 LLVM_DEBUG(dbgs() << printMBBReference(*MBB) << " Live-ins:");
1137 LLVM_DEBUG(dbgs() << ' ' << printReg(LIR.Reg) << '@' << LIR.Height);
1144 LLVM_DEBUG(dbgs() << ' ' << printRegUnit(RI->RegUnit, MTM.TRI) << '@'
1301 OS << " pred=" << printMBBReference(*Pred);
1313 OS << " succ=" << printMBBReference(*Succ);
1339 OS << " <- " << printMBBReference(*Block->Pred);
1347 OS << " -> " << printMBBReference(*Block->Succ);
lib/CodeGen/MachineVerifier.cpp 492 errs() << "- basic block: " << printMBBReference(*MBB) << ' '
547 errs() << "- p. register: " << printReg(PReg, TRI) << '\n';
551 errs() << "- v. register: " << printReg(VReg, TRI) << '\n';
558 errs() << "- regunit: " << printRegUnit(VRegOrUnit, TRI) << '\n';
563 errs() << "- lanemask: " << PrintLaneMask(LaneMask) << '\n';
645 << printMBBReference(*(*I)) << ".\n";
657 << printMBBReference(*(*I)) << ".\n";
1695 errs() << printReg(Reg, TRI) << " is not a "
2262 errs() << printMBBReference(*Pred)
2287 errs() << "Virtual register " << printReg(*I)
2324 errs() << "Virtual register " << printReg(Reg)
2330 errs() << "Virtual register " << printReg(Reg)
2349 errs() << printReg(Reg, TRI) << " still has defs or uses\n";
2649 errs() << " live into " << printMBBReference(*MFI) << '@'
2660 << printMBBReference(*(*PI)) << '@' << PEnd << "\nValno #"
2661 << VNI->id << " live into " << printMBBReference(*MFI) << '@'
2812 errs() << "Predecessor " << printMBBReference(*(*I))
2815 << printMBBReference(*MBB) << " has entry state ("
2828 errs() << "Successor " << printMBBReference(*(*I))
2831 << printMBBReference(*MBB) << " has exit state ("
lib/CodeGen/PHIElimination.cpp 278 LLVM_DEBUG(dbgs() << "Reusing " << printReg(IncomingReg) << " for "
599 LLVM_DEBUG(dbgs() << printReg(Reg) << " live-out before critical edge "
600 << printMBBReference(*PreMBB) << " -> "
601 << printMBBReference(MBB) << ": " << *BBI);
lib/CodeGen/PostRASchedulerList.cpp 325 << printMBBReference(MBB) << " ***\n";
lib/CodeGen/ProcessImplicitDefs.cpp 156 LLVM_DEBUG(dbgs() << printMBBReference(*MFI) << " has " << WorkList.size()
lib/CodeGen/ReachingDefAnalysis.cpp 50 LLVM_DEBUG(dbgs() << printMBBReference(*MBB) << ": entry\n");
72 LLVM_DEBUG(dbgs() << printMBBReference(*MBB)
112 LLVM_DEBUG(dbgs() << printReg(MO.getReg(), TRI) << ":\t" << CurInstr
lib/CodeGen/RegAllocBasic.cpp 221 LLVM_DEBUG(dbgs() << "spilling " << printReg(PhysReg, TRI)
lib/CodeGen/RegAllocFast.cpp 316 LLVM_DEBUG(dbgs() << "Spilling " << printReg(VirtReg, TRI)
317 << " in " << printReg(AssignedReg, TRI));
344 LLVM_DEBUG(dbgs() << "Reloading " << printReg(VirtReg, TRI) << " into "
345 << printReg(PhysReg, TRI) << '\n');
561 LLVM_DEBUG(dbgs() << printReg(PhysReg, TRI)
571 LLVM_DEBUG(dbgs() << printReg(VirtReg, TRI) << " corresponding "
572 << printReg(PhysReg, TRI) << " is reserved already.\n");
583 LLVM_DEBUG(dbgs() << printReg(PhysReg, TRI) << " is disabled.\n");
612 LLVM_DEBUG(dbgs() << "Assigning " << printReg(VirtReg, TRI) << " to "
613 << printReg(PhysReg, TRI) << '\n');
668 LLVM_DEBUG(dbgs() << "Search register for " << printReg(VirtReg)
670 << " with hint " << printReg(Hint0, TRI) << '\n');
678 LLVM_DEBUG(dbgs() << "\tPreferred Register 1: " << printReg(Hint0, TRI)
685 LLVM_DEBUG(dbgs() << "\tPreferred Register 1: " << printReg(Hint0, TRI)
699 LLVM_DEBUG(dbgs() << "\tPreferred Register 0: " << printReg(Hint1, TRI)
706 LLVM_DEBUG(dbgs() << "\tPreferred Register 0: " << printReg(Hint1, TRI)
717 LLVM_DEBUG(dbgs() << "\tRegister: " << printReg(PhysReg, TRI) << ' ');
898 LLVM_DEBUG(dbgs() << ' ' << printReg(Reg));
966 LLVM_DEBUG(dbgs() << "\tSetting " << printReg(Reg, TRI)
980 dbgs() << " " << printReg(Reg, TRI);
988 dbgs() << '=' << printReg(PhysRegState[Reg]);
lib/CodeGen/RegAllocGreedy.cpp 780 LLVM_DEBUG(dbgs() << "missed hint " << printReg(Hint, TRI) << '\n');
799 LLVM_DEBUG(dbgs() << printReg(PhysReg, TRI) << " is available at cost "
829 << printReg(PrevReg, TRI) << " to "
830 << printReg(PhysReg, TRI) << '\n');
1057 LLVM_DEBUG(dbgs() << "evicting " << printReg(PhysReg, TRI)
1152 dbgs() << printReg(PhysReg, TRI) << " would clobber CSR "
1153 << printReg(RegClassInfo.getLastCalleeSavedAlias(PhysReg), TRI)
1720 LLVM_DEBUG(dbgs() << printMBBReference(*BI.MBB) << " isolated.\n");
1911 LLVM_DEBUG(dbgs() << printReg(PhysReg, TRI) << "\tno positive bundles\n");
1914 LLVM_DEBUG(dbgs() << printReg(PhysReg, TRI) << "\tstatic = ";
1922 << printReg(GlobalCand[BestCand].PhysReg, TRI) << '\n';
1963 << printReg(VirtReg.reg, TRI) << " may ");
1989 LLVM_DEBUG(dbgs() << "Split for " << printReg(Cand.PhysReg, TRI) << " in "
2344 LLVM_DEBUG(dbgs() << printReg(PhysReg, TRI) << ' ' << Uses[SplitBefore]
2444 LLVM_DEBUG(dbgs() << printReg(LREdit.get(i)));
2636 << printReg(PhysReg, TRI) << '\n');
2697 << printReg(PhysReg, TRI) << '\n');
2761 << " succeeded with: " << printReg(PhysReg, TRI) << '\n');
2928 LLVM_DEBUG(dbgs() << "Trying to reconcile hints for: " << printReg(Reg, TRI)
2929 << '(' << printReg(PhysReg, TRI) << ")\n");
2950 LLVM_DEBUG(dbgs() << printReg(Reg, TRI) << '(' << printReg(CurrPhys, TRI)
2950 LLVM_DEBUG(dbgs() << printReg(Reg, TRI) << '(' << printReg(CurrPhys, TRI)
lib/CodeGen/RegAllocPBQP.cpp 687 LLVM_DEBUG(dbgs() << "VREG " << printReg(VReg, &TRI) << " -> SPILLED (Cost: "
696 LLVM_DEBUG(dbgs() << printReg(LI.reg, &TRI) << " ");
726 LLVM_DEBUG(dbgs() << "VREG " << printReg(VReg, &TRI) << " -> "
883 OS << NId << " (" << RegClassName << ':' << printReg(VReg, TRI) << ')';
892 OS << PrintNodeInfo(NId, *this) << ": " << Costs << '\n';
903 OS << PrintNodeInfo(N1Id, *this) << ' ' << M.getRows() << " rows / ";
904 OS << PrintNodeInfo(N2Id, *this) << ' ' << M.getCols() << " cols:\n";
918 << PrintNodeInfo(NId, *this) << "\\n"
lib/CodeGen/RegUsageInfoCollector.cpp 184 dbgs() << printReg(PReg, TRI) << " ";
lib/CodeGen/RegisterClassInfo.cpp 158 dbgs() << ' ' << printReg(RCI.Order[I], TRI);
lib/CodeGen/RegisterCoalescer.cpp 623 LLVM_DEBUG(dbgs() << "Extending: " << printReg(IntB.reg, TRI));
1120 << printMBBReference(*CopyLeftBB) << '\t' << CopyMI);
1138 << printMBBReference(MBB) << '\t' << CopyMI);
1417 << PrintLaneMask(SR.LaneMask) << " : " << SR << "\n");
1829 << printReg(CP.getSrcReg(), TRI) << " with "
1830 << printReg(CP.getDstReg(), TRI, CP.getSrcIdx()) << '\n');
1851 dbgs() << printReg(CP.getDstReg()) << " in "
1853 << printReg(CP.getSrcReg()) << " in "
1856 dbgs() << printReg(CP.getSrcReg(), TRI) << " in "
1857 << printReg(CP.getDstReg(), TRI, CP.getSrcIdx()) << '\n';
1938 LLVM_DEBUG(dbgs() << "Shrink LaneUses (Lane " << PrintLaneMask(S.LaneMask)
1964 dbgs() << "\tSuccess: " << printReg(CP.getSrcReg(), TRI, CP.getSrcIdx())
1965 << " -> " << printReg(CP.getDstReg(), TRI, CP.getDstIdx()) << '\n';
1968 dbgs() << printReg(CP.getDstReg(), TRI);
2003 LLVM_DEBUG(dbgs() << "\t\tInterference: " << printRegUnit(*UI, TRI)
2075 << printReg(DstReg, TRI) << " at " << CopyRegIdx << "\n");
2612 << printMBBReference(*DefMI->getParent())
2735 LLVM_DEBUG(dbgs() << "\t\tmerge " << printReg(Reg) << ':' << ValNo << '@'
2737 << printReg(Other.Reg) << ':' << V.OtherVNI->id << '@'
2775 LLVM_DEBUG(dbgs() << "\t\tinterference at " << printReg(Reg) << ':' << i
2798 LLVM_DEBUG(dbgs() << "\t\ttaints global " << printReg(Other.Reg) << ':'
2802 LLVM_DEBUG(dbgs() << "\t\ttaints local " << printReg(Other.Reg) << ':'
2845 LLVM_DEBUG(dbgs() << "\t\tconflict at " << printReg(Reg) << ':' << i << '@'
2956 LLVM_DEBUG(dbgs() << "\t\tpruned " << printReg(Other.Reg) << " at " << Def
2968 LLVM_DEBUG(dbgs() << "\t\tpruned all of " << printReg(Reg) << " at "
3047 LLVM_DEBUG(dbgs() << "\t\tPrune sublane " << PrintLaneMask(S.LaneMask)
3067 << PrintLaneMask(S.LaneMask) << " at " << Def
3253 LLVM_DEBUG(dbgs() << "\t\tjoined lanes: " << PrintLaneMask(LaneMask)
3346 LLVM_DEBUG(dbgs() << "\t\tLHST = " << printReg(CP.getDstReg()) << ' ' << LHS
3561 LLVM_DEBUG(dbgs() << "Apply terminal rule for: " << printReg(DstReg)
3720 LLVM_DEBUG(dbgs() << printReg(Reg) << " inflated to "
lib/CodeGen/RegisterPressure.cpp 100 dbgs() << printVRegOrUnit(P.RegUnit, TRI);
102 dbgs() << ':' << PrintLaneMask(P.LaneMask);
108 dbgs() << printVRegOrUnit(P.RegUnit, TRI);
110 dbgs() << ':' << PrintLaneMask(P.LaneMask);
lib/CodeGen/RegisterScavenging.cpp 290 LLVM_DEBUG(dbgs() << "Scavenger found unused reg: " << printReg(Reg, TRI)
563 LLVM_DEBUG(dbgs() << "Scavenged register: " << printReg(SReg, TRI) << "\n");
574 << printReg(SReg, TRI) << "\n");
597 LLVM_DEBUG(dbgs() << "Scavenged free register: " << printReg(Reg, TRI)
613 LLVM_DEBUG(dbgs() << "Scavenged register with spill: " << printReg(Reg, TRI)
lib/CodeGen/RegisterUsageInfo.cpp 97 OS << printReg(PReg, TRI) << " ";
lib/CodeGen/RenameIndependentSubregs.cpp 136 LLVM_DEBUG(dbgs() << printReg(Reg) << ": Found " << Classes.getNumClasses()
138 LLVM_DEBUG(dbgs() << printReg(Reg) << ": Splitting into newly created:");
144 LLVM_DEBUG(dbgs() << ' ' << printReg(NewVReg));
lib/CodeGen/ScheduleDAG.cpp 87 dbgs() << " Reg=" << printReg(getReg(), TRI);
lib/CodeGen/ScheduleDAGInstrs.cpp 1104 LLVM_DEBUG(dbgs() << "Fixup kills for " << printMBBReference(MBB) << '\n');
lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp 355 LLVM_DEBUG(dbgs() << "********** List Scheduling " << printMBBReference(*BB)
1472 else dbgs() << printReg(LRegs[0], TRI);
lib/CodeGen/SelectionDAG/ScheduleDAGVLIW.cpp 94 LLVM_DEBUG(dbgs() << "********** List Scheduling " << printMBBReference(*BB)
lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp 621 OS << ' ' << printReg(R->getReg(),
759 OS << "(SDNODE=" << PrintNodeId(*getSDNode()) << ':' << getResNo() << ')';
844 OS << PrintNodeId(*this) << ": ";
861 OS << PrintNodeId(*Value.getNode());
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp 805 << printMBBReference(*FuncInfo->MBB) << " '" << BlockName
825 << printMBBReference(*FuncInfo->MBB) << " '" << BlockName
847 << printMBBReference(*FuncInfo->MBB) << " '" << BlockName
871 << printMBBReference(*FuncInfo->MBB) << " '" << BlockName
884 << printMBBReference(*FuncInfo->MBB) << " '" << BlockName
895 << printMBBReference(*FuncInfo->MBB) << " '" << BlockName
910 << printMBBReference(*FuncInfo->MBB) << " '" << BlockName
935 << printMBBReference(*FuncInfo->MBB) << " '" << BlockName
955 << printMBBReference(*FuncInfo->MBB) << " '" << BlockName
974 << printMBBReference(*FuncInfo->MBB) << " '" << BlockName
1096 << printMBBReference(*FuncInfo->MBB) << " '"
lib/CodeGen/SplitKit.cpp 731 LLVM_DEBUG(dbgs() << " enterIntvAtEnd " << printMBBReference(MBB) << ", "
811 LLVM_DEBUG(dbgs() << " leaveIntvAtTop " << printMBBReference(MBB) << ", "
911 LLVM_DEBUG(dbgs() << "Def in " << printMBBReference(*DefMBB)
912 << " dominates " << printMBBReference(*MBB)
919 LLVM_DEBUG(dbgs() << "Def in " << printMBBReference(*DefMBB)
920 << " dominates " << printMBBReference(*MBB)
930 LLVM_DEBUG(dbgs() << "Def in " << printMBBReference(*DefMBB)
931 << " dominates " << printMBBReference(*MBB)
1072 << printMBBReference(*Dom.first) << ' ' << Dom.second
1149 << printReg(Edit->get(RegIdx)) << ')');
1182 LLVM_DEBUG(dbgs() << ':' << VNI->id << "*" << printMBBReference(*MBB));
1195 LLVM_DEBUG(dbgs() << ">" << printMBBReference(*MBB));
1338 LLVM_DEBUG(dbgs() << " rewr " << printMBBReference(*MI->getParent())
1708 LLVM_DEBUG(dbgs() << printMBBReference(*BI.MBB) << " [" << Start << ';'
1801 LLVM_DEBUG(dbgs() << printMBBReference(*BI.MBB) << " [" << Start << ';'
lib/CodeGen/StackColoring.cpp 737 << " at " << printMBBReference(*MBB) << " index ");
lib/CodeGen/StackMaps.cpp 195 OS << printReg(Loc.Reg, TRI);
202 OS << printReg(Loc.Reg, TRI);
211 OS << printReg(Loc.Reg, TRI);
235 OS << printReg(LO.Reg, TRI);
lib/CodeGen/TailDuplicator.cpp 114 dbgs() << "Malformed PHI in " << printMBBReference(*MBB) << ": "
117 << printMBBReference(*PredBB) << '\n';
125 dbgs() << "Warning: malformed PHI in " << printMBBReference(*MBB)
128 << printMBBReference(*PHIBB) << '\n';
132 dbgs() << "Malformed PHI in " << printMBBReference(*MBB) << ": "
134 dbgs() << " non-existing " << printMBBReference(*PHIBB) << '\n';
801 LLVM_DEBUG(dbgs() << "\n*** Tail-duplicating " << printMBBReference(*TailBB)
lib/CodeGen/TargetRegisterInfo.cpp 73 dbgs() << "Error: Super register " << printReg(*SR, this)
74 << " of reserved register " << printReg(Reg, this)
148 OS << printRegUnit(Unit, TRI);
521 dbgs() << printReg(Reg, TRI, SubRegIndex) << "\n";
lib/CodeGen/VirtRegMap.cpp 142 OS << '[' << printReg(Reg, TRI) << " -> "
143 << printReg(Virt2PhysMap[Reg], TRI) << "] "
151 OS << '[' << printReg(Reg, TRI) << " -> fi#" << Virt2StackSlotMap[Reg]
lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp 543 LLVM_DEBUG(dbgs() << " - Scavenged register: " << printReg(Reg, TRI) << "\n");
617 << printReg(DestReg, TRI) << " at " << *MI);
637 << printReg(AccumReg, TRI) << " in MI " << *MI);
663 << printReg(DestReg, TRI) << "\n");
691 LLVM_DEBUG(dbgs() << "Kill seen for chain " << printReg(MO.getReg(), TRI)
703 << printReg(I->first, TRI) << "\n");
lib/Target/AArch64/AArch64ConditionOptimizer.cpp 210 LLVM_DEBUG(dbgs() << "Flags not defined in " << printMBBReference(*MBB)
lib/Target/AArch64/AArch64ConditionalCompares.cpp 372 LLVM_DEBUG(dbgs() << "Flags not defined in " << printMBBReference(*MBB)
387 LLVM_DEBUG(dbgs() << printMBBReference(*MBB) << " has live-ins.\n");
400 LLVM_DEBUG(dbgs() << printMBBReference(*MBB) << " has more than "
462 LLVM_DEBUG(dbgs() << "\nTriangle: " << printMBBReference(*Head) << " -> "
463 << printMBBReference(*CmpBB) << " -> "
464 << printMBBReference(*Tail) << '\n');
570 LLVM_DEBUG(dbgs() << "Merging " << printMBBReference(*CmpBB) << " into "
571 << printMBBReference(*Head) << ":\n"
lib/Target/AArch64/AArch64FalkorHWPFFix.cpp 762 << printReg(ScratchReg, TRI) << '\n');
781 << printReg(ScratchReg, TRI) << '\n');
lib/Target/AArch64/AArch64FrameLowering.cpp 2029 LLVM_DEBUG(dbgs() << "CSR spill: (" << printReg(Reg1, TRI);
2030 if (RPI.isPaired()) dbgs() << ", " << printReg(Reg2, TRI);
2120 LLVM_DEBUG(dbgs() << "CSR restore: (" << printReg(Reg1, TRI);
2121 if (RPI.isPaired()) dbgs() << ", " << printReg(Reg2, TRI);
2248 << ' ' << printReg(Reg, RegInfo);
2276 LLVM_DEBUG(dbgs() << "Spilling " << printReg(UnspilledCSGPR, RegInfo)
lib/Target/AArch64/AArch64PBQPRegAlloc.cpp 249 LLVM_DEBUG(dbgs() << "Moving acc chain from " << printReg(Ra, TRI)
250 << " to " << printReg(Rd, TRI) << '\n';);
255 LLVM_DEBUG(dbgs() << "Creating new acc chain for " << printReg(Rd, TRI)
342 LLVM_DEBUG(dbgs() << "Killing chain " << printReg(r, TRI) << " at ";
lib/Target/AArch64/AArch64SpeculationHardening.cpp 310 if (TmpReg != 0) dbgs() << printReg(TmpReg, TRI) << " ";
335 << printReg(MI_Reg.second, TRI)
345 << printReg(MI_Reg.second, TRI)
lib/Target/AMDGPU/AMDGPUArgumentUsageInfo.cpp 30 OS << "Reg " << printReg(getRegister(), TRI);
lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp 270 dbgs() << "Dest: " << printReg(Element.DestReg, TRI)
273 dbgs() << printReg(SI.first, TRI) << '(' << printMBBReference(*SI.second)
273 dbgs() << printReg(SI.first, TRI) << '(' << printMBBReference(*SI.second)
503 dbgs() << " In: " << printReg(getBBSelectRegIn(), TRI);
504 dbgs() << ", Out: " << printReg(getBBSelectRegOut(), TRI) << "\n";
553 dbgs() << " In: " << printReg(getBBSelectRegIn(), TRI);
554 dbgs() << ", Out: " << printReg(getBBSelectRegOut(), TRI) << "\n";
661 LLVM_DEBUG(dbgs() << "Visiting " << printMBBReference(*MBB) << "\n");
698 LLVM_DEBUG(dbgs() << "Considering Register: " << printReg(Reg, TRI)
703 LLVM_DEBUG(dbgs() << "Add LiveOut (PHI): " << printReg(Reg, TRI) << "\n");
709 LLVM_DEBUG(dbgs() << "Add LiveOut (MBB " << printMBBReference(*MBB)
710 << "): " << printReg(Reg, TRI) << "\n");
721 LLVM_DEBUG(dbgs() << "Add LiveOut (Loop): " << printReg(Reg, TRI)
738 LLVM_DEBUG(dbgs() << "Considering Register: " << printReg(Reg, TRI)
743 << "): " << printReg(Reg, TRI) << "\n");
754 LLVM_DEBUG(dbgs() << "-Store Live Outs Begin (" << printMBBReference(*MBB)
780 << "Add LiveOut (PhiSource " << printMBBReference(*MBB)
781 << " -> " << printMBBReference(*(*SI))
782 << "): " << printReg(PHIReg, TRI) << "\n");
851 << "): " << printReg(PHIReg, TRI) << "\n");
874 << "): In:" << printReg(getBBSelectRegIn(), TRI)
875 << " Out:" << printReg(getBBSelectRegOut(), TRI) << " {";
877 OS << printReg(LI, TRI) << " ";
917 << printReg(Register, MRI->getTargetRegisterInfo()) << " with "
918 << printReg(NewRegister, MRI->getTargetRegisterInfo()) << "\n");
954 << printReg(NewRegister, MRI->getTargetRegisterInfo())
959 << printReg(Register, MRI->getTargetRegisterInfo())
961 << printReg(NewRegister, MRI->getTargetRegisterInfo())
1032 LLVM_DEBUG(dbgs() << printReg(Reg, TRI) << "\n");
1037 << printReg(Reg, MRI->getTargetRegisterInfo())
1041 << printReg(Reg, MRI->getTargetRegisterInfo())
1051 << printReg(Reg, TRI) << "\n");
1459 LLVM_DEBUG(dbgs() << " to " << printReg(getPHIDestReg(PHI), TRI)
1490 LLVM_DEBUG(dbgs() << printReg(CombinedSourceReg, TRI) << ", "
1491 << printMBBReference(*SourceMBB));
1502 LLVM_DEBUG(dbgs() << printReg(SourceReg, TRI) << ", "
1503 << printMBBReference(*SourcePred));
1516 LLVM_DEBUG(dbgs() << " with " << printReg(getPHIDestReg(PHI), TRI)
1534 LLVM_DEBUG(dbgs() << printReg(CombinedSourceReg, TRI) << ", "
1535 << printMBBReference(*LastMerge));
1544 LLVM_DEBUG(dbgs() << printReg(SourceReg, TRI) << ", "
1545 << printMBBReference(*SourcePred));
1572 LLVM_DEBUG(dbgs() << " register " << printReg(CombinedSourceReg, TRI)
1576 LLVM_DEBUG(dbgs() << printReg(getPHIDestReg(PHI), TRI) << " = PHI(");
1583 LLVM_DEBUG(dbgs() << printReg(CombinedSourceReg, TRI) << ", "
1584 << printMBBReference(*IfMBB));
1594 LLVM_DEBUG(dbgs() << printReg(SourceReg, TRI) << ", "
1595 << printMBBReference(*SourcePred));
1619 LLVM_DEBUG(dbgs() << "Register " << printReg(Reg, TRI) << " is "
1762 LLVM_DEBUG(dbgs() << "Merge PHI (" << printMBBReference(*MergeBB)
1763 << "): " << printReg(DestRegister, TRI) << " = PHI("
1764 << printReg(IfSourceRegister, TRI) << ", "
1765 << printMBBReference(*IfBB)
1766 << printReg(CodeSourceRegister, TRI) << ", "
1767 << printMBBReference(*CodeBB) << ")\n");
1825 LLVM_DEBUG(dbgs() << "Removing edge: " << printMBBReference(*Edge.first)
1826 << " -> " << printMBBReference(*Edge.second) << "\n");
1864 LLVM_DEBUG(dbgs() << "Moved " << printMBBReference(*CodeBBStart)
1865 << " through " << printMBBReference(*CodeBBEnd) << "\n");
1951 << printReg(Reg, MRI->getTargetRegisterInfo())
1955 << printReg(Reg, MRI->getTargetRegisterInfo())
2039 LLVM_DEBUG(dbgs() << "LiveOut: " << printReg(LI, TRI));
2065 LLVM_DEBUG(dbgs() << "Initializer for reg: " << printReg(Reg) << "\n");
2081 << printMBBReference(*CodeBB) << "\n");
2162 LLVM_DEBUG(dbgs() << "Entry PHI " << printReg(DestReg, TRI) << " = PHI(");
2188 << printReg(NewBackedgeReg, TRI) << " = PHI("
2189 << printReg(CurrentBackedgeReg, TRI) << ", "
2190 << printMBBReference(*getPHIPred(*PHIDefInstr, 0)) << ", "
2191 << printReg(getPHISourceReg(*PHIDefInstr, 1), TRI) << ", "
2192 << printMBBReference(*(*SRI).second));
2197 LLVM_DEBUG(dbgs() << printReg(SourceReg, TRI) << ", "
2198 << printMBBReference(*(*SRI).second) << ", ");
2206 LLVM_DEBUG(dbgs() << printReg(CurrentBackedgeReg, TRI) << ", "
2207 << printMBBReference(*Exit) << ")\n");
2237 << printReg(NewRegister, MRI->getTargetRegisterInfo())
2245 << printReg(Register, MRI->getTargetRegisterInfo())
2247 << printReg(NewRegister, MRI->getTargetRegisterInfo())
2265 LLVM_DEBUG(dbgs() << "DestReg: " << printReg(DestReg, TRI) << "\n");
2268 LLVM_DEBUG(dbgs() << "DestReg: " << printReg(DestReg, TRI)
2269 << " SourceReg: " << printReg(SourceReg, TRI) << "\n");
2456 LLVM_DEBUG(dbgs() << "Split Entry PHI " << printReg(NewDestReg, TRI)
2460 LLVM_DEBUG(dbgs() << printReg(PHISource, TRI) << ", "
2461 << printMBBReference(*Entry));
2464 LLVM_DEBUG(dbgs() << " ," << printReg(RegionSourceReg, TRI) << ", "
2465 << printMBBReference(*RegionSourceMBB) << ")\n");
2547 LLVM_DEBUG(dbgs() << "Split " << printMBBReference(*Entry) << " to "
2548 << printMBBReference(*Entry) << " -> "
2549 << printMBBReference(*EntrySucc) << "\n");
2688 LLVM_DEBUG(dbgs() << "BBSelectRegIn: " << printReg(BBSelectRegIn, TRI)
2690 LLVM_DEBUG(dbgs() << "BBSelectRegOut: " << printReg(BBSelectRegOut, TRI)
2712 LLVM_DEBUG(dbgs() << "BBSelectRegIn: " << printReg(BBSelectRegIn, TRI)
2714 LLVM_DEBUG(dbgs() << "BBSelectRegOut: " << printReg(BBSelectRegOut, TRI)
2819 LLVM_DEBUG(dbgs() << "Add LiveOut (BBSelect): " << printReg(SelectOut, TRI)
lib/Target/AMDGPU/AMDGPUPerfHintAnalysis.cpp 361 << print() << "<=>\n"
362 << Reference.print() << "Result:" << Result << '\n');
lib/Target/AMDGPU/GCNIterativeScheduler.cpp 67 OS << BB->getParent()->getName() << ":" << printMBBReference(*BB) << ' '
lib/Target/AMDGPU/GCNNSAReassign.cpp 298 dbgs() << " " << llvm::printReg((VRM->getPhys(LI->reg)), TRI);
335 << llvm::printReg((VRM->getPhys(Intervals.front()->reg)), TRI)
337 << llvm::printReg((VRM->getPhys(Intervals.back()->reg)), TRI)
lib/Target/AMDGPU/GCNRegBankReassign.cpp 94 dbgs() << P->printReg(Reg) << " to banks ";
234 OS << llvm::printReg(Reg, TRI);
238 OS << "<unassigned> " << llvm::printReg(Reg, TRI);
240 OS << llvm::printReg(Reg, TRI) << '('
241 << llvm::printReg(VRM->getPhys(Reg), TRI) << ')';
256 dbgs() << printBank(L) << ' ';
517 dbgs() << "Potential reassignments of " << printReg(Reg, SubReg)
548 LLVM_DEBUG(dbgs() << "Conflicting operands: " << printReg(Reg1, SubReg1) <<
549 " and " << printReg(Reg2, SubReg2) << '\n');
610 LLVM_DEBUG(dbgs() << "Trying register " << printReg(Reg) << '\n');
624 LLVM_DEBUG(dbgs() << "Try reassign " << printReg(C.Reg) << " in "; C.MI->dump();
646 LLVM_DEBUG(dbgs() << "Trying bank " << printBank(Bank) << '\n');
649 LLVM_DEBUG(dbgs() << "With bank " << printBank(Bank) << " -> "
663 LLVM_DEBUG(dbgs() << "No free registers in bank " << printBank(BS.Bank)
667 LLVM_DEBUG(dbgs() << "Found free register " << printReg(Reg)
669 << " in bank " << printBank(BS.Bank) << '\n');
lib/Target/AMDGPU/GCNRegPressure.cpp 52 dbgs() << " " << printReg(Reg, MRI.getTargetRegisterInfo())
450 dbgs() << " " << printReg(P.first, TRI)
451 << ":L" << PrintLaneMask(P.second)
455 dbgs() << " " << printReg(P.first, TRI)
457 << PrintLaneMask(I->second)
459 << PrintLaneMask(P.second)
466 dbgs() << " " << printReg(P.first, TRI)
467 << ":L" << PrintLaneMask(P.second)
504 OS << ' ' << printVRegOrUnit(Reg, TRI) << ':'
505 << PrintLaneMask(It->second);
lib/Target/AMDGPU/GCNSchedStrategy.cpp 574 LLVM_DEBUG(dbgs() << MF.getName() << ":" << printMBBReference(*MBB) << " "
lib/Target/AMDGPU/SIFixSGPRCopies.cpp 498 << printMBBReference(*MI2->getParent()) << " " << *MI2);
508 << printMBBReference(*MI1->getParent()) << " " << *MI1);
526 << printMBBReference(*MI1->getParent()) << " " << *MI1
528 << printMBBReference(*MI2->getParent()) << " to "
529 << printMBBReference(*I->getParent()) << " " << *MI2);
lib/Target/AMDGPU/SIFrameLowering.cpp 1034 dbgs() << "Spilling FP to " << printReg(Spill.VGPR, TRI)
1052 dbgs() << "FP requires fallback spill to " << printReg(Spill.VGPR, TRI)
1055 LLVM_DEBUG(dbgs() << "Saving FP with copy to " <<
lib/Target/AMDGPU/SIMachineFunctionInfo.cpp 423 OS << printReg(Reg, &TRI);
442 OS << printReg(Arg.getRegister(), &TRI);
lib/Target/AMDGPU/SIMachineScheduler.cpp 604 dbgs() << printVRegOrUnit(Reg, DAG->getTRI()) << ' ';
608 dbgs() << printVRegOrUnit(Reg, DAG->getTRI()) << ' ';
1635 << printVRegOrUnit(Reg, DAG->getTRI()) << ' ';
2047 << printMBBReference(*begin()->getParent()) << " ***\n";
lib/Target/AMDGPU/SIOptimizeExecMasking.cpp 345 << printReg(CopyToExec, TRI) << '\n');
lib/Target/AMDGPU/SIWholeQuadMode.cpp 231 << printMBBReference(*BII.first) << ":\n"
703 LLVM_DEBUG(dbgs() << "\nProcessing block " << printMBBReference(MBB)
lib/Target/ARC/ARCInstrInfo.cpp 313 LLVM_DEBUG(dbgs() << "Created store reg=" << printReg(SrcReg, TRI)
340 LLVM_DEBUG(dbgs() << "Created load reg=" << printReg(DestReg, TRI)
lib/Target/ARC/ARCRegisterInfo.cpp 68 LLVM_DEBUG(dbgs() << "Scavenged register " << printReg(BaseReg, TRI)
69 << " for FrameReg=" << printReg(FrameReg, TRI)
lib/Target/ARM/A15SDOptimizer.cpp 275 LLVM_DEBUG(dbgs() << printReg(FullReg) << "\n");
645 << printReg(NewReg) << "\n");
lib/Target/ARM/ARMBasicBlockInfo.cpp 100 LLVM_DEBUG(dbgs() << "Branch of destination " << printMBBReference(*DestBB)
101 << " from " << printMBBReference(*MI->getParent())
lib/Target/ARM/ARMConstantIslandPass.cpp 1074 << printMBBReference(*MI->getParent()) << ": "
1242 LLVM_DEBUG(dbgs() << "Found water after " << printMBBReference(*WaterBB)
1287 LLVM_DEBUG(dbgs() << "Split at end of " << printMBBReference(*UserMBB)
1711 LLVM_DEBUG(dbgs() << " Insert B to " << printMBBReference(*DestBB)
1713 << printMBBReference(*NextBB) << "\n");
2302 LLVM_DEBUG(dbgs() << printMBBReference(*MBB) << ": " << *NewJTMI);
lib/Target/ARM/ARMConstantPoolValue.cpp 296 O << printMBBReference(*MBB);
lib/Target/ARM/ARMFrameLowering.cpp 1928 << printReg(Reg, TRI)
1948 LLVM_DEBUG(dbgs() << printReg(Reg, TRI)
1955 << printReg(Reg, TRI)
1978 LLVM_DEBUG(dbgs() << printReg(Reg, TRI)
2008 LLVM_DEBUG(dbgs() << "Spilling " << printReg(Reg, TRI)
2060 LLVM_DEBUG(dbgs() << "Spilling " << printReg(Reg, TRI)
2071 LLVM_DEBUG(dbgs() << "Spilling " << printReg(Reg, TRI)
lib/Target/Hexagon/BitTracker.cpp 184 dbgs() << printReg(P.first, &ME.TRI) << " -> " << P.second << "\n";
801 dbgs() << "Visit FI(" << printMBBReference(*PI.getParent()) << "): " << PI;
818 dbgs() << " edge " << printMBBReference(*PB) << "->"
819 << printMBBReference(*PI.getParent());
829 dbgs() << " input reg: " << printReg(RU.Reg, &ME.TRI, RU.Sub)
836 dbgs() << "Output: " << printReg(DefRR.Reg, &ME.TRI, DefRR.Sub)
845 dbgs() << "Visit MI(" << printMBBReference(*MI.getParent()) << "): " << MI;
859 dbgs() << " input reg: " << printReg(RU.Reg, &ME.TRI, RU.Sub)
865 dbgs() << " " << printReg(P.first, &ME.TRI) << " cell: "
930 dbgs() << "Visit BR(" << printMBBReference(B) << "): " << MI;
946 dbgs() << " " << printMBBReference(*BTs[i]);
982 dbgs() << "queuing uses of modified reg " << printReg(Reg, &ME.TRI)
lib/Target/Hexagon/HexagonBitSimplify.cpp 175 OS << ' ' << printReg(R, P.TRI);
2459 dbgs() << __func__ << " on reg: " << printReg(RD.Reg, &HRI, RD.Sub)
3105 LLVM_DEBUG(dbgs() << "Processing loop in " << printMBBReference(*C.LB)
3133 dbgs() << ' ' << printReg(I.DefR, HRI) << "=phi("
3134 << printReg(I.PR.Reg, HRI, I.PR.Sub) << ":b" << I.PB->getNumber()
3135 << ',' << printReg(I.LR.Reg, HRI, I.LR.Sub) << ":b"
3255 << printReg(G.Inp.Reg, HRI, G.Inp.Sub)
3256 << " out: " << printReg(G.Out.Reg, HRI, G.Out.Sub) << "\n";
lib/Target/Hexagon/HexagonBitTracker.cpp 107 dbgs() << printReg(Reg, &TRI, Sub) << " in reg class "
lib/Target/Hexagon/HexagonBlockRanges.cpp 533 OS << printReg(I.first.Reg, &P.TRI, I.first.Sub) << " -> " << RL << "\n";
lib/Target/Hexagon/HexagonConstExtenders.cpp 452 OS << printReg(P.Rs.Reg, &P.HRI, P.Rs.Sub);
469 OS << printReg(P.Ex.Rs.Reg, &P.HRI, P.Ex.Rs.Sub);
498 OS << printReg(ED.Rd.Reg, &HRI, ED.Rd.Sub);
lib/Target/Hexagon/HexagonConstPropagation.cpp 93 dbgs() << printReg(Reg, TRI, SubReg);
615 dbgs() << " " << printReg(I.first, &TRI) << " -> " << I.second << '\n';
622 LLVM_DEBUG(dbgs() << "Visiting FI(" << printMBBReference(*MB) << "): " << PN);
647 LLVM_DEBUG(dbgs() << " edge " << printMBBReference(*PB) << "->"
648 << printMBBReference(*MB) << " not executable\n");
663 LLVM_DEBUG(dbgs() << " edge from " << printMBBReference(*PB) << ": "
664 << printReg(UseR.Reg, &MCE.TRI, UseR.SubReg) << SrcC
677 LLVM_DEBUG(dbgs() << "Visiting MI(" << printMBBReference(*MI.getParent())
735 << printMBBReference(B) << "): " << MI);
777 LLVM_DEBUG(dbgs() << " pushing edge " << printMBBReference(B) << " -> "
778 << printMBBReference(*TB) << "\n");
784 LLVM_DEBUG(dbgs() << "Visiting uses of " << printReg(Reg, &MCE.TRI)
878 << printMBBReference(*MF.getBlockNumbered(Edge.first)) << "->"
879 << printMBBReference(*MF.getBlockNumbered(Edge.second)) << '\n');
942 dbgs() << " " << printMBBReference(B) << " -> "
943 << printMBBReference(*SB) << '\n';
2801 dbgs() << "Top " << printReg(R.Reg, &HRI, R.SubReg)
2817 dbgs() << printReg(R, &TRI) << ": " << Inputs.get(R) << "\n";
3139 LLVM_DEBUG(dbgs() << "Rewrite(" << printMBBReference(B) << "):" << BrI);
lib/Target/Hexagon/HexagonEarlyIfConv.cpp 146 << ", PredR:" << printReg(P.FP.PredR, &P.TRI)
240 LLVM_DEBUG(dbgs() << "Checking flow pattern at " << printMBBReference(*B)
lib/Target/Hexagon/HexagonExpandCondsets.cpp 669 LLVM_DEBUG(dbgs() << "\nsplitting " << printMBBReference(*MI.getParent())
1145 << printReg(R1.Reg, TRI, R1.Sub) << " " << L1 << "\n "
1146 << printReg(R2.Reg, TRI, R2.Sub) << " " << L2 << "\n");
lib/Target/Hexagon/HexagonFrameLowering.cpp 447 dbgs() << " " << printMBBReference(*B);
470 dbgs() << printMBBReference(*DomB);
475 dbgs() << printMBBReference(*PDomB);
1421 dbgs() << ' ' << printReg(R, &TRI);
1442 LLVM_DEBUG(dbgs() << ' ' << printReg(R, TRI));
1545 dbgs() << ' ' << printReg(CSI[i].getReg(), TRI) << ":fi#" << FI << ":sp";
1558 dbgs() << printReg(R, TRI) << ' ';
2060 LLVM_DEBUG(dbgs() << "Index map for " << printMBBReference(B) << "\n"
2179 dbgs() << " " << printMBBReference(*R.first) << " { " << R.second
2213 dbgs() << " " << printMBBReference(*P.first) << ": {";
2234 LLVM_DEBUG(dbgs() << printMBBReference(B) << " dead map\n"
2258 LLVM_DEBUG(dbgs() << "Replacement reg:" << printReg(FoundR, &HRI)
lib/Target/Hexagon/HexagonGenInsert.cpp 189 OS << ' ' << printReg(R, P.TRI);
430 OS << printReg(*I, P.TRI);
483 OS << '(' << printReg(SrcR, P.TRI) << ',' << printReg(InsR, P.TRI)
483 OS << '(' << printReg(SrcR, P.TRI) << ',' << printReg(InsR, P.TRI)
584 dbgs() << " " << printReg(I->first, HRI) << ":\n";
797 dbgs() << __func__ << ": " << printReg(VR, HRI)
862 dbgs() << "Prefixes matching register " << printReg(VR, HRI) << "\n";
867 dbgs() << " (" << printReg(LL[i].first, HRI) << ",@"
914 dbgs() << printReg(VR, HRI) << " = insert(" << printReg(SrcR, HRI)
914 dbgs() << printReg(VR, HRI) << " = insert(" << printReg(SrcR, HRI)
915 << ',' << printReg(InsR, HRI) << ",#" << L << ",#"
931 dbgs() << "visiting block " << printMBBReference(*B) << "\n";
1542 dbgs() << printReg(VR, HRI) << " -> " << Pos << "\n";
lib/Target/Hexagon/HexagonGenPredicate.cpp 78 return OS << printReg(PR.Reg.R, &PR.TRI, PR.Reg.S);
226 LLVM_DEBUG(dbgs() << __func__ << ": " << printReg(Reg.R, TRI, Reg.S) << "\n");
231 LLVM_DEBUG(dbgs() << "Dead reg: " << printReg(Reg.R, TRI, Reg.S) << '\n');
lib/Target/Hexagon/HexagonHardwareLoops.cpp 359 if (isReg()) { OS << printReg(Contents.R.Reg, TRI, Contents.R.Sub); }
1014 << printMBBReference(**L->block_begin()));
1370 << printMBBReference(**L->block_begin()));
lib/Target/Hexagon/HexagonInstrInfo.cpp 501 LLVM_DEBUG(dbgs() << "\nCant analyze " << printMBBReference(MBB)
549 LLVM_DEBUG(dbgs() << "\nCant analyze " << printMBBReference(MBB)
559 LLVM_DEBUG(dbgs() << "\nRemoving branches out of " << printMBBReference(MBB));
632 << printMBBReference(MBB););
878 dbgs() << "Invalid registers for copy in " << printMBBReference(MBB) << ": "
879 << printReg(DestReg, &HRI) << " = " << printReg(SrcReg, &HRI) << '\n';
879 << printReg(DestReg, &HRI) << " = " << printReg(SrcReg, &HRI) << '\n';
4368 << printMBBReference(*NewTarget);
lib/Target/Hexagon/HexagonMachineScheduler.cpp 193 << printMBBReference(*BB) << " " << BB->getName()
247 << printMBBReference(*begin()->getParent()) << " ***\n";
lib/Target/Hexagon/HexagonOptAddrMode.cpp 622 LLVM_DEBUG(dbgs() << "[MI <" << printMBBReference(*UseMI->getParent())
749 LLVM_DEBUG(dbgs() << "\t\t[MI <" << printMBBReference(*UseMI->getParent())
lib/Target/Hexagon/HexagonSplitDouble.cpp 140 dbgs() << ' ' << printReg(I, &TRI);
248 LLVM_DEBUG(dbgs() << printReg(R, TRI) << " ~~");
271 LLVM_DEBUG(dbgs() << ' ' << printReg(T, TRI));
566 dbgs() << "For loop at " << printMBBReference(*HB) << " ind regs: ";
1150 LLVM_DEBUG(dbgs() << "Created mapping: " << printReg(DR, TRI) << " -> "
1151 << printReg(HiR, TRI) << ':' << printReg(LoR, TRI)
1151 << printReg(HiR, TRI) << ':' << printReg(LoR, TRI)
lib/Target/Hexagon/RDFGraph.cpp 53 OS << ':' << PrintLaneMask(P.Mask);
238 OS << printMBBReference(*T->getMBB());
279 OS << Print<NodeId>(P.Obj.Id, P.G) << ": --- " << printMBBReference(*BB)
1108 << printMBBReference(*MI->getParent()) << '\n';
lib/Target/Hexagon/RDFLiveness.cpp 63 OS << ' ' << printReg(I.first, &P.G.getTRI()) << '{';
815 dbgs() << printMBBReference(B) << "\t rec = {";
964 dbgs() << "\n-- " << printMBBReference(*B) << ": " << __func__
lib/Target/Hexagon/RDFRegisters.cpp 367 OS << ' ' << printRegUnit(U, &PRI.getTRI());
lib/Target/MSP430/MSP430BranchSelector.cpp 142 << printMBBReference(*DestBB) << ", Distance "
149 << printMBBReference(*MBB) << "\n");
lib/Target/Mips/MipsConstantIslandPass.cpp 987 << printMBBReference(*MI->getParent()) << ": "
1192 LLVM_DEBUG(dbgs() << "Found water after " << printMBBReference(*WaterBB)
1230 LLVM_DEBUG(dbgs() << "Split at end of " << printMBBReference(*UserMBB)
1465 LLVM_DEBUG(dbgs() << "Branch of destination " << printMBBReference(*DestBB)
1466 << " from " << printMBBReference(*MI->getParent())
1611 LLVM_DEBUG(dbgs() << " Insert B to " << printMBBReference(*DestBB)
1613 << printMBBReference(*NextBB) << "\n");
lib/Target/PowerPC/PPCCTRLoops.cpp 155 LLVM_DEBUG(dbgs() << printMBBReference(*MBB) << " (" << MBB->getFullName()
158 << printMBBReference(*BI->getParent()) << " ("
175 << printMBBReference(*BI->getParent()) << " ("
lib/Target/PowerPC/PPCExpandISEL.cpp 172 LLVM_DEBUG(dbgs() << printMBBReference(*MF->getBlockNumbered(I.first))
197 << printMBBReference(*MF->getBlockNumbered(BlockList.first))
lib/Target/PowerPC/PPCMIPeephole.cpp 1317 << printMBBReference(*MBBtoMoveCmp)
lib/Target/SystemZ/SystemZMachineScheduler.cpp 81 LLVM_DEBUG(dbgs() << "** Entering " << printMBBReference(*NextMBB));
101 << printMBBReference(*SinglePredMBB) << "\n";);
121 LLVM_DEBUG(dbgs() << "** Leaving " << printMBBReference(*MBB) << "\n";);
lib/Target/X86/MCTargetDesc/X86WinCOFFTargetStreamer.cpp 327 FuncOS << CFAVar << ' ' << printFPOReg(MRI, FrameReg) << ' ' << FrameRegOff
352 FuncOS << printFPOReg(MRI, RO.Reg) << ' ' << CFAVar << ' ' << RO.Offset
lib/Target/X86/X86DomainReassignment.cpp 359 dbgs() << printReg(Reg, MRI->getTargetRegisterInfo(), 0, MRI);
lib/Target/X86/X86FloatingPoint.cpp 508 LLVM_DEBUG(dbgs() << "\nSetting up live-ins for " << printMBBReference(*MBB)
547 LLVM_DEBUG(dbgs() << "Setting up live-outs for " << printMBBReference(*MBB)
utils/TableGen/RegisterInfoEmitter.cpp 667 OS << "LaneBitmask(0x" << PrintLaneMask(Val) << ')';
1634 OS << "\tLaneMask: " << PrintLaneMask(RC.LaneMask) << '\n';
1659 OS << "\tLaneMask: " << PrintLaneMask(SRI.LaneMask) << '\n';