reference, declarationdefinition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

include/llvm/CodeGen/MachineInstr.h
  640       return getDesc().getFlags() & (1ULL << MCFlag);
include/llvm/CodeGen/ScheduleDAG.h
  582       if (SU->isInstr()) return &SU->getInstr()->getDesc();
include/llvm/CodeGen/TargetInstrInfo.h
  101            (MI.getDesc().isRematerializable() &&
  879     assert(MI.getDesc().isSelect() && "MI must be a select instruction");
 1315     return MI.getDesc().isPredicable();
lib/CodeGen/AggressiveAntiDepBreaker.cpp
  408     if (i < MI.getDesc().getNumOperands())
  409       RC = TII->getRegClass(MI.getDesc(), i, TRI, MF);
  492     if (i < MI.getDesc().getNumOperands())
  493       RC = TII->getRegClass(MI.getDesc(), i, TRI, MF);
lib/CodeGen/BreakFalseDeps.cpp
  126     TII->getRegClass(MI->getDesc(), OpIdx, TRI, *MF);
  198   const MCInstrDesc &MCID = MI->getDesc();
lib/CodeGen/CriticalAntiDepBreaker.cpp
  194     if (i < MI.getDesc().getNumOperands())
  195       NewRC = TII->getRegClass(MI.getDesc(), i, TRI, MF);
  311     if (i < MI.getDesc().getNumOperands())
  312       NewRC = TII->getRegClass(MI.getDesc(), i, TRI, MF);
lib/CodeGen/DFAPacketizer.cpp
  122   const MCInstrDesc &MID = MI.getDesc();
  129   const MCInstrDesc &MID = MI.getDesc();
lib/CodeGen/DetectDeadLanes.cpp
  281   if (MI.getDesc().getNumDefs() != 1)
  429       assert(UseMI.getDesc().getNumDefs() == 1);
lib/CodeGen/ExecutionDomainFix.cpp
  237   const MCInstrDesc &MCID = MI->getDesc();
  259   for (unsigned i = mi->getDesc().getNumDefs(),
  260                 e = mi->getDesc().getNumOperands();
  271   for (unsigned i = 0, e = mi->getDesc().getNumDefs(); i != e; ++i) {
  290     for (unsigned i = mi->getDesc().getNumDefs(),
  291                   e = mi->getDesc().getNumOperands();
lib/CodeGen/GlobalISel/LegalizerInfo.cpp
  480   const MCOperandInfo *OpInfo = MI.getDesc().OpInfo;
  482   for (unsigned i = 0; i < MI.getDesc().getNumOperands(); ++i) {
lib/CodeGen/GlobalISel/Localizer.cpp
  122     assert(MI.getDesc().getNumDefs() == 1 &&
lib/CodeGen/GlobalISel/Utils.cpp
  144     MO.setReg(constrainOperandRegClass(MF, TRI, MRI, TII, RBI, I, I.getDesc(),
  150       int DefIdx = I.getDesc().getOperandConstraint(OpI, MCOI::TIED_TO);
lib/CodeGen/ImplicitNullChecks.cpp
  621   unsigned NumDefs = MI->getDesc().getNumDefs();
lib/CodeGen/LiveDebugValues.cpp
  284       const auto &IID = MI.getDesc();
lib/CodeGen/LiveRangeEdit.cpp
  293       MI->getDesc().getNumDefs() == 1) {
lib/CodeGen/MachineInstr.cpp
  135     : MCID(&MI.getDesc()), Info(MI.Info), debugLoc(MI.getDebugLoc()) {
  571     if (MII->getDesc().getFlags() & Mask) {
  840     return TII->getRegClass(getDesc(), OpIdx, TRI, MF);
 1025   const MCInstrDesc &MCID = getDesc();
 1400   for (unsigned i = MI.getDesc().getNumOperands(), e = MI.getNumOperands();
 1409   const MCInstrDesc &MCID = getDesc();
 1432   auto &OpInfo = getDesc().OpInfo[OpIdx];
 2090   return BuildMI(BB, I, Orig.getDebugLoc(), Orig.getDesc())
lib/CodeGen/MachineLICM.cpp
  850   for (unsigned i = 0, e = MI->getDesc().getNumOperands(); i != e; ++i) {
 1128   unsigned NumDefs = MI.getDesc().getNumDefs();
 1223   for (unsigned i = 0, e = MI.getDesc().getNumOperands(); i != e; ++i) {
lib/CodeGen/MachinePipeliner.cpp
  917     unsigned SchedClass = Inst->getDesc().getSchedClass();
  964     unsigned SchedClass = MI.getDesc().getSchedClass();
 3014   return canReserveResources(&MI.getDesc());
 3018   return reserveResources(&MI.getDesc());
lib/CodeGen/MachineVerifier.cpp
  921   const MCInstrDesc &MCID = MI->getDesc();
 1481   const MCInstrDesc &MCID = MI->getDesc();
 1595   const MCInstrDesc &MCID = MI->getDesc();
lib/CodeGen/PeepholeOptimizer.cpp
  869     NumDefs = MI.getDesc().getNumDefs();
 1169   assert(MI.getDesc().getNumDefs() == 1 &&
 1314   const MCInstrDesc &MCID = MI.getDesc();
 1333   const MCInstrDesc &MCID = MI.getDesc();
 1354   for (unsigned i = 0, e = MI.getDesc().getNumOperands(); i != e; ++i) {
 1517   if (MI.getDesc().getNumDefs() != 1)
 1755         const MCInstrDesc &MIDesc = MI->getDesc();
 1836   if (Def->getDesc().getNumDefs() != 1)
 2052            (DefIdx < Def->getDesc().getNumDefs() ||
 2053             Def->getDesc().isVariadic())) ||
lib/CodeGen/ReachingDefAnalysis.cpp
  101   const MCInstrDesc &MCID = MI->getDesc();
lib/CodeGen/RegAllocFast.cpp
 1013   const MCInstrDesc &MCID = MI.getDesc();
lib/CodeGen/RegisterCoalescer.cpp
 1238   const MCInstrDesc &MCID = DefMI->getDesc();
 1312                       CopyMI->getDesc().getNumOperands());
 1313   for (unsigned I = CopyMI->getDesc().getNumOperands(),
 1333   for (unsigned i = NewMI.getDesc().getNumOperands(),
lib/CodeGen/ScheduleDAGInstrs.cpp
  238   const MCInstrDesc *DefMIDesc = &SU->getInstr()->getDesc();
  265           (RegUse ? &UseSU->getInstr()->getDesc() : nullptr);
lib/CodeGen/SelectionDAG/FastISel.cpp
  840   const MCInstrDesc &MCID = Builder.getInstr()->getDesc();
lib/CodeGen/SelectionDAG/InstrEmitter.cpp
  303   const MCInstrDesc &MCID = MIB->getDesc();
lib/CodeGen/TargetInstrInfo.cpp
  159   const MCInstrDesc &MCID = MI.getDesc();
  196       MI.getDesc().getOperandConstraint(Idx1, MCOI::TIED_TO) == 0) {
  201              MI.getDesc().getOperandConstraint(Idx2, MCOI::TIED_TO) == 0) {
  291   const MCInstrDesc &MCID = MI.getDesc();
  327   const MCInstrDesc &MCID = MI.getDesc();
 1074   unsigned Class = MI.getDesc().getSchedClass();
 1108   return ItinData->getStageLatency(MI.getDesc().getSchedClass());
 1118   unsigned DefClass = DefMI.getDesc().getSchedClass();
 1145   unsigned DefClass = DefMI.getDesc().getSchedClass();
 1146   unsigned UseClass = UseMI.getDesc().getSchedClass();
lib/CodeGen/TargetLoweringBase.cpp
 1046     MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), MI->getDesc());
 1105   auto MIB = BuildMI(MF, MI.getDebugLoc(), MI.getDesc());
 1120   auto MIB = BuildMI(MF, MI.getDebugLoc(), MI.getDesc());
lib/CodeGen/TargetSchedule.cpp
  110     int UOps = InstrItins.getNumMicroOps(MI->getDesc().getSchedClass());
  135   unsigned SchedClass = MI->getDesc().getSchedClass();
  198       unsigned DefClass = DefMI->getDesc().getSchedClass();
  242       && !DefMI->getDesc().OpInfo[DefOperIdx].isOptionalDef()
  327     unsigned SchedClass = MI->getDesc().getSchedClass();
lib/CodeGen/TwoAddressInstructionPass.cpp
 1211   unsigned OpsNum = MI->getDesc().getNumOperands();
 1212   unsigned OtherOpIdx = MI->getDesc().getNumDefs();
 1251         OpsNum = MI->getDesc().getNumOperands();
 1463   const MCInstrDesc &MCID = MI->getDesc();
lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp
  518   unsigned RegClassID = ChainBegin->getDesc().OpInfo[0].RegClass;
lib/Target/AArch64/AArch64CallLowering.cpp
  913         *MF.getSubtarget().getRegBankInfo(), *MIB, MIB->getDesc(), Info.Callee,
  999         *MF.getSubtarget().getRegBankInfo(), *MIB, MIB->getDesc(), Info.Callee,
lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp
  141     const MCInstrDesc &Desc = MI.getDesc();
lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
   94   const MCInstrDesc &Desc = OldMI.getDesc();
lib/Target/AArch64/AArch64FastISel.cpp
 1138     const MCInstrDesc &II = MIB->getDesc();
lib/Target/AArch64/AArch64InstrInfo.cpp
   93   const MCInstrDesc &Desc = MI.getDesc();
 1583       assert(MI.getDesc().getNumOperands() == 3 &&
 1612       assert(MI.getDesc().getNumOperands() == 4 &&
 1619       assert(MI.getDesc().getNumOperands() == 4 &&
 1642       assert(MI.getDesc().getNumOperands() == 3 && MI.getOperand(0).isReg() &&
lib/Target/AMDGPU/GCNHazardRecognizer.cpp
  675   const MCInstrDesc &Desc = MI.getDesc();
lib/Target/AMDGPU/SIFoldOperands.cpp
  194     if (MI->getDesc().TSFlags & SIInstrFlags::IsPacked &&
  195         !(MI->getDesc().TSFlags & SIInstrFlags::IsMAI) &&
  486   const MCInstrDesc &Desc = UseMI->getDesc();
  820     const MCInstrDesc &UseDesc = UseMI->getDesc();
  840   const MCInstrDesc &FoldDesc = OpToFold.getParent()->getDesc();
  929   const MCInstrDesc &Desc = MI.getDesc();
lib/Target/AMDGPU/SIISelLowering.cpp
10399     if (const MCOperandInfo *OpInfo = MI.getDesc().OpInfo) {
lib/Target/AMDGPU/SIInstrInfo.cpp
  138     return MI.getNumOperands() == MI.getDesc().getNumOperands();
 1720   return findCommutedOpIndices(MI.getDesc(), SrcOpIdx0, SrcOpIdx1);
 2259     unsigned NumOps = MI.getDesc().getNumOperands() +
 2260       MI.getDesc().getNumImplicitUses();
 2926   const MCInstrDesc &InstDesc = MI.getDesc();
 3451       if (usesConstantBus(MRI, MO, MI.getDesc().OpInfo[OpIdx])) {
 3499       if (usesConstantBus(MRI, MO, MI.getDesc().OpInfo[OpIdx])) {
 3953   const MCInstrDesc &InstDesc = MI.getDesc();
 5785   const MCInstrDesc &Desc = MI.getDesc();
 6265   const auto RCID = MI.getDesc().OpInfo[Idx].RegClass;
lib/Target/AMDGPU/SIInstrInfo.h
  332     return MI.getDesc().TSFlags & SIInstrFlags::SALU;
  340     return MI.getDesc().TSFlags & SIInstrFlags::VALU;
  356     return MI.getDesc().TSFlags & SIInstrFlags::SOP1;
  364     return MI.getDesc().TSFlags & SIInstrFlags::SOP2;
  372     return MI.getDesc().TSFlags & SIInstrFlags::SOPC;
  380     return MI.getDesc().TSFlags & SIInstrFlags::SOPK;
  388     return MI.getDesc().TSFlags & SIInstrFlags::SOPP;
  396     return MI.getDesc().TSFlags & SIInstrFlags::IsPacked;
  404     return MI.getDesc().TSFlags & SIInstrFlags::VOP1;
  412     return MI.getDesc().TSFlags & SIInstrFlags::VOP2;
  420     return MI.getDesc().TSFlags & SIInstrFlags::VOP3;
  428     return MI.getDesc().TSFlags & SIInstrFlags::SDWA;
  436     return MI.getDesc().TSFlags & SIInstrFlags::VOPC;
  444     return MI.getDesc().TSFlags & SIInstrFlags::MUBUF;
  452     return MI.getDesc().TSFlags & SIInstrFlags::MTBUF;
  460     return MI.getDesc().TSFlags & SIInstrFlags::SMRD;
  470     return MI.getDesc().TSFlags & SIInstrFlags::DS;
  480     return MI.getDesc().TSFlags & SIInstrFlags::MIMG;
  488     return MI.getDesc().TSFlags & SIInstrFlags::Gather4;
  496     return MI.getDesc().TSFlags & SIInstrFlags::FLAT;
  502     auto Flags = MI.getDesc().TSFlags;
  517     return MI.getDesc().TSFlags & SIInstrFlags::EXP;
  525     return MI.getDesc().TSFlags & SIInstrFlags::WQM;
  533     return MI.getDesc().TSFlags & SIInstrFlags::DisableWQM;
  541     return MI.getDesc().TSFlags & SIInstrFlags::VGPRSpill;
  549     return MI.getDesc().TSFlags & SIInstrFlags::SGPRSpill;
  557     return MI.getDesc().TSFlags & SIInstrFlags::DPP;
  565     return MI.getDesc().TSFlags & SIInstrFlags::VOP3P;
  573     return MI.getDesc().TSFlags & SIInstrFlags::VINTRP;
  581     return MI.getDesc().TSFlags & SIInstrFlags::IsMAI;
  589     return MI.getDesc().TSFlags & SIInstrFlags::IsDOT;
  597     return MI.getDesc().TSFlags & (SIInstrFlags::SALU | SIInstrFlags::SMRD);
  601     return MI.getDesc().TSFlags & SIInstrFlags::VM_CNT;
  605     return MI.getDesc().TSFlags & SIInstrFlags::LGKM_CNT;
  609     return MI.getDesc().TSFlags & SIInstrFlags::SOPK_ZEXT;
  619     return MI.getDesc().TSFlags & SIInstrFlags::SCALAR_STORE;
  627     return MI.getDesc().TSFlags & SIInstrFlags::FIXED_SIZE;
  635     return MI.getDesc().TSFlags & SIInstrFlags::FPClamp;
  643     return MI.getDesc().TSFlags & SIInstrFlags::IntClamp;
  651       return MI.getDesc().TSFlags & ClampFlags;
  655     return MI.getDesc().TSFlags & SIInstrFlags::FPDPRounding;
  663     return MI.getDesc().TSFlags & SIInstrFlags::FPAtomic;
  709     if (!MI.getDesc().OpInfo || OpIdx >= MI.getDesc().NumOperands) {
  709     if (!MI.getDesc().OpInfo || OpIdx >= MI.getDesc().NumOperands) {
  713     return isInlineConstant(DefMO, MI.getDesc().OpInfo[OpIdx]);
  720     return isInlineConstant(MO, MI.getDesc().OpInfo[OpIdx].OperandType);
  725     if (!MI.getDesc().OpInfo || OpIdx >= MI.getDesc().NumOperands)
  725     if (!MI.getDesc().OpInfo || OpIdx >= MI.getDesc().NumOperands)
  737     return isInlineConstant(MO, MI.getDesc().OpInfo[OpIdx].OperandType);
lib/Target/AMDGPU/SIMemoryLegalizer.cpp
  577   assert(MI->getDesc().TSFlags & SIInstrFlags::maybeAtomic);
  591   assert(MI->getDesc().TSFlags & SIInstrFlags::maybeAtomic);
  605   assert(MI->getDesc().TSFlags & SIInstrFlags::maybeAtomic);
  638   assert(MI->getDesc().TSFlags & SIInstrFlags::maybeAtomic);
 1292       if (!(MI->getDesc().TSFlags & SIInstrFlags::maybeAtomic))
lib/Target/AMDGPU/SIShrinkInstructions.cpp
  172   for (unsigned i = MI.getDesc().getNumOperands() +
  173          MI.getDesc().getNumImplicitUses() +
  174          MI.getDesc().getNumImplicitDefs(), e = MI.getNumOperands();
lib/Target/ARC/ARCInstrInfo.cpp
  409   return MI.getDesc().getSize();
  413   const MCInstrDesc &MID = MI.getDesc();
  419   const MCInstrDesc &MID = MI.getDesc();
lib/Target/ARM/ARMBaseInstrInfo.cpp
  149   uint64_t TSFlags = MI.getDesc().TSFlags;
  169   const MCInstrDesc &MCID = MI.getDesc();
  669   if ((MI.getDesc().TSFlags & ARMII::DomainMask) == ARMII::DomainNEON)
  705   const MCInstrDesc &MCID = MI.getDesc();
 2257       BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), DefMI->getDesc(), DestReg);
 2260   const MCInstrDesc &DefDesc = DefMI->getDesc();
 2524   const MCInstrDesc &Desc = MI.getDesc();
 3215   const MCInstrDesc &DefMCID = DefMI.getDesc();
 3225   const MCInstrDesc &UseMCID = UseMI.getDesc();
 3336     const MCInstrDesc &Desc = MI.getDesc();
 3639   const MCInstrDesc &Desc = MI.getDesc();
 3801   return MI.getNumOperands() + 1 - MI.getDesc().getNumOperands();
 4285       ItinData, *ResolvedDefMI, DefIdx, ResolvedDefMI->getDesc(), DefAdj, DefMO,
 4286       Reg, *ResolvedUseMI, UseIdx, ResolvedUseMI->getDesc(), UseAdj);
 4614   const MCInstrDesc &MCID = MI.getDesc();
 4645   const MCInstrDesc &MCID = MI.getDesc();
 4700   unsigned DDomain = DefMI.getDesc().TSFlags & ARMII::DomainMask;
 4701   unsigned UDomain = UseMI.getDesc().TSFlags & ARMII::DomainMask;
 4722   unsigned DDomain = DefMI.getDesc().TSFlags & ARMII::DomainMask;
 4724     unsigned DefClass = DefMI.getDesc().getSchedClass();
 4855   unsigned Domain = MI.getDesc().TSFlags & ARMII::DomainMask;
 4952     for (unsigned i = MI.getDesc().getNumOperands(); i; --i)
 4971     for (unsigned i = MI.getDesc().getNumOperands(); i; --i)
 5004     for (unsigned i = MI.getDesc().getNumOperands(); i; --i)
 5039       for (unsigned i = MI.getDesc().getNumOperands(); i; --i)
 5199   assert(OpNum < MI.getDesc().getNumDefs() && "OpNum is not a def");
 5252   assert(DefIdx < MI.getDesc().getNumDefs() && "Invalid definition index");
 5279   assert(DefIdx < MI.getDesc().getNumDefs() && "Invalid definition index");
 5302   assert(DefIdx < MI.getDesc().getNumDefs() && "Invalid definition index");
lib/Target/ARM/ARMBaseRegisterInfo.cpp
  499   const MCInstrDesc &Desc = MI->getDesc();
  685   const MCInstrDesc &Desc = MI->getDesc();
  799        (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4 ||
  800        (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode6 ||
  801        (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrModeT2_i7 ||
  802        (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrModeT2_i7s2 ||
  803        (MI.getDesc().TSFlags & ARMII::AddrModeMask) ==
  813   const MCInstrDesc &MCID = MI.getDesc();
lib/Target/ARM/ARMCallLowering.cpp
  536           *MIB.getInstr(), MIB->getDesc(), Info.Callee, CalleeIdx));
lib/Target/ARM/ARMConstantIslandPass.cpp
  591     unsigned NumOps = MI->getDesc().getNumOperands();
 1524   U.CPEMI = BuildMI(NewIsland, DebugLoc(), CPEMI->getDesc())
 1990         BBInfo[MBB->getNumber()].Size -= LastMI->getDesc().getSize();
 2169     const MCInstrDesc &MCID = MI->getDesc();
 2363     const MCInstrDesc &MCID = MI->getDesc();
lib/Target/ARM/ARMExpandPseudoInsts.cpp
   94   const MCInstrDesc &Desc = OldMI.getDesc();
  672   unsigned Lane = MI.getOperand(MI.getDesc().getNumOperands() - 3).getImm();
lib/Target/ARM/ARMFastISel.cpp
  264   const MCInstrDesc &MCID = MI->getDesc();
lib/Target/ARM/ARMFrameLowering.cpp
 1532         const MCInstrDesc &MCID = MI.getDesc();
 1538         switch (MI.getDesc().TSFlags & ARMII::AddrModeMask) {
lib/Target/ARM/ARMHazardRecognizer.cpp
   21   const MCInstrDesc &MCID = MI->getDesc();
   42     const MCInstrDesc &MCID = MI->getDesc();
   45       const MCInstrDesc &LastMCID = LastMI->getDesc();
lib/Target/ARM/ARMISelLowering.cpp
10722   const MCInstrDesc *MCID = &MI.getDesc();
10738            MI.getDesc().getNumOperands() + 5 - MI.getDesc().getSize()
10738            MI.getDesc().getNumOperands() + 5 - MI.getDesc().getSize()
lib/Target/ARM/ARMLoadStoreOptimizer.cpp
  219   unsigned NumOperands = MI.getDesc().getNumOperands();
  472     return (MI->getNumOperands() - MI->getDesc().getNumOperands() + 1) * 4;
  475     return (MI->getNumOperands() - MI->getDesc().getNumOperands() + 1) * 8;
  507           MBBI->getOperand(MBBI->getDesc().getNumOperands() - 3);
  524           MBBI->getOperand(MBBI->getDesc().getNumOperands() - 3);
lib/Target/ARM/ARMLowOverheadLoops.cpp
  274       else if (MI.getDesc().isCall()) {
lib/Target/ARM/MLxExpansionPass.cpp
  184   const MCInstrDesc &MCID = MI->getDesc();
  339     const MCInstrDesc &MCID = MI->getDesc();
lib/Target/ARM/Thumb2ITBlockPass.cpp
  171   const MCInstrDesc &MCID = MI->getDesc();
lib/Target/ARM/Thumb2InstrInfo.cpp
  469   const MCInstrDesc &Desc = MI.getDesc();
  706   const MCInstrDesc &MCID = MI.getDesc();
lib/Target/ARM/Thumb2SizeReduction.cpp
  362     if (!HasImplicitCPSRDef(MI->getDesc()))
  645     const MCInstrDesc &MCID = MI->getDesc();
  805   const MCInstrDesc &MCID = MI->getDesc();
  865   const MCInstrDesc &MCID = MI->getDesc();
lib/Target/ARM/ThumbRegisterInfo.cpp
  370   const MCInstrDesc &Desc = MI.getDesc();
lib/Target/AVR/AVRFrameLowering.cpp
  157   assert(MBBI->getDesc().isReturn() &&
lib/Target/AVR/AVRInstrInfo.cpp
  287     if (!I->getDesc().isBranch()) {
lib/Target/Hexagon/HexagonBitSimplify.cpp
 1314     unsigned NumD = MI->getDesc().getNumDefs();
lib/Target/Hexagon/HexagonFrameLowering.cpp
 2087           auto *RC = HII.getRegClass(In.getDesc(), OpNum, &HRI, MF);
 2255         auto *RC = HII.getRegClass(SI.getDesc(), 2, &HRI, MF);
lib/Target/Hexagon/HexagonHardwareLoops.cpp
  441       if (DI->getDesc().isAdd()) {
  992   if (MI->getDesc().isCall())
 1640       if (DI->getDesc().isAdd()) {
lib/Target/Hexagon/HexagonInstrInfo.cpp
 1556   const uint64_t F = MI.getDesc().TSFlags;
 1645   if (!MI.getDesc().isPredicable())
 1705   if (MI.getDesc().isTerminator() || MI.isPosition())
 2005   const uint64_t F = MI.getDesc().TSFlags;
 2014   return !isTC1(MI) && !isTC2Early(MI) && !MI.getDesc().mayLoad() &&
 2015          !MI.getDesc().mayStore() &&
 2016          MI.getDesc().getOpcode() != Hexagon::S2_allocframe &&
 2017          MI.getDesc().getOpcode() != Hexagon::L2_deallocframe &&
 2029   const uint64_t F = MI.getDesc().TSFlags;
 2088   if (!ProdMI.getDesc().getNumDefs())
 2152   unsigned SchedClass = MI.getDesc().getSchedClass();
 2176   const MCInstrDesc &MID = MI.getDesc();
 2199   const uint64_t F = MI.getDesc().TSFlags;
 2344   unsigned SchedClass = MI.getDesc().getSchedClass();
 2399   const uint64_t F = MI.getDesc().TSFlags;
 2421   const uint64_t F = MI.getDesc().TSFlags;
 2433   const uint64_t F = MI.getDesc().TSFlags;
 2439   const uint64_t F = MI.getDesc().TSFlags;
 2451   const uint64_t F = MI.getDesc().TSFlags;
 2567   const uint64_t F = MI.getDesc().TSFlags;
 2593   unsigned SchedClass = MI.getDesc().getSchedClass();
 2598   unsigned SchedClass = MI.getDesc().getSchedClass();
 2603   unsigned SchedClass = MI.getDesc().getSchedClass();
 2608   unsigned SchedClass = MI.getDesc().getSchedClass();
 2997   if (MI.getDesc().mayLoad() || MI.getDesc().mayStore()) {
 2997   if (MI.getDesc().mayLoad() || MI.getDesc().mayStore()) {
 3043   const uint64_t F = MI.getDesc().TSFlags;
 3053   const uint64_t F = MI.getDesc().TSFlags;
 3148   const uint64_t F = MI.getDesc().TSFlags;
 3285   const uint64_t F = MI.getDesc().TSFlags;
 4082   return ItinData->getStageLatency(MI.getDesc().getSchedClass());
 4160   const uint64_t F = MI.getDesc().TSFlags;
 4191   const uint64_t F = MI.getDesc().TSFlags;
 4204   const uint64_t F = MI.getDesc().TSFlags;
 4222   const uint64_t F = MI.getDesc().TSFlags;
 4242   if (MI.getDesc().mayLoad() || MI.getDesc().mayStore()) {
 4242   if (MI.getDesc().mayLoad() || MI.getDesc().mayStore()) {
 4295   unsigned Size = MI.getDesc().getSize();
 4326   const uint64_t F = MI.getDesc().TSFlags;
 4332   const InstrStage &IS = *II.beginStage(MI.getDesc().getSchedClass());
 4399                       << "  Class: " << NewMI->getDesc().getSchedClass());
lib/Target/Hexagon/HexagonNewValueJump.cpp
  570               (MI.getDesc().isCompare()) &&
lib/Target/Hexagon/HexagonOptAddrMode.cpp
  126   const MCInstrDesc &MID = MI.getDesc();
  193     const MCInstrDesc &UseMID = UseMI.getDesc();
  356     const MCInstrDesc &MID = MI->getDesc();
  415   const MCInstrDesc &MID = UseMI->getDesc();
  443     const MCInstrDesc &MID = MI.getDesc();
  624     const MCInstrDesc &UseMID = UseMI->getDesc();
  671   const MCInstrDesc &MID = UseMI->getDesc();
lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
  337   return MI.getDesc().isTerminator() || MI.getDesc().isCall();
  337   return MI.getDesc().isTerminator() || MI.getDesc().isCall();
  654   const MCInstrDesc& MCID = PacketMI.getDesc();
  869   const MCInstrDesc& MCID = PI.getDesc();
 1052   const MCInstrDesc& TID = MI.getDesc();
lib/Target/Hexagon/RDFGraph.cpp
  627   const MCInstrDesc &D = In.getDesc();
lib/Target/Lanai/LanaiDelaySlotFiller.cpp
   97     if (I->getDesc().hasDelaySlot()) {
  229   MCInstrDesc MCID = MI->getDesc();
lib/Target/Lanai/LanaiInstrInfo.cpp
  514       BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), DefMI->getDesc(), DestReg);
  517   const MCInstrDesc &DefDesc = DefMI->getDesc();
lib/Target/MSP430/MSP430InstrInfo.cpp
  301   const MCInstrDesc &Desc = MI.getDesc();
lib/Target/Mips/Mips16InstrInfo.cpp
  148   switch (MI.getDesc().getOpcode()) {
lib/Target/Mips/MipsAsmPrinter.cpp
  166   for (unsigned int I = MI.getDesc().getNumOperands(), E = MI.getNumOperands();
lib/Target/Mips/MipsBranchExpansion.cpp
  226   for (unsigned I = 0, E = Br.getDesc().getNumOperands(); I < E; ++I) {
  342   for (unsigned I = 0, E = Br->getDesc().getNumOperands(); I < E; ++I) {
  712     assert(I.Br->getDesc().getNumOperands() == 1);
lib/Target/Mips/MipsConstantIslandPass.cpp
 1646       switch(I->getDesc().getOpcode()) {
lib/Target/Mips/MipsDelaySlotFiller.cpp
  351   update(MI, 0, MI.getDesc().getNumOperands());
  361     update(MI, MI.getDesc().getNumOperands(), MI.getNumOperands());
lib/Target/Mips/MipsInstrInfo.cpp
  567   return (MI.getDesc().TSFlags & MipsII::IsCTI) == 0;
  572   return (MI.getDesc().TSFlags & MipsII::HasForbiddenSlot) != 0;
  579     return MI.getDesc().getSize();
  650     for (unsigned J = 0, E = I->getDesc().getNumOperands(); J < E; ++J) {
  658     for (unsigned J = I->getDesc().getNumOperands(), E = I->getNumOperands();
  667     for (unsigned J = 0, E = I->getDesc().getNumOperands(); J < E; ++J) {
  686   const MCInstrDesc &MCID = MI.getDesc();
lib/Target/Mips/MipsSEInstrInfo.cpp
  413   switch (MI.getDesc().getOpcode()) {
lib/Target/NVPTX/NVPTXAsmPrinter.cpp
  154   const MCInstrDesc &MCID = MI->getDesc();
lib/Target/NVPTX/NVPTXReplaceImageHandles.cpp
   81   const MCInstrDesc &MCID = MI.getDesc();
lib/Target/PowerPC/PPCInstrInfo.cpp
  159   unsigned DefClass = MI.getDesc().getSchedClass();
  407     assert(MI.getDesc().getOperandConstraint(0, MCOI::TIED_TO) &&
  427     return BuildMI(MF, MI.getDebugLoc(), MI.getDesc())
 1340   const MCInstrDesc &UseMCID = UseMI.getDesc();
lib/Target/PowerPC/PPCRegisterInfo.cpp
 1259   const MCInstrDesc &MCID = MI.getDesc();
lib/Target/RISCV/RISCVInstrInfo.cpp
  206   assert(LastInst.getDesc().isConditionalBranch() &&
  253     if (J->getDesc().isUnconditionalBranch() ||
  254         J->getDesc().isIndirectBranch()) {
  270   if (I->getDesc().isIndirectBranch())
  278   if (NumTerminators == 1 && I->getDesc().isUnconditionalBranch()) {
  284   if (NumTerminators == 1 && I->getDesc().isConditionalBranch()) {
  290   if (NumTerminators == 2 && std::prev(I)->getDesc().isConditionalBranch() &&
  291       I->getDesc().isUnconditionalBranch()) {
  309   if (!I->getDesc().isUnconditionalBranch() &&
  310       !I->getDesc().isConditionalBranch())
  323   if (!I->getDesc().isConditionalBranch())
  423   assert(MI.getDesc().isBranch() && "Unexpected opcode!");
lib/Target/SystemZ/SystemZElimCompare.cpp
  326   unsigned CompareFlags = Compare.getDesc().TSFlags;
  347       unsigned Flags = MI->getDesc().TSFlags;
lib/Target/SystemZ/SystemZHazardRecognizer.cpp
  120   const MCInstrDesc &MID = MI->getDesc();
lib/Target/SystemZ/SystemZInstrBuilder.h
   30   const MCInstrDesc &MCID = MI->getDesc();
lib/Target/SystemZ/SystemZInstrInfo.cpp
  311   const MCInstrDesc &MCID = MI.getDesc();
  903   const MCInstrDesc &MCID = MI->getDesc();
 1402   return MI.getDesc().getSize();
lib/Target/SystemZ/SystemZRegisterInfo.cpp
  305     if (MI->getDesc().TSFlags & SystemZII::HasIndex
lib/Target/SystemZ/SystemZShortenInst.cpp
   68   if (MI.getDesc().getOperandConstraint(0, MCOI::TIED_TO) &&
lib/Target/WebAssembly/WebAssemblyCallIndirectFixup.cpp
  130              make_range(MI.operands_begin() + MI.getDesc().getNumDefs() + 1,
  133         Ops.push_back(MI.getOperand(MI.getDesc().getNumDefs()));
  136         while (MI.getNumOperands() > MI.getDesc().getNumDefs())
lib/Target/WebAssembly/WebAssemblyExplicitLocals.cpp
  271       assert(MI.getDesc().getNumDefs() <= 1);
  272       if (MI.getDesc().getNumDefs() == 1) {
lib/Target/WebAssembly/WebAssemblyMCInstLower.cpp
  210   const MCInstrDesc &Desc = MI->getDesc();
lib/Target/WebAssembly/WebAssemblyRegStackify.cpp
  434         if (UseInst->getDesc().getNumDefs() == 0)
lib/Target/WebAssembly/WebAssemblySetP2AlignOperands.cpp
   65   assert(MI.getDesc().OpInfo[OperandNo].OperandType ==
lib/Target/X86/X86AvoidStoreForwardingBlocks.cpp
  290   const MCInstrDesc &Descl = MI->getDesc();
  350     if (MI.getDesc().isCall())
  374         if (PBInst->getDesc().isCall())
lib/Target/X86/X86CallFrameOptimization.cpp
  562         unsigned NumOps = DefMov->getDesc().getNumOperands();
lib/Target/X86/X86CallLowering.cpp
  453         *MF.getSubtarget().getRegBankInfo(), *MIB, MIB->getDesc(), Info.Callee,
lib/Target/X86/X86DiscriminateMemOps.cpp
  113       if (BypassPrefetchInstructions && IsPrefetchOpcode(MI.getDesc().Opcode))
  129       if (X86II::getMemoryOperandNo(MI.getDesc().TSFlags) < 0)
  131       if (BypassPrefetchInstructions && IsPrefetchOpcode(MI.getDesc().Opcode))
lib/Target/X86/X86DomainReassignment.cpp
  566     const MCInstrDesc &Desc = DefMI->getDesc();
lib/Target/X86/X86EvexToVex.cpp
  219   const MCInstrDesc &Desc = MI.getDesc();
lib/Target/X86/X86FastISel.cpp
  229   AM.IndexReg = constrainOperandRegClass(MIB->getDesc(), AM.IndexReg,
 3960     unsigned IndexReg = constrainOperandRegClass(Result->getDesc(),
lib/Target/X86/X86FixupLEAs.cpp
  446   const MCInstrDesc &Desc = MI.getDesc();
lib/Target/X86/X86FlagsCopyLowering.cpp
  849   CMovI.getOperand(CMovI.getDesc().getNumOperands() - 1)
lib/Target/X86/X86FloatingPoint.cpp
  419     uint64_t Flags = MI.getDesc().TSFlags;
 1115   unsigned NumOps = MI.getDesc().getNumOperands();
 1176   unsigned NumOps = MI.getDesc().getNumOperands();
 1287   unsigned NumOperands = MI.getDesc().getNumOperands();
 1383   unsigned NumOperands = MI.getDesc().getNumOperands();
lib/Target/X86/X86InsertPrefetch.cpp
  195       int Offset = X86II::getMemoryOperandNo(Current->getDesc().TSFlags);
  198       unsigned Bias = X86II::getOperandBias(Current->getDesc());
lib/Target/X86/X86InstrBuilder.h
  202   const MCInstrDesc &MCID = MI->getDesc();
lib/Target/X86/X86InstrInfo.cpp
  687   unsigned ShiftCountMask = (MI.getDesc().TSFlags & X86II::REX_W) ? 63 : 31;
 1373   unsigned Case = getThreeSrcCommuteCase(MI.getDesc().TSFlags, SrcOpIdx1,
 1418   unsigned Case = getThreeSrcCommuteCase(MI.getDesc().TSFlags, SrcOpIdx1,
 1807     unsigned OpNo = MI.getDesc().getNumOperands() - 1;
 1858                                                       MI.getDesc().TSFlags);
 1878   uint64_t TSFlags = MI.getDesc().TSFlags;
 1980   const MCInstrDesc &Desc = MI.getDesc();
 2140                                                       MI.getDesc().TSFlags);
 2153       if ((MI.getDesc().getOperandConstraint(Desc.getNumDefs(),
 2189         MI.getOperand(MI.getDesc().getNumOperands() - 1).getImm());
 2199         MI.getOperand(MI.getDesc().getNumOperands() - 1).getImm());
 2210         MI.getOperand(MI.getDesc().getNumOperands() - 1).getImm());
 3198   const MCInstrDesc &Desc = MemOp.getDesc();
 3823     Op.first->getOperand(Op.first->getDesc().getNumOperands() - 1)
 4648         Reg, TII.getRegClass(NewMI.getDesc(), Idx, &TRI, MF));
 4671   unsigned NumOps = MI.getDesc().getNumOperands() - 2;
 4744       const TargetRegisterClass *RC = getRegClass(MI.getDesc(), OpNum, &RI, MF);
 4768       const TargetRegisterClass *RC = getRegClass(MI.getDesc(), OpNum, &RI, MF);
 4787       const TargetRegisterClass *RC = getRegClass(MI.getDesc(), OpNum, &RI, MF);
 4844   unsigned NumOps = MI.getDesc().getNumOperands();
 4846       NumOps > 1 && MI.getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1;
 4900       const TargetRegisterClass *RC = getRegClass(MI.getDesc(), OpNum,
 4942       bool HasDef = MI.getDesc().getNumDefs();
 4947           0 == MI.getDesc().getOperandConstraint(CommuteOpIdx1, MCOI::TIED_TO);
 4949           0 == MI.getDesc().getOperandConstraint(CommuteOpIdx2, MCOI::TIED_TO);
 5204   unsigned NumOps = LoadMI.getDesc().getNumOperands();
 6591   unsigned NumOperands = MI.getDesc().getNumOperands();
 6690   uint16_t dom = (MI.getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
 6694   unsigned NumOperands = MI.getDesc().getNumOperands();
 6821   uint16_t domain = (MI.getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
 6862   uint16_t dom = (MI.getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
 8081       MI.getDesc().hasImplicitUseOfPhysReg(X86::RSP) ||
 8082       MI.getDesc().hasImplicitDefOfPhysReg(X86::RSP))
 8087       MI.getDesc().hasImplicitUseOfPhysReg(X86::RIP) ||
 8088       MI.getDesc().hasImplicitDefOfPhysReg(X86::RIP))
lib/Target/X86/X86InstrInfo.h
  522     return MI.getDesc().TSFlags & X86II::LOCK;
lib/Target/X86/X86MCInstLower.cpp
 2147       unsigned Width = getRegisterWidth(MI->getDesc().OpInfo[0]);
 2219       unsigned Width = getRegisterWidth(MI->getDesc().OpInfo[0]);
 2250       unsigned Width = getRegisterWidth(MI->getDesc().OpInfo[0]);
 2267       unsigned Width = getRegisterWidth(MI->getDesc().OpInfo[0]);
lib/Target/X86/X86OptimizeLEAs.cpp
  336   const MCInstrDesc &Desc = MI.getDesc();
  439     const MCInstrDesc &Desc = MI.getDesc();
  505     const MCInstrDesc &Desc = MI.getDesc();
  634           const MCInstrDesc &Desc = MI.getDesc();
lib/Target/X86/X86SpeculativeLoadHardening.cpp
 1701         const MCInstrDesc &Desc = MI.getDesc();
 1744             MI.getDesc().getNumDefs() == 1 && MI.getOperand(0).isReg() &&
 1779           const MCInstrDesc &Desc = MI.getDesc();
 2177         const MCInstrDesc &Desc = UseMI.getDesc();
 2207       if (UseMI.getDesc().getNumDefs() > 1)