reference, declarationdefinition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h
  752       OutMIs[NewInsnID]->setDesc(TII.get(NewOpcode));
lib/CodeGen/ExpandPostRAPseudos.cpp
   98     MI->setDesc(TII->get(TargetOpcode::KILL));
  111       MI->setDesc(TII->get(TargetOpcode::KILL));
  138     MI->setDesc(TII->get(TargetOpcode::KILL));
  155       MI->setDesc(TII->get(TargetOpcode::KILL));
lib/CodeGen/GlobalISel/CombinerHelper.cpp
  450   MI.setDesc(
lib/CodeGen/GlobalISel/LegalizerHelper.cpp
 1888       MI.setDesc(TII.get(TargetOpcode::G_BUILD_VECTOR_TRUNC));
 3688     MI.setDesc(TII.get(TargetOpcode::G_CTLZ));
 3738     MI.setDesc(TII.get(TargetOpcode::G_CTTZ));
 3780     MI.setDesc(TII.get(TargetOpcode::G_CTPOP));
lib/CodeGen/InlineSpiller.cpp
  474         MI.setDesc(TII.get(TargetOpcode::KILL));
 1520       RMEnt->setDesc(TII.get(TargetOpcode::KILL));
lib/CodeGen/LiveRangeEdit.cpp
  348     MI->setDesc(TII.get(TargetOpcode::KILL));
lib/CodeGen/PeepholeOptimizer.cpp
 1006       CopyLike.setDesc(TII.get(TargetOpcode::COPY));
lib/CodeGen/ProcessImplicitDefs.cpp
   87       UserMI->setDesc(TII->get(TargetOpcode::IMPLICIT_DEF));
lib/CodeGen/RegisterCoalescer.cpp
 1552       CopyMI->setDesc(TII->get(TargetOpcode::IMPLICIT_DEF));
lib/CodeGen/TwoAddressInstructionPass.cpp
 1771         mi->setDesc(TII->get(TargetOpcode::COPY));
 1863     MI.setDesc(TII->get(TargetOpcode::IMPLICIT_DEF));
lib/CodeGen/VirtRegMap.cpp
  387     MI.setDesc(TII->get(TargetOpcode::KILL));
lib/Target/AArch64/AArch64CompressJumpTables.cpp
  123     MI.setDesc(TII->get(AArch64::JumpTableDest8));
  128     MI.setDesc(TII->get(AArch64::JumpTableDest16));
lib/Target/AArch64/AArch64InstrInfo.cpp
 1200     CmpInstr.setDesc(MCID);
 1459   MI->setDesc(get(NewOpc));
 3484       MI.setDesc(TII->get(UnscaledOp));
lib/Target/AArch64/AArch64InstructionSelector.cpp
  751   I.setDesc(TII.get(AArch64::COPY));
 1308     I.setDesc(TII.get(TargetOpcode::COPY));
 1354       I.setDesc(TII.get(TargetOpcode::PHI));
 1440     I.setDesc(TII.get(AArch64::BR));
 1480     I.setDesc(TII.get(Opc));
 1575     I.setDesc(TII.get(MovOpc));
 1618     I.setDesc(TII.get(SrcSize == 64 ? AArch64::UBFMXri : AArch64::UBFMWri));
 1648     I.setDesc(TII.get(DstSize == 64 ? AArch64::BFMXri : AArch64::BFMWri));
 1680     I.setDesc(TII.get(AArch64::ADDXri));
 1696       I.setDesc(TII.get(AArch64::LOADgot));
 1704       I.setDesc(TII.get(AArch64::ADR));
 1707       I.setDesc(TII.get(AArch64::MOVaddr));
 1736         I.setDesc(TII.get(AArch64::LDARB));
 1762     I.setDesc(TII.get(NewOpc));
 1843     I.setDesc(TII.get(NewOpc));
 1878     I.setDesc(TII.get(NewOpc));
 1936     I.setDesc(TII.get(AArch64::ANDXri));
 1990       I.setDesc(TII.get(TargetOpcode::COPY));
 1994         I.setDesc(TII.get(AArch64::XTNv4i16));
 2137     I.setDesc(TII.get(NewOpc));
 2280     I.setDesc(TII.get(TargetOpcode::IMPLICIT_DEF));
 2295       I.setDesc(TII.get(AArch64::MOVaddrBA));
 2451   I.setDesc(TII.get(Opc));
 2506   I.setDesc(TII.get(Opc));
 3359   I.setDesc(TII.get(MovOpc));
lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
  115   I.setDesc(TII.get(TargetOpcode::COPY));
  210   I.setDesc(TII.get(TargetOpcode::PHI));
  274     I.setDesc(TII.get(InstOpc));
  292     I.setDesc(TII.get(InstOpc));
  322       I.setDesc(TII.get(Opc));
  410     I.setDesc(TII.get(NewOpc));
  553     I.setDesc(TII.get(TargetOpcode::IMPLICIT_DEF));
 1206   I.setDesc(TII.get(TargetOpcode::COPY));
 1428     I.setDesc(TII.get(Opcode));
 1604   I.setDesc(TII.get(IsVGPR ? AMDGPU::V_MOV_B32_e32 : AMDGPU::S_MOV_B32));
 1761     I.setDesc(TII.get(AMDGPU::ATOMIC_FENCE));
lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
 1235     MI.setDesc(B.getTII().get(TargetOpcode::G_BITCAST));
lib/Target/AMDGPU/R600ClauseMergePass.cpp
  178   RootCFAlu.setDesc(TII->get(LatrCFAlu.getOpcode()));
lib/Target/AMDGPU/R600ControlFlowFinalizer.cpp
  557             MI->setDesc(TII->get(R600::CF_ALU));
lib/Target/AMDGPU/R600InstrInfo.cpp
  782       CfAlu->setDesc(get(R600::CF_ALU_PUSH_BEFORE));
  798     CfAlu->setDesc(get(R600::CF_ALU_PUSH_BEFORE));
  827     CfAlu->setDesc(get(R600::CF_ALU));
  852     CfAlu->setDesc(get(R600::CF_ALU));
lib/Target/AMDGPU/SIFixSGPRCopies.cpp
  649             MI.setDesc(TII->get(SMovOp));
lib/Target/AMDGPU/SIFoldOperands.cpp
  276     MI->setDesc(TII.get(AMDGPU::IMPLICIT_DEF));
  349       MI->setDesc(TII->get(NewOpc));
  355       MI->setDesc(TII->get(Opc));
  360       MI->setDesc(TII->get(AMDGPU::S_SETREG_IMM32_B32));
  646       UseMI->setDesc(TII->get(AMDGPU::V_ACCVGPR_WRITE_B32));
  659     UseMI->setDesc(TII->get(MovOp));
  693         UseMI->setDesc(TII->get(AMDGPU::REG_SEQUENCE));
  765         UseMI->setDesc(TII->get(AMDGPU::V_ACCVGPR_WRITE_B32));
  768         UseMI->setDesc(TII->get(AMDGPU::V_ACCVGPR_READ_B32));
  788         UseMI->setDesc(TII->get(AMDGPU::S_MOV_B32));
  811         UseMI->setDesc(TII->get(AMDGPU::COPY));
  939   MI.setDesc(NewDesc);
  996       MI->setDesc(TII->get(UseCopy ? AMDGPU::COPY : AMDGPU::V_MOV_B32_e32));
lib/Target/AMDGPU/SIISelLowering.cpp
 3039     MI.setDesc(TII->getKillTerminatorFromPseudo(MI.getOpcode()));
 3053   MI.setDesc(TII->getKillTerminatorFromPseudo(MI.getOpcode()));
10432       MI.setDesc(TII->get(NoRetAtomicOp));
10450       MI.setDesc(TII->get(NoRetAtomicOp));
lib/Target/AMDGPU/SIInsertSkips.cpp
  417     MI.setDesc(TII->get(AMDGPU::S_BRANCH));
  419     MI.setDesc(TII->get(IsVCCZ ? AMDGPU::S_CBRANCH_EXECZ
lib/Target/AMDGPU/SIInstrInfo.cpp
 1379     MI.setDesc(get(AMDGPU::S_MOV_B64));
 1385     MI.setDesc(get(AMDGPU::S_MOV_B32));
 1391     MI.setDesc(get(AMDGPU::S_XOR_B64));
 1397     MI.setDesc(get(AMDGPU::S_XOR_B32));
 1403     MI.setDesc(get(AMDGPU::S_OR_B32));
 1409     MI.setDesc(get(AMDGPU::S_ANDN2_B64));
 1415     MI.setDesc(get(AMDGPU::S_ANDN2_B32));
 1533     MI.setDesc(get(ST.isWave32() ? AMDGPU::S_OR_SAVEEXEC_B32
 1540     MI.setDesc(get(ST.isWave32() ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64));
 1708     CommutedMI->setDesc(get(CommutedOpcode));
 2340     UseMI.setDesc(get(NewOpc));
 2415       UseMI.setDesc(get(NewOpc));
 2494       UseMI.setDesc(get(NewOpc));
 4103   MI.setDesc(get(CommutedOpc));
 5007     Inst.setDesc(NewDesc);
 5084         Inst.setDesc(get(AMDGPU::IMPLICIT_DEF));
 5123     Inst.setDesc(get(NewOpc));
lib/Target/AMDGPU/SIOptimizeExecMasking.cpp
  184     MI.setDesc(TII.get(AMDGPU::COPY));
  190     MI.setDesc(TII.get(AMDGPU::S_XOR_B64));
  196     MI.setDesc(TII.get(AMDGPU::S_XOR_B32));
  202     MI.setDesc(TII.get(AMDGPU::S_OR_B32));
  208     MI.setDesc(TII.get(AMDGPU::S_ANDN2_B64));
  214     MI.setDesc(TII.get(AMDGPU::S_ANDN2_B32));
lib/Target/AMDGPU/SIShrinkInstructions.cpp
  206       MI.setDesc(TII->get(SOPKOpc));
  216     MI.setDesc(NewDesc);
  295   MI.setDesc(TII->get(NewOpcode));
  370         MI.setDesc(TII->get(Opc));
  583             MI.setDesc(TII->get(AMDGPU::V_BFREV_B32_e32));
  655             MI.setDesc(TII->get(Opc));
  675             MI.setDesc(TII->get(AMDGPU::S_MOVK_I32));
  677             MI.setDesc(TII->get(AMDGPU::S_BREV_B32));
lib/Target/AMDGPU/SIWholeQuadMode.cpp
  866       MI->setDesc(TII->get(MovOp));
  871       MI->setDesc(TII->get(AMDGPU::COPY));
lib/Target/ARC/ARCOptAddrMode.cpp
  458   Ldst.setDesc(AST->getInstrInfo()->get(NewOpcode));
lib/Target/ARM/ARMBaseInstrInfo.cpp
  502     MI.setDesc(get(getMatchingCondBranchOpcode(Opc)));
 1624   MI.setDesc(get(ARM::VMOVD));
 2536       MI.setDesc(TII.get(ARM::MOVr));
 2544       MI.setDesc(TII.get(ARM::SUBri));
 3324   UseMI.setDesc(get(NewUseOpc));
 4956     MI.setDesc(get(ARM::VORRd));
 4979     MI.setDesc(get(ARM::VGETLNi32));
 5009     MI.setDesc(get(ARM::VSETLNi32));
 5045         MI.setDesc(get(ARM::VDUPLN32d));
 5092       MI.setDesc(get(ARM::VEXTd32));
lib/Target/ARM/ARMConstantIslandPass.cpp
 1632   MI->setDesc(TII->get(ARM::tBfar));
 1807       U.MI->setDesc(TII->get(NewOpc));
 1845         Br.MI->setDesc(TII->get(NewOpc));
 2305     CPEMI->setDesc(TII->get(JTOpc));
lib/Target/ARM/ARMISelLowering.cpp
10427     MI.setDesc(TII->get(ARM::t2STR_PRE));
10430     MI.setDesc(TII->get(ARM::t2STRB_PRE));
10433     MI.setDesc(TII->get(ARM::t2STRH_PRE));
10742     MI.setDesc(*MCID);
lib/Target/ARM/ARMInstructionSelector.cpp
  255   MIB->setDesc(TII.get(ARM::VMOVDRR));
  287   MIB->setDesc(TII.get(ARM::VMOVRRD));
  676     MIB->setDesc(TII.get(Opc));
  714     MIB->setDesc(TII.get(Opc));
  734     MIB->setDesc(TII.get(Opcodes.ADDrr));
  746       MIB->setDesc(TII.get(Opcodes.MOVi32imm));
  749       MIB->setDesc(TII.get(Opcodes.ConstPoolLoad));
  755       MIB->setDesc(TII.get(Opcodes.MOVi32imm));
  757       MIB->setDesc(TII.get(Opcodes.LDRLIT_ga_abs));
  806   MIB->setDesc(TII.get(ARM::MOVsr));
  872       I.setDesc(TII.get(Opcodes.AND));
  900       I.setDesc(TII.get(NewOpc));
  956     I.setDesc(TII.get(COPY));
  982     I.setDesc(TII.get(ARM::MOVi));
  997     MIB->setDesc(TII.get(LoadOpcode));
 1028     I.setDesc(TII.get(COPY));
 1065     I.setDesc(TII.get(Opcodes.ADDrr));
 1071     I.setDesc(TII.get(Opcodes.ADDri));
 1115     I.setDesc(TII.get(NewOpc));
 1159     I.setDesc(TII.get(PHI));
lib/Target/ARM/ARMLoadStoreOptimizer.cpp
 1949       PrevMI.setDesc(TII->get(NewOpc));
lib/Target/ARM/Thumb1FrameLowering.cpp
 1054       (*MIB).setDesc(TII.get(ARM::tPOP_RET));
lib/Target/ARM/Thumb2InstrInfo.cpp
  488       MI.setDesc(TII.get(ARM::tMOVr));
  503       MI.setDesc(TII.get(ARM::t2SUBri));
  505       MI.setDesc(TII.get(ARM::t2ADDri));
  522       MI.setDesc(TII.get(NewOpc));
  641       MI.setDesc(TII.get(NewOpc));
  685           MI.setDesc(TII.get(positiveOffsetOpcode(NewOpc)));
lib/Target/ARM/ThumbRegisterInfo.cpp
  407         MI.setDesc(TII.get(NewOpc));
  528     MI.setDesc(TII.get(UseRR ? ARM::tLDRr : ARM::tLDRi));
  550       MI.setDesc(TII.get(UseRR ? ARM::tSTRr : ARM::tSTRi));
lib/Target/AVR/AVRFrameLowering.cpp
  354     MI.setDesc(TII.get(STOpc));
lib/Target/AVR/AVRRegisterInfo.cpp
  153     MI.setDesc(TII.get(AVR::MOVWRdRr));
lib/Target/Hexagon/HexagonBitSimplify.cpp
 1928   MI->setDesc(HII.get(Hexagon::S2_storerf_io));
 1995       MI->setDesc(HII.get(Hexagon::S4_storeirb_io));
 1998       MI->setDesc(HII.get(Hexagon::S4_storeirh_io));
 2001       MI->setDesc(HII.get(Hexagon::S4_storeiri_io));
lib/Target/Hexagon/HexagonCFGOptimizer.cpp
  102   MI.setDesc(TII->get(NewOpcode));
lib/Target/Hexagon/HexagonConstPropagation.cpp
 2502   MI.setDesc(HII.get(Hexagon::A2_nop));
 3154       BrI.setDesc(JD);
lib/Target/Hexagon/HexagonExpandCondsets.cpp
  694       MI.setDesc(HII->get(TargetOpcode::COPY));
lib/Target/Hexagon/HexagonInstrInfo.cpp
 1359       MI.setDesc(get(Hexagon::J2_jump));
 1363       MI.setDesc(get(Hexagon::J2_jumpr));
 1366       MI.setDesc(get(Hexagon::J2_jumprt));
 1369       MI.setDesc(get(Hexagon::J2_jumprf));
 1372       MI.setDesc(get(Hexagon::J2_jumprtnewpt));
 1375       MI.setDesc(get(Hexagon::J2_jumprfnewpt));
 1378       MI.setDesc(get(Hexagon::J2_jumprtnew));
 1381       MI.setDesc(get(Hexagon::J2_jumprfnew));
 1597   MI.setDesc(get(PredOpc));
 4382   MI.setDesc(get(NewOpcode));
 4410   MI.setDesc(get(getInvertedPredicatedOpcode(MI.getOpcode())));
lib/Target/Hexagon/HexagonPeephole.cpp
  252                 MI.setDesc(QII->get(NewOp));
lib/Target/Hexagon/HexagonRDFOpt.cpp
  272   MI.setDesc(HII.get(NewOpc));
lib/Target/Hexagon/HexagonRegisterInfo.cpp
  206       MI.setDesc(HII.get(Hexagon::A2_addi));
  212       MI.setDesc(HII.get(Hexagon::A2_addi));
lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
  373   MI.setDesc(HII->get(CurOpcode));
  394   MI->setDesc(HII->get(HII->getNonDotCurOp(*MI)));
  459   MI.setDesc(HII->get(NewOpcode));
  465   MI.setDesc(HII->get(NewOpcode));
lib/Target/Lanai/LanaiInstrInfo.cpp
  429     MI->setDesc(get(flagSettingOpcodeVariant(MI->getOpcode())));
lib/Target/Lanai/LanaiRegisterInfo.cpp
  211       MI.setDesc(TII->get(getRRMOpcodeVariant(MI.getOpcode())));
lib/Target/MSP430/MSP430RegisterInfo.cpp
  135     MI.setDesc(TII.get(MSP430::MOV16rr));
lib/Target/Mips/MicroMipsSizeReduction.cpp
  704     MI->setDesc(MipsII->get(Entry.NarrowOpc()));
lib/Target/Mips/MipsConstantIslandPass.cpp
 1109     UserMI->setDesc(TII->get(U.getLongFormOpcode()));
 1511     MI->setDesc(TII->get(Mips::BimmX16));
 1527     MI->setDesc(TII->get(Mips::JalB16));
 1554     MI->setDesc(TII->get(LongFormOpcode));
 1592         MI->setDesc(TII->get(OppositeBranchOpcode));
 1662             I->setDesc(TII->get(Mips::LwRxPcTcp16));
lib/Target/Mips/MipsDelaySlotFiller.cpp
  640           DSI->setDesc(TII->get(getEquivalentCallShort(DSI->getOpcode())));
lib/Target/Mips/MipsInstructionSelector.cpp
  294     I.setDesc(TII.get(COPY));
  381     I.setDesc(TII.get(TargetOpcode::PHI));
lib/Target/PowerPC/PPCInstrInfo.cpp
 1443       MI.setDesc(get(Pred[0].getImm() ? (isPPC64 ? PPC::BDNZLR8 : PPC::BDNZLR)
 1446       MI.setDesc(get(PPC::BCLR));
 1449       MI.setDesc(get(PPC::BCLRn));
 1452       MI.setDesc(get(PPC::BCCLR));
 1462       MI.setDesc(get(Pred[0].getImm() ? (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ)
 1468       MI.setDesc(get(PPC::BC));
 1476       MI.setDesc(get(PPC::BCn));
 1484       MI.setDesc(get(PPC::BCC));
 1501       MI.setDesc(get(isPPC64 ? (setLR ? PPC::BCCTRL8 : PPC::BCCTR8)
 1506       MI.setDesc(get(isPPC64 ? (setLR ? PPC::BCCTRL8n : PPC::BCCTR8n)
 1512     MI.setDesc(get(isPPC64 ? (setLR ? PPC::BCCCTRL8 : PPC::BCCCTR8)
 1977     MI->setDesc(NewDesc);
 2124     MI.setDesc(get(Opcode));
 2142     MI.setDesc(get(Subtarget.isPPC64() ? PPC::LD : PPC::LWZ));
 2181       MI.setDesc(get(PPC::DFLOADf64));
 2185       MI.setDesc(get(PPC::LD));
 2192       MI.setDesc(get(PPC::DFSTOREf64));
 2196       MI.setDesc(get(PPC::STD));
 2203       MI.setDesc(get(PPC::LXSDX));
 2205       MI.setDesc(get(PPC::LDX));
 2212       MI.setDesc(get(PPC::STXSDX));
 2215       MI.setDesc(get(PPC::STDX));
 2227     MI.setDesc(get(PPC::ISYNC));
 2309     MI.setDesc(get(LII.Is64Bit ? PPC::ANDIo8 : PPC::ANDIo));
 2316     MI.setDesc(get(LII.Is64Bit ? PPC::LI8 : PPC::LI));
 2627   MI.setDesc(get(XFormOpcode));
 2841         CompareUseMI.setDesc(get(UseOpc == PPC::ISEL8 ? PPC::LI8 : PPC::LI));
 2852       CompareUseMI.setDesc(get(PPC::COPY));
 3688   MI.setDesc(get(III.ImmOpcode));
 3769   MI.setDesc(get(III.ImmOpcode));
 3790         MI.setDesc(get(PPC::COPY));
lib/Target/PowerPC/PPCMIPeephole.cpp
  600           SrcMI->setDesc(TII->get(Opc));
  644           SrcMI->setDesc(TII->get(Opc));
  784           LiMI->setDesc(TII->get(LiMI->getOpcode() == PPC::LI ? PPC::ADDI
 1256       CMPI1->setDesc(TII->get(NewOpCode));
 1373   MI.setDesc(TII->get(PPC::RLDIC));
lib/Target/PowerPC/PPCReduceCRLogicals.cpp
  237     FirstTerminator->setDesc(TII->get(InvertedOpcode));
lib/Target/PowerPC/PPCRegisterInfo.cpp
 1124     MI.setDesc(TII.get(NewOpcode));
lib/Target/PowerPC/PPCVSXFMAMutate.cpp
  259         MI.setDesc(TII->get(AltOpc));
lib/Target/Sparc/DelaySlotFiller.cpp
  188       slot->setDesc(Subtarget->getInstrInfo()->get(SP::RET));
  391   AddMI->setDesc(TII->get((AddMI->getOpcode() == SP::ADDrr)
  430   OrMI->setDesc(TII->get((OrMI->getOpcode() == SP::ORrr)
  467   RestoreMI->setDesc(TII->get(SP::RESTOREri));
lib/Target/Sparc/SparcInstrInfo.cpp
  501     MI.setDesc(get(Subtarget.is64Bit() ? SP::LDXri : SP::LDri));
lib/Target/Sparc/SparcRegisterInfo.cpp
  192       MI.setDesc(TII.get(SP::STDFri));
  205       MI.setDesc(TII.get(SP::LDDFri));
lib/Target/SystemZ/SystemZElimCompare.cpp
  234   Branch->setDesc(TII->get(BRCT));
  277   Branch->setDesc(TII->get(LATOpcode));
  562   Branch->setDesc(TII->get(FusedOpcode));
lib/Target/SystemZ/SystemZFrameLowering.cpp
  507     MBBI->setDesc(ZII->get(NewOpcode));
lib/Target/SystemZ/SystemZISelLowering.cpp
 7469   MI.setDesc(TII->get(Opcode));
lib/Target/SystemZ/SystemZInstrInfo.cpp
  111   EarlierMI->setDesc(get(HighOpcode));
  112   MI->setDesc(get(LowOpcode));
  127   MI->setDesc(get(NewOpcode));
  142   MI.setDesc(get(IsHigh ? HighOpcode : LowOpcode));
  159     MI.setDesc(get(LowOpcodeK));
  167     MI.setDesc(get(DestIsHigh ? HighOpcode : LowOpcode));
  181   MI.setDesc(get(Opcode));
  191   MI.setDesc(get(Opcode));
  236   MI->setDesc(get(SystemZ::LG));
  662   UseMI.setDesc(get(NewUseOpc));
  726     MI.setDesc(get(SystemZ::CondTrap));
  733     MI.setDesc(get(SystemZ::CondReturn));
  744     MI.setDesc(get(SystemZ::CallBRCL));
  756     MI.setDesc(get(SystemZ::CallBCR));
 1375       MI.setDesc(get(DestIsHigh ? SystemZ::RISBHH : SystemZ::RISBLL));
 1377       MI.setDesc(get(DestIsHigh ? SystemZ::RISBHL : SystemZ::RISBLH));
lib/Target/SystemZ/SystemZLongBranch.cpp
  394     Branch->setDesc(TII->get(SystemZ::JG));
  397     Branch->setDesc(TII->get(SystemZ::BRCL));
lib/Target/SystemZ/SystemZPostRewrite.cpp
   95     MBBI->setDesc(TII->get(LowOpcode));
   97     MBBI->setDesc(TII->get(HighOpcode));
  146     MBBI->setDesc(TII->get(LowOpcode));
  148     MBBI->setDesc(TII->get(HighOpcode));
  223     MI.setDesc(TII->get(TargetMemOpcode));
lib/Target/SystemZ/SystemZRegisterInfo.cpp
  332   MI->setDesc(TII->get(OpcodeForOffset));
lib/Target/SystemZ/SystemZShortenInst.cpp
   95     MI.setDesc(TII->get(LLIxL));
  100     MI.setDesc(TII->get(LLIxH));
  111     MI.setDesc(TII->get(Opcode));
  122     MI.setDesc(TII->get(Opcode));
  135     MI.setDesc(TII->get(Opcode));
  168     MI.setDesc(TII->get(Opcode));
  183     MI.setDesc(TII->get(Opcode));
  189     MI.setDesc(TII->get(Opcode));
  344       MI.setDesc(TII->get(TwoOperandOpcode));
lib/Target/WebAssembly/WebAssemblyCallIndirectFixup.cpp
  117         MI.setDesc(Desc);
lib/Target/WebAssembly/WebAssemblyLowerBrUnless.cpp
   81           Def->setDesc(TII.get(NE_I32));
   85           Def->setDesc(TII.get(EQ_I32));
   89           Def->setDesc(TII.get(LE_S_I32));
   93           Def->setDesc(TII.get(LT_S_I32));
   97           Def->setDesc(TII.get(GE_S_I32));
  101           Def->setDesc(TII.get(GT_S_I32));
  105           Def->setDesc(TII.get(LE_U_I32));
  109           Def->setDesc(TII.get(LT_U_I32));
  113           Def->setDesc(TII.get(GE_U_I32));
  117           Def->setDesc(TII.get(GT_U_I32));
  121           Def->setDesc(TII.get(NE_I64));
  125           Def->setDesc(TII.get(EQ_I64));
  129           Def->setDesc(TII.get(LE_S_I64));
  133           Def->setDesc(TII.get(LT_S_I64));
  137           Def->setDesc(TII.get(GE_S_I64));
  141           Def->setDesc(TII.get(GT_S_I64));
  145           Def->setDesc(TII.get(LE_U_I64));
  149           Def->setDesc(TII.get(LT_U_I64));
  153           Def->setDesc(TII.get(GE_U_I64));
  157           Def->setDesc(TII.get(GT_U_I64));
  161           Def->setDesc(TII.get(NE_F32));
  165           Def->setDesc(TII.get(EQ_F32));
  169           Def->setDesc(TII.get(NE_F64));
  173           Def->setDesc(TII.get(EQ_F64));
lib/Target/WebAssembly/WebAssemblyPeephole.cpp
  128   MI.setDesc(TII.get(WebAssembly::FALLTHROUGH_RETURN));
lib/Target/WebAssembly/WebAssemblyRegStackify.cpp
  107     MI->setDesc(TII->get(WebAssembly::CONST_I32));
  110     MI->setDesc(TII->get(WebAssembly::CONST_I64));
  113     MI->setDesc(TII->get(WebAssembly::CONST_F32));
  118     MI->setDesc(TII->get(WebAssembly::CONST_F64));
  124     MI->setDesc(TII->get(WebAssembly::SPLAT_v4i32));
lib/Target/X86/X86EvexToVex.cpp
  267   MI.setDesc(TII->get(NewOpc));
lib/Target/X86/X86FloatingPoint.cpp
  843     I->setDesc(TII->get(Opcode));
 1103   MI.setDesc(TII->get(getConcreteOpcode(MI.getOpcode())));
 1149   MI.setDesc(TII->get(getConcreteOpcode(MI.getOpcode())));
 1201   MI.setDesc(TII->get(getConcreteOpcode(MI.getOpcode())));
 1397   MI.setDesc(TII->get(getConcreteOpcode(MI.getOpcode())));
 1423   MI.setDesc(TII->get(getConcreteOpcode(MI.getOpcode())));
lib/Target/X86/X86ISelLowering.cpp
30404   MI.setDesc(TII->get(Opc));
lib/Target/X86/X86InstrInfo.cpp
 1556     WorkingMI.setDesc(get(Opc));
 1568     WorkingMI.setDesc(get(Opc));
 1588         WorkingMI.setDesc(get(Opc));
 1665       WorkingMI.setDesc(get(Opc));
 1676     WorkingMI.setDesc(get(X86::SHUFPDrri));
 1685     WorkingMI.setDesc(get(X86::MOVSDrr));
 1801     WorkingMI.setDesc(get(Opc));
 1852       WorkingMI.setDesc(get(Opc));
 1863       WorkingMI.setDesc(get(Opc));
 3596     CmpInstr.setDesc(get(NewOpcode));
 3881   MIB->setDesc(Desc);
 3901   MIB->setDesc(Desc);
 3918   MIB->setDesc(TII.get(MinusOne ? X86::DEC32r : X86::INC32r));
 3943       MIB->setDesc(TII.get(MIB->getOpcode() ==
 3952     MIB->setDesc(TII.get(X86::POP64r));
 3959     MIB->setDesc(TII.get(X86::POP32r));
 4000   MIB->setDesc(TII.get(X86::MOV64rm));
 4011   MIB->setDesc(TII.get(XorOp));
 4028     MIB->setDesc(LoadDesc);
 4031     MIB->setDesc(BroadcastDesc);
 4051     MIB->setDesc(StoreDesc);
 4054     MIB->setDesc(ExtractDesc);
 4065   MIB->setDesc(Desc);
 4159     MIB->setDesc(get(X86::VCMPPSYrri));
 4165     MIB->setDesc(get(X86::VPTERNLOGDZrri));
 4180     MIB->setDesc(get(Opc));
 4214     MI.setDesc(get(X86::MOV32ri));
 4243   case X86::ADD8rr_DB:    MIB->setDesc(get(X86::OR8rr));    break;
 4244   case X86::ADD16rr_DB:   MIB->setDesc(get(X86::OR16rr));   break;
 4245   case X86::ADD32rr_DB:   MIB->setDesc(get(X86::OR32rr));   break;
 4246   case X86::ADD64rr_DB:   MIB->setDesc(get(X86::OR64rr));   break;
 4247   case X86::ADD8ri_DB:    MIB->setDesc(get(X86::OR8ri));    break;
 4248   case X86::ADD16ri_DB:   MIB->setDesc(get(X86::OR16ri));   break;
 4249   case X86::ADD32ri_DB:   MIB->setDesc(get(X86::OR32ri));   break;
 4250   case X86::ADD64ri32_DB: MIB->setDesc(get(X86::OR64ri32)); break;
 4251   case X86::ADD16ri8_DB:  MIB->setDesc(get(X86::OR16ri8));  break;
 4252   case X86::ADD32ri8_DB:  MIB->setDesc(get(X86::OR32ri8));  break;
 4253   case X86::ADD64ri8_DB:  MIB->setDesc(get(X86::OR64ri8));  break;
 5046     MI.setDesc(get(NewOpc));
 5266     MI.setDesc(get(NewOpc));
 5570       DataMI->setDesc(get(NewOpc));
 6724       MI.setDesc(get(table[Domain - 1]));
 6786     MI.setDesc(get(table[Domain - 1]));
 6811       MI.setDesc(get(X86::SHUFPSrri));
 6907   MI.setDesc(get(table[Domain - 1]));
lib/Target/X86/X86InstructionSelector.cpp
  303   I.setDesc(TII.get(X86::COPY));
  535   I.setDesc(TII.get(NewOpc));
  571   I.setDesc(TII.get(NewOpc));
  623   I.setDesc(TII.get(NewOpc));
  675   I.setDesc(TII.get(NewOpc));
  700   I.setDesc(TII.get(X86::COPY));
  766   I.setDesc(TII.get(X86::COPY));
  921     I.setDesc(TII.get(X86::COPY));
 1172       I.setDesc(TII.get(X86::VEXTRACTF32x4Z256rr));
 1174       I.setDesc(TII.get(X86::VEXTRACTF128rr));
 1179       I.setDesc(TII.get(X86::VEXTRACTF32x4Zrr));
 1181       I.setDesc(TII.get(X86::VEXTRACTF64x4Zrr));
 1305       I.setDesc(TII.get(X86::VINSERTF32x4Z256rr));
 1307       I.setDesc(TII.get(X86::VINSERTF128rr));
 1312       I.setDesc(TII.get(X86::VINSERTF32x4Zrr));
 1314       I.setDesc(TII.get(X86::VINSERTF64x4Zrr));
 1509     I.setDesc(TII.get(X86::IMPLICIT_DEF));
 1511     I.setDesc(TII.get(X86::PHI));