|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
lib/CodeGen/AsmPrinter/DbgEntityHistoryCalculator.cpp 285 else if (MO.getReg() != FrameReg ||
lib/CodeGen/CallingConvLower.cpp 285 if (Loc1.getLocReg() != Loc2.getLocReg())
lib/CodeGen/ExpandPostRAPseudos.cpp 110 if (DstReg != InsReg) {
lib/CodeGen/GlobalISel/CallLowering.cpp 439 if (Loc1.getLocReg() != Loc2.getLocReg())
lib/CodeGen/GlobalISel/CombinerHelper.cpp 473 if (UseDstReg != ChosenDstReg) {
lib/CodeGen/LiveDebugValues.cpp 1301 return Op.isReg() && Op.getReg() != SP && Op.getReg() != FP;
lib/CodeGen/MachineCopyPropagation.cpp 418 if (MOUse.getReg() != CopyDstReg) {
lib/CodeGen/MachineInstr.cpp 893 if (!MO.isReg() || MO.getReg() != Reg)
971 if (!MO.isReg() || MO.getReg() != Reg)
1146 if (!MO.isReg() || MO.getReg() != FromReg)
1152 if (!MO.isReg() || MO.getReg() != FromReg)
1363 if (getOperand(i).getReg() != Reg)
1918 if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg)
1926 if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg || MO.getSubReg() == 0)
lib/CodeGen/MachineSink.cpp 828 if (PostRA && DbgMO.getReg() != DstMO->getReg())
lib/CodeGen/MachineVerifier.cpp 1634 MO->getReg() != MOTied.getReg())
1679 Reg != MI->getOperand(DefIdx).getReg())
lib/CodeGen/RegAllocGreedy.cpp 2946 if (CurrPhys != PhysReg && (!MRI->getRegClass(Reg)->contains(PhysReg) ||
2958 if (CurrPhys != PhysReg) {
lib/CodeGen/RegisterCoalescer.cpp 1428 } else if (NewMI.getOperand(0).getReg() != CopyDstReg) {
lib/CodeGen/SwiftErrorValueTracking.cpp 208 -> bool { return V.second != VRegs[0].second; }) !=
lib/CodeGen/TargetInstrInfo.cpp 948 if (MO.isDef() && Reg != DefReg)
lib/CodeGen/TwoAddressInstructionPass.cpp 1548 MI->getOperand(i).getReg() != RegA);
1744 if (SrcReg != DstReg &&
lib/CodeGen/UnreachableBlockElim.cpp 182 if (InputReg != OutputReg) {
lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp 632 if (DestReg != AccumReg)
649 if (DestReg != AccumReg) {
lib/Target/AArch64/AArch64CallLowering.cpp 352 if (CurVReg != CurArgInfo.Regs[0]) {
650 if (CopyRHS != Reg) {
lib/Target/AArch64/AArch64CollectLOH.cpp 216 MI.getOperand(0).getReg() != MI.getOperand(1).getReg();
lib/Target/AArch64/AArch64InstrInfo.cpp 2338 if (BaseOp1.isReg() && BaseOp1.getReg() != BaseOp2.getReg())
lib/Target/AArch64/AArch64InstructionSelector.cpp 4000 if (DstReg != I.getOperand(0).getReg()) {
lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp 1287 (IsPromotableZeroStore && Reg != getLdStRegOp(MI).getReg())) {
lib/Target/AMDGPU/R600Packetizer.cpp 191 if (PredI != PredJ)
201 if (MII->getOperand(0).getReg() != MIJ->getOperand(0).getReg())
lib/Target/AMDGPU/SIFoldOperands.cpp 1254 Src0->getReg() != Src1->getReg() ||
lib/Target/AMDGPU/SIISelLowering.cpp 3685 I->getOperand(0).getReg() != InputReg)
lib/Target/AMDGPU/SIInstrInfo.cpp 3383 Dst.getReg() != TiedMO.getReg()) {
3501 if (MO.getReg() != SGPRUsed)
lib/Target/AMDGPU/SILoadStoreOptimizer.cpp 151 if (AddrReg[i]->getReg() != AddrRegNext.getReg() ||
lib/Target/AMDGPU/SIShrinkInstructions.cpp 511 I->getOperand(0).getReg() != X ||
lib/Target/ARM/ARMBaseInstrInfo.cpp 1008 MI.getOperand(1).getReg() != MI.getOperand(2).getReg()))
1803 if (Addr0 != Addr1) {
lib/Target/ARM/ARMConstantIslandPass.cpp 2243 if (Load->getOperand(1).getReg() != BaseReg ||
2244 Load->getOperand(2).getReg() != ShiftedIdxReg ||
2262 Add->getOperand(2).getReg() != BaseReg ||
2263 Add->getOperand(3).getReg() != Load->getOperand(0).getReg() ||
2266 if (Add->getOperand(0).getReg() != MI->getOperand(0).getReg())
2274 if (Load->getOperand(0).getReg() != MI->getOperand(0).getReg())
lib/Target/ARM/Thumb2SizeReduction.cpp 755 if (Reg0 != Reg2) {
758 if (Reg1 != Reg0)
765 } else if (Reg0 != Reg1) {
770 MI->getOperand(CommOpIdx2).getReg() != Reg0)
lib/Target/BPF/BPFMIPeephole.cpp 267 if (dst != src)
lib/Target/Hexagon/HexagonInstrInfo.cpp 1048 if (MD.getReg() != MS.getReg() && !MS.isUndef()) {
1240 if (Rd != Rs)
1244 if (Rd != Rt)
1263 if (Op0.getReg() != Op2.getReg()) {
1264 unsigned S = Op0.getReg() != Op3.getReg() ? PState & ~RegState::Kill
1274 if (Op0.getReg() != Op3.getReg()) {
1297 if (Op0.getReg() != Op2.getReg()) {
1298 unsigned S = Op0.getReg() != Op3.getReg() ? PState & ~RegState::Kill
1311 if (Op0.getReg() != Op3.getReg()) {
1895 if (BaseRegA != BaseRegB || BaseSubA != BaseSubB)
lib/Target/Hexagon/HexagonNewValueJump.cpp 661 if (Op.getReg() != UseR)
lib/Target/Hexagon/HexagonOptAddrMode.cpp 365 if (!BaseOp.isReg() || BaseOp.getReg() != AddDefR)
lib/Target/Hexagon/HexagonSubtarget.cpp 294 BaseOp0->getReg() != BaseOp1->getReg())
lib/Target/Hexagon/HexagonVLIWPacketizer.cpp 520 if (Reg != MJ.getOperand(BPJ).getReg())
lib/Target/Mips/MicroMipsSizeReduction.cpp 481 if (Reg1 != Reg2)
lib/Target/Mips/MipsExpandPseudo.cpp 593 assert((OldVal != Ptr) && "Clobbered the wrong ptr reg!");
594 assert((OldVal != Incr) && "Clobbered the wrong reg!");
lib/Target/PowerPC/PPCFrameLowering.cpp 385 if (DstReg != SrcReg)
394 if (DstReg != SrcReg)
403 if (DstReg != SrcReg)
lib/Target/PowerPC/PPCISelLowering.cpp11326 if (ptrA != ZeroReg) {
lib/Target/PowerPC/PPCInstrInfo.cpp 1534 if (Pred1[1].getReg() != Pred2[1].getReg())
lib/Target/PowerPC/PPCQPXLoadSplat.cpp 100 if (SplatReg != SrcReg) {
135 (SrcReg != SplatReg &&
lib/Target/PowerPC/PPCVSXFMAMutate.cpp 192 && Reg2 != OldFMAReg) {
196 && Reg3 != OldFMAReg) {
lib/Target/RISCV/RISCVExpandPseudoInsts.cpp 277 assert(OldValReg != ScratchReg && "OldValReg and ScratchReg must be unique");
278 assert(OldValReg != MaskReg && "OldValReg and MaskReg must be unique");
279 assert(ScratchReg != MaskReg && "ScratchReg and MaskReg must be unique");
lib/Target/RISCV/RISCVISelLowering.cpp 1267 if (SequenceMBBI->getOperand(1).getReg() != LHS ||
1268 SequenceMBBI->getOperand(2).getReg() != RHS ||
lib/Target/RISCV/RISCVMergeBaseOffset.cpp 236 if (DestReg != BaseAddrReg)
lib/Target/SystemZ/SystemZInstrInfo.cpp 161 if (DestReg != SrcReg) {
lib/Target/SystemZ/SystemZPostRewrite.cpp 120 if (DestReg != Src1Reg && DestReg != Src2Reg) {
120 if (DestReg != Src1Reg && DestReg != Src2Reg) {
139 if (DestReg != Src1Reg && DestReg == Src2Reg) {
227 if (DstReg != SrcMO.getReg()) {
lib/Target/SystemZ/SystemZShortenInst.cpp 338 if ((MI.getOperand(0).getReg() != MI.getOperand(1).getReg()) &&
340 MI.getOperand(0).getReg() != MI.getOperand(2).getReg() ||
lib/Target/X86/X86CallFrameOptimization.cpp 428 (I->getOperand(X86::AddrBaseReg).getReg() != StackPtr) ||
lib/Target/X86/X86FixupBWInsts.cpp 329 if (Op.getReg() != (Op.isDef() ? NewDestReg : NewSrcReg))
lib/Target/X86/X86FixupLEAs.cpp 390 if (DestReg != BaseReg)
498 if ((SrcR1 == 0 || SrcR1 != DstR) && (SrcR2 == 0 || SrcR2 != DstR))
498 if ((SrcR1 == 0 || SrcR1 != DstR) && (SrcR2 == 0 || SrcR2 != DstR))
578 if (DestReg != BaseReg)
635 assert(DestReg != BaseReg && "DestReg == BaseReg should be handled already!");
644 bool BIK = Base.isKill() && BaseReg != IndexReg;
lib/Target/X86/X86InstrInfo.cpp 1959 if (Op2Reg != MI.getOperand(CommutableOpIdx1).getReg())
lib/Target/X86/X86MCInstLower.cpp 1354 if (SrcRegs[I] != DestRegs[I]) {
1368 if (SrcRegs[I] != DestRegs[I])
1450 if (SrcRegs[I] != DestRegs[I]) {
lib/Target/X86/X86SpeculativeLoadHardening.cpp 1994 HardenOpRegs.front()->getReg() != IndexMO.getReg()))
2000 HardenOpRegs[0]->getReg() != HardenOpRegs[1]->getReg()) &&