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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
include/llvm/CodeGen/LiveVariables.h 217 if (MO.isReg() && MO.isKill() && MO.getReg() == reg) {
include/llvm/CodeGen/MachineInstrBuilder.h 499 getKillRegState(RegOp.isKill()) | getDeadRegState(RegOp.isDead()) |
lib/CodeGen/BranchFolding.cpp 2054 if (MO.isKill() && Uses.count(Reg))
2069 if (!MO.isReg() || !MO.isUse() || !MO.isKill())
lib/CodeGen/ExpandPostRAPseudos.cpp 120 MI->getOperand(2).isKill());
166 DstMO.getReg(), SrcMO.getReg(), SrcMO.isKill());
lib/CodeGen/LiveDebugValues.cpp 869 return MO.isKill();
1002 if (!TII->isCopyInstr(MI, SrcRegOp, DestRegOp) || !SrcRegOp->isKill() ||
lib/CodeGen/LivePhysRegs.cpp 97 if (!O->isKill())
lib/CodeGen/LiveVariables.cpp 692 if (MO.isReg() && MO.isKill()) {
788 else if (I->isKill())
lib/CodeGen/MIRCanonicalizerPass.cpp 360 if (!MO.isDef() && MO.isKill()) {
lib/CodeGen/MachineBasicBlock.cpp 909 !OI->isUse() || !OI->isKill() || OI->isUndef())
lib/CodeGen/MachineInstr.cpp 643 if (Check == CheckKillDead && MO.isKill() != OMO.isKill())
643 if (Check == CheckKillDead && MO.isKill() != OMO.isKill())
953 if (!isKill || MO.isKill())
1809 if (MO.isKill())
1818 } else if (hasAliases && MO.isKill() && Register::isPhysicalRegister(Reg)) {
1855 if (!MO.isReg() || !MO.isUse() || !MO.isKill())
lib/CodeGen/MachineInstrBundle.cpp 163 if (MO.isKill())
172 if (MO.isKill())
344 if (MO.isKill())
lib/CodeGen/MachineLICM.cpp 801 return MO.isKill() || MRI->hasOneNonDBGUse(MO.getReg());
lib/CodeGen/MachineOperand.cpp 761 if (isKill())
lib/CodeGen/MachineTraceMetrics.cpp 720 } else if (MO.isKill())
lib/CodeGen/MachineVerifier.cpp 1885 if (MO->isKill() && !LRQ.isKill()) {
1945 if (MO->isKill())
1949 if (LiveVars && Register::isVirtualRegister(Reg) && MO->isKill()) {
lib/CodeGen/RegAllocFast.cpp 827 } else if (MO.isKill()) {
834 } else if (MO.isKill()) {
861 return MO.isKill() || Dead;
871 if (MO.isKill()) {
lib/CodeGen/RegisterScavenging.cpp 144 if (MO.isKill())
335 else if (MO.isKill())
lib/CodeGen/TargetInstrInfo.cpp 179 bool Reg1IsKill = MI.getOperand(Idx1).isKill();
180 bool Reg2IsKill = MI.getOperand(Idx2).isKill();
613 storeRegToStackSlot(*MBB, Pos, MO.getReg(), MO.isKill(), FI, RC, TRI);
832 bool KillA = OpA.isKill();
833 bool KillX = OpX.isKill();
834 bool KillY = OpY.isKill();
lib/CodeGen/TwoAddressInstructionPass.cpp 266 if (!UseMO.isKill())
308 if (MO.isKill() || (LIS && isPlainlyKilled(&OtherMI, MOReg, LIS))) {
920 if (MOReg != Reg && (MO.isKill() ||
973 MO.isKill() || (LIS && isPlainlyKilled(&OtherMI, MOReg, LIS));
1101 bool isKill = MO.isKill() || (LIS && isPlainlyKilled(KillMI, MOReg, LIS));
1144 !(MO.isKill() || (LIS && isPlainlyKilled(&OtherMI, MOReg, LIS))))
1394 if (NewMIs[1]->getOperand(NewSrcIdx).isKill()) {
1402 if (MO.isKill()) {
1594 if (MO.isKill()) {
1619 if (MO.isKill()) {
1826 bool isKill = UseMO.isKill();
lib/CodeGen/VirtRegMap.cpp 530 if ((MO.readsReg() && (MO.isDef() || MO.isKill())) ||
lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp 557 if (U.isKill())
644 if (MI->getOperand(3).isKill()) {
690 if (MO.isKill() && ActiveChains.find(MO.getReg()) != ActiveChains.end()) {
lib/Target/AArch64/AArch64AdvSIMDScalarPass.cpp 310 KillSrc0 = MOSrc0->isKill();
329 KillSrc1 = MOSrc1->isKill();
lib/Target/AArch64/AArch64ISelLowering.cpp 1346 bool NZCVKilled = MI.getOperand(4).isKill();
lib/Target/AArch64/AArch64InstrInfo.cpp 3255 storeRegToStackSlot(MBB, InsertPt, SrcReg, SrcMO.isKill(), FrameIndex,
3304 storeRegToStackSlot(MBB, InsertPt, WidenedSrcReg, SrcMO.isKill(),
3995 bool Src0IsKill = MUL->getOperand(1).isKill();
3997 bool Src1IsKill = MUL->getOperand(2).isKill();
4007 Src2IsKill = Root.getOperand(IdxOtherOpd).isKill();
4072 bool Src0IsKill = MUL->getOperand(1).isKill();
4074 bool Src1IsKill = MUL->getOperand(2).isKill();
lib/Target/AArch64/AArch64SIMDInstrOpt.cpp 431 unsigned Src0IsKill = getKillRegState(MI.getOperand(1).isKill());
433 unsigned Src1IsKill = getKillRegState(MI.getOperand(2).isKill());
439 unsigned Src2IsKill = getKillRegState(MI.getOperand(3).isKill());
639 StRegKill[i] = getKillRegState(DefiningMI->getOperand(2*i+1).isKill());
lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp 230 MO.isKill(), MO.isDead(), MO.isUndef(),
lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp 1049 if (UseIsOutsideDefMBB && UseOperand->isKill()) {
lib/Target/AMDGPU/SIFormMemoryClauses.cpp 143 if (MO.isKill())
lib/Target/AMDGPU/SIInsertSkips.cpp 401 if (!ReadsSreg && Op2.isKill()) {
lib/Target/AMDGPU/SIInstrInfo.cpp 1647 bool IsKill = RegOp.isKill();
2042 CondReg.setIsKill(OrigCond.isKill());
2095 CondReg.setIsKill(Cond[1].isKill());
2403 Src0->setIsKill(Src1->isKill());
3052 Use.setIsKill(Orig.isKill());
4107 bool Src0Kill = Src0.isKill();
4112 Src0.ChangeToRegister(Src1.getReg(), false, false, Src1.isKill());
lib/Target/AMDGPU/SIOptimizeExecMasking.cpp 305 if (CopyToExecInst->getOperand(1).isKill() &&
lib/Target/AMDGPU/SIPeepholeSDWA.cpp 281 To.setIsKill(From.isKill());
1198 Copy.addReg(Op.getReg(), Op.isKill() ? RegState::Kill : 0,
lib/Target/AMDGPU/SIRegisterInfo.cpp 763 bool IsKill = MI->getOperand(0).isKill();
1048 VData->getReg(), VData->isKill(),
1078 VData->getReg(), VData->isKill(),
lib/Target/AMDGPU/SIShrinkInstructions.cpp 263 if (!Op.isKill())
lib/Target/ARC/ARCRegisterInfo.cpp 107 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill()))
lib/Target/ARM/ARMAsmPrinter.cpp 1668 assert(MI->getOperand(1).isKill() && "We need the index register as scratch!");
lib/Target/ARM/ARMBaseInstrInfo.cpp 288 if (MO.isUse() && MO.isKill()) {
1638 if (MI.getOperand(1).isKill()) {
3316 bool isKill = UseMI.getOperand(OpIdx).isKill();
lib/Target/ARM/ARMConstantIslandPass.cpp 2067 BaseRegKill = BaseRegKill || MO.isKill();
2200 if (!MI->getOperand(0).isKill()) // FIXME: needed now?
2211 IdxRegKill = MI->getOperand(1).isKill();
2229 !Shift->getOperand(2).isKill())
2245 !Load->getOperand(2).isKill())
2264 !Add->getOperand(3).isKill())
lib/Target/ARM/ARMExpandPseudoInsts.cpp 625 bool SrcIsKill = MI.getOperand(OpIdx).isKill();
715 getKillRegState(MO.isKill()));
762 bool SrcIsKill = MI.getOperand(OpIdx).isKill();
1624 bool SrcIsKill = MI.getOperand(OpIdx).isKill();
lib/Target/ARM/ARMISelLowering.cpp10624 bool ABSSrcKIll = MI.getOperand(1).isKill();
lib/Target/ARM/ARMLoadStoreOptimizer.cpp 863 bool IsKill = MO.isKill();
957 if (!MO.isReg() || !MO.isKill())
1265 bool BaseKill = BaseOP.isKill();
1391 bool BaseKill = getLoadStoreBaseOp(*MI).isKill();
1446 getKillRegState(MO.isKill())))
1484 .addReg(MO.getReg(), getKillRegState(MO.isKill()))
1493 .addReg(MO.getReg(), getKillRegState(MO.isKill()))
1678 MI->getOperand(0).isDead() : MI->getOperand(0).isKill();
1681 MI->getOperand(1).isDead() : MI->getOperand(1).isKill();
1683 bool BaseKill = BaseOp.isKill();
1982 if (Use.isKill()) {
lib/Target/ARM/MLxExpansionPass.cpp 277 bool Src1Kill = MI->getOperand(2).isKill();
278 bool Src2Kill = MI->getOperand(3).isKill();
lib/Target/ARM/Thumb2ITBlockPass.cpp 115 if (!MO.isReg() || MO.isDef() || !MO.isKill())
lib/Target/ARM/Thumb2SizeReduction.cpp 522 if (!MI->getOperand(0).isKill())
562 OffsetKill = MI->getOperand(2).isKill();
727 if (MI->getOperand(0).isKill())
995 if (MO.isKill()) {
1094 if (MO && !MO->isKill())
lib/Target/AVR/AVRExpandPseudoInsts.cpp 146 bool DstIsKill = MI.getOperand(1).isKill();
147 bool SrcIsKill = MI.getOperand(2).isKill();
179 bool DstIsKill = MI.getOperand(1).isKill();
180 bool SrcIsKill = MI.getOperand(2).isKill();
225 bool SrcIsKill = MI.getOperand(1).isKill();
277 bool SrcIsKill = MI.getOperand(1).isKill();
329 bool SrcIsKill = MI.getOperand(1).isKill();
392 bool DstIsKill = MI.getOperand(1).isKill();
422 bool DstIsKill = MI.getOperand(0).isKill();
423 bool SrcIsKill = MI.getOperand(1).isKill();
455 bool DstIsKill = MI.getOperand(0).isKill();
456 bool SrcIsKill = MI.getOperand(1).isKill();
584 bool SrcIsKill = MI.getOperand(1).isKill();
633 bool SrcIsDead = MI.getOperand(1).isKill();
664 bool SrcIsDead = MI.getOperand(1).isKill();
696 bool SrcIsKill = MI.getOperand(1).isKill();
750 bool SrcIsKill = MI.getOperand(1).isKill();
971 bool SrcIsKill = MI.getOperand(1).isKill();
1018 bool SrcIsKill = MI.getOperand(1).isKill();
1048 bool SrcIsKill = MI.getOperand(2).isKill();
1082 bool SrcIsKill = MI.getOperand(2).isKill();
1115 bool DstIsKill = MI.getOperand(0).isKill();
1116 bool SrcIsKill = MI.getOperand(2).isKill();
1178 bool SrcIsKill = MI.getOperand(1).isKill();
1208 bool SrcIsKill = MI.getOperand(0).isKill();
1251 bool DstIsKill = MI.getOperand(1).isKill();
1284 bool DstIsKill = MI.getOperand(1).isKill();
1327 bool DstIsKill = MI.getOperand(1).isKill();
1371 bool SrcIsKill = MI.getOperand(1).isKill();
1425 bool SrcIsKill = MI.getOperand(1).isKill();
1479 bool SrcIsKill = MI.getOperand(1).isKill();
lib/Target/AVR/AVRFrameLowering.cpp 328 bool SrcIsKill = MI.getOperand(2).isKill();
lib/Target/AVR/AVRRelaxMemOperations.cpp 112 .addReg(Src.getReg(), getKillRegState(Src.isKill()));
116 .addReg(Ptr.getReg(), getKillRegState(Ptr.isKill()));
lib/Target/Hexagon/HexagonBlockRanges.cpp 326 bool IsKill = Op.isKill();
lib/Target/Hexagon/HexagonCopyToCombine.cpp 240 if (!Op.isReg() || Op.getReg() != RegNotKilled || !Op.isKill())
762 unsigned LoRegKillFlag = getKillRegState(LoOperand.isKill());
809 unsigned HiRegKillFlag = getKillRegState(HiOperand.isKill());
858 unsigned LoRegKillFlag = getKillRegState(LoOperand.isKill());
859 unsigned HiRegKillFlag = getKillRegState(HiOperand.isKill());
lib/Target/Hexagon/HexagonExpandCondsets.cpp 949 if (!MS.isKill())
lib/Target/Hexagon/HexagonFrameLowering.cpp 1599 bool IsKill = MI->getOperand(2).isKill();
1662 bool IsKill = MI->getOperand(2).isKill();
1751 bool IsKill = MI->getOperand(2).isKill();
1838 bool IsKill = MI->getOperand(2).isKill();
lib/Target/Hexagon/HexagonInstrInfo.cpp 1049 copyPhysReg(MBB, MI, DL, MD.getReg(), MS.getReg(), MS.isKill());
1064 unsigned Kill = getKillRegState(MI.getOperand(1).isKill());
1075 copyPhysReg(MBB, MI, DL, DstReg, SrcSubLo, MI.getOperand(1).isKill());
1084 copyPhysReg(MBB, MI, DL, DstReg, SrcSubHi, MI.getOperand(1).isKill());
1237 unsigned K1 = getKillRegState(Op1.isKill());
1238 unsigned K2 = getKillRegState(Op2.isKill());
1239 unsigned K3 = getKillRegState(Op3.isKill());
lib/Target/Hexagon/HexagonNewValueJump.cpp 659 if (!Op.isReg() || !Op.isUse() || !Op.isKill())
706 cmpInstr->getOperand(0).isKill())
709 cmpInstr->getOperand(1).isKill())
lib/Target/Hexagon/HexagonSplitDouble.cpp 609 bool isKill = Op.isKill();
lib/Target/Hexagon/HexagonStoreWidening.cpp 435 .addReg(MR.getReg(), getKillRegState(MR.isKill()), MR.getSubReg())
458 .addReg(MR.getReg(), getKillRegState(MR.isKill()), MR.getSubReg())
lib/Target/Mips/MipsISelLowering.cpp 1276 .addReg(Divisor.getReg(), getKillRegState(Divisor.isKill()))
lib/Target/Mips/MipsSEFrameLowering.cpp 193 .addReg(Src, getKillRegState(I->getOperand(0).isKill()));
235 unsigned SrcKill = getKillRegState(I->getOperand(0).isKill());
267 unsigned SrcKill = getKillRegState(I->getOperand(1).isKill());
326 TII.storeRegToStack(MBB, I, LoReg, I->getOperand(1).isKill(), FI, RC,
328 TII.storeRegToStack(MBB, I, HiReg, I->getOperand(2).isKill(), FI, RC,
390 TII.storeRegToStack(MBB, I, SrcReg, Op1.isKill(), FI, RC, &RegInfo, 0);
lib/Target/Mips/MipsSEInstrInfo.cpp 744 LoInst.addReg(SrcLo.getReg(), getKillRegState(SrcLo.isKill()));
745 HiInst.addReg(SrcHi.getReg(), getKillRegState(SrcHi.isKill()));
755 unsigned KillSrc = getKillRegState(Src.isKill());
lib/Target/PowerPC/PPCInstrInfo.cpp 400 bool Reg1IsKill = MI.getOperand(1).isKill();
401 bool Reg2IsKill = MI.getOperand(2).isKill();
2468 if (MO.isReg() && MO.isUse() && MO.isKill() &&
2630 ADDMI->getOperand(ScaleRegIdx).isKill());
2698 if (!RegOperand.isKill())
2714 if (!MO.isKill())
2765 bool IsForwardingOperandKilled = MI.getOperand(ForwardingOperand).isKill();
3637 if (PostRA && MI.getOperand(OpNoForForwarding).isKill())
3651 RegMO->isKill());
3698 if (IsFwdFeederRegKilled || RegMO->isKill())
3756 if (PostRA && MI.getOperand(ConstantOpNo).isKill())
lib/Target/PowerPC/PPCQPXLoadSplat.cpp 153 if (!MI->getOperand(1).isKill())
lib/Target/PowerPC/PPCRegisterInfo.cpp 550 bool KillNegSizeReg = MI.getOperand(1).isKill();
663 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill()));
789 RegState::Implicit | getKillRegState(MI.getOperand(0).isKill()));
876 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill()));
lib/Target/PowerPC/PPCVSXFMAMutate.cpp 224 bool AddRegKill = AddendMI->getOperand(1).isKill();
225 bool KilledProdRegKill = MI.getOperand(KilledProdOp).isKill();
226 bool OtherProdRegKill = MI.getOperand(OtherProdOp).isKill();
lib/Target/PowerPC/PPCVSXSwapRemoval.cpp 878 bool IsKill1 = MI->getOperand(1).isKill();
879 bool IsKill2 = MI->getOperand(2).isKill();
lib/Target/RISCV/RISCVISelLowering.cpp 1165 TII.storeRegToStackSlot(*BB, MI, SrcReg, MI.getOperand(2).isKill(), FI, SrcRC,
1201 .addReg(LoReg, getKillRegState(MI.getOperand(1).isKill()))
1206 .addReg(HiReg, getKillRegState(MI.getOperand(2).isKill()))
lib/Target/SystemZ/SystemZInstrInfo.cpp 79 unsigned Reg128Killed = getKillRegState(LowRegOp.isKill());
163 SystemZ::LR, 32, MI.getOperand(1).isKill(),
202 Size, MI.getOperand(1).isKill(), MI.getOperand(1).isUndef());
977 .addReg(Src.getReg(), getKillRegState(Src.isKill()),
986 if (Op.isReg() && Op.isKill())
lib/Target/X86/X86AvoidStoreForwardingBlocks.cpp 431 NewStore->getOperand(X86::AddrNumOperands).setIsKill(StoreSrcVReg.isKill());
511 getBaseOperand(LastLoad).setIsKill(LoadBase.isKill());
517 getBaseOperand(StInst->getPrevNode()).setIsKill(StoreBase.isKill());
lib/Target/X86/X86ExpandPseudo.cpp 358 InArg.isKill());
lib/Target/X86/X86FixupLEAs.cpp 644 bool BIK = Base.isKill() && BaseReg != IndexReg;
lib/Target/X86/X86FlagsCopyLowering.cpp 571 if (FlagUse->isKill())
lib/Target/X86/X86FloatingPoint.cpp 1024 (Op.isKill() || // Marked kill.
1611 if (Op.isUse() && Op.isKill())
lib/Target/X86/X86ISelLowering.cpp29950 NextMIIt->getOperand(1).isKill()) {
lib/Target/X86/X86InstrInfo.cpp 721 isKill = Src.isKill();
738 isKill = Src.isKill();
794 bool IsKill = MI.getOperand(1).isKill();
835 bool IsKill2 = MI.getOperand(2).isKill();
1066 if (LV && Src2.isKill())
1319 if (Src.isKill())
5542 getKillRegState(ImpOp.isKill()) |
lib/Target/X86/X86RegisterInfo.cpp 698 MI.getOperand(1).isKill());
lib/Target/XCore/XCoreRegisterInfo.cpp 77 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill()))
113 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill()))
147 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill()))
190 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill()))