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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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Declarations
include/llvm/CodeGen/MachineRegisterInfo.h 720 Register createVirtualRegister(const TargetRegisterClass *RegClass,
References
include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h 83 MIB.addDef(MRI.createVirtualRegister(RC));
lib/CodeGen/EarlyIfConversion.cpp 597 DstReg = MRI->createVirtualRegister(MRI->getRegClass(PHIDst));
lib/CodeGen/GlobalISel/Utils.cpp 35 return MRI.createVirtualRegister(&RegClass);
lib/CodeGen/LiveIntervals.cpp 1662 Register NewVReg = MRI->createVirtualRegister(RegClass);
lib/CodeGen/LiveRangeEdit.cpp 35 Register VReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg));
55 Register VReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg));
lib/CodeGen/LocalStackSlotAllocation.cpp 414 BaseReg = Fn.getRegInfo().createVirtualRegister(RC);
lib/CodeGen/MIRVRegNamerUtils.cpp 342 return MRI.createVirtualRegister(RC, OS.str());
lib/CodeGen/MachineBasicBlock.cpp 516 Register VirtReg = MRI.createVirtualRegister(RC);
lib/CodeGen/MachineFunction.cpp 600 VReg = MRI.createVirtualRegister(RC);
lib/CodeGen/MachineLICM.cpp 1306 Register Reg = MRI->createVirtualRegister(RC);
lib/CodeGen/MachineLoopUtils.cpp 55 R = MRI.createVirtualRegister(MRI.getRegClass(OrigR));
lib/CodeGen/MachinePipeliner.cpp 364 Register NewReg = MRI.createVirtualRegister(RC);
lib/CodeGen/MachineSSAUpdater.cpp 121 Register NewVR = MRI->createVirtualRegister(RC);
lib/CodeGen/ModuloSchedule.cpp 548 NewReg = MRI.createVirtualRegister(RC);
664 Register NewReg = MRI.createVirtualRegister(RC);
811 SplitReg = MRI.createVirtualRegister(MRI.getRegClass(Def));
1033 Register NewReg = MRI.createVirtualRegister(RC);
1436 Register R = MRI.createVirtualRegister(RC);
1483 Register R = MRI.createVirtualRegister(RC);
1504 R = MRI.createVirtualRegister(RC);
1681 Register R = MRI.createVirtualRegister(RC);
lib/CodeGen/PHIElimination.cpp 282 entry = IncomingReg = MF.getRegInfo().createVirtualRegister(RC);
lib/CodeGen/PeepholeOptimizer.cpp 584 Register NewVR = MRI->createVirtualRegister(RC);
764 Register NewVR = MRI.createVirtualRegister(NewRC);
1232 Register NewVReg = MRI->createVirtualRegister(DefRC);
lib/CodeGen/RenameIndependentSubregs.cpp 141 Register NewVReg = MRI->createVirtualRegister(RegClass);
lib/CodeGen/SelectionDAG/FastISel.cpp 2017 return MRI.createVirtualRegister(RC);
lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp 351 return RegInfo->createVirtualRegister(
524 VReg = MRI.createVirtualRegister(RC);
lib/CodeGen/SelectionDAG/InstrEmitter.cpp 176 VRBase = MRI->createVirtualRegister(DstRC);
247 VRBase = MRI->createVirtualRegister(RC);
275 Register VReg = MRI->createVirtualRegister(RC);
322 Register NewVReg = MRI->createVirtualRegister(OpRC);
389 Register NewVReg = MRI->createVirtualRegister(IIRC);
467 Register NewReg = MRI->createVirtualRegister(RC);
523 VRBase = MRI->createVirtualRegister(TRC);
537 VRBase = MRI->createVirtualRegister(TRC);
575 VRBase = MRI->createVirtualRegister(SRC);
616 Register NewVReg = MRI->createVirtualRegister(DstRC);
633 Register NewVReg = MRI->createVirtualRegister(TRI->getAllocatableClass(RC));
lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp 811 Register VRBase = MRI.createVirtualRegister(SU->CopyDstRC);
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp 7977 Register R = AssignedReg ? Register(*I) : RegInfo.createVirtualRegister(RC);
8272 Regs.push_back(RegInfo.createVirtualRegister(RC));
9768 RegInfo.createVirtualRegister(TLI->getRegClassFor(RegVT));
lib/CodeGen/SwiftErrorValueTracking.cpp 37 auto VReg = MF->getRegInfo().createVirtualRegister(RC);
59 Register VReg = MF->getRegInfo().createVirtualRegister(RC);
133 Register VReg = MF->getRegInfo().createVirtualRegister(RC);
243 UpwardsUse ? UUseVReg : MF->getRegInfo().createVirtualRegister(RC);
lib/CodeGen/TailDuplicator.cpp 353 Register NewDef = MRI->createVirtualRegister(RC);
392 Register NewReg = MRI->createVirtualRegister(RC);
436 Register NewReg = MRI->createVirtualRegister(NewRC);
lib/CodeGen/TargetInstrInfo.cpp 828 Register NewVR = MRI.createVirtualRegister(RC);
lib/CodeGen/TwoAddressInstructionPass.cpp 1364 Register Reg = MRI->createVirtualRegister(RC);
lib/Target/AArch64/AArch64AdvSIMDScalarPass.cpp 343 Src0 = MRI->createVirtualRegister(&AArch64::FPR64RegClass);
349 Src1 = MRI->createVirtualRegister(&AArch64::FPR64RegClass);
357 Register Dst = MRI->createVirtualRegister(&AArch64::FPR64RegClass);
lib/Target/AArch64/AArch64CleanupLocalDynamicTLSPass.cpp 122 *TLSBaseAddrReg = RegInfo.createVirtualRegister(&AArch64::GPR64RegClass);
lib/Target/AArch64/AArch64ConditionalCompares.cpp 635 MRI->createVirtualRegister(TII->getRegClass(MCID, 0, TRI, *MF));
lib/Target/AArch64/AArch64FastISel.cpp 3480 Register SrcReg = MRI.createVirtualRegister(&AArch64::GPR64RegClass);
4020 Register Reg64 = MRI.createVirtualRegister(&AArch64::GPR64RegClass);
4173 Register TmpReg = MRI.createVirtualRegister(RC);
4294 Register TmpReg = MRI.createVirtualRegister(RC);
4403 Register TmpReg = MRI.createVirtualRegister(RC);
4462 Register Src64 = MRI.createVirtualRegister(&AArch64::GPR64RegClass);
lib/Target/AArch64/AArch64ISelLowering.cpp 3355 MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
12394 Register NewVR = MRI->createVirtualRegister(RC);
lib/Target/AArch64/AArch64InstrInfo.cpp 4171 Register NewVR = MRI.createVirtualRegister(OrrRC);
4213 Register NewVR = MRI.createVirtualRegister(SubRC);
4263 Register NewVR = MRI.createVirtualRegister(OrrRC);
4538 Register NewVR = MRI.createVirtualRegister(RC);
4585 Register NewVR = MRI.createVirtualRegister(RC);
4645 Register NewVR = MRI.createVirtualRegister(RC);
4665 Register NewVR = MRI.createVirtualRegister(RC);
4685 Register NewVR = MRI.createVirtualRegister(RC);
lib/Target/AArch64/AArch64InstructionSelector.cpp 724 MRI.createVirtualRegister(&AArch64::FPR32RegClass);
1093 Register ArgsAddrReg = MRI.createVirtualRegister(&AArch64::GPR64RegClass);
1133 : MRI.createVirtualRegister(&AArch64::GPR64RegClass);
1552 const Register DefGPRReg = MRI.createVirtualRegister(&GPRRC);
1805 Register LdReg = MRI.createVirtualRegister(&AArch64::GPR32RegClass);
2046 Register ExtSrc = MRI.createVirtualRegister(&AArch64::GPR64allRegClass);
2241 Def1Reg = MRI.createVirtualRegister(&AArch64::GPR32RegClass);
2251 Register Def2Reg = MRI.createVirtualRegister(&AArch64::GPR32RegClass);
2340 Register TargetReg = MRI.createVirtualRegister(&AArch64::GPR64RegClass);
2341 Register ScratchReg = MRI.createVirtualRegister(&AArch64::GPR64spRegClass);
2750 Register SubToRegDef = MRI.createVirtualRegister(DstRC);
2757 Register SubToRegDef2 = MRI.createVirtualRegister(DstRC);
2835 DstReg = MRI.createVirtualRegister(DstRC);
2991 Register ImpDefReg = MRI.createVirtualRegister(&AArch64::FPR128RegClass);
2997 Register InsertReg = MRI.createVirtualRegister(&AArch64::FPR128RegClass);
3320 Dst = MRI.createVirtualRegister(DstRC);
3752 DstReg = MRI.createVirtualRegister(DstRC);
3905 Register Reg = MRI.createVirtualRegister(RC);
3984 SrcReg = MRI.createVirtualRegister(&AArch64::FPR32RegClass);
3993 DstReg = MRI.createVirtualRegister(&AArch64::FPR32RegClass);
4559 Register NarrowReg = MRI.createVirtualRegister(&AArch64::GPR32RegClass);
lib/Target/AArch64/AArch64RegisterInfo.cpp 503 MF.getRegInfo().createVirtualRegister(&AArch64::GPR64RegClass);
533 MF.getRegInfo().createVirtualRegister(&AArch64::GPR64RegClass);
lib/Target/AArch64/AArch64SIMDInstrOpt.cpp 445 DupDest = MRI.createVirtualRegister(RC);
457 DupDest = MRI.createVirtualRegister(RC);
528 ZipDest.push_back(MRI->createVirtualRegister(&I.RC));
lib/Target/AMDGPU/AMDGPUCallLowering.cpp 320 ReturnAddrVReg = MRI.createVirtualRegister(&AMDGPU::CCR_SGPR_64RegClass);
lib/Target/AMDGPU/AMDGPUISelLowering.cpp 4096 VReg = MRI.createVirtualRegister(RC);
lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp 221 Register DstReg = MRI->createVirtualRegister(&SubRC);
330 Register UnusedCarry = MRI->createVirtualRegister(TRI.getWaveMaskRegClass());
353 Register DstLo = MRI->createVirtualRegister(&HalfRC);
354 Register DstHi = MRI->createVirtualRegister(&HalfRC);
365 Register CarryReg = MRI->createVirtualRegister(CarryRC);
372 .addDef(MRI->createVirtualRegister(CarryRC), RegState::Dead)
954 BaseReg = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass);
959 Register OverflowVal = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass);
964 Register NewBaseReg = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass);
1058 Register Undef = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass);
1245 Register TmpReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass);
1320 Register ExtReg = MRI->createVirtualRegister(&AMDGPU::SReg_64RegClass);
1321 Register UndefReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass);
1444 Register LoReg = MRI->createVirtualRegister(RC);
1445 Register HiReg = MRI->createVirtualRegister(RC);
1640 Register ImmReg = MRI->createVirtualRegister(&RegRC);
1652 Register HiReg = MRI->createVirtualRegister(&RegRC);
1653 Register LoReg = MRI->createVirtualRegister(&RegRC);
1654 Register MaskLo = MRI->createVirtualRegister(&RegRC);
1940 Register OffsetReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass);
2009 Register HighBits = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass);
lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp 1161 Register GetReg = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp 619 return MRI->createVirtualRegister(TII->getPreferredSelectRegClass(32));
1408 MRI->createVirtualRegister(MRI->getRegClass(DestReg));
1934 Register TrueBBReg = MRI->createVirtualRegister(RegClass);
1935 Register FalseBBReg = MRI->createVirtualRegister(RegClass);
2001 Register NextDestReg = MRI->createVirtualRegister(RegClass);
2061 Register PHIDestReg = MRI->createVirtualRegister(RegClass);
2062 Register IfSourceReg = MRI->createVirtualRegister(RegClass);
2177 Register NewBackedgeReg = MRI->createVirtualRegister(RegClass);
2314 Register CodeBBSelectReg = MRI->createVirtualRegister(RegClass);
2451 Register NewDestReg = MRI->createVirtualRegister(RegClass);
2740 MRI->createVirtualRegister(MRI->getRegClass(InReg));
2741 Register NewInReg = MRI->createVirtualRegister(MRI->getRegClass(InReg));
lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp 699 Register SaveExecReg = MRI.createVirtualRegister(WaveRC);
700 Register InitSaveExecReg = MRI.createVirtualRegister(WaveRC);
706 Register PhiExec = MRI.createVirtualRegister(WaveRC);
707 Register NewExec = MRI.createVirtualRegister(WaveRC);
777 = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
786 Register NewCondReg = MRI.createVirtualRegister(WaveRC);
799 Register AndReg = MRI.createVirtualRegister(WaveRC);
881 Register NewCondReg = MRI.createVirtualRegister(WaveRC);
892 Register AndReg = MRI.createVirtualRegister(WaveRC);
1007 Register SGPR = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
lib/Target/AMDGPU/AMDILCFGStructurizer.cpp 1311 HeadMBB->getParent()->getRegInfo().createVirtualRegister(I32RC);
1320 HeadMBB->getParent()->getRegInfo().createVirtualRegister(I32RC);
lib/Target/AMDGPU/GCNDPPCombine.cpp 436 MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass));
lib/Target/AMDGPU/R600OptimizeVectorRegisters.cpp 210 Register DstReg = MRI->createVirtualRegister(&R600::R600_Reg128RegClass);
lib/Target/AMDGPU/SIAddIMGInit.cpp 133 MRI.createVirtualRegister(TII->getOpRegClass(MI, DstIdx));
151 MRI.createVirtualRegister(TII->getOpRegClass(MI, DstIdx));
154 MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
lib/Target/AMDGPU/SIFixSGPRCopies.cpp 298 Register TmpReg = MRI.createVirtualRegister(NewSrcRC);
306 Register TmpAReg = MRI.createVirtualRegister(NewSrcRC);
623 = MRI->createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
lib/Target/AMDGPU/SIFoldOperands.cpp 258 Register NewReg0 = MRI.createVirtualRegister(Dst0RC);
707 auto Tmp = MRI->createVirtualRegister(&AMDGPU::AGPR_32RegClass);
734 auto Tmp = MRI->createVirtualRegister(&AMDGPU::AGPR_32RegClass);
745 Vgpr = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass);
749 auto Tmp = MRI->createVirtualRegister(&AMDGPU::AGPR_32RegClass);
lib/Target/AMDGPU/SIISelLowering.cpp 2003 Register NewVR = MRI->createVirtualRegister(RC);
2299 MF.getRegInfo().createVirtualRegister(&AMDGPU::CCR_SGPR_64RegClass),
3143 Register Reg = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
3184 Register PhiExec = MRI.createVirtualRegister(BoolRC);
3185 Register NewExec = MRI.createVirtualRegister(BoolRC);
3186 Register CurrentIdxReg = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
3187 Register CondReg = MRI.createVirtualRegister(BoolRC);
3223 IdxReg = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
3287 Register SaveExec = MRI.createVirtualRegister(BoolXExecRC);
3288 Register TmpExec = MRI.createVirtualRegister(BoolXExecRC);
3361 Register Tmp = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
3436 Register PhiReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
3437 Register InitReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
3551 Register PhiReg = MRI.createVirtualRegister(VecRC);
3610 Register DestSub0 = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
3611 Register DestSub1 = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
3679 Register CountReg = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
3759 Register DstLo = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
3760 Register DstHi = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
3762 Register SrcCondCopy = MRI.createVirtualRegister(CondRC);
10260 MRI.createVirtualRegister(&AMDGPU::VReg_1RegClass), MVT::i1);
10329 SDValue UndefReg = DAG.getRegister(MRI.createVirtualRegister(RC), VT);
lib/Target/AMDGPU/SIInstrInfo.cpp 827 Register SReg = MRI.createVirtualRegister(BoolXExecRC);
840 Register SReg = MRI.createVirtualRegister(BoolXExecRC);
854 Register SReg = MRI.createVirtualRegister(BoolXExecRC);
870 Register SReg = MRI.createVirtualRegister(BoolXExecRC);
884 Register SReg = MRI.createVirtualRegister(BoolXExecRC);
896 Register SReg = MRI.createVirtualRegister(BoolXExecRC);
897 Register SReg2 = MRI.createVirtualRegister(RI.getBoolRC());
914 Register SReg = MRI.createVirtualRegister(BoolXExecRC);
915 Register SReg2 = MRI.createVirtualRegister(RI.getBoolRC());
945 Register Reg = MRI.createVirtualRegister(RI.getBoolRC());
958 Register Reg = MRI.createVirtualRegister(RI.getBoolRC());
1098 Register Tmp = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
1217 Register Tmp = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
1582 auto Tmp = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
1782 Register PCReg = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
2235 Register DstElt = MRI.createVirtualRegister(EltRC);
3846 Register Reg = MRI.createVirtualRegister(VRC);
3861 Register SubReg = MRI.createVirtualRegister(SubRC);
3873 Register NewSuperReg = MRI.createVirtualRegister(SuperRC);
4037 Register Reg = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
4043 Register Reg = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
4069 Register Reg = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
4141 Register Reg = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
4147 Register Reg = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
4215 Register DstReg = MRI.createVirtualRegister(SRC);
4220 Register NewSrcReg = MRI.createVirtualRegister(VRC);
4236 Register SGPR = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
4288 Register DstReg = MRI.createVirtualRegister(DstRC);
4339 Register SaveExec = MRI.createVirtualRegister(BoolXExecRC);
4340 Register CondReg0 = MRI.createVirtualRegister(BoolXExecRC);
4341 Register CondReg1 = MRI.createVirtualRegister(BoolXExecRC);
4342 Register AndCond = MRI.createVirtualRegister(BoolXExecRC);
4343 Register SRsrcSub0 = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
4344 Register SRsrcSub1 = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
4345 Register SRsrcSub2 = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
4346 Register SRsrcSub3 = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
4347 Register SRsrc = MRI.createVirtualRegister(&AMDGPU::SGPR_128RegClass);
4415 Register SaveExec = MRI.createVirtualRegister(BoolXExecRC);
4483 Register Zero64 = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
4484 Register SRsrcFormatLo = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
4485 Register SRsrcFormatHi = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
4486 Register NewSRsrc = MRI.createVirtualRegister(&AMDGPU::SGPR_128RegClass);
4698 Register NewVAddrLo = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
4699 Register NewVAddrHi = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
4700 Register NewVAddr = MRI.createVirtualRegister(&AMDGPU::VReg_64RegClass);
4703 Register CondReg0 = MRI.createVirtualRegister(BoolXExecRC);
4704 Register CondReg1 = MRI.createVirtualRegister(BoolXExecRC);
4744 Register NewVAddr = MRI.createVirtualRegister(&AMDGPU::VReg_64RegClass);
5088 NewDstReg = MRI.createVirtualRegister(NewDstRC);
5112 Register ResultReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
5145 Register TmpReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
5146 Register ResultReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
5175 Register NewDest = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
5195 Register Temp = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
5196 Register NewDest = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
5240 Register NewDest = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
5241 Register Interm = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
5269 Register NewDest = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
5270 Register Interm = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
5312 Register DestSub0 = MRI.createVirtualRegister(NewDestSubRC);
5318 Register DestSub1 = MRI.createVirtualRegister(NewDestSubRC);
5321 Register FullDestReg = MRI.createVirtualRegister(NewDestRC);
5349 Register FullDestReg = MRI.createVirtualRegister(&AMDGPU::VReg_64RegClass);
5350 Register DestSub0 = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
5351 Register DestSub1 = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
5353 Register CarryReg = MRI.createVirtualRegister(CarryRC);
5354 Register DeadCarryReg = MRI.createVirtualRegister(CarryRC);
5450 Register DestSub0 = MRI.createVirtualRegister(NewDestSubRC);
5455 Register DestSub1 = MRI.createVirtualRegister(NewDestSubRC);
5460 Register FullDestReg = MRI.createVirtualRegister(NewDestRC);
5491 Register Interm = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
5507 Register NewDest = MRI.createVirtualRegister(DestRC);
5534 Register MidReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
5535 Register ResultReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
5574 Register MidRegLo = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
5575 Register MidRegHi = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
5576 Register ResultReg = MRI.createVirtualRegister(&AMDGPU::VReg_64RegClass);
5599 Register TmpReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
5600 Register ResultReg = MRI.createVirtualRegister(&AMDGPU::VReg_64RegClass);
5655 Register ResultReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
5663 Register ImmReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
5664 Register TmpReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
5682 Register ImmReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
5692 Register ImmReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
5693 Register TmpReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
6075 Register DstReg = MRI.createVirtualRegister(RI.getBoolRC());
6102 Register DstReg = MRI.createVirtualRegister(RI.getBoolRC());
6103 Register BackEdgeReg = MRI.createVirtualRegister(RI.getBoolRC());
6113 Register ZeroReg = MRI.createVirtualRegister(RI.getBoolRC());
6197 Register UnusedCarry = MRI.createVirtualRegister(RI.getBoolRC());
lib/Target/AMDGPU/SILoadStoreOptimizer.cpp 903 Register DestReg = MRI->createVirtualRegister(SuperRC);
911 Register ImmReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass);
915 BaseReg = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass);
1004 Register ImmReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass);
1008 BaseReg = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass);
1045 Register DestReg = MRI->createVirtualRegister(SuperRC);
1099 Register DestReg = MRI->createVirtualRegister(SuperRC);
1151 Register DestReg = MRI->createVirtualRegister(SuperRC);
1308 Register SrcReg = MRI->createVirtualRegister(SuperRC);
1360 Register Reg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass);
1391 Register CarryReg = MRI->createVirtualRegister(CarryRC);
1392 Register DeadCarryReg = MRI->createVirtualRegister(CarryRC);
1394 Register DestSub0 = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass);
1395 Register DestSub1 = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass);
1415 Register FullDestReg = MRI->createVirtualRegister(&AMDGPU::VReg_64RegClass);
lib/Target/AMDGPU/SILowerControlFlow.cpp 217 : MRI->createVirtualRegister(BoolRC);
223 Register Tmp = MRI->createVirtualRegister(BoolRC);
293 Register CopyReg = MRI->createVirtualRegister(BoolRC);
301 MRI->createVirtualRegister(BoolRC) : DstReg;
lib/Target/AMDGPU/SILowerI1Copies.cpp 430 return MRI.createVirtualRegister(ST.isWave32() ? &AMDGPU::SReg_32RegClass
lib/Target/AMDGPU/SIPeepholeSDWA.cpp 1192 Register VGPR = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass);
lib/Target/AMDGPU/SIRegisterInfo.cpp 362 Register OffsetReg = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
364 Register FIReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
lib/Target/AMDGPU/SIWholeQuadMode.cpp 559 Register SaveReg = MRI->createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
799 SavedNonWWMReg = MRI->createVirtualRegister(BoolRC);
805 SavedWQMReg = MRI->createVirtualRegister(BoolRC);
903 LiveMaskReg = MRI->createVirtualRegister(TRI->getBoolRC());
lib/Target/ARC/ARCExpandPseudos.cpp 62 unsigned AddrReg = MF.getRegInfo().createVirtualRegister(&ARC::GPR32RegClass);
lib/Target/ARC/ARCISelLowering.cpp 493 unsigned VReg = RegInfo.createVirtualRegister(&ARC::GPR32RegClass);
538 unsigned VReg = RegInfo.createVirtualRegister(&ARC::GPR32RegClass);
lib/Target/ARM/A15SDOptimizer.cpp 422 MRI->createVirtualRegister(QPR ? &ARM::QPRRegClass : &ARM::DPRRegClass);
437 Register Out = MRI->createVirtualRegister(TRC);
451 Register Out = MRI->createVirtualRegister(&ARM::QPRRegClass);
469 Register Out = MRI->createVirtualRegister(&ARM::DPRRegClass);
481 Register Out = MRI->createVirtualRegister(&ARM::DPR_VFP2RegClass);
497 Register Out = MRI->createVirtualRegister(&ARM::DPRRegClass);
lib/Target/ARM/ARMBaseInstrInfo.cpp 3317 Register NewReg = MRI->createVirtualRegister(MRI->getRegClass(Reg));
lib/Target/ARM/ARMBaseRegisterInfo.cpp 822 ScratchReg = MF.getRegInfo().createVirtualRegister(RegClass);
lib/Target/ARM/ARMFastISel.cpp 2967 Register TempReg = MF->getRegInfo().createVirtualRegister(&ARM::rGPRRegClass);
lib/Target/ARM/ARMISelDAGToDAG.cpp 4719 Register GPVR = MRI.createVirtualRegister(&ARM::GPRPairRegClass);
4755 Register GPVR = MRI.createVirtualRegister(&ARM::GPRPairRegClass);
lib/Target/ARM/ARMISelLowering.cpp 9378 Register NewVReg1 = MRI->createVirtualRegister(TRC);
9384 Register NewVReg2 = MRI->createVirtualRegister(TRC);
9390 Register NewVReg3 = MRI->createVirtualRegister(TRC);
9408 Register NewVReg1 = MRI->createVirtualRegister(TRC);
9413 Register NewVReg2 = MRI->createVirtualRegister(TRC);
9418 Register NewVReg3 = MRI->createVirtualRegister(TRC);
9423 Register NewVReg4 = MRI->createVirtualRegister(TRC);
9429 Register NewVReg5 = MRI->createVirtualRegister(TRC);
9444 Register NewVReg1 = MRI->createVirtualRegister(TRC);
9450 Register NewVReg2 = MRI->createVirtualRegister(TRC);
9572 Register NewVReg1 = MRI->createVirtualRegister(TRC);
9585 Register VReg1 = MRI->createVirtualRegister(TRC);
9592 VReg2 = MRI->createVirtualRegister(TRC);
9610 Register NewVReg3 = MRI->createVirtualRegister(TRC);
9615 Register NewVReg4 = MRI->createVirtualRegister(TRC);
9628 Register NewVReg1 = MRI->createVirtualRegister(TRC);
9651 Register VReg1 = MRI->createVirtualRegister(TRC);
9667 Register NewVReg2 = MRI->createVirtualRegister(TRC);
9674 Register NewVReg3 = MRI->createVirtualRegister(TRC);
9679 Register NewVReg4 = MRI->createVirtualRegister(TRC);
9689 Register NewVReg5 = MRI->createVirtualRegister(TRC);
9698 NewVReg6 = MRI->createVirtualRegister(TRC);
9710 Register NewVReg1 = MRI->createVirtualRegister(TRC);
9723 Register VReg1 = MRI->createVirtualRegister(TRC);
9730 VReg2 = MRI->createVirtualRegister(TRC);
9752 Register VReg1 = MRI->createVirtualRegister(TRC);
9769 Register NewVReg3 = MRI->createVirtualRegister(TRC);
9775 Register NewVReg4 = MRI->createVirtualRegister(TRC);
9782 Register NewVReg5 = MRI->createVirtualRegister(TRC);
10069 Register srcOut = MRI.createVirtualRegister(TRC);
10070 Register destOut = MRI.createVirtualRegister(TRC);
10071 Register scratch = MRI.createVirtualRegister(IsNeon ? VecTRC : TRC);
10084 Register srcOut = MRI.createVirtualRegister(TRC);
10085 Register destOut = MRI.createVirtualRegister(TRC);
10086 Register scratch = MRI.createVirtualRegister(TRC);
10129 Register varEnd = MRI.createVirtualRegister(TRC);
10133 Vtmp = MRI.createVirtualRegister(TRC);
10179 Register varLoop = MRI.createVirtualRegister(TRC);
10180 Register varPhi = MRI.createVirtualRegister(TRC);
10181 Register srcLoop = MRI.createVirtualRegister(TRC);
10182 Register srcPhi = MRI.createVirtualRegister(TRC);
10183 Register destLoop = MRI.createVirtualRegister(TRC);
10184 Register destPhi = MRI.createVirtualRegister(TRC);
10198 Register scratch = MRI.createVirtualRegister(IsNeon ? VecTRC : TRC);
10239 Register srcOut = MRI.createVirtualRegister(TRC);
10240 Register destOut = MRI.createVirtualRegister(TRC);
10241 Register scratch = MRI.createVirtualRegister(TRC);
10301 Register Reg = MRI.createVirtualRegister(&ARM::rGPRRegClass);
10629 Register NewRsbDstReg = MRI.createVirtualRegister(
10709 Register TmpReg = MRI.createVirtualRegister(isThumb1 ? &ARM::tGPRRegClass
17115 Register NewVR = MRI->createVirtualRegister(RC);
lib/Target/ARM/ARMInstructionSelector.cpp 549 auto ZeroReg = MRI.createVirtualRegister(&ARM::GPRRegClass);
559 auto IntermediateRes = MRI.createVirtualRegister(&ARM::GPRRegClass);
688 auto AddressReg = MRI.createVirtualRegister(&ARM::GPRRegClass);
718 auto Offset = MRI.createVirtualRegister(&ARM::GPRRegClass);
879 Register AndResult = MRI.createVirtualRegister(&ARM::GPRRegClass);
930 Register IgnoredBits = MRI.createVirtualRegister(&ARM::GPRRegClass);
1101 Register ValueToStore = MRI.createVirtualRegister(&ARM::GPRRegClass);
lib/Target/ARM/MLxExpansionPass.cpp 288 MRI->createVirtualRegister(TII->getRegClass(MCID1, 0, TRI, MF));
lib/Target/ARM/ThumbRegisterInfo.cpp 146 LdReg = MF.getRegInfo().createVirtualRegister(&ARM::tGPRRegClass);
536 VReg = MF.getRegInfo().createVirtualRegister(&ARM::tGPRRegClass);
lib/Target/AVR/AVRFrameLowering.cpp 514 MF.getRegInfo().createVirtualRegister(&AVR::DREGSRegClass);
lib/Target/AVR/AVRISelDAGToDAG.cpp 268 unsigned VReg = RI.createVirtualRegister(&AVR::PTRDISPREGSRegClass);
297 unsigned VReg = RI.createVirtualRegister(&AVR::PTRDISPREGSRegClass);
lib/Target/AVR/AVRISelLowering.cpp 1518 unsigned ShiftAmtReg = RI.createVirtualRegister(&AVR::LD8RegClass);
1519 unsigned ShiftAmtReg2 = RI.createVirtualRegister(&AVR::LD8RegClass);
1520 Register ShiftReg = RI.createVirtualRegister(RC);
1521 Register ShiftReg2 = RI.createVirtualRegister(RC);
lib/Target/BPF/BPFISelLowering.cpp 239 Register VReg = RegInfo.createVirtualRegister(
573 Register PromotedReg0 = RegInfo.createVirtualRegister(RC);
574 Register PromotedReg1 = RegInfo.createVirtualRegister(RC);
575 Register PromotedReg2 = RegInfo.createVirtualRegister(RC);
609 ScratchReg = MRI.createVirtualRegister(&BPF::GPRRegClass);
lib/Target/Hexagon/HexagonBitSimplify.cpp 1345 Register NewR = MRI.createVirtualRegister(FRC);
1412 Register Reg = MRI.createVirtualRegister(RC);
1609 Register NewR = MRI.createVirtualRegister(FRC);
1628 Register NewR = MRI.createVirtualRegister(FRC);
2025 Register NewR = MRI.createVirtualRegister(&Hexagon::DoubleRegsRegClass);
2057 NewR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
2063 NewR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
2097 Register NewR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
2154 Register NewR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
2298 NewR = MRI.createVirtualRegister(&Hexagon::DoubleRegsRegClass);
2359 unsigned NewR = MRI.createVirtualRegister(&Hexagon::PredRegsRegClass);
2368 Register NewR = MRI.createVirtualRegister(&Hexagon::PredRegsRegClass);
2541 Register NewR = MRI.createVirtualRegister(FRC);
2613 Register NewR = MRI.createVirtualRegister(FRC);
2678 Register NewR = MRI.createVirtualRegister(FRC);
3071 Register PhiR = MRI->createVirtualRegister(PhiRC);
3083 Register NewDR = MRI->createVirtualRegister(RC);
3284 PrehR = MRI->createVirtualRegister(RC);
lib/Target/Hexagon/HexagonConstExtenders.cpp 1528 llvm::Register DefR = MRI->createVirtualRegister(&Hexagon::IntRegsRegClass);
lib/Target/Hexagon/HexagonConstPropagation.cpp 2874 Register NewR = MRI->createVirtualRegister(PredRC);
2896 Register NewR = MRI->createVirtualRegister(NewRC);
2983 NewR = MRI->createVirtualRegister(RC);
3012 Register NewR = MRI->createVirtualRegister(RC);
3049 NewR = MRI->createVirtualRegister(RC);
3081 NewR = MRI->createVirtualRegister(RC);
lib/Target/Hexagon/HexagonEarlyIfConv.cpp 801 Register MuxR = MRI->createVirtualRegister(DRC);
1000 NewR = MRI->createVirtualRegister(RC);
lib/Target/Hexagon/HexagonFrameLowering.cpp 1579 Register TmpR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
1604 Register TmpR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
1635 Register TmpR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
1670 Register TmpR0 = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
1671 Register TmpR1 = MRI.createVirtualRegister(RC);
1705 Register TmpR0 = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
1706 Register TmpR1 = MRI.createVirtualRegister(RC);
lib/Target/Hexagon/HexagonGenInsert.cpp 1402 Register NewVR = MRI->createVirtualRegister(RC);
lib/Target/Hexagon/HexagonGenPredicate.cpp 268 Register NewPR = MRI->createVirtualRegister(PredRC);
421 RegisterSubReg NewPR = MRI->createVirtualRegister(PredRC);
435 Register NewOutR = MRI->createVirtualRegister(RC);
lib/Target/Hexagon/HexagonHardwareLoops.cpp 913 Register SubR = MRI->createVirtualRegister(IntRC);
934 Register SubR = MRI->createVirtualRegister(IntRC);
953 Register AddR = MRI->createVirtualRegister(IntRC);
974 Register LsrR = MRI->createVirtualRegister(IntRC);
1247 Register CountReg = MRI->createVirtualRegister(&Hexagon::IntRegsRegClass);
1260 Register CountReg = MRI->createVirtualRegister(&Hexagon::IntRegsRegClass);
1589 Register NewR = MRI->createVirtualRegister(RC);
1908 Register NewPR = MRI->createVirtualRegister(RC);
lib/Target/Hexagon/HexagonISelLowering.cpp 289 Register PredR = MRI.createVirtualRegister(&Hexagon::PredRegsRegClass);
739 Register VReg = MRI.createVirtualRegister(RC);
lib/Target/Hexagon/HexagonInstrInfo.cpp 1996 Register NewReg = MRI.createVirtualRegister(TRC);
lib/Target/Hexagon/HexagonRegisterInfo.cpp 220 Register TmpR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
lib/Target/Hexagon/HexagonSplitDouble.cpp 677 Register NewR = MRI->createVirtualRegister(RC);
816 Register TmpR = MRI->createVirtualRegister(IntRC);
956 Register TmpR1 = MRI->createVirtualRegister(IntRC);
961 Register TmpR2 = MRI->createVirtualRegister(IntRC);
1116 Register NewDR = MRI->createVirtualRegister(DoubleRC);
1148 Register LoR = MRI->createVirtualRegister(IntRC);
1149 Register HiR = MRI->createVirtualRegister(IntRC);
lib/Target/Hexagon/HexagonStoreWidening.cpp 444 Register VReg = MF->getRegInfo().createVirtualRegister(RC);
lib/Target/Hexagon/HexagonVExtract.cpp 70 Register ElemR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
89 Register IdxR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
147 Register BaseR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
lib/Target/Lanai/LanaiISelLowering.cpp 463 Register VReg = RegInfo.createVirtualRegister(&Lanai::GPRRegClass);
516 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i32));
lib/Target/Lanai/LanaiMachineFunctionInfo.cpp 21 MF.getRegInfo().createVirtualRegister(&Lanai::GPRRegClass);
lib/Target/MSP430/MSP430ISelLowering.cpp 638 Register VReg = RegInfo.createVirtualRegister(&MSP430::GR16RegClass);
695 Reg = MF.getRegInfo().createVirtualRegister(
1485 Register ShiftAmtReg = RI.createVirtualRegister(&MSP430::GR8RegClass);
1486 Register ShiftAmtReg2 = RI.createVirtualRegister(&MSP430::GR8RegClass);
1487 Register ShiftReg = RI.createVirtualRegister(RC);
1488 Register ShiftReg2 = RI.createVirtualRegister(RC);
lib/Target/Mips/Mips16ISelDAGToDAG.cpp 78 V0 = RegInfo.createVirtualRegister(RC);
79 V1 = RegInfo.createVirtualRegister(RC);
80 V2 = RegInfo.createVirtualRegister(RC);
lib/Target/Mips/MipsISelLowering.cpp 1258 Register VReg = MF.getRegInfo().createVirtualRegister(RC);
1481 Register Scratch = RegInfo.createVirtualRegister(RegInfo.getRegClass(OldVal));
1520 Register PtrCopy = RegInfo.createVirtualRegister(RegInfo.getRegClass(Ptr));
1521 Register IncrCopy = RegInfo.createVirtualRegister(RegInfo.getRegClass(Incr));
1557 Register ScrReg = RegInfo.createVirtualRegister(RC);
1586 Register AlignedAddr = RegInfo.createVirtualRegister(RCp);
1587 Register ShiftAmt = RegInfo.createVirtualRegister(RC);
1588 Register Mask = RegInfo.createVirtualRegister(RC);
1589 Register Mask2 = RegInfo.createVirtualRegister(RC);
1590 Register Incr2 = RegInfo.createVirtualRegister(RC);
1591 Register MaskLSB2 = RegInfo.createVirtualRegister(RCp);
1592 Register PtrLSB2 = RegInfo.createVirtualRegister(RC);
1593 Register MaskUpper = RegInfo.createVirtualRegister(RC);
1594 Register Scratch = RegInfo.createVirtualRegister(RC);
1595 Register Scratch2 = RegInfo.createVirtualRegister(RC);
1596 Register Scratch3 = RegInfo.createVirtualRegister(RC);
1679 Register Off = RegInfo.createVirtualRegister(RC);
1744 Register Scratch = MRI.createVirtualRegister(RC);
1752 Register PtrCopy = MRI.createVirtualRegister(MRI.getRegClass(Ptr));
1753 Register OldValCopy = MRI.createVirtualRegister(MRI.getRegClass(OldVal));
1754 Register NewValCopy = MRI.createVirtualRegister(MRI.getRegClass(NewVal));
1796 Register AlignedAddr = RegInfo.createVirtualRegister(RCp);
1797 Register ShiftAmt = RegInfo.createVirtualRegister(RC);
1798 Register Mask = RegInfo.createVirtualRegister(RC);
1799 Register Mask2 = RegInfo.createVirtualRegister(RC);
1800 Register ShiftedCmpVal = RegInfo.createVirtualRegister(RC);
1801 Register ShiftedNewVal = RegInfo.createVirtualRegister(RC);
1802 Register MaskLSB2 = RegInfo.createVirtualRegister(RCp);
1803 Register PtrLSB2 = RegInfo.createVirtualRegister(RC);
1804 Register MaskUpper = RegInfo.createVirtualRegister(RC);
1805 Register MaskedCmpVal = RegInfo.createVirtualRegister(RC);
1806 Register MaskedNewVal = RegInfo.createVirtualRegister(RC);
1821 Register Scratch = RegInfo.createVirtualRegister(RC);
1822 Register Scratch2 = RegInfo.createVirtualRegister(RC);
1860 Register Off = RegInfo.createVirtualRegister(RC);
3591 Reg = MF.getRegInfo().createVirtualRegister(
lib/Target/Mips/MipsInstructionSelector.cpp 151 Register LUiReg = B.getMRI()->createVirtualRegister(&Mips::GPR32RegClass);
266 Register PseudoMULTuReg = MRI.createVirtualRegister(&Mips::ACC64RegClass);
317 Register JTIndex = MRI.createVirtualRegister(&Mips::GPR32RegClass);
325 Register DestAddress = MRI.createVirtualRegister(&Mips::GPR32RegClass);
333 Register Dest = MRI.createVirtualRegister(&Mips::GPR32RegClass);
345 Register DestTmp = MRI.createVirtualRegister(&Mips::GPR32RegClass);
424 Register HILOReg = MRI.createVirtualRegister(&Mips::ACC64RegClass);
483 Register GPRReg = MRI.createVirtualRegister(&Mips::GPR32RegClass);
494 Register GPRRegHigh = MRI.createVirtualRegister(&Mips::GPR32RegClass);
495 Register GPRRegLow = MRI.createVirtualRegister(&Mips::GPR32RegClass);
535 Register ResultInFPR = MRI.createVirtualRegister(&Mips::FGR32RegClass);
574 Register LWGOTDef = MRI.createVirtualRegister(&Mips::GPR32RegClass);
587 Register LUiReg = MRI.createVirtualRegister(&Mips::GPR32RegClass);
642 Register Temp = MRI.createVirtualRegister(&Mips::GPR32RegClass);
756 Register TrueInReg = MRI.createVirtualRegister(&Mips::GPR32RegClass);
792 Register LeaReg = MRI.createVirtualRegister(&Mips::GPR32RegClass);
lib/Target/Mips/MipsMachineFunction.cpp 50 MF.getRegInfo().createVirtualRegister(&getGlobalBaseRegClass(MF));
77 V0 = RegInfo.createVirtualRegister(RC);
78 V1 = RegInfo.createVirtualRegister(RC);
lib/Target/Mips/MipsSEFrameLowering.cpp 174 Register VR = MRI.createVirtualRegister(RC);
189 Register VR = MRI.createVirtualRegister(RC);
207 Register VR0 = MRI.createVirtualRegister(RC);
208 Register VR1 = MRI.createVirtualRegister(RC);
232 Register VR0 = MRI.createVirtualRegister(RC);
233 Register VR1 = MRI.createVirtualRegister(RC);
265 Register VR0 = MRI.createVirtualRegister(RC);
266 Register VR1 = MRI.createVirtualRegister(RC);
541 Register VR = MF.getRegInfo().createVirtualRegister(RC);
lib/Target/Mips/MipsSEISelLowering.cpp 3067 Register VR2 = RegInfo.createVirtualRegister(RC);
3073 Register VR1 = RegInfo.createVirtualRegister(RC);
3136 Register RD1 = RegInfo.createVirtualRegister(RC);
3142 Register RD2 = RegInfo.createVirtualRegister(RC);
3183 Wt = RegInfo.createVirtualRegister(&Mips::MSA128WEvensRegClass);
3190 Register Wt = RegInfo.createVirtualRegister(
3227 Register Wt = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
3253 Register Wt = RegInfo.createVirtualRegister(
3289 Register Wt = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
3375 Register Wt = RegInfo.createVirtualRegister(VecRC);
3385 Register LaneTmp1 = RegInfo.createVirtualRegister(GPRRC);
3393 Register WdTmp1 = RegInfo.createVirtualRegister(VecRC);
3399 Register WdTmp2 = RegInfo.createVirtualRegister(VecRC);
3418 Register LaneTmp2 = RegInfo.createVirtualRegister(GPRRC);
3447 Register Wt1 = RegInfo.createVirtualRegister(
3450 Register Wt2 = RegInfo.createVirtualRegister(
3482 Register Wt1 = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
3483 Register Wt2 = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
3527 Register Rs = RegInfo.createVirtualRegister(&Mips::GPR32RegClass);
3531 Register Tmp = RegInfo.createVirtualRegister(&Mips::GPR64RegClass);
3580 Register Rt = RegInfo.createVirtualRegister(RC);
3588 Register Tmp = RegInfo.createVirtualRegister(&Mips::GPR32RegClass);
3667 Register Wtemp = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
3676 Register Rtemp = RegInfo.createVirtualRegister(GPRRC);
3682 Register Rtemp2 = RegInfo.createVirtualRegister(GPRRC);
3684 Register Wtemp2 = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
3685 Register Wtemp3 = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
3698 Register Wtemp2 = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
3779 Register Wtemp = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
3784 WPHI = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
3789 Register Rtemp = RegInfo.createVirtualRegister(GPRRC);
3791 ? RegInfo.createVirtualRegister(&Mips::FGR64RegClass)
3797 Register Rtemp2 = RegInfo.createVirtualRegister(GPRRC);
3822 Register Ws1 = RegInfo.createVirtualRegister(RC);
3823 Register Ws2 = RegInfo.createVirtualRegister(RC);
3851 Register Ws1 = RegInfo.createVirtualRegister(RC);
3852 Register Ws2 = RegInfo.createVirtualRegister(RC);
lib/Target/Mips/MipsSEInstrInfo.cpp 631 Register Reg = RegInfo.createVirtualRegister(RC);
lib/Target/Mips/MipsSERegisterInfo.cpp 225 Register Reg = RegInfo.createVirtualRegister(PtrRC);
lib/Target/PowerPC/PPCISelDAGToDAG.cpp 394 Register InVRSAVE = RegInfo->createVirtualRegister(&PPC::GPRCRegClass);
395 Register UpdatedVRSAVE = RegInfo->createVirtualRegister(&PPC::GPRCRegClass);
450 Register TempReg = RegInfo->createVirtualRegister(&PPC::GPRCRegClass);
458 RegInfo->createVirtualRegister(&PPC::GPRC_and_GPRC_NOR0RegClass);
473 GlobalBaseReg = RegInfo->createVirtualRegister(&PPC::G8RC_and_G8RC_NOX0RegClass);
lib/Target/PowerPC/PPCISelLowering.cpp10355 RegInfo.createVirtualRegister( AtomicSize == 8 ? &PPC::G8RCRegClass
10388 Register ExtReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass);
10462 Register PtrReg = RegInfo.createVirtualRegister(RC);
10463 Register Shift1Reg = RegInfo.createVirtualRegister(GPRC);
10465 isLittleEndian ? Shift1Reg : RegInfo.createVirtualRegister(GPRC);
10466 Register Incr2Reg = RegInfo.createVirtualRegister(GPRC);
10467 Register MaskReg = RegInfo.createVirtualRegister(GPRC);
10468 Register Mask2Reg = RegInfo.createVirtualRegister(GPRC);
10469 Register Mask3Reg = RegInfo.createVirtualRegister(GPRC);
10470 Register Tmp2Reg = RegInfo.createVirtualRegister(GPRC);
10471 Register Tmp3Reg = RegInfo.createVirtualRegister(GPRC);
10472 Register Tmp4Reg = RegInfo.createVirtualRegister(GPRC);
10473 Register TmpDestReg = RegInfo.createVirtualRegister(GPRC);
10476 (!BinOpcode) ? Incr2Reg : RegInfo.createVirtualRegister(GPRC);
10503 Ptr1Reg = RegInfo.createVirtualRegister(RC);
10560 Register SReg = RegInfo.createVirtualRegister(GPRC);
10567 ValueReg = RegInfo.createVirtualRegister(GPRC);
10571 Register ValueSReg = RegInfo.createVirtualRegister(GPRC);
10625 Register mainDstReg = MRI.createVirtualRegister(RC);
10626 Register restoreDstReg = MRI.createVirtualRegister(RC);
10678 Register LabelReg = MRI.createVirtualRegister(PtrRC);
10766 Register Tmp = MRI.createVirtualRegister(RC);
11024 Register ReadAgainReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass);
11032 Register CmpReg = RegInfo.createVirtualRegister(&PPC::CRRCRegClass);
11277 Register PtrReg = RegInfo.createVirtualRegister(RC);
11278 Register Shift1Reg = RegInfo.createVirtualRegister(GPRC);
11280 isLittleEndian ? Shift1Reg : RegInfo.createVirtualRegister(GPRC);
11281 Register NewVal2Reg = RegInfo.createVirtualRegister(GPRC);
11282 Register NewVal3Reg = RegInfo.createVirtualRegister(GPRC);
11283 Register OldVal2Reg = RegInfo.createVirtualRegister(GPRC);
11284 Register OldVal3Reg = RegInfo.createVirtualRegister(GPRC);
11285 Register MaskReg = RegInfo.createVirtualRegister(GPRC);
11286 Register Mask2Reg = RegInfo.createVirtualRegister(GPRC);
11287 Register Mask3Reg = RegInfo.createVirtualRegister(GPRC);
11288 Register Tmp2Reg = RegInfo.createVirtualRegister(GPRC);
11289 Register Tmp4Reg = RegInfo.createVirtualRegister(GPRC);
11290 Register TmpDestReg = RegInfo.createVirtualRegister(GPRC);
11292 Register TmpReg = RegInfo.createVirtualRegister(GPRC);
11327 Ptr1Reg = RegInfo.createVirtualRegister(RC);
11440 Register MFFSReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass);
11466 Register Dest = RegInfo.createVirtualRegister(
11479 Register CRReg = RegInfo.createVirtualRegister(&PPC::CRRCRegClass);
11589 Register OldFPSCRTmpReg = RegInfo.createVirtualRegister(&PPC::G8RCRegClass);
11593 Register ImDefReg = RegInfo.createVirtualRegister(&PPC::G8RCRegClass);
11594 Register ExtSrcReg = RegInfo.createVirtualRegister(&PPC::G8RCRegClass);
11605 Register NewFPSCRTmpReg = RegInfo.createVirtualRegister(&PPC::G8RCRegClass);
11612 Register NewFPSCRReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass);
15047 Register NewVR = MRI->createVirtualRegister(RC);
lib/Target/PowerPC/PPCInstrInfo.cpp 867 FirstReg = MRI.createVirtualRegister(FirstRC);
lib/Target/PowerPC/PPCMIPeephole.cpp 655 MF->getRegInfo().createVirtualRegister(&PPC::G8RCRegClass);
1296 Register NewVReg = MRI->createVirtualRegister(&PPC::CRRCRegClass);
lib/Target/PowerPC/PPCRegisterInfo.cpp 529 Register Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
558 NegSizeReg = MF.getRegInfo().createVirtualRegister(G8RC);
566 NegSizeReg = MF.getRegInfo().createVirtualRegister(G8RC);
583 NegSizeReg = MF.getRegInfo().createVirtualRegister(GPRC);
591 NegSizeReg = MF.getRegInfo().createVirtualRegister(GPRC);
657 Register Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
669 Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
702 Register Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
714 Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
746 Register Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
794 Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
825 Register Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
835 Register RegO = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
872 Register Reg = MF.getRegInfo().createVirtualRegister(GPRC);
898 Register Reg = MF.getRegInfo().createVirtualRegister(GPRC);
1096 unsigned SRegHi = MF.getRegInfo().createVirtualRegister(RC),
1097 SReg = MF.getRegInfo().createVirtualRegister(RC);
lib/Target/PowerPC/PPCVSXCopy.cpp 105 Register NewVReg = MRI.createVirtualRegister(SrcRC);
127 Register NewVReg = MRI.createVirtualRegister(DstRC);
lib/Target/PowerPC/PPCVSXSwapRemoval.cpp 899 Register NewVReg = MRI->createVirtualRegister(DstRC);
913 Register VSRCTmp1 = MRI->createVirtualRegister(&PPC::VSRCRegClass);
914 Register VSRCTmp2 = MRI->createVirtualRegister(&PPC::VSRCRegClass);
lib/Target/RISCV/RISCVFrameLowering.cpp 86 Register ScratchReg = MRI.createVirtualRegister(&RISCV::GPRRegClass);
219 MF.getRegInfo().createVirtualRegister(&RISCV::GPRRegClass);
lib/Target/RISCV/RISCVISelLowering.cpp 1122 Register ReadAgainReg = RegInfo.createVirtualRegister(&RISCV::GPRRegClass);
1710 Register VReg = RegInfo.createVirtualRegister(RC);
1788 Register LoVReg = RegInfo.createVirtualRegister(&RISCV::GPRRegClass);
1800 Register HiVReg = RegInfo.createVirtualRegister(&RISCV::GPRRegClass);
1983 const Register Reg = RegInfo.createVirtualRegister(RC);
lib/Target/RISCV/RISCVInstrInfo.cpp 169 Register Result = MRI.createVirtualRegister(&RISCV::GPRRegClass);
396 Register ScratchReg = MRI.createVirtualRegister(&RISCV::GPRRegClass);
lib/Target/RISCV/RISCVRegisterInfo.cpp 131 Register ScratchReg = MRI.createVirtualRegister(&RISCV::GPRRegClass);
lib/Target/Sparc/SparcISelDAGToDAG.cpp 234 Register GPVR = MRI.createVirtualRegister(&SP::IntPairRegClass);
281 Register GPVR = MRI.createVirtualRegister(&SP::IntPairRegClass);
lib/Target/Sparc/SparcISelLowering.cpp 420 Register VRegHi = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
448 Register VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
527 Reg = MF.getRegInfo().createVirtualRegister(&SP::IntRegsRegClass);
555 Register VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
lib/Target/Sparc/SparcInstrInfo.cpp 485 GlobalBaseReg = RegInfo.createVirtualRegister(PtrRC);
lib/Target/SystemZ/SystemZISelLowering.cpp 1354 Register VReg = MRI.createVirtualRegister(RC);
6511 Register Reg = MRI.createVirtualRegister(&SystemZ::ADDR64BitRegClass);
6839 Register OrigVal = MRI.createVirtualRegister(RC);
6840 Register OldVal = MRI.createVirtualRegister(RC);
6842 MRI.createVirtualRegister(RC) : Src2.getReg());
6843 Register RotatedOldVal = (IsSubWord ? MRI.createVirtualRegister(RC) : OldVal);
6844 Register RotatedNewVal = (IsSubWord ? MRI.createVirtualRegister(RC) : NewVal);
6876 Register Tmp = MRI.createVirtualRegister(RC);
6885 Register Tmp2 = MRI.createVirtualRegister(RC);
6957 Register OrigVal = MRI.createVirtualRegister(RC);
6958 Register OldVal = MRI.createVirtualRegister(RC);
6959 Register NewVal = MRI.createVirtualRegister(RC);
6960 Register RotatedOldVal = (IsSubWord ? MRI.createVirtualRegister(RC) : OldVal);
6961 Register RotatedAltVal = (IsSubWord ? MRI.createVirtualRegister(RC) : Src2);
6962 Register RotatedNewVal = (IsSubWord ? MRI.createVirtualRegister(RC) : NewVal);
7066 Register OrigOldVal = MRI.createVirtualRegister(RC);
7067 Register OldVal = MRI.createVirtualRegister(RC);
7068 Register CmpVal = MRI.createVirtualRegister(RC);
7069 Register SwapVal = MRI.createVirtualRegister(RC);
7070 Register StoreVal = MRI.createVirtualRegister(RC);
7071 Register RetryOldVal = MRI.createVirtualRegister(RC);
7072 Register RetryCmpVal = MRI.createVirtualRegister(RC);
7073 Register RetrySwapVal = MRI.createVirtualRegister(RC);
7175 Register Tmp1 = MRI.createVirtualRegister(&SystemZ::GR128BitRegClass);
7176 Register Tmp2 = MRI.createVirtualRegister(&SystemZ::GR128BitRegClass);
7202 Register In128 = MRI.createVirtualRegister(&SystemZ::GR128BitRegClass);
7206 Register NewIn128 = MRI.createVirtualRegister(&SystemZ::GR128BitRegClass);
7207 Register Zero64 = MRI.createVirtualRegister(&SystemZ::GR64BitRegClass);
7251 Register ThisSrcReg = MRI.createVirtualRegister(RC);
7253 MRI.createVirtualRegister(RC));
7254 Register NextSrcReg = MRI.createVirtualRegister(RC);
7256 MRI.createVirtualRegister(RC));
7259 Register ThisCountReg = MRI.createVirtualRegister(RC);
7260 Register NextCountReg = MRI.createVirtualRegister(RC);
7351 Register Reg = MRI.createVirtualRegister(&SystemZ::ADDR64BitRegClass);
7360 Register Reg = MRI.createVirtualRegister(&SystemZ::ADDR64BitRegClass);
7416 uint64_t This1Reg = MRI.createVirtualRegister(RC);
7417 uint64_t This2Reg = MRI.createVirtualRegister(RC);
7418 uint64_t End2Reg = MRI.createVirtualRegister(RC);
7521 Register DstReg = MRI->createVirtualRegister(RC);
lib/Target/SystemZ/SystemZInstrInfo.cpp 588 Register TReg = MRI.createVirtualRegister(&SystemZ::GR32BitRegClass);
589 Register FReg = MRI.createVirtualRegister(&SystemZ::GR32BitRegClass);
lib/Target/SystemZ/SystemZLDCleanup.cpp 135 *TLSBaseAddrReg = RegInfo.createVirtualRegister(&SystemZ::GR64BitRegClass);
lib/Target/SystemZ/SystemZRegisterInfo.cpp 302 MF.getRegInfo().createVirtualRegister(&SystemZ::ADDR64BitRegClass);
lib/Target/WebAssembly/WebAssemblyCFGStackify.cpp 968 Register ExnReg = MRI.createVirtualRegister(&WebAssembly::EXNREFRegClass);
lib/Target/WebAssembly/WebAssemblyExplicitLocals.cpp 247 Register NewReg = MRI.createVirtualRegister(RC);
276 Register NewReg = MRI.createVirtualRegister(RC);
348 Register NewReg = MRI.createVirtualRegister(RC);
lib/Target/WebAssembly/WebAssemblyFixIrreducibleControlFlow.cpp 362 Register Reg = MRI.createVirtualRegister(&WebAssembly::I32RegClass);
lib/Target/WebAssembly/WebAssemblyFrameLowering.cpp 176 SPReg = MRI.createVirtualRegister(PtrRC);
186 Register BasePtr = MRI.createVirtualRegister(PtrRC);
193 Register OffsetReg = MRI.createVirtualRegister(PtrRC);
202 Register BitmaskReg = MRI.createVirtualRegister(PtrRC);
247 Register OffsetReg = MRI.createVirtualRegister(PtrRC);
252 SPReg = MRI.createVirtualRegister(PtrRC);
lib/Target/WebAssembly/WebAssemblyISelLowering.cpp 375 Tmp0 = MRI.createVirtualRegister(MRI.getRegClass(InReg));
376 Tmp1 = MRI.createVirtualRegister(MRI.getRegClass(InReg));
377 CmpReg = MRI.createVirtualRegister(&WebAssembly::I32RegClass);
378 EqzReg = MRI.createVirtualRegister(&WebAssembly::I32RegClass);
379 FalseReg = MRI.createVirtualRegister(MRI.getRegClass(OutReg));
380 TrueReg = MRI.createVirtualRegister(MRI.getRegClass(OutReg));
396 Tmp1 = MRI.createVirtualRegister(MRI.getRegClass(InReg));
398 MRI.createVirtualRegister(&WebAssembly::I32RegClass);
399 Register AndReg = MRI.createVirtualRegister(&WebAssembly::I32RegClass);
928 MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrVT));
lib/Target/WebAssembly/WebAssemblyLateEHPrepare.cpp 135 Register DstReg = MRI.createVirtualRegister(&WebAssembly::EXNREFRegClass);
344 Register Reg = MRI.createVirtualRegister(&WebAssembly::I32RegClass);
lib/Target/WebAssembly/WebAssemblyLowerBrUnless.cpp 191 Register Tmp = MRI.createVirtualRegister(&WebAssembly::I32RegClass);
lib/Target/WebAssembly/WebAssemblyPeephole.cpp 66 Register NewReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg));
120 Register NewReg = MRI.createVirtualRegister(RegClass);
lib/Target/WebAssembly/WebAssemblyRegStackify.cpp 123 Register TempReg = MRI.createVirtualRegister(&WebAssembly::I32RegClass);
502 Register NewReg = MRI.createVirtualRegister(MRI.getRegClass(Reg));
538 Register NewReg = MRI.createVirtualRegister(MRI.getRegClass(Reg));
610 Register TeeReg = MRI.createVirtualRegister(RegClass);
611 Register DefReg = MRI.createVirtualRegister(RegClass);
lib/Target/WebAssembly/WebAssemblyRegisterInfo.cpp 120 Register OffsetOp = MRI.createVirtualRegister(PtrRC);
124 FIRegOperand = MRI.createVirtualRegister(PtrRC);
lib/Target/WebAssembly/WebAssemblyReplacePhysRegs.cpp 92 VReg = MRI.createVirtualRegister(RC);
lib/Target/X86/X86AvoidStoreForwardingBlocks.cpp 394 Register Reg1 = MRI->createVirtualRegister(
lib/Target/X86/X86CallFrameOptimization.cpp 542 Register UndefReg = MRI->createVirtualRegister(&X86::GR64RegClass);
543 Reg = MRI->createVirtualRegister(&X86::GR64RegClass);
lib/Target/X86/X86CmovConversion.cpp 756 Register TmpReg = MRI->createVirtualRegister(RC);
lib/Target/X86/X86DomainReassignment.cpp 185 Register Reg = MRI->createVirtualRegister(
lib/Target/X86/X86FixupSetCC.cpp 139 Register ZeroReg = MRI->createVirtualRegister(RC);
140 Register InsertReg = MRI->createVirtualRegister(RC);
lib/Target/X86/X86FlagsCopyLowering.cpp 743 Register Reg = MRI->createVirtualRegister(PromoteRC);
817 Register TmpReg = MRI->createVirtualRegister(PromoteRC);
934 NewReg = MRI->createVirtualRegister(&X86::GR32RegClass);
943 NewReg = MRI->createVirtualRegister(&SetBRC);
978 Register ZeroReg = MRI->createVirtualRegister(&X86::GR32RegClass);
1003 Register ResultReg = MRI->createVirtualRegister(&SetBRC);
lib/Target/X86/X86FrameLowering.cpp 588 : MRI.createVirtualRegister(RegClass),
590 : MRI.createVirtualRegister(RegClass),
592 : MRI.createVirtualRegister(RegClass),
594 : MRI.createVirtualRegister(RegClass),
596 : MRI.createVirtualRegister(RegClass),
598 : MRI.createVirtualRegister(RegClass),
600 : MRI.createVirtualRegister(RegClass),
602 : MRI.createVirtualRegister(RegClass),
604 : MRI.createVirtualRegister(RegClass);
lib/Target/X86/X86ISelLowering.cpp 3328 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
3477 FR.VReg = MF.getRegInfo().createVirtualRegister(getRegClassFor(FR.VT));
22245 Register Vreg = MRI.createVirtualRegister(AddrRegClass);
29214 Register mainDstReg = MRI.createVirtualRegister(RC);
29215 Register fallDstReg = MRI.createVirtualRegister(RC);
29351 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
29352 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
29380 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
29405 Register RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
29415 Register OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
29427 Register NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
29452 Register OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
29466 Register TmpReg = MRI.createVirtualRegister(AddrRegClass);
29483 Register NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
30052 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
30053 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
30054 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
30055 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
30437 Register ZReg = MRI.createVirtualRegister(PtrRC);
30445 Register SSPCopyReg = MRI.createVirtualRegister(PtrRC);
30489 Register mainDstReg = MRI.createVirtualRegister(RC);
30490 Register restoreDstReg = MRI.createVirtualRegister(RC);
30541 LabelReg = MRI.createVirtualRegister(PtrRC);
30687 Register ZReg = MRI.createVirtualRegister(PtrRC);
30695 Register SSPCopyReg = MRI.createVirtualRegister(PtrRC);
30710 Register PrevSSPReg = MRI.createVirtualRegister(PtrRC);
30728 Register SspSubReg = MRI.createVirtualRegister(PtrRC);
30742 Register SspFirstShrReg = MRI.createVirtualRegister(PtrRC);
30752 Register SspSecondShrReg = MRI.createVirtualRegister(PtrRC);
30764 Register SspAfterShlReg = MRI.createVirtualRegister(PtrRC);
30769 Register Value128InReg = MRI.createVirtualRegister(PtrRC);
30777 Register DecReg = MRI.createVirtualRegister(PtrRC);
30778 Register CounterReg = MRI.createVirtualRegister(PtrRC);
30818 Register Tmp = MRI.createVirtualRegister(RC);
30906 VR = MRI->createVirtualRegister(TRC);
31032 Register IReg = MRI->createVirtualRegister(&X86::GR32_NOSPRegClass);
31041 Register BReg = MRI->createVirtualRegister(&X86::GR64RegClass);
31042 Register IReg64 = MRI->createVirtualRegister(&X86::GR64_NOSPRegClass);
31068 Register OReg = MRI->createVirtualRegister(&X86::GR32RegClass);
31069 Register OReg64 = MRI->createVirtualRegister(&X86::GR64RegClass);
31070 Register TReg = MRI->createVirtualRegister(&X86::GR64RegClass);
31264 Register OldCW = MF->getRegInfo().createVirtualRegister(&X86::GR32RegClass);
31269 Register NewCW = MF->getRegInfo().createVirtualRegister(&X86::GR32RegClass);
31275 MF->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
31379 Register computedAddrVReg = MRI.createVirtualRegister(AddrRegClass);
46192 Register NewVR = MRI->createVirtualRegister(RC);
lib/Target/X86/X86InstrInfo.cpp 743 NewSrc = MF.getRegInfo().createVirtualRegister(RC);
780 Register InRegLEA = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
781 Register OutRegLEA = RegInfo.createVirtualRegister(&X86::GR32RegClass);
845 InRegLEA2 = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
847 InRegLEA2 = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
6029 GlobalBaseReg = RegInfo.createVirtualRegister(
7768 PC = RegInfo.createVirtualRegister(&X86::GR32RegClass);
7789 Register PBReg = RegInfo.createVirtualRegister(&X86::GR64RegClass);
7790 Register GOTReg = RegInfo.createVirtualRegister(&X86::GR64RegClass);
7927 *TLSBaseAddrReg = RegInfo.createVirtualRegister(is64Bit
lib/Target/X86/X86InstructionSelector.cpp 252 Register ExtSrc = MRI.createVirtualRegister(DstRC);
824 TransitRegFrom = MRI.createVirtualRegister(
862 DefReg = MRI.createVirtualRegister(getRegClass(DstTy, DstReg, MRI));
1037 Register FlagReg1 = MRI.createVirtualRegister(&X86::GR8RegClass);
1038 Register FlagReg2 = MRI.createVirtualRegister(&X86::GR8RegClass);
1452 Register AddrReg = MRI.createVirtualRegister(&X86::GR64RegClass);
1652 Register Zero32 = MRI.createVirtualRegister(&X86::GR32RegClass);
1690 Register SourceSuperReg = MRI.createVirtualRegister(&X86::GR16RegClass);
1691 Register ResultSuperReg = MRI.createVirtualRegister(&X86::GR16RegClass);
lib/Target/X86/X86SpeculativeLoadHardening.cpp 446 PS->PoisonReg = MRI->createVirtualRegister(PS->RC);
479 PS->InitialReg = MRI->createVirtualRegister(PS->RC);
480 Register PredStateSubReg = MRI->createVirtualRegister(&X86::GR32RegClass);
753 Register UpdatedStateReg = MRI->createVirtualRegister(PS->RC);
910 Register Reg = MRI->createVirtualRegister(UnfoldedRC);
963 TargetAddrSSA.Initialize(MRI->createVirtualRegister(&X86::GR64RegClass));
1105 Register TargetReg = MRI->createVirtualRegister(&X86::GR64RegClass);
1156 Register AddrReg = MRI->createVirtualRegister(&X86::GR64RegClass);
1178 Register UpdatedStateReg = MRI->createVirtualRegister(PS->RC);
1881 Register Reg = MRI->createVirtualRegister(&X86::GR32RegClass);
1908 Register TmpReg = MRI->createVirtualRegister(PS->RC);
1928 Register PredStateReg = MRI->createVirtualRegister(PS->RC);
1929 Register TmpReg = MRI->createVirtualRegister(PS->RC);
2036 Register TmpReg = MRI->createVirtualRegister(OpRC);
2048 Register VStateReg = MRI->createVirtualRegister(&X86::VR128RegClass);
2057 Register VBStateReg = MRI->createVirtualRegister(OpRC);
2087 Register VStateReg = MRI->createVirtualRegister(OpRC);
2295 Register NarrowStateReg = MRI->createVirtualRegister(RC);
2305 Register NewReg = MRI->createVirtualRegister(RC);
2341 Register UnhardenedReg = MRI->createVirtualRegister(DefRC);
2496 ExpectedRetAddrReg = MRI->createVirtualRegister(AddrRC);
2519 ExpectedRetAddrReg = MRI->createVirtualRegister(AddrRC);
2543 Register ActualRetAddrReg = MRI->createVirtualRegister(AddrRC);
2560 Register UpdatedStateReg = MRI->createVirtualRegister(PS->RC);
lib/Target/XCore/XCoreISelLowering.cpp 1312 Register VReg = RegInfo.createVirtualRegister(&XCore::GRRegsRegClass);
1363 Register VReg = RegInfo.createVirtualRegister(&XCore::GRRegsRegClass);