reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

include/llvm/CodeGen/MachineInstr.h

  450       if (MO.isDef() && MO.isImplicit())

include/llvm/CodeGen/MachineInstrBuilder.h

  498   return getDefRegState(RegOp.isDef()) | getImplRegState(RegOp.isImplicit()) |

lib/CodeGen/AggressiveAntiDepBreaker.cpp

  232   if (!MO.isReg() || !MO.isImplicit())
  245   return(Op && Op->isImplicit());
  880           if (!AntiDepOp || AntiDepOp->isImplicit()) {

lib/CodeGen/AsmPrinter/DwarfDebug.cpp

  594             if (MO.isImplicit())

lib/CodeGen/GlobalISel/CSEInfo.cpp

  348     assert(!MO.isImplicit() && "Unhandled case");

lib/CodeGen/InlineSpiller.cpp

  815     if (MO.isImplicit()) {
  884       if (!MO.isReg() || !MO.isImplicit())
 1523         if (MO.isReg() && MO.isImplicit() && MO.isDef() && !MO.isDead())

lib/CodeGen/MIRParser/MIParser.cpp

 1076   assert(MO.isImplicit());

lib/CodeGen/MIRPrinter.cpp

  720          !MI.getOperand(I).isImplicit();

lib/CodeGen/MachineCSE.cpp

  603       if (MO.isImplicit() && !MO.isDead() && CSMI->getOperand(i).isDead())
  608       if (MO.isImplicit() && !MO.isDead() && OldReg == NewReg)

lib/CodeGen/MachineCopyPropagation.cpp

  372     if (&MIUse != &Use && MIUse.isReg() && MIUse.isImplicit() &&
  397         MOUse.isImplicit())

lib/CodeGen/MachineInstr.cpp

  219   bool isImpReg = Op.isReg() && Op.isImplicit();
  221     while (OpNo && Operands[OpNo-1].isReg() && Operands[OpNo-1].isImplicit()) {
  711     if (MO.isReg() && MO.isImplicit())
  725     if (!MO.isReg() || !MO.isDef() || MO.isImplicit())
  934     if (MO.isReg() && MO.isUse() && MO.isImplicit() && MO.getReg() == Reg)
 1403     if ((MO.isReg() && MO.isImplicit()) || MO.isRegMask())
 1501     if (!MO.isReg() || !MO.isDef() || MO.isImplicit())
 1830     if (getOperand(OpIdx).isImplicit() &&
 1895     if (getOperand(OpIdx).isImplicit() &&

lib/CodeGen/MachineLICM.cpp

  440     if (MO.isImplicit()) {
  852     if (!MO.isReg() || MO.isImplicit())
 1225     if (!MO.isReg() || MO.isImplicit())

lib/CodeGen/MachineOperand.cpp

  752     if (isImplicit())

lib/CodeGen/MachineVerifier.cpp

  889     if (!MO.isReg() || !MO.isImplicit())
 1607     else if (MO->isImplicit())
 1617       if (MO->isImplicit())
 1641     if (MO->isReg() && !MO->isImplicit() && !MI->isVariadic() && MO->getReg())
 1669           if (!OtherMO.isImplicit())
 2022             if (!MOP.isReg() || !MOP.isImplicit())
 2219     if (MODef.isTied() || MODef.isImplicit() || MODef.isInternalRead() ||
 2232       if (MO0.isImplicit() || MO0.isInternalRead() || MO0.isEarlyClobber() ||

lib/CodeGen/ModuloSchedule.cpp

 1320       if (!MO.isReg() || MO.getReg().isPhysical() || MO.isImplicit())

lib/CodeGen/PeepholeOptimizer.cpp

 1359     if (MO.isImplicit() && MO.isDead())
 1851     if (MO.isImplicit() && MO.isDead())
 2054           Def->getOperand(DefIdx).isImplicit()) &&

lib/CodeGen/RegAllocFast.cpp

 1066                     (MO.isImplicit() || MO.isDead()) ? regFree : regReserved);

lib/CodeGen/RegisterCoalescer.cpp

 1318       assert(MO.isImplicit() && "No explicit operands after implicit operands.");
 1338       assert(MO.isImplicit() && MO.isDead() &&

lib/CodeGen/SelectionDAG/InstrEmitter.cpp

  348            MIB->getOperand(Idx-1).isImplicit())

lib/CodeGen/StackMaps.cpp

   56                      !MI->getOperand(0).isImplicit()) {
   61          !MI->getOperand(CheckStartIdx).isImplicit())
   78            MI->getOperand(ScratchIdx).isImplicit() &&
  148     if (MOI->isImplicit())

lib/CodeGen/TargetSchedule.cpp

  241   if (SCDesc->isValid() && !DefMI->getOperand(DefOperIdx).isImplicit()

lib/CodeGen/TwoAddressInstructionPass.cpp

  240     if (MO.isImplicit())

lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp

  152       assert(!MO.isImplicit() && "Unexpected implicit def!");

lib/Target/AArch64/AArch64InstrInfo.cpp

 5410     if (MOP.isReg() && !MOP.isImplicit() &&

lib/Target/AArch64/AArch64MCInstLower.cpp

  259     if (MO.isImplicit())

lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp

  595     if (!UseOp.isImplicit() || !TII.isFLAT(*UseOp.getParent()))

lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp

  229     return MachineOperand::CreateReg(DstReg, MO.isDef(), MO.isImplicit(),

lib/Target/AMDGPU/GCNNSAReassign.cpp

  203         if (U.isImplicit())

lib/Target/AMDGPU/GCNRegBankReassign.cpp

  434     if (U.isImplicit())

lib/Target/AMDGPU/SIFoldOperands.cpp

  554     if (UseOp.isImplicit() || UseOp.getSubReg() != AMDGPU::NoSubRegister)
  825         UseOp.isImplicit() ||

lib/Target/AMDGPU/SIFormMemoryClauses.cpp

  137   if (MO.isImplicit())

lib/Target/AMDGPU/SIInstrInfo.cpp

 3122   if (MO.isImplicit()) {
 3378       if (!TiedMO.isReg() || !TiedMO.isImplicit() || !TiedMO.isUse()) {

lib/Target/AMDGPU/SIShrinkInstructions.cpp

  177     if ((MO.isReg() && MO.isImplicit()) || MO.isRegMask())
  281           MI.getOperand(i).isImplicit()) {

lib/Target/ARC/ARCMCInstLower.cpp

   85     if (MO.isImplicit())

lib/Target/ARM/ARMAsmPrinter.cpp

 1123         if (MO.isImplicit())

lib/Target/ARM/ARMBaseInstrInfo.cpp

 2459     if (MO.isReg() && !MO.isImplicit() &&
 4320   if (DefMO.isImplicit() || UseMI.getOperand(UseIdx).isImplicit())
 4320   if (DefMO.isImplicit() || UseMI.getOperand(UseIdx).isImplicit())
 4749       if (MI.getOperand(i).isImplicit() ||

lib/Target/ARM/ARMLoadStoreOptimizer.cpp

  876         assert(MO.isImplicit());

lib/Target/ARM/ARMMCInstLower.cpp

   78     if (MO.isImplicit())

lib/Target/ARM/Thumb1FrameLowering.cpp

  642       if (MO.isReg() && (MO.isImplicit() || MO.isDef()))
  757       if (MO.isReg() && (MO.isImplicit() || MO.isDef()) &&
  760         if (!MO.isImplicit())

lib/Target/ARM/Thumb2SizeReduction.cpp

  381     if (!MO.isReg() || MO.isImplicit())
  952     if (MO.isReg() && MO.isImplicit() && MO.getReg() == ARM::CPSR)

lib/Target/AVR/AVRMCInstLower.cpp

   74       if (MO.isImplicit())

lib/Target/BPF/BPFMCInstLower.cpp

   60       if (MO.isImplicit())

lib/Target/Hexagon/HexagonConstPropagation.cpp

 2793       if (!MO.isReg() || !MO.isUse() || MO.isImplicit())
 2814           if (!MO.isReg() || !MO.isUse() || MO.isImplicit())

lib/Target/Hexagon/HexagonExpandCondsets.cpp

  889     if (!MO.isReg() || !MO.isImplicit())

lib/Target/Hexagon/HexagonGenMux.cpp

  172     if (!MO.isReg() || MO.isImplicit())

lib/Target/Hexagon/HexagonHardwareLoops.cpp

 1723       if (MO.isImplicit())

lib/Target/Hexagon/HexagonHazardRecognizer.cpp

  116     if (MO.isReg() && MO.isDef() && !MO.isImplicit())

lib/Target/Hexagon/HexagonInstrInfo.cpp

 1583     if (!Op.isReg() || !Op.isDef() || Op.isImplicit())
 3101     if (MO.isReg() && MO.isDef() && MO.isImplicit() && (MO.getReg() == PredReg))
 4104     if (DefMO.isImplicit()) {
 4115     if (UseMO.isImplicit()) {
 4272   if (Cond[1].isImplicit())

lib/Target/Hexagon/HexagonMCInstLower.cpp

  125       if (MO.isImplicit())

lib/Target/Hexagon/HexagonOptAddrMode.cpp

  423   BaseOp.setImplicit(AddRegOp.isImplicit());

lib/Target/Hexagon/HexagonSplitDouble.cpp

  621     auto CO = MachineOperand::CreateReg(R, Op.isDef(), Op.isImplicit(), isKill,

lib/Target/Hexagon/HexagonVLIWPacketizer.cpp

  312       if (MO.isReg() && MO.getReg() == DepReg && !MO.isImplicit())
  790     if (!MO.isReg() || !MO.isDef() || !MO.isImplicit())
  803     if (MO.isReg() && MO.isUse() && MO.isImplicit() && MO.getReg() == DepReg)
  833     if (!MO.isReg() || MO.getReg() != DepReg || !MO.isImplicit())

lib/Target/Hexagon/RDFGraph.cpp

 1292     if (!Op.isReg() || !Op.isDef() || Op.isImplicit())
 1337     if (!Op.isReg() || !Op.isDef() || !Op.isImplicit())

lib/Target/Hexagon/RDFLiveness.cpp

  890       if (!Op.isReg() || !Op.isDef() || Op.isImplicit())

lib/Target/Lanai/LanaiMCInstLower.cpp

  103       if (MO.isImplicit())

lib/Target/MSP430/MSP430MCInstLower.cpp

  128       if (MO.isImplicit()) continue;

lib/Target/Mips/MipsMCInstLower.cpp

  187     if (MO.isImplicit()) break;

lib/Target/Mips/MipsSEInstrInfo.cpp

  690     if (MO.isImplicit())

lib/Target/PowerPC/PPCInstrInfo.cpp

  162     if (!MO.isReg() || !MO.isDef() || MO.isImplicit())
 2286     if (MO.isImplicit())
 2395       if (MO.isReg() && MO.isUse() && !MO.isImplicit()) {

lib/Target/RISCV/RISCVMCInstLower.cpp

   97     if (MO.isImplicit())

lib/Target/Sparc/DelaySlotFiller.cpp

  335       if (MO.isImplicit() && MI->getOpcode() == SP::RETL)

lib/Target/Sparc/SparcMCInstLower.cpp

   73     if (MO.isImplicit())

lib/Target/SystemZ/SystemZMCInstLower.cpp

   99     if (!MO.isReg() || !MO.isImplicit())

lib/Target/WebAssembly/WebAssemblyMCInstLower.cpp

  224       if (MO.isImplicit())

lib/Target/WebAssembly/WebAssemblyRegStackify.cpp

  812         assert(!Op.isImplicit() &&

lib/Target/WebAssembly/WebAssemblyReplacePhysRegs.cpp

   90       if (!MO.isImplicit()) {

lib/Target/WebAssembly/WebAssemblyUtilities.cpp

   33   if (!MO.isReg() || MO.isImplicit() || !MO.isDef())

lib/Target/X86/X86FloatingPoint.cpp

  985         assert(MO.isDef() && MO.isImplicit());

lib/Target/X86/X86InstrInfo.cpp

 5488     else if (Op.isReg() && Op.isImplicit())

lib/Target/X86/X86MCInstLower.cpp

  406     if (MO.isImplicit())

lib/Target/X86/X86SpeculativeLoadHardening.cpp

  486     assert(ZeroEFLAGSDefOp && ZeroEFLAGSDefOp->isImplicit() &&

lib/Target/XCore/XCoreMCInstLower.cpp

   85       if (MO.isImplicit()) break;