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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
include/llvm/CodeGen/LiveIntervals.h 427 removeRegUnit(*Units);
include/llvm/CodeGen/LivePhysRegs.h 84 LiveRegs.insert(*SubRegs);
include/llvm/CodeGen/LiveRegUnits.h 89 Units.set(*Unit);
105 Units.reset(*Unit);
119 if (Units.test(*Unit))
include/llvm/CodeGen/TargetRegisterInfo.h 389 if (*RUA == *RUB) return true;
389 if (*RUA == *RUB) return true;
390 if (*RUA < *RUB) ++RUA;
390 if (*RUA < *RUB) ++RUA;
399 if (*Units == RegUnit)
include/llvm/MC/MCRegisterInfo.h 504 return *SRIter;
541 if (*I == RegB)
605 return std::make_pair(*RUIter, *MaskListIter);
678 for (RRI = MCRegUnitRootIterator(*RI, MCRI); RRI.isValid(); ++RRI) {
680 if (!(!IncludeSelf && Reg == *SI))
691 return *SI;
707 RRI = MCRegUnitRootIterator(*RI, MCRI);
715 while (!IncludeSelf && isValid() && *SI == Reg);
lib/CodeGen/AggressiveAntiDepBreaker.cpp 258 PassthruRegs.insert(*SubRegs);
335 unsigned SubregReg = *SubRegs;
lib/CodeGen/AsmPrinter/DwarfExpression.cpp 120 Reg = TRI.getDwarfRegNum(*SR, false);
122 unsigned Idx = TRI.getSubRegIndex(*SR, MachineReg);
145 unsigned Idx = TRI.getSubRegIndex(MachineReg, *SR);
148 Reg = TRI.getDwarfRegNum(*SR, false);
lib/CodeGen/BranchFolding.cpp 1957 Uses.erase(*SubRegs); // Use sub-registers to be conservative
lib/CodeGen/BreakFalseDeps.cpp 117 for (MCRegUnitRootIterator Root(*Unit, TRI); Root.isValid(); ++Root) {
lib/CodeGen/CriticalAntiDepBreaker.cpp 234 KeepRegs.set(*SubRegs);
238 KeepRegs.set(*SuperRegs);
246 KeepRegs.set(*SubRegs);
290 unsigned SubregReg = *SRI;
300 Classes[*SR] = reinterpret_cast<TargetRegisterClass *>(-1);
lib/CodeGen/DeadMachineInstructionElim.cpp 150 LivePhysRegs.reset(*SR);
lib/CodeGen/EarlyIfConversion.cpp 267 ClobberedRegUnits.set(*Units);
388 LiveRegUnits.erase(*Units);
397 if (ClobberedRegUnits.test(*Units))
398 LiveRegUnits.insert(*Units);
lib/CodeGen/IfConversion.cpp 1515 if (!LiveBeforeMI.count(*S))
1958 ExtUses.insert(*SubRegs);
1966 RedefsByFalse.insert(*SubRegs);
lib/CodeGen/InterferenceCache.cpp 101 RegUnits[i].VirtTag = LIUArray[*Units].getTag();
118 RegUnits.push_back(LIUArray[*Units]);
119 RegUnits.back().Fixed = &LIS->getRegUnit(*Units);
129 if (LIUArray[*Units].changedSince(RegUnits[i].VirtTag))
lib/CodeGen/LiveIntervals.cpp 277 unsigned Reg = *Super;
296 unsigned Reg = *Super;
329 unsigned Unit = *Units;
703 const LiveRange &RURange = getRegUnit(*Unit);
1011 if (LiveRange *LR = getRegUnitLI(*Units))
1012 updateRange(*LR, *Units, LaneBitmask::getNone());
1628 if (LiveRange *LR = getCachedRegUnit(*Unit))
lib/CodeGen/LivePhysRegs.cpp 268 if (LiveRegs.contains(*SReg) && !MRI.isReserved(*SReg)) {
268 if (LiveRegs.contains(*SReg) && !MRI.isReserved(*SReg)) {
lib/CodeGen/LiveRegMatrix.cpp 96 if (Func(*Units, VRegInterval))
139 if (!Matrix[*Unit].empty())
218 if (query(LR, *Units).checkInterference())
lib/CodeGen/LiveVariables.cpp 198 unsigned SubReg = *SubRegs;
222 PartDefRegs.insert(*SubRegs);
252 unsigned SubReg = *SubRegs;
264 Processed.insert(*SS);
276 PhysRegUse[*SubRegs] = &MI;
291 unsigned SubReg = *SubRegs;
340 unsigned SubReg = *SubRegs;
355 PartUses.insert(*SS);
371 unsigned SubReg = *SubRegs;
392 PhysRegUse[*SS] = LastRefOrPartRef;
395 PartUses.erase(*SS);
437 if ((PhysRegDef[*SR] || PhysRegUse[*SR]) && MO.clobbersPhysReg(*SR))
437 if ((PhysRegDef[*SR] || PhysRegUse[*SR]) && MO.clobbersPhysReg(*SR))
437 if ((PhysRegDef[*SR] || PhysRegUse[*SR]) && MO.clobbersPhysReg(*SR))
438 Super = *SR;
450 Live.insert(*SubRegs);
453 unsigned SubReg = *SubRegs;
465 Live.insert(*SS);
475 unsigned SubReg = *SubRegs;
493 unsigned SubReg = *SubRegs;
lib/CodeGen/MachineCopyPropagation.cpp 93 auto CI = Copies.find(*RUI);
103 auto I = Copies.find(*RUI);
127 Copies[*RUI] = {MI, {}, true};
132 auto I = Copies.insert({*RUI, {nullptr, {}, false}});
159 findCopyForUnit(*RUI, TRI, /*MustBeAvailable=*/true);
246 if (MachineInstr *Copy = Tracker.findCopyForUnit(*RUI, *TRI)) {
lib/CodeGen/MachineFrameInfo.cpp 131 BV.reset(*S);
lib/CodeGen/MachineInstrBundle.cpp 199 unsigned SubReg = *SubRegs;
lib/CodeGen/MachinePipeliner.cpp 1561 Uses.insert(*Units);
1574 if (!Uses.count(*Units))
1575 LiveOutRegs.push_back(RegisterMaskPair(*Units,
lib/CodeGen/MachineRegisterInfo.cpp 663 unsigned Reg = *Super;
lib/CodeGen/MachineSink.cpp 1170 SuccBB->removeLiveIn(*S);
1217 RegUnits.insert(*RI);
lib/CodeGen/MachineTraceMetrics.cpp 726 SparseSet<LiveRegUnit>::iterator I = RegUnits.find(*Units);
738 RegUnits.erase(*Units);
744 LiveRegUnit &LRU = RegUnits[*Units];
915 SparseSet<LiveRegUnit>::iterator I = RegUnits.find(*Units);
935 LiveRegUnit &LRU = RegUnits[*Units];
lib/CodeGen/MachineVerifier.cpp 127 RV.push_back(*SubRegs);
806 regsLive.insert(*SubRegs);
815 regsLive.insert(*SubRegs);
1961 if (MRI->isReservedRegUnit(*Units))
1963 if (const LiveRange *LR = LiveInts->getCachedRegUnit(*Units))
1964 checkLivenessAtUse(MO, MONum, UseIdx, *LR, *Units);
2010 if (regsLive.count(*SubRegs)) {
2030 if (*SubRegs == Reg) {
lib/CodeGen/ReachingDefAnalysis.cpp 46 LiveRegs[*Unit] = -1;
47 MBBReachingDefs[MBBNumber][*Unit].push_back(LiveRegs[*Unit]);
47 MBBReachingDefs[MBBNumber][*Unit].push_back(LiveRegs[*Unit]);
116 LiveRegs[*Unit] = CurInstr;
117 MBBReachingDefs[MBBNumber][*Unit].push_back(CurInstr);
182 for (int Def : MBBReachingDefs[MBBNumber][*Unit]) {
lib/CodeGen/RegAllocBasic.cpp 212 LiveIntervalUnion::Query &Q = Matrix->query(VirtReg, *Units);
lib/CodeGen/RegAllocFast.cpp 144 UsedInInstr.insert(*Units);
150 if (UsedInInstr.count(*Units))
lib/CodeGen/RegAllocGreedy.cpp 819 LiveIntervalUnion::Query subQ(VirtReg, Matrix->getLiveUnions()[*Units]);
894 LiveIntervalUnion::Query &Q = Matrix->query(VirtReg, *Units);
976 LiveIntervalUnion::Query &Q = Matrix->query(VirtReg, *Units);
1063 LiveIntervalUnion::Query &Q = Matrix->query(VirtReg, *Units);
2168 if (!Matrix->query(const_cast<LiveInterval&>(SA->getParent()), *Units)
2180 Matrix->getLiveUnions()[*Units] .find(StartIdx);
2203 const LiveRange &LR = LIS->getRegUnit(*Units);
2535 LiveIntervalUnion::Query &Q = Matrix->query(VirtReg, *Units);
lib/CodeGen/RegAllocPBQP.cpp 625 if (VRegLI.overlaps(LIS.getRegUnit(*Units))) {
lib/CodeGen/RegUsageInfoCollector.cpp 213 SavedRegs.set(*SR);
lib/CodeGen/RegisterCoalescer.cpp 1455 if (LiveRange *LR = LIS->getCachedRegUnit(*Units))
1470 if (LiveRange *LR = LIS->getCachedRegUnit(*Units))
1998 for (MCRegUnitRootIterator RI(*UI, TRI); RI.isValid(); ++RI) {
2002 if (RHS.overlaps(LIS->getRegUnit(*UI))) {
2003 LLVM_DEBUG(dbgs() << "\t\tInterference: " << printRegUnit(*UI, TRI)
2080 LiveRange &LR = LIS->getRegUnit(*UI);
lib/CodeGen/RegisterPressure.cpp 526 addRegLanes(RegUnits, RegisterMaskPair(*Units, LaneBitmask::getAll()));
561 addRegLanes(RegUnits, RegisterMaskPair(*Units, LaneBitmask::getAll()));
lib/CodeGen/RegisterScavenging.cpp 101 BV.set(*RUI);
106 BV.reset(*RUI);
224 if (isRegUsed(*SubRegs)) {
230 if (isRegUsed(*SR)) {
lib/CodeGen/ScheduleDAGInstrs.cpp 334 if (Uses.contains(*SubReg))
335 Uses.eraseAll(*SubReg);
337 Defs.eraseAll(*SubReg);
lib/CodeGen/StackMaps.cpp 95 RegNum = TRI->getDwarfRegNum(*SR, false);
lib/CodeGen/TargetRegisterInfo.cpp 61 RegisterSet.set(*AI);
72 if (!RegisterSet[*SR] && !is_contained(Exceptions, Reg)) {
73 dbgs() << "Error: Super register " << printReg(*SR, this)
81 Checked.set(*SR);
lib/CodeGen/VirtRegMap.cpp 476 const LiveRange &UnitRange = LIS->getRegUnit(*Unit);
lib/MC/MCRegisterInfo.cpp 27 if (RC->contains(*Supers) && Reg == getSubReg(*Supers, SubIdx))
27 if (RC->contains(*Supers) && Reg == getSubReg(*Supers, SubIdx))
28 return *Supers;
40 return *Subs;
51 if (*Subs == SubReg)
lib/MCA/HardwareUnits/RegisterFile.cpp 105 RegisterRenamingInfo &OtherEntry = RegisterMappings[*I].second;
108 MRI.isSuperRegister(*I, OtherEntry.RenameAs))) {
202 ZeroRegisters.setBit(*I);
206 ZeroRegisters.clearBit(*I);
216 RegisterMappings[*I].first = Write;
217 RegisterMappings[*I].second.AliasRegID = 0U;
232 RegisterMappings[*I].first = Write;
233 RegisterMappings[*I].second.AliasRegID = 0U;
237 ZeroRegisters.setBit(*I);
239 ZeroRegisters.clearBit(*I);
276 WriteRef &OtherWR = RegisterMappings[*I].first;
285 WriteRef &OtherWR = RegisterMappings[*I].first;
344 RegisterMappings[*I].second.AliasRegID = AliasedReg;
374 const WriteRef &WR = RegisterMappings[*I].first;
lib/Target/AArch64/AArch64RegisterInfo.cpp 164 UpdatedMask[*SubReg / 32] |= 1u << (*SubReg % 32);
164 UpdatedMask[*SubReg / 32] |= 1u << (*SubReg % 32);
lib/Target/AMDGPU/GCNHazardRecognizer.cpp 471 BV.set(*RUI);
lib/Target/AMDGPU/SIRegisterInfo.cpp 43 const int *PSets = getRegUnitPressureSets(*U);
1895 LiveRange &LR = LIS->getRegUnit(*Units);
lib/Target/AMDGPU/SIWholeQuadMode.cpp 286 LiveRange &LR = LIS->getRegUnit(*RegUnit);
584 LiveRange &LR = LIS->getRegUnit(*MCRegUnitIterator(AMDGPU::SCC, TRI));
936 LIS->removeRegUnit(*MCRegUnitIterator(AMDGPU::SCC, TRI));
lib/Target/ARM/ARMAsmPrinter.cpp 283 if (!ARM::DPRRegClass.contains(*SR))
285 bool Lane0 = TRI->getSubReg(*SR, ARM::ssub_0) == Reg;
286 O << ARMInstPrinter::getRegisterName(*SR) << (Lane0 ? "[0]" : "[1]");
lib/Target/ARM/ARMBaseRegisterInfo.cpp 213 if (Reserved.test(*SI))
294 if (ARM::GPRPairRegClass.contains(*Supers))
295 return RI->getSubReg(*Supers, Odd ? ARM::gsub_1 : ARM::gsub_0);
lib/Target/ARM/Thumb2ITBlockPass.cpp 103 UsesDefs.insert(*Subreg);
lib/Target/BPF/BPFMIChecking.cpp 150 if (std::find(search_begin, search_end, *SR) == search_end)
lib/Target/Hexagon/HexagonAsmPrinter.cpp 70 unsigned Pair = *SR;
lib/Target/Hexagon/HexagonBlockRanges.cpp 276 SRs.insert({*I, 0});
lib/Target/Hexagon/HexagonCopyToCombine.cpp 448 LastDef[*SubRegs] = &MI;
lib/Target/Hexagon/HexagonFrameLowering.cpp 253 if (*SubRegs > RegNo)
254 RegNo = *SubRegs;
256 if (!RegNo || *SubRegs < RegNo)
257 RegNo = *SubRegs;
312 if (CSR[*S])
438 CSR[*S] = true;
1444 SRegs[*SR] = true;
1456 SRegs[*SR] = false;
1471 TmpSup[*SR] = true;
1476 if (!Reserved[*SR])
1495 if (!SRegs[*SR])
lib/Target/Hexagon/HexagonGenMux.cpp 148 SRs[*I] = true;
353 if (LPR.contains(*S))
lib/Target/Hexagon/HexagonInstrInfo.cpp 2108 if (RegB == *SubRegs)
2113 if (RegA == *SubRegs)
4106 int Idx = DefMI.findRegisterDefOperandIdx(*SR, false, false, &HRI);
4117 int Idx = UseMI.findRegisterUseOperandIdx(*SR, false, &HRI);
lib/Target/Hexagon/RDFLiveness.cpp 896 Live.reset(*SR);
914 Live.set(*SR);
lib/Target/Hexagon/RDFRegisters.cpp 91 PU.set(*U);
327 Regs.set(*S);
lib/Target/Mips/MCTargetDesc/MipsOptionRecord.cpp 79 unsigned CurrentSubReg = *SubRegIt;
lib/Target/PowerPC/PPCVSXFMAMutate.cpp 320 unsigned Unit = *Units;
lib/Target/SystemZ/SystemZInstrInfo.cpp 1013 LiveRange &CCLiveRange = LIS->getRegUnit(*CCUnit);
lib/Target/SystemZ/SystemZRegisterInfo.cpp 392 if (NewRC->contains(*SI)) {
393 PhysClobbered.set(*SI);
lib/Target/X86/X86ISelLowering.cpp 2845 RegMask[*SubRegs / 32] &= ~(1u << (*SubRegs % 32));
2845 RegMask[*SubRegs / 32] &= ~(1u << (*SubRegs % 32));
4076 RegMask[*SubRegs / 32] &= ~(1u << (*SubRegs % 32));
4076 RegMask[*SubRegs / 32] &= ~(1u << (*SubRegs % 32));
lib/Target/X86/X86RegisterInfo.cpp 529 Reserved.set(*I);
537 Reserved.set(*I);
543 Reserved.set(*I);
558 Reserved.set(*I);