reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

include/llvm/CodeGen/LivePhysRegs.h

   59     LiveRegs.setUniverse(TRI.getNumRegs());
   69     LiveRegs.setUniverse(TRI.getNumRegs());
   81     assert(Reg <= TRI->getNumRegs() && "Expected a physical register.");
   91     assert(Reg <= TRI->getNumRegs() && "Expected a physical register.");

lib/CodeGen/AggressiveAntiDepBreaker.cpp

  154   State = new AggressiveAntiDepState(TRI->getNumRegs(), BB);
  210   for (unsigned Reg = 0; Reg != TRI->getNumRegs(); ++Reg) {
  526   BitVector BV(TRI->getNumRegs(), false);
  800   for (unsigned Reg = 0; Reg < TRI->getNumRegs(); ++Reg) {
  807   BitVector RegAliases(TRI->getNumRegs());

lib/CodeGen/CallingConvLower.cpp

   37   UsedRegs.resize((TRI.getNumRegs()+31)/32);

lib/CodeGen/CriticalAntiDepBreaker.cpp

   49       Classes(TRI->getNumRegs(), nullptr), KillIndices(TRI->getNumRegs(), 0),
   49       Classes(TRI->getNumRegs(), nullptr), KillIndices(TRI->getNumRegs(), 0),
   50       DefIndices(TRI->getNumRegs(), 0), KeepRegs(TRI->getNumRegs(), false) {}
   50       DefIndices(TRI->getNumRegs(), 0), KeepRegs(TRI->getNumRegs(), false) {}
   56   for (unsigned i = 0, e = TRI->getNumRegs(); i != e; ++i) {
  119   for (unsigned Reg = 0; Reg != TRI->getNumRegs(); ++Reg) {
  265         for (unsigned i = 0, e = TRI->getNumRegs(); i != e; ++i)
  467     for (unsigned Reg = 0; Reg < TRI->getNumRegs(); ++Reg) {
  521   std::vector<unsigned> LastNewReg(TRI->getNumRegs(), 0);

lib/CodeGen/ExecutionDomainFix.cpp

  444     AliasMap.resize(TRI->getNumRegs());

lib/CodeGen/IfConversion.cpp

 1481   LiveBeforeMI.setUniverse(TRI->getNumRegs());

lib/CodeGen/InterferenceCache.cpp

   47   if (PhysRegEntriesCount == TRI->getNumRegs()) return;
   49   PhysRegEntriesCount = TRI->getNumRegs();

lib/CodeGen/LiveIntervals.cpp

  919         UsableRegs.resize(TRI->getNumRegs(), true);

lib/CodeGen/LiveVariables.cpp

  426   for (unsigned Reg = 1, NumRegs = TRI->getNumRegs(); Reg != NumRegs; ++Reg) {
  625   const unsigned NumRegs = TRI->getNumRegs();

lib/CodeGen/MIRParser/MIParser.cpp

  114   for (unsigned I = 0, E = TRI->getNumRegs(); I < E; ++I) {

lib/CodeGen/MIRPrinter.cpp

  250   for (int I = 0, E = TRI->getNumRegs(); I < E; I++) {

lib/CodeGen/MachineFrameInfo.cpp

  116   BitVector BV(TRI->getNumRegs());

lib/CodeGen/MachineFunction.cpp

  465   unsigned NumRegs = getSubtarget().getRegisterInfo()->getNumRegs();

lib/CodeGen/MachineLICM.cpp

  493   unsigned NumRegs = TRI->getNumRegs();

lib/CodeGen/MachineOperand.cpp

  317       unsigned RegMaskSize = (TRI->getNumRegs() + 31) / 32;
  873       for (unsigned i = 0; i < TRI->getNumRegs(); ++i) {
  900       for (unsigned Reg = 0, E = TRI->getNumRegs(); Reg < E; ++Reg) {

lib/CodeGen/MachineRegisterInfo.cpp

   48   unsigned NumRegs = getTargetRegisterInfo()->getNumRegs();
  259   for (unsigned i = 1, e = getTargetRegisterInfo()->getNumRegs(); i != e; ++i)
  515   assert(ReservedRegs.size() == getTargetRegisterInfo()->getNumRegs() &&
  616   assert(Reg && (Reg < TRI->getNumRegs()) &&

lib/CodeGen/MachineVerifier.cpp

  220       return Reg < TRI->getNumRegs() && TRI->isInAllocatableClass(Reg) &&

lib/CodeGen/RegAllocFast.cpp

  978   for (unsigned Reg = 1, E = TRI->getNumRegs(); Reg != E; ++Reg) {
 1249   PhysRegState.assign(TRI->getNumRegs(), regDisabled);

lib/CodeGen/RegUsageInfoCollector.cpp

  128   unsigned RegMaskSize = MachineOperand::getRegMaskSize(TRI->getNumRegs());
  155   for (unsigned PReg = 1, PRegE = TRI->getNumRegs(); PReg < PRegE; ++PReg) {
  182     for (unsigned PReg = 1, PRegE = TRI->getNumRegs(); PReg < PRegE; ++PReg) {

lib/CodeGen/RegUsageInfoPropagate.cpp

   68                                           ->getNumRegs())

lib/CodeGen/RegisterClassInfo.cpp

   62     CalleeSavedAliases.resize(TRI->getNumRegs(), 0);

lib/CodeGen/RegisterPressure.cpp

  227   unsigned NumRegUnits = TRI.getNumRegs();

lib/CodeGen/RegisterScavenging.cpp

  299   BitVector Mask(TRI->getNumRegs());

lib/CodeGen/RegisterUsageInfo.cpp

   95     for (unsigned PReg = 1, PRegE = TRI->getNumRegs(); PReg < PRegE; ++PReg) {

lib/CodeGen/ScheduleDAGInstrs.cpp

  778   Defs.setUniverse(TRI->getNumRegs());
  779   Uses.setUniverse(TRI->getNumRegs());

lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp

  121   LiveRegDefs.resize(TRI->getNumRegs(), nullptr);
  122   LiveRegCycles.resize(TRI->getNumRegs(), 0);

lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp

  365   LiveRegDefs.reset(new SUnit*[TRI->getNumRegs() + 1]());
  366   LiveRegGens.reset(new SUnit*[TRI->getNumRegs() + 1]());
  577   unsigned CallResource = TRI->getNumRegs();
  782   unsigned CallResource = TRI->getNumRegs();
  854   unsigned CallResource = TRI->getNumRegs();
 1397       unsigned CallResource = TRI->getNumRegs();
 1409                                makeArrayRef(LiveRegDefs.get(), TRI->getNumRegs()),
 1471                  if (LRegs[0] == TRI->getNumRegs()) dbgs() << "CallResource";

lib/CodeGen/StackMaps.cpp

  262   for (unsigned Reg = 0, NumRegs = TRI->getNumRegs(); Reg != NumRegs; ++Reg)

lib/CodeGen/TargetFrameLoweringImpl.cpp

   66   CalleeSaves.resize(TRI.getNumRegs());
   84   SavedRegs.resize(TRI.getNumRegs());

lib/CodeGen/TargetRegisterInfo.cpp

   67   BitVector Checked(getNumRegs());
  105     else if (Reg < TRI->getNumRegs()) {
  219   BitVector Allocatable(getNumRegs());
  465   unsigned N = (getNumRegs()+31) / 32;

lib/MC/MCRegisterInfo.cpp

   46   assert(SubReg && SubReg < getNumRegs() && "This is not a register");
  120     report_fatal_error("unknown codeview register " + (RegNum < getNumRegs()

lib/MCA/HardwareUnits/RegisterFile.cpp

   28       RegisterMappings(mri.getNumRegs(), {WriteRef(), RegisterRenamingInfo()}),
   29       ZeroRegisters(mri.getNumRegs(), false) {
  476   for (unsigned I = 0, E = MRI.getNumRegs(); I < E; ++I) {

lib/Target/AArch64/AArch64RegisterInfo.cpp

  154   unsigned RegMaskSize = MachineOperand::getRegMaskSize(getNumRegs());
  198   BitVector Reserved(getNumRegs());

lib/Target/AArch64/AArch64SpeculationHardening.cpp

  660   RegsNeedingCSDBBeforeUse.resize(TRI->getNumRegs());
  661   RegsAlreadyMasked.resize(TRI->getNumRegs());

lib/Target/AMDGPU/R600RegisterInfo.cpp

   32   BitVector Reserved(getNumRegs());

lib/Target/AMDGPU/SIMachineFunctionInfo.cpp

  354   OtherUsedRegs.resize(TRI->getNumRegs());

lib/Target/AMDGPU/SIRegisterInfo.cpp

  140   BitVector Reserved(getNumRegs());

lib/Target/ARC/ARCRegisterInfo.cpp

  140   BitVector Reserved(getNumRegs());

lib/Target/ARM/ARMBaseRegisterInfo.cpp

  192   BitVector Reserved(getNumRegs());

lib/Target/AVR/AVRRegisterInfo.cpp

   53   BitVector Reserved(getNumRegs());

lib/Target/BPF/BPFRegisterInfo.cpp

   38   BitVector Reserved(getNumRegs());

lib/Target/Hexagon/HexagonBlockRanges.cpp

  354       for (unsigned PR = 1, N = TRI.getNumRegs(); PR != N; ++PR) {
  474   unsigned NumRegs = TRI.getNumRegs();

lib/Target/Hexagon/HexagonFrameLowering.cpp

 1934   SavedRegs.resize(HRI.getNumRegs());

lib/Target/Hexagon/HexagonGenMux.cpp

  183   unsigned NR = HRI->getNumRegs();

lib/Target/Hexagon/HexagonRegisterInfo.cpp

  132   BitVector Reserved(getNumRegs());

lib/Target/Hexagon/RDFDeadCode.cpp

   71       for (unsigned R = 0, RN = DFG.getTRI().getNumRegs(); R != RN; ++R) {

lib/Target/Hexagon/RDFGraph.cpp

   59   if (P.Obj.Reg > 0 && P.Obj.Reg < TRI.getNumRegs())
 1288   BitVector DoneDefs(TRI.getNumRegs());
 1317   BitVector DoneClobbers(TRI.getNumRegs());
 1328     for (unsigned i = 1, e = TRI.getNumRegs(); i != e; ++i)

lib/Target/Hexagon/RDFLiveness.cpp

  874   BitVector LiveIn(TRI.getNumRegs()), Live(TRI.getNumRegs());
  874   BitVector LiveIn(TRI.getNumRegs()), Live(TRI.getNumRegs());

lib/Target/Hexagon/RDFRegisters.cpp

   30   RegInfos.resize(TRI.getNumRegs());
   32   BitVector BadRC(TRI.getNumRegs());
   87     for (unsigned i = 1, e = TRI.getNumRegs(); i != e; ++i) {
  108     for (unsigned i = 1, e = TRI.getNumRegs(); i != e; ++i) {
  199   unsigned NumRegs = TRI.getNumRegs();
  334   BitVector Regs(PRI.getTRI().getNumRegs());
  341     BitVector AR(PRI.getTRI().getNumRegs());

lib/Target/Lanai/LanaiRegisterInfo.cpp

   43   BitVector Reserved(getNumRegs());

lib/Target/MSP430/MSP430RegisterInfo.cpp

   74   BitVector Reserved(getNumRegs());

lib/Target/Mips/MipsDelaySlotFiller.cpp

  347     : TRI(TRI), Defs(TRI.getNumRegs(), false), Uses(TRI.getNumRegs(), false) {}
  347     : TRI(TRI), Defs(TRI.getNumRegs(), false), Uses(TRI.getNumRegs(), false) {}
  378   BitVector CallerSavedRegs(TRI.getNumRegs(), true);
  414   BitVector NewDefs(TRI.getNumRegs()), NewUses(TRI.getNumRegs());
  414   BitVector NewDefs(TRI.getNumRegs()), NewUses(TRI.getNumRegs());

lib/Target/Mips/MipsRegisterInfo.cpp

  159   BitVector Reserved(getNumRegs());

lib/Target/NVPTX/NVPTXRegisterInfo.cpp

  108   BitVector Reserved(getNumRegs());

lib/Target/PowerPC/PPCFrameLowering.cpp

 2145   BitVector BVCalleeSaved(TRI->getNumRegs());

lib/Target/PowerPC/PPCRegisterInfo.cpp

  272   BitVector Reserved(getNumRegs());

lib/Target/RISCV/RISCVRegisterInfo.cpp

   70   BitVector Reserved(getNumRegs());
   73   for (size_t Reg = 0; Reg < getNumRegs(); Reg++) {

lib/Target/Sparc/SparcRegisterInfo.cpp

   55   BitVector Reserved(getNumRegs());

lib/Target/SystemZ/SystemZRegisterInfo.cpp

  224   BitVector Reserved(getNumRegs());
  385   BitVector PhysClobbered(getNumRegs());

lib/Target/WebAssembly/WebAssemblyRegisterInfo.cpp

   46   BitVector Reserved(getNumRegs());

lib/Target/X86/X86ISelLowering.cpp

 4068     unsigned RegMaskSize = MachineOperand::getRegMaskSize(TRI->getNumRegs());

lib/Target/X86/X86RegisterInfo.cpp

  520   BitVector Reserved(getNumRegs());

lib/Target/XCore/XCoreRegisterInfo.cpp

  230   BitVector Reserved(getNumRegs());

tools/llvm-exegesis/lib/BenchmarkResult.cpp

   52     StringMap<unsigned> Map(RegInfo.getNumRegs());
   55     for (unsigned I = 1, E = RegInfo.getNumRegs(); I < E; ++I)
   57     assert(Map.size() == RegInfo.getNumRegs() && "Size prediction failed");

tools/llvm-exegesis/lib/RegisterAliasing.cpp

   16   BitVector AliasedBits(RegInfo.getNumRegs());
   28     : SourceBits(RegInfo.getNumRegs()), AliasedBits(RegInfo.getNumRegs()),
   28     : SourceBits(RegInfo.getNumRegs()), AliasedBits(RegInfo.getNumRegs()),
   29       Origins(RegInfo.getNumRegs()) {}
   63       EmptyRegisters(RegInfo.getNumRegs()) {}

tools/llvm-exegesis/lib/SnippetFile.cpp

  102     for (unsigned I = 0, E = RegInfo->getNumRegs(); I < E; ++I) {

tools/llvm-exegesis/lib/Uops.cpp

  191   BitVector Defs(State.getRegInfo().getNumRegs());

unittests/tools/llvm-exegesis/X86/RegisterAliasingTest.cpp

   46   const BitVector NoReservedReg(RegInfo.getNumRegs());
   51   BitVector sum(RegInfo.getNumRegs());
   63   const BitVector NoReservedReg(RegInfo.getNumRegs());