|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
lib/CodeGen/BreakFalseDeps.cpp 132 !OpRC->contains(CurrMO.getReg()))
lib/CodeGen/CalcSpillWeights.cpp 74 if (rc->contains(CopiedPReg))
lib/CodeGen/MachineCopyPropagation.cpp 328 return URC->contains(CopySrcReg);
355 if (SuperRC->contains(CopySrcReg))
lib/CodeGen/MachineFunction.cpp 595 assert((VRegRC == RC || (VRegRC->contains(PReg) &&
lib/CodeGen/MachineVerifier.cpp 1693 if (!DRC->contains(Reg)) {
lib/CodeGen/RegAllocFast.cpp 674 RC.contains(Hint0)) {
695 RC.contains(Hint1) && !isRegUsedInInstr(Hint1)) {
lib/CodeGen/RegAllocGreedy.cpp 2946 if (CurrPhys != PhysReg && (!MRI->getRegClass(Reg)->contains(PhysReg) ||
lib/CodeGen/RegisterCoalescer.cpp 431 } else if (!MRI.getRegClass(Src)->contains(Dst)) {
1267 if (!DefRC->contains(NewDstReg))
lib/CodeGen/TargetInstrInfo.cpp 455 return RC->contains(LiveOp.getReg()) ? RC : nullptr;
lib/CodeGen/TargetRegisterInfo.cpp 199 RC->contains(reg) && (!BestRC || BestRC->hasSubClass(RC)))
lib/Target/AArch64/AArch64AdvSIMDScalarPass.cpp 110 return AArch64::GPR64RegClass.contains(Reg);
121 return (AArch64::FPR64RegClass.contains(Reg) && SubReg == 0) ||
122 (AArch64::FPR128RegClass.contains(Reg) && SubReg == AArch64::dsub);
lib/Target/AArch64/AArch64AsmPrinter.cpp 630 if (AArch64::GPR32allRegClass.contains(Reg) ||
631 AArch64::GPR64allRegClass.contains(Reg))
636 if (AArch64::ZPRRegClass.contains(Reg)) {
638 } else if (AArch64::PPRRegClass.contains(Reg)) {
lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp 165 } else if (RC->contains(AArch64::WZR))
167 else if (RC->contains(AArch64::XZR))
lib/Target/AArch64/AArch64FastISel.cpp 3894 if (!MRI.getRegClass(SrcReg)->contains(DestReg))
lib/Target/AArch64/AArch64FrameLowering.cpp 1855 if (AArch64::GPR64RegClass.contains(RPI.Reg1))
1857 else if (AArch64::FPR64RegClass.contains(RPI.Reg1))
1859 else if (AArch64::FPR128RegClass.contains(RPI.Reg1))
1869 if (AArch64::GPR64RegClass.contains(NextReg) &&
1875 if (AArch64::FPR64RegClass.contains(NextReg) &&
1880 if (AArch64::FPR128RegClass.contains(NextReg))
2207 if (AArch64::GPR64RegClass.contains(Reg) &&
2221 if (AArch64::GPR64RegClass.contains(PairedReg) &&
lib/Target/AArch64/AArch64ISelLowering.cpp 4256 if (AArch64::GPR64RegClass.contains(*I))
4258 else if (AArch64::FPR64RegClass.contains(*I))
12387 if (AArch64::GPR64RegClass.contains(*I))
12389 else if (AArch64::FPR64RegClass.contains(*I))
lib/Target/AArch64/AArch64InstrInfo.cpp 1075 if (!OpRegCstraints->contains(Reg))
1607 return (AArch64::GPR32RegClass.contains(DstReg) ||
1608 AArch64::GPR64RegClass.contains(DstReg));
1637 return (AArch64::FPR64RegClass.contains(DstReg) ||
1638 AArch64::FPR128RegClass.contains(DstReg));
2466 if (AArch64::GPR32spRegClass.contains(DestReg) &&
2467 (AArch64::GPR32spRegClass.contains(SrcReg) || SrcReg == AArch64::WZR)) {
2523 if (AArch64::PPRRegClass.contains(DestReg) &&
2524 AArch64::PPRRegClass.contains(SrcReg)) {
2534 if (AArch64::ZPRRegClass.contains(DestReg) &&
2535 AArch64::ZPRRegClass.contains(SrcReg)) {
2543 if (AArch64::GPR64spRegClass.contains(DestReg) &&
2544 (AArch64::GPR64spRegClass.contains(SrcReg) || SrcReg == AArch64::XZR)) {
2565 if (AArch64::DDDDRegClass.contains(DestReg) &&
2566 AArch64::DDDDRegClass.contains(SrcReg)) {
2575 if (AArch64::DDDRegClass.contains(DestReg) &&
2576 AArch64::DDDRegClass.contains(SrcReg)) {
2585 if (AArch64::DDRegClass.contains(DestReg) &&
2586 AArch64::DDRegClass.contains(SrcReg)) {
2594 if (AArch64::QQQQRegClass.contains(DestReg) &&
2595 AArch64::QQQQRegClass.contains(SrcReg)) {
2604 if (AArch64::QQQRegClass.contains(DestReg) &&
2605 AArch64::QQQRegClass.contains(SrcReg)) {
2614 if (AArch64::QQRegClass.contains(DestReg) &&
2615 AArch64::QQRegClass.contains(SrcReg)) {
2622 if (AArch64::XSeqPairsClassRegClass.contains(DestReg) &&
2623 AArch64::XSeqPairsClassRegClass.contains(SrcReg)) {
2630 if (AArch64::WSeqPairsClassRegClass.contains(DestReg) &&
2631 AArch64::WSeqPairsClassRegClass.contains(SrcReg)) {
2638 if (AArch64::FPR128RegClass.contains(DestReg) &&
2639 AArch64::FPR128RegClass.contains(SrcReg)) {
2659 if (AArch64::FPR64RegClass.contains(DestReg) &&
2660 AArch64::FPR64RegClass.contains(SrcReg)) {
2676 if (AArch64::FPR32RegClass.contains(DestReg) &&
2677 AArch64::FPR32RegClass.contains(SrcReg)) {
2693 if (AArch64::FPR16RegClass.contains(DestReg) &&
2694 AArch64::FPR16RegClass.contains(SrcReg)) {
2714 if (AArch64::FPR8RegClass.contains(DestReg) &&
2715 AArch64::FPR8RegClass.contains(SrcReg)) {
2736 if (AArch64::FPR64RegClass.contains(DestReg) &&
2737 AArch64::GPR64RegClass.contains(SrcReg)) {
2742 if (AArch64::GPR64RegClass.contains(DestReg) &&
2743 AArch64::FPR64RegClass.contains(SrcReg)) {
2749 if (AArch64::FPR32RegClass.contains(DestReg) &&
2750 AArch64::GPR32RegClass.contains(SrcReg)) {
2755 if (AArch64::GPR32RegClass.contains(DestReg) &&
2756 AArch64::FPR32RegClass.contains(SrcReg)) {
2763 assert(AArch64::GPR64RegClass.contains(SrcReg) && "Invalid NZCV copy");
2772 assert(AArch64::GPR64RegClass.contains(DestReg) && "Invalid NZCV copy");
3283 if (AArch64::GPR32RegClass.contains(SrcReg)) {
3286 } else if (AArch64::FPR32RegClass.contains(SrcReg)) {
3293 if (AArch64::FPR64RegClass.contains(SrcReg)) {
lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp 952 bool IsStoreXReg = TRI->getRegClass(AArch64::GPR64RegClassID)->contains(StRt);
955 TRI->getRegClass(AArch64::GPR32RegClassID)->contains(StRt)) &&
lib/Target/AArch64/AArch64PBQPRegAlloc.cpp 37 return AArch64::FPR32RegClass.contains(reg) ||
38 AArch64::FPR64RegClass.contains(reg) ||
39 AArch64::FPR128RegClass.contains(reg);
lib/Target/AArch64/AArch64SpeculationHardening.cpp 433 assert(AArch64::GPR32allRegClass.contains(Reg) ||
434 AArch64::GPR64allRegClass.contains(Reg));
448 const bool Is64Bit = AArch64::GPR64allRegClass.contains(Reg);
485 return Op.isReg() && (AArch64::GPR32allRegClass.contains(Op.getReg()) ||
486 AArch64::GPR64allRegClass.contains(Op.getReg()));
536 if (!(AArch64::GPR32allRegClass.contains(Reg) ||
537 AArch64::GPR64allRegClass.contains(Reg)))
lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp 768 if (AMDGPU::SReg_32RegClass.contains(Reg)) {
769 assert(!AMDGPU::TTMP_32RegClass.contains(Reg) &&
773 } else if (AMDGPU::VGPR_32RegClass.contains(Reg)) {
776 } else if (AMDGPU::AGPR_32RegClass.contains(Reg)) {
780 } else if (AMDGPU::SReg_64RegClass.contains(Reg)) {
781 assert(!AMDGPU::TTMP_64RegClass.contains(Reg) &&
785 } else if (AMDGPU::VReg_64RegClass.contains(Reg)) {
788 } else if (AMDGPU::AReg_64RegClass.contains(Reg)) {
792 } else if (AMDGPU::VReg_96RegClass.contains(Reg)) {
795 } else if (AMDGPU::SReg_96RegClass.contains(Reg)) {
797 } else if (AMDGPU::SReg_128RegClass.contains(Reg)) {
798 assert(!AMDGPU::TTMP_128RegClass.contains(Reg) &&
802 } else if (AMDGPU::VReg_128RegClass.contains(Reg)) {
805 } else if (AMDGPU::AReg_128RegClass.contains(Reg)) {
809 } else if (AMDGPU::SReg_256RegClass.contains(Reg)) {
810 assert(!AMDGPU::TTMP_256RegClass.contains(Reg) &&
814 } else if (AMDGPU::VReg_256RegClass.contains(Reg)) {
817 } else if (AMDGPU::SReg_512RegClass.contains(Reg)) {
818 assert(!AMDGPU::TTMP_512RegClass.contains(Reg) &&
822 } else if (AMDGPU::VReg_512RegClass.contains(Reg)) {
825 } else if (AMDGPU::AReg_512RegClass.contains(Reg)) {
829 } else if (AMDGPU::SReg_1024RegClass.contains(Reg)) {
832 } else if (AMDGPU::VReg_1024RegClass.contains(Reg)) {
835 } else if (AMDGPU::AReg_1024RegClass.contains(Reg)) {
lib/Target/AMDGPU/AMDGPUTargetMachine.cpp 1052 !AMDGPU::SGPR_128RegClass.contains(MFI->ScratchRSrcReg)) {
1057 !AMDGPU::SGPR_32RegClass.contains(MFI->ScratchWaveOffsetReg)) {
1062 !AMDGPU::SGPR_32RegClass.contains(MFI->FrameOffsetReg)) {
1067 !AMDGPU::SGPR_32RegClass.contains(MFI->StackPtrOffsetReg)) {
1085 if (!RC.contains(Reg))
lib/Target/AMDGPU/GCNRegBankReassign.cpp 449 return AMDGPU::SGPR_32RegClass.contains(PhysReg);
lib/Target/AMDGPU/R600ControlFlowFinalizer.cpp 307 if (R600::R600_Reg128RegClass.contains(Reg))
316 if (R600::R600_Reg128RegClass.contains(Reg))
lib/Target/AMDGPU/R600InstrInfo.cpp 66 if ((R600::R600_Reg128RegClass.contains(DestReg) ||
67 R600::R600_Reg128VerticalRegClass.contains(DestReg)) &&
68 (R600::R600_Reg128RegClass.contains(SrcReg) ||
69 R600::R600_Reg128VerticalRegClass.contains(SrcReg))) {
71 } else if((R600::R600_Reg64RegClass.contains(DestReg) ||
72 R600::R600_Reg64VerticalRegClass.contains(DestReg)) &&
73 (R600::R600_Reg64RegClass.contains(SrcReg) ||
74 R600::R600_Reg64VerticalRegClass.contains(SrcReg))) {
248 if (R600::R600_LDS_SRC_REGRegClass.contains(I->getReg()))
624 if (R600::R600_KC0RegClass.contains(Src.first->getReg()) ||
625 R600::R600_KC1RegClass.contains(Src.first->getReg())) {
1195 if (Register::isVirtualRegister(Reg) || !IndirectRC->contains(Reg))
lib/Target/AMDGPU/R600MachineScheduler.cpp 213 return RC->contains(Reg);
lib/Target/AMDGPU/SIISelLowering.cpp 1996 if (AMDGPU::SReg_64RegClass.contains(*I))
1998 else if (AMDGPU::SReg_32RegClass.contains(*I))
2347 if (AMDGPU::SReg_64RegClass.contains(*I))
2349 else if (AMDGPU::SReg_32RegClass.contains(*I))
lib/Target/AMDGPU/SIInstrInfo.cpp 531 assert(AMDGPU::VGPR_32RegClass.contains(SrcReg) ||
532 AMDGPU::SReg_32RegClass.contains(SrcReg) ||
533 AMDGPU::AGPR_32RegClass.contains(SrcReg));
534 unsigned Opc = AMDGPU::AGPR_32RegClass.contains(SrcReg) ?
551 if (AMDGPU::SReg_32RegClass.contains(SrcReg)) {
556 assert(AMDGPU::VGPR_32RegClass.contains(SrcReg));
565 if (!AMDGPU::SReg_32RegClass.contains(SrcReg)) {
577 if (AMDGPU::SReg_64RegClass.contains(SrcReg)) {
582 assert(AMDGPU::VGPR_32RegClass.contains(SrcReg));
591 if (!AMDGPU::SReg_64RegClass.contains(SrcReg)) {
602 assert(AMDGPU::SReg_32RegClass.contains(SrcReg));
610 assert(AMDGPU::VGPR_32RegClass.contains(SrcReg) ||
611 AMDGPU::SReg_32RegClass.contains(SrcReg) ||
612 AMDGPU::AGPR_32RegClass.contains(SrcReg));
613 if (!AMDGPU::VGPR_32RegClass.contains(SrcReg)) {
3127 return AMDGPU::SReg_32RegClass.contains(MO.getReg()) ||
3128 AMDGPU::SReg_64RegClass.contains(MO.getReg());
3224 if (!Register::isVirtualRegister(Reg) && !RC->contains(Reg)) {
3293 if (!RC->contains(Reg)) {
lib/Target/AMDGPU/SIRegisterInfo.cpp 1275 if (BaseClass->contains(Reg)) {
lib/Target/ARC/ARCInstrInfo.cpp 285 assert(ARC::GPR32RegClass.contains(SrcReg) &&
287 assert(ARC::GPR32RegClass.contains(DestReg) &&
lib/Target/ARC/ARCRegisterInfo.cpp 210 assert(ARC::GPR32RegClass.contains(Reg) && "Unexpected register operand");
lib/Target/ARM/A15SDOptimizer.cpp 141 return TRC->contains(Reg);
lib/Target/ARM/ARMAsmPrinter.cpp 209 if(ARM::GPRPairRegClass.contains(Reg)) {
283 if (!ARM::DPRRegClass.contains(*SR))
310 if (ARM::GPRPairRegClass.contains(RegBegin)) {
404 if (!ARM::QPRRegClass.contains(Reg))
423 if(!ARM::GPRPairRegClass.contains(Reg))
lib/Target/ARM/ARMBaseInstrInfo.cpp 834 bool GPRDest = ARM::GPRRegClass.contains(DestReg);
835 bool GPRSrc = ARM::GPRRegClass.contains(SrcReg);
845 bool SPRDest = ARM::SPRRegClass.contains(DestReg);
846 bool SPRSrc = ARM::SPRRegClass.contains(SrcReg);
930 assert(ARM::GPRRegClass.contains(SrcReg));
936 assert(ARM::GPRRegClass.contains(DestReg));
942 assert(ARM::GPRRegClass.contains(SrcReg));
948 assert(ARM::GPRRegClass.contains(DestReg));
4739 if (!ARM::hGPRRegClass.contains(MI.getOperand(0).getReg()) &&
4740 !ARM::hGPRRegClass.contains(MI.getOperand(1).getReg())) {
5182 } else if (ARM::SPRRegClass.contains(Reg)) {
5209 if (ARM::SPRRegClass.contains(Reg)) {
5214 assert(ARM::DPRRegClass.contains(DReg) && "Can only break D-reg deps");
lib/Target/ARM/ARMBaseRegisterInfo.cpp 294 if (ARM::GPRPairRegClass.contains(*Supers))
818 (Register::isVirtualRegister(FrameReg) || RegClass->contains(FrameReg)))
lib/Target/ARM/ARMFastISel.cpp 2160 if (!SrcRC->contains(DstReg))
lib/Target/ARM/ARMFrameLowering.cpp 1534 if (RegClass && !RegClass->contains(ARM::SP))
1713 if (!ARM::GPRRegClass.contains(Reg)) {
1715 if (ARM::SPRRegClass.contains(Reg))
1717 else if (ARM::DPRRegClass.contains(Reg))
1719 else if (ARM::QPRRegClass.contains(Reg))
lib/Target/ARM/ARMISelLowering.cpp 2838 if (ARM::GPRRegClass.contains(*I))
2840 else if (ARM::DPRRegClass.contains(*I))
9852 !ARM::tGPRRegClass.contains(Reg) &&
9853 !ARM::hGPRRegClass.contains(Reg))
9855 if (Subtarget->isThumb1Only() && !ARM::tGPRRegClass.contains(Reg))
9857 if (!Subtarget->isThumb() && !ARM::GPRRegClass.contains(Reg))
17108 if (ARM::GPRRegClass.contains(*I))
17110 else if (ARM::DPRRegClass.contains(*I))
lib/Target/ARM/ARMSubtarget.cpp 462 ARM::GPRRegClass.contains(PhysReg);
lib/Target/ARM/Thumb1FrameLowering.cpp 464 return ((ARM::tGPRRegClass.contains(Src) || Src == ARM::LR) &&
465 ARM::hGPRRegClass.contains(Dst));
829 if (ARM::tGPRRegClass.contains(Reg) || Reg == ARM::LR) {
831 } else if (ARM::hGPRRegClass.contains(Reg) && Reg != ARM::LR) {
837 if ((ARM::tGPRRegClass.contains(Reg) || Reg == ARM::LR) &&
955 if (ARM::tGPRRegClass.contains(Reg) || Reg == ARM::LR) {
957 } else if (ARM::hGPRRegClass.contains(Reg) && Reg != ARM::LR) {
965 if ((ARM::tGPRRegClass.contains(Reg)) &&
1030 if (!(ARM::tGPRRegClass.contains(Reg) || Reg == ARM::LR))
lib/Target/ARM/Thumb1InstrInfo.cpp 49 if (st.hasV6Ops() || ARM::hGPRRegClass.contains(SrcReg)
50 || !ARM::tGPRRegClass.contains(DestReg))
lib/Target/ARM/Thumb2InstrInfo.cpp 653 RegClass->contains(FrameReg))) {
694 RegClass->contains(FrameReg));
lib/Target/AVR/AVRISelDAGToDAG.cpp 255 AVR::PTRDISPREGSRegClass.contains(Reg));
lib/Target/AVR/AVRInstrInfo.cpp 69 } else if (SrcReg == AVR::SP && AVR::DREGSRegClass.contains(DestReg)) {
71 } else if (DestReg == AVR::SP && AVR::DREGSRegClass.contains(SrcReg)) {
lib/Target/AVR/AVRRegisterInfo.cpp 270 assert(AVR::DREGSRegClass.contains(Reg) && "can only split 16-bit registers");
lib/Target/Hexagon/HexagonAsmPrinter.cpp 68 assert(Hexagon::IntRegsRegClass.contains(Reg));
71 assert(Hexagon::DoubleRegsRegClass.contains(Pair));
135 if (Hexagon::DoubleRegsRegClass.contains(RegNumber))
lib/Target/Hexagon/HexagonBitTracker.cpp 121 if (RC.contains(Reg))
1250 bool Is64 = DoubleRegsRegClass.contains(PReg);
1251 assert(PReg == 0 || Is64 || IntRegsRegClass.contains(PReg));
lib/Target/Hexagon/HexagonCopyToCombine.cpp 138 return Hexagon::IntRegsRegClass.contains(DestReg) &&
139 Hexagon::IntRegsRegClass.contains(SrcReg);
158 return Hexagon::IntRegsRegClass.contains(DestReg) &&
230 if (Hexagon::IntRegsRegClass.contains(Reg))
232 if (Hexagon::HvxVRRegClass.contains(Reg))
446 if (Hexagon::DoubleRegsRegClass.contains(Reg)) {
449 } else if (Hexagon::IntRegsRegClass.contains(Reg))
589 if (Hexagon::IntRegsRegClass.contains(LoRegDef)) {
592 } else if (Hexagon::HvxVRRegClass.contains(LoRegDef)) {
869 if (Hexagon::DoubleRegsRegClass.contains(DoubleDestReg)) {
871 } else if (Hexagon::HvxWRRegClass.contains(DoubleDestReg)) {
lib/Target/Hexagon/HexagonFrameLowering.cpp 1575 if (!Hexagon::ModRegsRegClass.contains(DstR) ||
1576 !Hexagon::ModRegsRegClass.contains(SrcR))
2435 if (!Hexagon::DoubleRegsRegClass.contains(R))
lib/Target/Hexagon/HexagonGenMux.cpp 124 return Hexagon::DoubleRegsRegClass.contains(Reg);
lib/Target/Hexagon/HexagonInstrInfo.cpp 810 if (Hexagon::CtrRegsRegClass.contains(DestReg) &&
811 Hexagon::IntRegsRegClass.contains(SrcReg)) {
816 if (Hexagon::IntRegsRegClass.contains(DestReg) &&
817 Hexagon::CtrRegsRegClass.contains(SrcReg)) {
822 if (Hexagon::ModRegsRegClass.contains(DestReg) &&
823 Hexagon::IntRegsRegClass.contains(SrcReg)) {
828 if (Hexagon::PredRegsRegClass.contains(SrcReg) &&
829 Hexagon::IntRegsRegClass.contains(DestReg)) {
834 if (Hexagon::IntRegsRegClass.contains(SrcReg) &&
835 Hexagon::PredRegsRegClass.contains(DestReg)) {
840 if (Hexagon::PredRegsRegClass.contains(SrcReg) &&
841 Hexagon::IntRegsRegClass.contains(DestReg)) {
865 if (Hexagon::HvxQRRegClass.contains(SrcReg) &&
866 Hexagon::HvxVRRegClass.contains(DestReg)) {
870 if (Hexagon::HvxQRRegClass.contains(DestReg) &&
871 Hexagon::HvxVRRegClass.contains(SrcReg)) {
3310 if (Hexagon::PredRegsRegClass.contains(DstReg) &&
3321 if (Hexagon::PredRegsRegClass.contains(DstReg) &&
3346 if (Hexagon::PredRegsRegClass.contains(DstReg) &&
3361 if (Hexagon::PredRegsRegClass.contains(Src1Reg) &&
3742 if (Hexagon::IntRegsRegClass.contains(SrcReg) &&
3796 Hexagon::IntRegsRegClass.contains(SrcReg) &&
3815 if (Hexagon::IntRegsRegClass.contains(DstReg) && (Hexagon::R31 == DstReg))
3830 if ((Hexagon::PredRegsRegClass.contains(SrcReg) &&
3832 (Hexagon::IntRegsRegClass.contains(DstReg) && (Hexagon::R31 == DstReg)))
3843 if (Hexagon::PredRegsRegClass.contains(SrcReg) && (Hexagon::P0 == SrcReg))
3856 if (Hexagon::IntRegsRegClass.contains(Src1Reg) &&
3898 Hexagon::IntRegsRegClass.contains(Src1Reg) &&
3947 if (Hexagon::IntRegsRegClass.contains(SrcReg) &&
4010 Hexagon::PredRegsRegClass.contains(SrcReg) && Hexagon::P0 == SrcReg &&
4018 if (Hexagon::PredRegsRegClass.contains(DstReg) &&
lib/Target/Hexagon/HexagonNewValueJump.cpp 156 if (!Hexagon::IntRegsRegClass.contains(Op.getReg()))
lib/Target/Hexagon/HexagonVLIWPacketizer.cpp 948 Hexagon::PredRegsRegClass.contains(Op.getReg()))
998 Hexagon::PredRegsRegClass.contains(Dep.getReg())) {
1018 Hexagon::PredRegsRegClass.contains(PReg1) &&
1019 Hexagon::PredRegsRegClass.contains(PReg2) &&
lib/Target/Mips/MicroMipsSizeReduction.cpp 294 if (MO.isReg() && Mips::GPRMM16RegClass.contains(MO.getReg()))
301 if (MO.isReg() && Mips::GPRMM16ZeroRegClass.contains(MO.getReg()))
lib/Target/Mips/Mips16InstrInfo.cpp 75 if (Mips::CPU16RegsRegClass.contains(DestReg) &&
76 Mips::GPR32RegClass.contains(SrcReg))
78 else if (Mips::GPR32RegClass.contains(DestReg) &&
79 Mips::CPU16RegsRegClass.contains(SrcReg))
82 (Mips::CPU16RegsRegClass.contains(DestReg)))
85 (Mips::CPU16RegsRegClass.contains(DestReg)))
lib/Target/Mips/MipsAsmPrinter.cpp 346 if (Mips::FGR32RegClass.contains(Reg)) {
349 } else if (Mips::AFGR64RegClass.contains(Reg)) {
353 } else if (Mips::GPR32RegClass.contains(Reg))
lib/Target/Mips/MipsFastISel.cpp 1733 if (!MRI.getRegClass(SrcReg)->contains(DestReg))
lib/Target/Mips/MipsSEFrameLowering.cpp 50 if (Mips::ACC64RegClass.contains(Src))
54 if (Mips::ACC64DSPRegClass.contains(Src))
57 if (Mips::ACC128RegClass.contains(Src))
462 if (Mips::AFGR64RegClass.contains(Reg)) {
480 } else if (Mips::FGR64RegClass.contains(Reg)) {
lib/Target/Mips/MipsSEISelDAGToDAG.cpp 118 if (!MRI->getRegClass(MO.getReg())->contains(ZeroReg))
lib/Target/Mips/MipsSEInstrInfo.cpp 90 if (Mips::GPR32RegClass.contains(DestReg)) { // Copy to CPU Reg.
91 if (Mips::GPR32RegClass.contains(SrcReg)) {
96 } else if (Mips::CCRRegClass.contains(SrcReg))
98 else if (Mips::FGR32RegClass.contains(SrcReg))
100 else if (Mips::HI32RegClass.contains(SrcReg)) {
103 } else if (Mips::LO32RegClass.contains(SrcReg)) {
106 } else if (Mips::HI32DSPRegClass.contains(SrcReg))
108 else if (Mips::LO32DSPRegClass.contains(SrcReg))
110 else if (Mips::DSPCCRegClass.contains(SrcReg)) {
115 else if (Mips::MSACtrlRegClass.contains(SrcReg))
118 else if (Mips::GPR32RegClass.contains(SrcReg)) { // Copy from CPU Reg.
119 if (Mips::CCRRegClass.contains(DestReg))
121 else if (Mips::FGR32RegClass.contains(DestReg))
123 else if (Mips::HI32RegClass.contains(DestReg))
125 else if (Mips::LO32RegClass.contains(DestReg))
127 else if (Mips::HI32DSPRegClass.contains(DestReg))
129 else if (Mips::LO32DSPRegClass.contains(DestReg))
131 else if (Mips::DSPCCRegClass.contains(DestReg)) {
136 } else if (Mips::MSACtrlRegClass.contains(DestReg)) {
149 else if (Mips::GPR64RegClass.contains(DestReg)) { // Copy to CPU64 Reg.
150 if (Mips::GPR64RegClass.contains(SrcReg))
152 else if (Mips::HI64RegClass.contains(SrcReg))
154 else if (Mips::LO64RegClass.contains(SrcReg))
156 else if (Mips::FGR64RegClass.contains(SrcReg))
159 else if (Mips::GPR64RegClass.contains(SrcReg)) { // Copy from CPU64 Reg.
160 if (Mips::HI64RegClass.contains(DestReg))
162 else if (Mips::LO64RegClass.contains(DestReg))
164 else if (Mips::FGR64RegClass.contains(DestReg))
167 else if (Mips::MSA128BRegClass.contains(DestReg)) { // Copy to MSA reg
168 if (Mips::MSA128BRegClass.contains(SrcReg))
lib/Target/PowerPC/PPCAsmPrinter.cpp 551 if (PPC::F4RCRegClass.contains(Reg) ||
552 PPC::F8RCRegClass.contains(Reg) ||
553 PPC::QBRCRegClass.contains(Reg) ||
554 PPC::QFRCRegClass.contains(Reg) ||
555 PPC::QSRCRegClass.contains(Reg) ||
556 PPC::VFRCRegClass.contains(Reg) ||
557 PPC::VRRCRegClass.contains(Reg) ||
558 PPC::VSFRCRegClass.contains(Reg) ||
559 PPC::VSSRCRegClass.contains(Reg)
563 if (PPC::SPERCRegClass.contains(Reg))
lib/Target/PowerPC/PPCFrameLowering.cpp 367 if (!MO.isReg() || !PPC::VRRCRegClass.contains(MO.getReg()))
1321 if (PPC::CRBITRCRegClass.contains(Reg))
1889 if (PPC::GPRCRegClass.contains(Reg)) {
1897 } else if (PPC::G8RCRegClass.contains(Reg)) {
1905 } else if (PPC::F8RCRegClass.contains(Reg)) {
1913 } else if (PPC::CRBITRCRegClass.contains(Reg) ||
1914 PPC::CRRCRegClass.contains(Reg)) {
1916 } else if (PPC::VRSAVERCRegClass.contains(Reg)) {
1918 } else if (PPC::VRRCRegClass.contains(Reg) ||
1919 PPC::SPERCRegClass.contains(Reg)) {
1984 if (PPC::G8RCRegClass.contains(BP)) {
1987 } else if (PPC::GPRCRegClass.contains(BP)) {
2038 (PPC::CRBITRCRegClass.contains(Reg) ||
2039 PPC::CRRCRegClass.contains(Reg)))) {
2056 if (PPC::VRSAVERCRegClass.contains(Reg)) {
2155 (!PPC::F8RCRegClass.contains(Reg) &&
2156 !PPC::VFRCRegClass.contains(Reg)) ||
2167 if (!PPC::G8RCRegClass.contains(Reg) && !PPC::GPRCRegClass.contains(Reg)) {
2167 if (!PPC::G8RCRegClass.contains(Reg) && !PPC::GPRCRegClass.contains(Reg)) {
lib/Target/PowerPC/PPCISelLowering.cpp 6948 if (PPC::G8RCRegClass.contains(*I))
6950 else if (PPC::F8RCRegClass.contains(*I))
6952 else if (PPC::CRRCRegClass.contains(*I))
6954 else if (PPC::VRRCRegClass.contains(*I))
14376 PPC::GPRCRegClass.contains(R.first))
15036 if (PPC::G8RCRegClass.contains(*I))
15038 else if (PPC::F8RCRegClass.contains(*I))
15040 else if (PPC::CRRCRegClass.contains(*I))
15042 else if (PPC::VRRCRegClass.contains(*I))
lib/Target/PowerPC/PPCInstrInfo.cpp 195 IsRegCR = PPC::CRRCRegClass.contains(Reg) ||
196 PPC::CRBITRCRegClass.contains(Reg);
861 if (MRI.getRegClass(FirstReg)->contains(PPC::R0) ||
862 MRI.getRegClass(FirstReg)->contains(PPC::X0)) {
864 MRI.getRegClass(FirstReg)->contains(PPC::X0) ?
911 if (PPC::F8RCRegClass.contains(DestReg) &&
912 PPC::VSRCRegClass.contains(SrcReg)) {
920 } else if (PPC::F8RCRegClass.contains(SrcReg) &&
921 PPC::VSRCRegClass.contains(DestReg)) {
932 if (PPC::CRBITRCRegClass.contains(SrcReg) &&
933 PPC::GPRCRegClass.contains(DestReg)) {
945 } else if (PPC::CRRCRegClass.contains(SrcReg) &&
946 PPC::G8RCRegClass.contains(DestReg)) {
950 } else if (PPC::CRRCRegClass.contains(SrcReg) &&
951 PPC::GPRCRegClass.contains(DestReg)) {
955 } else if (PPC::G8RCRegClass.contains(SrcReg) &&
956 PPC::VSFRCRegClass.contains(DestReg)) {
963 } else if (PPC::VSFRCRegClass.contains(SrcReg) &&
964 PPC::G8RCRegClass.contains(DestReg)) {
970 } else if (PPC::SPERCRegClass.contains(SrcReg) &&
971 PPC::GPRCRegClass.contains(DestReg)) {
975 } else if (PPC::GPRCRegClass.contains(SrcReg) &&
976 PPC::SPERCRegClass.contains(DestReg)) {
1072 if (PPC::GPRCRegClass.contains(Reg) ||
1073 PPC::GPRC_NOR0RegClass.contains(Reg)) {
1075 } else if (PPC::G8RCRegClass.contains(Reg) ||
1076 PPC::G8RC_NOX0RegClass.contains(Reg)) {
1078 } else if (PPC::F8RCRegClass.contains(Reg)) {
1080 } else if (PPC::F4RCRegClass.contains(Reg)) {
1082 } else if (PPC::SPERCRegClass.contains(Reg)) {
1084 } else if (PPC::CRRCRegClass.contains(Reg)) {
1086 } else if (PPC::CRBITRCRegClass.contains(Reg)) {
1088 } else if (PPC::VRRCRegClass.contains(Reg)) {
1090 } else if (PPC::VSRCRegClass.contains(Reg)) {
1092 } else if (PPC::VSFRCRegClass.contains(Reg)) {
1094 } else if (PPC::VSSRCRegClass.contains(Reg)) {
1096 } else if (PPC::VRSAVERCRegClass.contains(Reg)) {
1098 } else if (PPC::QFRCRegClass.contains(Reg)) {
1100 } else if (PPC::QSRCRegClass.contains(Reg)) {
1102 } else if (PPC::QBRCRegClass.contains(Reg)) {
1104 } else if (PPC::SPILLTOVSRRCRegClass.contains(Reg)) {
1158 if (PPC::GPRCRegClass.contains(Reg) ||
1159 PPC::GPRC_NOR0RegClass.contains(Reg)) {
1161 } else if (PPC::G8RCRegClass.contains(Reg) ||
1162 PPC::G8RC_NOX0RegClass.contains(Reg)) {
1164 } else if (PPC::F8RCRegClass.contains(Reg)) {
1166 } else if (PPC::F4RCRegClass.contains(Reg)) {
1168 } else if (PPC::SPERCRegClass.contains(Reg)) {
1170 } else if (PPC::CRRCRegClass.contains(Reg)) {
1172 } else if (PPC::CRBITRCRegClass.contains(Reg)) {
1174 } else if (PPC::VRRCRegClass.contains(Reg)) {
1176 } else if (PPC::VSRCRegClass.contains(Reg)) {
1178 } else if (PPC::VSFRCRegClass.contains(Reg)) {
1180 } else if (PPC::VSSRCRegClass.contains(Reg)) {
1182 } else if (PPC::VRSAVERCRegClass.contains(Reg)) {
1184 } else if (PPC::QFRCRegClass.contains(Reg)) {
1186 } else if (PPC::QSRCRegClass.contains(Reg)) {
1188 } else if (PPC::QBRCRegClass.contains(Reg)) {
1190 } else if (PPC::SPILLTOVSRRCRegClass.contains(Reg)) {
1572 if (MO.isDef() && RC->contains(MO.getReg())) {
2180 if (PPC::VSFRCRegClass.contains(TargetReg)) {
2190 if (PPC::VSFRCRegClass.contains(SrcReg)) {
2202 if (PPC::VSFRCRegClass.contains(TargetReg))
2210 if (PPC::VSFRCRegClass.contains(SrcReg)) {
lib/Target/PowerPC/PPCVSXCopy.cpp 55 } else if (RC->contains(Reg)) {
lib/Target/PowerPC/PPCVSXFMAMutate.cpp 138 ->contains(AddendSrcReg))
lib/Target/PowerPC/PPCVSXSwapRemoval.cpp 163 return RC->contains(Reg);
lib/Target/RISCV/RISCVFrameLowering.cpp 406 if (RISCV::FPR32RegClass.contains(Regs[i]) ||
407 RISCV::FPR64RegClass.contains(Regs[i]))
lib/Target/Sparc/SparcInstrInfo.cpp 359 } else if (SP::ASRRegsRegClass.contains(DestReg) &&
360 SP::IntRegsRegClass.contains(SrcReg)) {
364 } else if (SP::IntRegsRegClass.contains(DestReg) &&
365 SP::ASRRegsRegClass.contains(SrcReg)) {
lib/Target/SystemZ/SystemZFrameLowering.cpp 106 if (SystemZ::GR64BitRegClass.contains(Reg) && SavedRegs.test(Reg)) {
150 if (SystemZ::GR64BitRegClass.contains(Reg)) {
196 if (SystemZ::GR64BitRegClass.contains(Reg))
209 if (SystemZ::FP64BitRegClass.contains(Reg)) {
214 if (SystemZ::VR128BitRegClass.contains(Reg)) {
241 if (SystemZ::FP64BitRegClass.contains(Reg))
244 if (SystemZ::VR128BitRegClass.contains(Reg))
275 SystemZ::GR64BitRegClass.contains(Reg))
371 if (SystemZ::GR64BitRegClass.contains(Reg)) {
439 if (SystemZ::FP64BitRegClass.contains(Reg)) {
446 } else if (SystemZ::VR128BitRegClass.contains(Reg)) {
lib/Target/SystemZ/SystemZInstrInfo.cpp 792 if (SystemZ::VR128BitRegClass.contains(DestReg) &&
793 SystemZ::FP128BitRegClass.contains(SrcReg)) {
806 if (SystemZ::FP128BitRegClass.contains(DestReg) &&
807 SystemZ::VR128BitRegClass.contains(SrcReg)) {
858 else if (SystemZ::AR32BitRegClass.contains(DestReg) &&
859 SystemZ::GR32BitRegClass.contains(SrcReg))
861 else if (SystemZ::GR32BitRegClass.contains(DestReg) &&
862 SystemZ::AR32BitRegClass.contains(SrcReg))
1175 if (DstPhys && !SystemZ::GRH32BitRegClass.contains(DstPhys) && SrcReg &&
lib/Target/SystemZ/SystemZRegisterInfo.cpp 45 if (SystemZ::GR32BitRegClass.contains(PhysReg))
47 assert (SystemZ::GRH32BitRegClass.contains(PhysReg) &&
68 RC->contains(Reg) && !MRI->isReserved(Reg))
72 RC->contains(Reg) && !MRI->isReserved(Reg))
392 if (NewRC->contains(*SI)) {
lib/Target/SystemZ/SystemZRegisterInfo.h 35 if (SystemZ::GRH32BitRegClass.contains(Reg))
37 assert(SystemZ::GR32BitRegClass.contains(Reg) && "Invalid GRX32");
lib/Target/SystemZ/SystemZShortenInst.cpp 82 (SystemZ::GRH32BitRegClass.contains(Reg) ? SystemZ::subreg_h32
lib/Target/X86/X86AsmPrinter.cpp 394 if (!X86::GR8RegClass.contains(Reg) &&
395 !X86::GR16RegClass.contains(Reg) &&
396 !X86::GR32RegClass.contains(Reg) &&
397 !X86::GR64RegClass.contains(Reg))
lib/Target/X86/X86DomainReassignment.cpp 224 (X86::GR8RegClass.contains(DstReg) ||
225 X86::GR16RegClass.contains(DstReg)))
229 (X86::GR8RegClass.contains(SrcReg) ||
230 X86::GR16RegClass.contains(SrcReg)))
lib/Target/X86/X86FastISel.cpp 1249 if (!SrcRC->contains(DstReg))
lib/Target/X86/X86FloatingPoint.cpp 294 return X86::RFP80RegClass.contains(DstReg) ||
295 X86::RFP80RegClass.contains(SrcReg);
429 X86::RFP80RegClass.contains(MI.getOperand(0).getReg()))
lib/Target/X86/X86FrameLowering.cpp 1391 if (X86::FR64RegClass.contains(Reg)) {
2017 if (!X86::GR64RegClass.contains(Reg) && !X86::GR32RegClass.contains(Reg))
2017 if (!X86::GR64RegClass.contains(Reg) && !X86::GR32RegClass.contains(Reg))
2033 if (X86::GR64RegClass.contains(Reg) || X86::GR32RegClass.contains(Reg))
2033 if (X86::GR64RegClass.contains(Reg) || X86::GR32RegClass.contains(Reg))
2038 if (X86::VK16RegClass.contains(Reg))
2055 if (X86::VR128RegClass.contains(Reg)) {
2081 if (!X86::GR64RegClass.contains(Reg) && !X86::GR32RegClass.contains(Reg))
2081 if (!X86::GR64RegClass.contains(Reg) && !X86::GR32RegClass.contains(Reg))
2114 if (X86::GR64RegClass.contains(Reg) || X86::GR32RegClass.contains(Reg))
2114 if (X86::GR64RegClass.contains(Reg) || X86::GR32RegClass.contains(Reg))
2119 if (X86::VK16RegClass.contains(Reg))
2194 if (X86::GR64RegClass.contains(Reg) ||
2195 X86::GR32RegClass.contains(Reg))
2200 if (X86::VK16RegClass.contains(Reg))
2211 if (!X86::GR64RegClass.contains(Reg) &&
2212 !X86::GR32RegClass.contains(Reg))
lib/Target/X86/X86ISelLowering.cpp 2650 if (X86::GR64RegClass.contains(*I))
46074 if (RC && RC->contains(DestReg))
46187 if (X86::GR64RegClass.contains(*I))
lib/Target/X86/X86InstrInfo.cpp 2884 return X86::GR8_ABCD_HRegClass.contains(Reg);
2897 if (X86::VK16RegClass.contains(SrcReg)) {
2898 if (X86::GR64RegClass.contains(DestReg)) {
2902 if (X86::GR32RegClass.contains(DestReg))
2910 if (X86::VK16RegClass.contains(DestReg)) {
2911 if (X86::GR64RegClass.contains(SrcReg)) {
2915 if (X86::GR32RegClass.contains(SrcReg))
2925 if (X86::GR64RegClass.contains(DestReg)) {
2926 if (X86::VR128XRegClass.contains(SrcReg))
2931 if (X86::VR64RegClass.contains(SrcReg))
2934 } else if (X86::GR64RegClass.contains(SrcReg)) {
2936 if (X86::VR128XRegClass.contains(DestReg))
2941 if (X86::VR64RegClass.contains(DestReg))
2948 if (X86::GR32RegClass.contains(DestReg) &&
2949 X86::VR128XRegClass.contains(SrcReg))
2955 if (X86::VR128XRegClass.contains(DestReg) &&
2956 X86::GR32RegClass.contains(SrcReg))
4574 if (X86::VR128RegClass.contains(Reg)) {
4582 } else if (X86::VR256RegClass.contains(Reg)) {
4591 } else if (X86::GR64RegClass.contains(Reg)) {
4600 } else if (X86::GR32RegClass.contains(Reg)) {
lib/Target/X86/X86InstructionSelector.cpp 217 if (X86::GR64RegClass.contains(Reg))
219 if (X86::GR32RegClass.contains(Reg))
221 if (X86::GR16RegClass.contains(Reg))
223 if (X86::GR8RegClass.contains(Reg))
lib/Target/X86/X86MachineFunctionInfo.cpp 25 if (X86::GR64RegClass.contains(Reg) || X86::GR32RegClass.contains(Reg))
25 if (X86::GR64RegClass.contains(Reg) || X86::GR32RegClass.contains(Reg))
lib/Target/X86/X86RegisterInfo.cpp 758 if (Opc == X86::LEA64_32r && X86::GR32RegClass.contains(BasePtr))
lib/Target/XCore/XCoreInstrInfo.cpp 335 bool GRDest = XCore::GRRegsRegClass.contains(DestReg);
336 bool GRSrc = XCore::GRRegsRegClass.contains(SrcReg);
lib/Target/XCore/XCoreRegisterInfo.cpp 305 assert(XCore::GRRegsRegClass.contains(Reg) && "Unexpected register operand");
tools/llvm-exegesis/lib/AArch64/Target.cpp 47 if (AArch64::GPR32RegClass.contains(Reg))
49 if (AArch64::GPR64RegClass.contains(Reg))
tools/llvm-exegesis/lib/Mips/Target.cpp 49 if (Mips::GPR32RegClass.contains(Reg))
51 if (Mips::GPR64RegClass.contains(Reg))
tools/llvm-exegesis/lib/PowerPC/Target.cpp 56 if (PPC::GPRCRegClass.contains(Reg))
58 if (PPC::G8RCRegClass.contains(Reg))
tools/llvm-exegesis/lib/X86/Target.cpp 666 if (X86::GR8RegClass.contains(Reg))
668 if (X86::GR16RegClass.contains(Reg))
670 if (X86::GR32RegClass.contains(Reg))
672 if (X86::GR64RegClass.contains(Reg))
675 if (X86::VR64RegClass.contains(Reg))
677 if (X86::VR128XRegClass.contains(Reg)) {
684 if (X86::VR256XRegClass.contains(Reg)) {
690 if (X86::VR512RegClass.contains(Reg))
693 if (X86::RSTRegClass.contains(Reg)) {
696 if (X86::RFP32RegClass.contains(Reg) || X86::RFP64RegClass.contains(Reg) ||
696 if (X86::RFP32RegClass.contains(Reg) || X86::RFP64RegClass.contains(Reg) ||
697 X86::RFP80RegClass.contains(Reg)) {