|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/AArch64/AArch64GenInstrInfo.inc18212 MI.getOperand(1).getReg() == AArch64::WZR
18213 || MI.getOperand(1).getReg() == AArch64::XZR
18288 MI.getOperand(0).getReg() == AArch64::WSP
18289 || MI.getOperand(0).getReg() == AArch64::SP
18290 || MI.getOperand(1).getReg() == AArch64::WSP
18291 || MI.getOperand(1).getReg() == AArch64::SP
18301 MI.getOperand(1).getReg() == AArch64::WZR
18302 || MI.getOperand(1).getReg() == AArch64::XZR
18338 MI.getOperand(1).getReg() == AArch64::WZR
18339 || MI.getOperand(1).getReg() == AArch64::XZR
gen/lib/Target/AArch64/AArch64GenSubtargetInfo.inc18059 MI->getOperand(0).getReg() == AArch64::D0
18060 || MI->getOperand(0).getReg() == AArch64::D1
18061 || MI->getOperand(0).getReg() == AArch64::D2
18062 || MI->getOperand(0).getReg() == AArch64::D3
18063 || MI->getOperand(0).getReg() == AArch64::D4
18064 || MI->getOperand(0).getReg() == AArch64::D5
18065 || MI->getOperand(0).getReg() == AArch64::D6
18066 || MI->getOperand(0).getReg() == AArch64::D7
18067 || MI->getOperand(0).getReg() == AArch64::D8
18068 || MI->getOperand(0).getReg() == AArch64::D9
18069 || MI->getOperand(0).getReg() == AArch64::D10
18070 || MI->getOperand(0).getReg() == AArch64::D11
18071 || MI->getOperand(0).getReg() == AArch64::D12
18072 || MI->getOperand(0).getReg() == AArch64::D13
18073 || MI->getOperand(0).getReg() == AArch64::D14
18074 || MI->getOperand(0).getReg() == AArch64::D15
18075 || MI->getOperand(0).getReg() == AArch64::D16
18076 || MI->getOperand(0).getReg() == AArch64::D17
18077 || MI->getOperand(0).getReg() == AArch64::D18
18078 || MI->getOperand(0).getReg() == AArch64::D19
18079 || MI->getOperand(0).getReg() == AArch64::D20
18080 || MI->getOperand(0).getReg() == AArch64::D21
18081 || MI->getOperand(0).getReg() == AArch64::D22
18082 || MI->getOperand(0).getReg() == AArch64::D23
18083 || MI->getOperand(0).getReg() == AArch64::D24
18084 || MI->getOperand(0).getReg() == AArch64::D25
18085 || MI->getOperand(0).getReg() == AArch64::D26
18086 || MI->getOperand(0).getReg() == AArch64::D27
18087 || MI->getOperand(0).getReg() == AArch64::D28
18088 || MI->getOperand(0).getReg() == AArch64::D29
18089 || MI->getOperand(0).getReg() == AArch64::D30
18090 || MI->getOperand(0).getReg() == AArch64::D31
18096 MI->getOperand(0).getReg() == AArch64::Q0
18097 || MI->getOperand(0).getReg() == AArch64::Q1
18098 || MI->getOperand(0).getReg() == AArch64::Q2
18099 || MI->getOperand(0).getReg() == AArch64::Q3
18100 || MI->getOperand(0).getReg() == AArch64::Q4
18101 || MI->getOperand(0).getReg() == AArch64::Q5
18102 || MI->getOperand(0).getReg() == AArch64::Q6
18103 || MI->getOperand(0).getReg() == AArch64::Q7
18104 || MI->getOperand(0).getReg() == AArch64::Q8
18105 || MI->getOperand(0).getReg() == AArch64::Q9
18106 || MI->getOperand(0).getReg() == AArch64::Q10
18107 || MI->getOperand(0).getReg() == AArch64::Q11
18108 || MI->getOperand(0).getReg() == AArch64::Q12
18109 || MI->getOperand(0).getReg() == AArch64::Q13
18110 || MI->getOperand(0).getReg() == AArch64::Q14
18111 || MI->getOperand(0).getReg() == AArch64::Q15
18112 || MI->getOperand(0).getReg() == AArch64::Q16
18113 || MI->getOperand(0).getReg() == AArch64::Q17
18114 || MI->getOperand(0).getReg() == AArch64::Q18
18115 || MI->getOperand(0).getReg() == AArch64::Q19
18116 || MI->getOperand(0).getReg() == AArch64::Q20
18117 || MI->getOperand(0).getReg() == AArch64::Q21
18118 || MI->getOperand(0).getReg() == AArch64::Q22
18119 || MI->getOperand(0).getReg() == AArch64::Q23
18120 || MI->getOperand(0).getReg() == AArch64::Q24
18121 || MI->getOperand(0).getReg() == AArch64::Q25
18122 || MI->getOperand(0).getReg() == AArch64::Q26
18123 || MI->getOperand(0).getReg() == AArch64::Q27
18124 || MI->getOperand(0).getReg() == AArch64::Q28
18125 || MI->getOperand(0).getReg() == AArch64::Q29
18126 || MI->getOperand(0).getReg() == AArch64::Q30
18127 || MI->getOperand(0).getReg() == AArch64::Q31
18205 MI->getOperand(0).getReg() == AArch64::D0
18206 || MI->getOperand(0).getReg() == AArch64::D1
18207 || MI->getOperand(0).getReg() == AArch64::D2
18208 || MI->getOperand(0).getReg() == AArch64::D3
18209 || MI->getOperand(0).getReg() == AArch64::D4
18210 || MI->getOperand(0).getReg() == AArch64::D5
18211 || MI->getOperand(0).getReg() == AArch64::D6
18212 || MI->getOperand(0).getReg() == AArch64::D7
18213 || MI->getOperand(0).getReg() == AArch64::D8
18214 || MI->getOperand(0).getReg() == AArch64::D9
18215 || MI->getOperand(0).getReg() == AArch64::D10
18216 || MI->getOperand(0).getReg() == AArch64::D11
18217 || MI->getOperand(0).getReg() == AArch64::D12
18218 || MI->getOperand(0).getReg() == AArch64::D13
18219 || MI->getOperand(0).getReg() == AArch64::D14
18220 || MI->getOperand(0).getReg() == AArch64::D15
18221 || MI->getOperand(0).getReg() == AArch64::D16
18222 || MI->getOperand(0).getReg() == AArch64::D17
18223 || MI->getOperand(0).getReg() == AArch64::D18
18224 || MI->getOperand(0).getReg() == AArch64::D19
18225 || MI->getOperand(0).getReg() == AArch64::D20
18226 || MI->getOperand(0).getReg() == AArch64::D21
18227 || MI->getOperand(0).getReg() == AArch64::D22
18228 || MI->getOperand(0).getReg() == AArch64::D23
18229 || MI->getOperand(0).getReg() == AArch64::D24
18230 || MI->getOperand(0).getReg() == AArch64::D25
18231 || MI->getOperand(0).getReg() == AArch64::D26
18232 || MI->getOperand(0).getReg() == AArch64::D27
18233 || MI->getOperand(0).getReg() == AArch64::D28
18234 || MI->getOperand(0).getReg() == AArch64::D29
18235 || MI->getOperand(0).getReg() == AArch64::D30
18236 || MI->getOperand(0).getReg() == AArch64::D31
18242 MI->getOperand(0).getReg() == AArch64::Q0
18243 || MI->getOperand(0).getReg() == AArch64::Q1
18244 || MI->getOperand(0).getReg() == AArch64::Q2
18245 || MI->getOperand(0).getReg() == AArch64::Q3
18246 || MI->getOperand(0).getReg() == AArch64::Q4
18247 || MI->getOperand(0).getReg() == AArch64::Q5
18248 || MI->getOperand(0).getReg() == AArch64::Q6
18249 || MI->getOperand(0).getReg() == AArch64::Q7
18250 || MI->getOperand(0).getReg() == AArch64::Q8
18251 || MI->getOperand(0).getReg() == AArch64::Q9
18252 || MI->getOperand(0).getReg() == AArch64::Q10
18253 || MI->getOperand(0).getReg() == AArch64::Q11
18254 || MI->getOperand(0).getReg() == AArch64::Q12
18255 || MI->getOperand(0).getReg() == AArch64::Q13
18256 || MI->getOperand(0).getReg() == AArch64::Q14
18257 || MI->getOperand(0).getReg() == AArch64::Q15
18258 || MI->getOperand(0).getReg() == AArch64::Q16
18259 || MI->getOperand(0).getReg() == AArch64::Q17
18260 || MI->getOperand(0).getReg() == AArch64::Q18
18261 || MI->getOperand(0).getReg() == AArch64::Q19
18262 || MI->getOperand(0).getReg() == AArch64::Q20
18263 || MI->getOperand(0).getReg() == AArch64::Q21
18264 || MI->getOperand(0).getReg() == AArch64::Q22
18265 || MI->getOperand(0).getReg() == AArch64::Q23
18266 || MI->getOperand(0).getReg() == AArch64::Q24
18267 || MI->getOperand(0).getReg() == AArch64::Q25
18268 || MI->getOperand(0).getReg() == AArch64::Q26
18269 || MI->getOperand(0).getReg() == AArch64::Q27
18270 || MI->getOperand(0).getReg() == AArch64::Q28
18271 || MI->getOperand(0).getReg() == AArch64::Q29
18272 || MI->getOperand(0).getReg() == AArch64::Q30
18273 || MI->getOperand(0).getReg() == AArch64::Q31
18285 MI->getOperand(0).getReg() == AArch64::D0
18286 || MI->getOperand(0).getReg() == AArch64::D1
18287 || MI->getOperand(0).getReg() == AArch64::D2
18288 || MI->getOperand(0).getReg() == AArch64::D3
18289 || MI->getOperand(0).getReg() == AArch64::D4
18290 || MI->getOperand(0).getReg() == AArch64::D5
18291 || MI->getOperand(0).getReg() == AArch64::D6
18292 || MI->getOperand(0).getReg() == AArch64::D7
18293 || MI->getOperand(0).getReg() == AArch64::D8
18294 || MI->getOperand(0).getReg() == AArch64::D9
18295 || MI->getOperand(0).getReg() == AArch64::D10
18296 || MI->getOperand(0).getReg() == AArch64::D11
18297 || MI->getOperand(0).getReg() == AArch64::D12
18298 || MI->getOperand(0).getReg() == AArch64::D13
18299 || MI->getOperand(0).getReg() == AArch64::D14
18300 || MI->getOperand(0).getReg() == AArch64::D15
18301 || MI->getOperand(0).getReg() == AArch64::D16
18302 || MI->getOperand(0).getReg() == AArch64::D17
18303 || MI->getOperand(0).getReg() == AArch64::D18
18304 || MI->getOperand(0).getReg() == AArch64::D19
18305 || MI->getOperand(0).getReg() == AArch64::D20
18306 || MI->getOperand(0).getReg() == AArch64::D21
18307 || MI->getOperand(0).getReg() == AArch64::D22
18308 || MI->getOperand(0).getReg() == AArch64::D23
18309 || MI->getOperand(0).getReg() == AArch64::D24
18310 || MI->getOperand(0).getReg() == AArch64::D25
18311 || MI->getOperand(0).getReg() == AArch64::D26
18312 || MI->getOperand(0).getReg() == AArch64::D27
18313 || MI->getOperand(0).getReg() == AArch64::D28
18314 || MI->getOperand(0).getReg() == AArch64::D29
18315 || MI->getOperand(0).getReg() == AArch64::D30
18316 || MI->getOperand(0).getReg() == AArch64::D31
18322 MI->getOperand(0).getReg() == AArch64::Q0
18323 || MI->getOperand(0).getReg() == AArch64::Q1
18324 || MI->getOperand(0).getReg() == AArch64::Q2
18325 || MI->getOperand(0).getReg() == AArch64::Q3
18326 || MI->getOperand(0).getReg() == AArch64::Q4
18327 || MI->getOperand(0).getReg() == AArch64::Q5
18328 || MI->getOperand(0).getReg() == AArch64::Q6
18329 || MI->getOperand(0).getReg() == AArch64::Q7
18330 || MI->getOperand(0).getReg() == AArch64::Q8
18331 || MI->getOperand(0).getReg() == AArch64::Q9
18332 || MI->getOperand(0).getReg() == AArch64::Q10
18333 || MI->getOperand(0).getReg() == AArch64::Q11
18334 || MI->getOperand(0).getReg() == AArch64::Q12
18335 || MI->getOperand(0).getReg() == AArch64::Q13
18336 || MI->getOperand(0).getReg() == AArch64::Q14
18337 || MI->getOperand(0).getReg() == AArch64::Q15
18338 || MI->getOperand(0).getReg() == AArch64::Q16
18339 || MI->getOperand(0).getReg() == AArch64::Q17
18340 || MI->getOperand(0).getReg() == AArch64::Q18
18341 || MI->getOperand(0).getReg() == AArch64::Q19
18342 || MI->getOperand(0).getReg() == AArch64::Q20
18343 || MI->getOperand(0).getReg() == AArch64::Q21
18344 || MI->getOperand(0).getReg() == AArch64::Q22
18345 || MI->getOperand(0).getReg() == AArch64::Q23
18346 || MI->getOperand(0).getReg() == AArch64::Q24
18347 || MI->getOperand(0).getReg() == AArch64::Q25
18348 || MI->getOperand(0).getReg() == AArch64::Q26
18349 || MI->getOperand(0).getReg() == AArch64::Q27
18350 || MI->getOperand(0).getReg() == AArch64::Q28
18351 || MI->getOperand(0).getReg() == AArch64::Q29
18352 || MI->getOperand(0).getReg() == AArch64::Q30
18353 || MI->getOperand(0).getReg() == AArch64::Q31
18365 MI->getOperand(0).getReg() == AArch64::D0
18366 || MI->getOperand(0).getReg() == AArch64::D1
18367 || MI->getOperand(0).getReg() == AArch64::D2
18368 || MI->getOperand(0).getReg() == AArch64::D3
18369 || MI->getOperand(0).getReg() == AArch64::D4
18370 || MI->getOperand(0).getReg() == AArch64::D5
18371 || MI->getOperand(0).getReg() == AArch64::D6
18372 || MI->getOperand(0).getReg() == AArch64::D7
18373 || MI->getOperand(0).getReg() == AArch64::D8
18374 || MI->getOperand(0).getReg() == AArch64::D9
18375 || MI->getOperand(0).getReg() == AArch64::D10
18376 || MI->getOperand(0).getReg() == AArch64::D11
18377 || MI->getOperand(0).getReg() == AArch64::D12
18378 || MI->getOperand(0).getReg() == AArch64::D13
18379 || MI->getOperand(0).getReg() == AArch64::D14
18380 || MI->getOperand(0).getReg() == AArch64::D15
18381 || MI->getOperand(0).getReg() == AArch64::D16
18382 || MI->getOperand(0).getReg() == AArch64::D17
18383 || MI->getOperand(0).getReg() == AArch64::D18
18384 || MI->getOperand(0).getReg() == AArch64::D19
18385 || MI->getOperand(0).getReg() == AArch64::D20
18386 || MI->getOperand(0).getReg() == AArch64::D21
18387 || MI->getOperand(0).getReg() == AArch64::D22
18388 || MI->getOperand(0).getReg() == AArch64::D23
18389 || MI->getOperand(0).getReg() == AArch64::D24
18390 || MI->getOperand(0).getReg() == AArch64::D25
18391 || MI->getOperand(0).getReg() == AArch64::D26
18392 || MI->getOperand(0).getReg() == AArch64::D27
18393 || MI->getOperand(0).getReg() == AArch64::D28
18394 || MI->getOperand(0).getReg() == AArch64::D29
18395 || MI->getOperand(0).getReg() == AArch64::D30
18396 || MI->getOperand(0).getReg() == AArch64::D31
18402 MI->getOperand(0).getReg() == AArch64::Q0
18403 || MI->getOperand(0).getReg() == AArch64::Q1
18404 || MI->getOperand(0).getReg() == AArch64::Q2
18405 || MI->getOperand(0).getReg() == AArch64::Q3
18406 || MI->getOperand(0).getReg() == AArch64::Q4
18407 || MI->getOperand(0).getReg() == AArch64::Q5
18408 || MI->getOperand(0).getReg() == AArch64::Q6
18409 || MI->getOperand(0).getReg() == AArch64::Q7
18410 || MI->getOperand(0).getReg() == AArch64::Q8
18411 || MI->getOperand(0).getReg() == AArch64::Q9
18412 || MI->getOperand(0).getReg() == AArch64::Q10
18413 || MI->getOperand(0).getReg() == AArch64::Q11
18414 || MI->getOperand(0).getReg() == AArch64::Q12
18415 || MI->getOperand(0).getReg() == AArch64::Q13
18416 || MI->getOperand(0).getReg() == AArch64::Q14
18417 || MI->getOperand(0).getReg() == AArch64::Q15
18418 || MI->getOperand(0).getReg() == AArch64::Q16
18419 || MI->getOperand(0).getReg() == AArch64::Q17
18420 || MI->getOperand(0).getReg() == AArch64::Q18
18421 || MI->getOperand(0).getReg() == AArch64::Q19
18422 || MI->getOperand(0).getReg() == AArch64::Q20
18423 || MI->getOperand(0).getReg() == AArch64::Q21
18424 || MI->getOperand(0).getReg() == AArch64::Q22
18425 || MI->getOperand(0).getReg() == AArch64::Q23
18426 || MI->getOperand(0).getReg() == AArch64::Q24
18427 || MI->getOperand(0).getReg() == AArch64::Q25
18428 || MI->getOperand(0).getReg() == AArch64::Q26
18429 || MI->getOperand(0).getReg() == AArch64::Q27
18430 || MI->getOperand(0).getReg() == AArch64::Q28
18431 || MI->getOperand(0).getReg() == AArch64::Q29
18432 || MI->getOperand(0).getReg() == AArch64::Q30
18433 || MI->getOperand(0).getReg() == AArch64::Q31
18445 && MI->getOperand(0).getReg() == AArch64::LR
18453 && MI->getOperand(0).getReg() == AArch64::LR
18461 && MI->getOperand(0).getReg() == AArch64::LR
18575 MI->getOperand(0).getReg() == AArch64::Q0
18576 || MI->getOperand(0).getReg() == AArch64::Q1
18577 || MI->getOperand(0).getReg() == AArch64::Q2
18578 || MI->getOperand(0).getReg() == AArch64::Q3
18579 || MI->getOperand(0).getReg() == AArch64::Q4
18580 || MI->getOperand(0).getReg() == AArch64::Q5
18581 || MI->getOperand(0).getReg() == AArch64::Q6
18582 || MI->getOperand(0).getReg() == AArch64::Q7
18583 || MI->getOperand(0).getReg() == AArch64::Q8
18584 || MI->getOperand(0).getReg() == AArch64::Q9
18585 || MI->getOperand(0).getReg() == AArch64::Q10
18586 || MI->getOperand(0).getReg() == AArch64::Q11
18587 || MI->getOperand(0).getReg() == AArch64::Q12
18588 || MI->getOperand(0).getReg() == AArch64::Q13
18589 || MI->getOperand(0).getReg() == AArch64::Q14
18590 || MI->getOperand(0).getReg() == AArch64::Q15
18591 || MI->getOperand(0).getReg() == AArch64::Q16
18592 || MI->getOperand(0).getReg() == AArch64::Q17
18593 || MI->getOperand(0).getReg() == AArch64::Q18
18594 || MI->getOperand(0).getReg() == AArch64::Q19
18595 || MI->getOperand(0).getReg() == AArch64::Q20
18596 || MI->getOperand(0).getReg() == AArch64::Q21
18597 || MI->getOperand(0).getReg() == AArch64::Q22
18598 || MI->getOperand(0).getReg() == AArch64::Q23
18599 || MI->getOperand(0).getReg() == AArch64::Q24
18600 || MI->getOperand(0).getReg() == AArch64::Q25
18601 || MI->getOperand(0).getReg() == AArch64::Q26
18602 || MI->getOperand(0).getReg() == AArch64::Q27
18603 || MI->getOperand(0).getReg() == AArch64::Q28
18604 || MI->getOperand(0).getReg() == AArch64::Q29
18605 || MI->getOperand(0).getReg() == AArch64::Q30
18606 || MI->getOperand(0).getReg() == AArch64::Q31
20276 MI->getOperand(0).getReg() == AArch64::D0
20277 || MI->getOperand(0).getReg() == AArch64::D1
20278 || MI->getOperand(0).getReg() == AArch64::D2
20279 || MI->getOperand(0).getReg() == AArch64::D3
20280 || MI->getOperand(0).getReg() == AArch64::D4
20281 || MI->getOperand(0).getReg() == AArch64::D5
20282 || MI->getOperand(0).getReg() == AArch64::D6
20283 || MI->getOperand(0).getReg() == AArch64::D7
20284 || MI->getOperand(0).getReg() == AArch64::D8
20285 || MI->getOperand(0).getReg() == AArch64::D9
20286 || MI->getOperand(0).getReg() == AArch64::D10
20287 || MI->getOperand(0).getReg() == AArch64::D11
20288 || MI->getOperand(0).getReg() == AArch64::D12
20289 || MI->getOperand(0).getReg() == AArch64::D13
20290 || MI->getOperand(0).getReg() == AArch64::D14
20291 || MI->getOperand(0).getReg() == AArch64::D15
20292 || MI->getOperand(0).getReg() == AArch64::D16
20293 || MI->getOperand(0).getReg() == AArch64::D17
20294 || MI->getOperand(0).getReg() == AArch64::D18
20295 || MI->getOperand(0).getReg() == AArch64::D19
20296 || MI->getOperand(0).getReg() == AArch64::D20
20297 || MI->getOperand(0).getReg() == AArch64::D21
20298 || MI->getOperand(0).getReg() == AArch64::D22
20299 || MI->getOperand(0).getReg() == AArch64::D23
20300 || MI->getOperand(0).getReg() == AArch64::D24
20301 || MI->getOperand(0).getReg() == AArch64::D25
20302 || MI->getOperand(0).getReg() == AArch64::D26
20303 || MI->getOperand(0).getReg() == AArch64::D27
20304 || MI->getOperand(0).getReg() == AArch64::D28
20305 || MI->getOperand(0).getReg() == AArch64::D29
20306 || MI->getOperand(0).getReg() == AArch64::D30
20307 || MI->getOperand(0).getReg() == AArch64::D31
20313 MI->getOperand(0).getReg() == AArch64::Q0
20314 || MI->getOperand(0).getReg() == AArch64::Q1
20315 || MI->getOperand(0).getReg() == AArch64::Q2
20316 || MI->getOperand(0).getReg() == AArch64::Q3
20317 || MI->getOperand(0).getReg() == AArch64::Q4
20318 || MI->getOperand(0).getReg() == AArch64::Q5
20319 || MI->getOperand(0).getReg() == AArch64::Q6
20320 || MI->getOperand(0).getReg() == AArch64::Q7
20321 || MI->getOperand(0).getReg() == AArch64::Q8
20322 || MI->getOperand(0).getReg() == AArch64::Q9
20323 || MI->getOperand(0).getReg() == AArch64::Q10
20324 || MI->getOperand(0).getReg() == AArch64::Q11
20325 || MI->getOperand(0).getReg() == AArch64::Q12
20326 || MI->getOperand(0).getReg() == AArch64::Q13
20327 || MI->getOperand(0).getReg() == AArch64::Q14
20328 || MI->getOperand(0).getReg() == AArch64::Q15
20329 || MI->getOperand(0).getReg() == AArch64::Q16
20330 || MI->getOperand(0).getReg() == AArch64::Q17
20331 || MI->getOperand(0).getReg() == AArch64::Q18
20332 || MI->getOperand(0).getReg() == AArch64::Q19
20333 || MI->getOperand(0).getReg() == AArch64::Q20
20334 || MI->getOperand(0).getReg() == AArch64::Q21
20335 || MI->getOperand(0).getReg() == AArch64::Q22
20336 || MI->getOperand(0).getReg() == AArch64::Q23
20337 || MI->getOperand(0).getReg() == AArch64::Q24
20338 || MI->getOperand(0).getReg() == AArch64::Q25
20339 || MI->getOperand(0).getReg() == AArch64::Q26
20340 || MI->getOperand(0).getReg() == AArch64::Q27
20341 || MI->getOperand(0).getReg() == AArch64::Q28
20342 || MI->getOperand(0).getReg() == AArch64::Q29
20343 || MI->getOperand(0).getReg() == AArch64::Q30
20344 || MI->getOperand(0).getReg() == AArch64::Q31
20357 MI->getOperand(0).getReg() == AArch64::Q0
20358 || MI->getOperand(0).getReg() == AArch64::Q1
20359 || MI->getOperand(0).getReg() == AArch64::Q2
20360 || MI->getOperand(0).getReg() == AArch64::Q3
20361 || MI->getOperand(0).getReg() == AArch64::Q4
20362 || MI->getOperand(0).getReg() == AArch64::Q5
20363 || MI->getOperand(0).getReg() == AArch64::Q6
20364 || MI->getOperand(0).getReg() == AArch64::Q7
20365 || MI->getOperand(0).getReg() == AArch64::Q8
20366 || MI->getOperand(0).getReg() == AArch64::Q9
20367 || MI->getOperand(0).getReg() == AArch64::Q10
20368 || MI->getOperand(0).getReg() == AArch64::Q11
20369 || MI->getOperand(0).getReg() == AArch64::Q12
20370 || MI->getOperand(0).getReg() == AArch64::Q13
20371 || MI->getOperand(0).getReg() == AArch64::Q14
20372 || MI->getOperand(0).getReg() == AArch64::Q15
20373 || MI->getOperand(0).getReg() == AArch64::Q16
20374 || MI->getOperand(0).getReg() == AArch64::Q17
20375 || MI->getOperand(0).getReg() == AArch64::Q18
20376 || MI->getOperand(0).getReg() == AArch64::Q19
20377 || MI->getOperand(0).getReg() == AArch64::Q20
20378 || MI->getOperand(0).getReg() == AArch64::Q21
20379 || MI->getOperand(0).getReg() == AArch64::Q22
20380 || MI->getOperand(0).getReg() == AArch64::Q23
20381 || MI->getOperand(0).getReg() == AArch64::Q24
20382 || MI->getOperand(0).getReg() == AArch64::Q25
20383 || MI->getOperand(0).getReg() == AArch64::Q26
20384 || MI->getOperand(0).getReg() == AArch64::Q27
20385 || MI->getOperand(0).getReg() == AArch64::Q28
20386 || MI->getOperand(0).getReg() == AArch64::Q29
20387 || MI->getOperand(0).getReg() == AArch64::Q30
20388 || MI->getOperand(0).getReg() == AArch64::Q31
20606 if (MI->getOperand(1).getReg() == AArch64::WZR ||
20608 MI->getOperand(1).getReg() == AArch64::XZR)
20857 MI->getOperand(0).getReg() == AArch64::D0
20858 || MI->getOperand(0).getReg() == AArch64::D1
20859 || MI->getOperand(0).getReg() == AArch64::D2
20860 || MI->getOperand(0).getReg() == AArch64::D3
20861 || MI->getOperand(0).getReg() == AArch64::D4
20862 || MI->getOperand(0).getReg() == AArch64::D5
20863 || MI->getOperand(0).getReg() == AArch64::D6
20864 || MI->getOperand(0).getReg() == AArch64::D7
20865 || MI->getOperand(0).getReg() == AArch64::D8
20866 || MI->getOperand(0).getReg() == AArch64::D9
20867 || MI->getOperand(0).getReg() == AArch64::D10
20868 || MI->getOperand(0).getReg() == AArch64::D11
20869 || MI->getOperand(0).getReg() == AArch64::D12
20870 || MI->getOperand(0).getReg() == AArch64::D13
20871 || MI->getOperand(0).getReg() == AArch64::D14
20872 || MI->getOperand(0).getReg() == AArch64::D15
20873 || MI->getOperand(0).getReg() == AArch64::D16
20874 || MI->getOperand(0).getReg() == AArch64::D17
20875 || MI->getOperand(0).getReg() == AArch64::D18
20876 || MI->getOperand(0).getReg() == AArch64::D19
20877 || MI->getOperand(0).getReg() == AArch64::D20
20878 || MI->getOperand(0).getReg() == AArch64::D21
20879 || MI->getOperand(0).getReg() == AArch64::D22
20880 || MI->getOperand(0).getReg() == AArch64::D23
20881 || MI->getOperand(0).getReg() == AArch64::D24
20882 || MI->getOperand(0).getReg() == AArch64::D25
20883 || MI->getOperand(0).getReg() == AArch64::D26
20884 || MI->getOperand(0).getReg() == AArch64::D27
20885 || MI->getOperand(0).getReg() == AArch64::D28
20886 || MI->getOperand(0).getReg() == AArch64::D29
20887 || MI->getOperand(0).getReg() == AArch64::D30
20888 || MI->getOperand(0).getReg() == AArch64::D31
20894 MI->getOperand(0).getReg() == AArch64::Q0
20895 || MI->getOperand(0).getReg() == AArch64::Q1
20896 || MI->getOperand(0).getReg() == AArch64::Q2
20897 || MI->getOperand(0).getReg() == AArch64::Q3
20898 || MI->getOperand(0).getReg() == AArch64::Q4
20899 || MI->getOperand(0).getReg() == AArch64::Q5
20900 || MI->getOperand(0).getReg() == AArch64::Q6
20901 || MI->getOperand(0).getReg() == AArch64::Q7
20902 || MI->getOperand(0).getReg() == AArch64::Q8
20903 || MI->getOperand(0).getReg() == AArch64::Q9
20904 || MI->getOperand(0).getReg() == AArch64::Q10
20905 || MI->getOperand(0).getReg() == AArch64::Q11
20906 || MI->getOperand(0).getReg() == AArch64::Q12
20907 || MI->getOperand(0).getReg() == AArch64::Q13
20908 || MI->getOperand(0).getReg() == AArch64::Q14
20909 || MI->getOperand(0).getReg() == AArch64::Q15
20910 || MI->getOperand(0).getReg() == AArch64::Q16
20911 || MI->getOperand(0).getReg() == AArch64::Q17
20912 || MI->getOperand(0).getReg() == AArch64::Q18
20913 || MI->getOperand(0).getReg() == AArch64::Q19
20914 || MI->getOperand(0).getReg() == AArch64::Q20
20915 || MI->getOperand(0).getReg() == AArch64::Q21
20916 || MI->getOperand(0).getReg() == AArch64::Q22
20917 || MI->getOperand(0).getReg() == AArch64::Q23
20918 || MI->getOperand(0).getReg() == AArch64::Q24
20919 || MI->getOperand(0).getReg() == AArch64::Q25
20920 || MI->getOperand(0).getReg() == AArch64::Q26
20921 || MI->getOperand(0).getReg() == AArch64::Q27
20922 || MI->getOperand(0).getReg() == AArch64::Q28
20923 || MI->getOperand(0).getReg() == AArch64::Q29
20924 || MI->getOperand(0).getReg() == AArch64::Q30
20925 || MI->getOperand(0).getReg() == AArch64::Q31
20933 if (MI->getOperand(1).getReg() == AArch64::WZR ||
20935 MI->getOperand(1).getReg() == AArch64::XZR)
21387 if (MI->getOperand(1).getReg() == AArch64::WZR ||
21389 MI->getOperand(1).getReg() == AArch64::XZR)
21400 MI->getOperand(0).getReg() == AArch64::D0
21401 || MI->getOperand(0).getReg() == AArch64::D1
21402 || MI->getOperand(0).getReg() == AArch64::D2
21403 || MI->getOperand(0).getReg() == AArch64::D3
21404 || MI->getOperand(0).getReg() == AArch64::D4
21405 || MI->getOperand(0).getReg() == AArch64::D5
21406 || MI->getOperand(0).getReg() == AArch64::D6
21407 || MI->getOperand(0).getReg() == AArch64::D7
21408 || MI->getOperand(0).getReg() == AArch64::D8
21409 || MI->getOperand(0).getReg() == AArch64::D9
21410 || MI->getOperand(0).getReg() == AArch64::D10
21411 || MI->getOperand(0).getReg() == AArch64::D11
21412 || MI->getOperand(0).getReg() == AArch64::D12
21413 || MI->getOperand(0).getReg() == AArch64::D13
21414 || MI->getOperand(0).getReg() == AArch64::D14
21415 || MI->getOperand(0).getReg() == AArch64::D15
21416 || MI->getOperand(0).getReg() == AArch64::D16
21417 || MI->getOperand(0).getReg() == AArch64::D17
21418 || MI->getOperand(0).getReg() == AArch64::D18
21419 || MI->getOperand(0).getReg() == AArch64::D19
21420 || MI->getOperand(0).getReg() == AArch64::D20
21421 || MI->getOperand(0).getReg() == AArch64::D21
21422 || MI->getOperand(0).getReg() == AArch64::D22
21423 || MI->getOperand(0).getReg() == AArch64::D23
21424 || MI->getOperand(0).getReg() == AArch64::D24
21425 || MI->getOperand(0).getReg() == AArch64::D25
21426 || MI->getOperand(0).getReg() == AArch64::D26
21427 || MI->getOperand(0).getReg() == AArch64::D27
21428 || MI->getOperand(0).getReg() == AArch64::D28
21429 || MI->getOperand(0).getReg() == AArch64::D29
21430 || MI->getOperand(0).getReg() == AArch64::D30
21431 || MI->getOperand(0).getReg() == AArch64::D31
21437 MI->getOperand(0).getReg() == AArch64::Q0
21438 || MI->getOperand(0).getReg() == AArch64::Q1
21439 || MI->getOperand(0).getReg() == AArch64::Q2
21440 || MI->getOperand(0).getReg() == AArch64::Q3
21441 || MI->getOperand(0).getReg() == AArch64::Q4
21442 || MI->getOperand(0).getReg() == AArch64::Q5
21443 || MI->getOperand(0).getReg() == AArch64::Q6
21444 || MI->getOperand(0).getReg() == AArch64::Q7
21445 || MI->getOperand(0).getReg() == AArch64::Q8
21446 || MI->getOperand(0).getReg() == AArch64::Q9
21447 || MI->getOperand(0).getReg() == AArch64::Q10
21448 || MI->getOperand(0).getReg() == AArch64::Q11
21449 || MI->getOperand(0).getReg() == AArch64::Q12
21450 || MI->getOperand(0).getReg() == AArch64::Q13
21451 || MI->getOperand(0).getReg() == AArch64::Q14
21452 || MI->getOperand(0).getReg() == AArch64::Q15
21453 || MI->getOperand(0).getReg() == AArch64::Q16
21454 || MI->getOperand(0).getReg() == AArch64::Q17
21455 || MI->getOperand(0).getReg() == AArch64::Q18
21456 || MI->getOperand(0).getReg() == AArch64::Q19
21457 || MI->getOperand(0).getReg() == AArch64::Q20
21458 || MI->getOperand(0).getReg() == AArch64::Q21
21459 || MI->getOperand(0).getReg() == AArch64::Q22
21460 || MI->getOperand(0).getReg() == AArch64::Q23
21461 || MI->getOperand(0).getReg() == AArch64::Q24
21462 || MI->getOperand(0).getReg() == AArch64::Q25
21463 || MI->getOperand(0).getReg() == AArch64::Q26
21464 || MI->getOperand(0).getReg() == AArch64::Q27
21465 || MI->getOperand(0).getReg() == AArch64::Q28
21466 || MI->getOperand(0).getReg() == AArch64::Q29
21467 || MI->getOperand(0).getReg() == AArch64::Q30
21468 || MI->getOperand(0).getReg() == AArch64::Q31
21482 MI->getOperand(0).getReg() == AArch64::D0
21483 || MI->getOperand(0).getReg() == AArch64::D1
21484 || MI->getOperand(0).getReg() == AArch64::D2
21485 || MI->getOperand(0).getReg() == AArch64::D3
21486 || MI->getOperand(0).getReg() == AArch64::D4
21487 || MI->getOperand(0).getReg() == AArch64::D5
21488 || MI->getOperand(0).getReg() == AArch64::D6
21489 || MI->getOperand(0).getReg() == AArch64::D7
21490 || MI->getOperand(0).getReg() == AArch64::D8
21491 || MI->getOperand(0).getReg() == AArch64::D9
21492 || MI->getOperand(0).getReg() == AArch64::D10
21493 || MI->getOperand(0).getReg() == AArch64::D11
21494 || MI->getOperand(0).getReg() == AArch64::D12
21495 || MI->getOperand(0).getReg() == AArch64::D13
21496 || MI->getOperand(0).getReg() == AArch64::D14
21497 || MI->getOperand(0).getReg() == AArch64::D15
21498 || MI->getOperand(0).getReg() == AArch64::D16
21499 || MI->getOperand(0).getReg() == AArch64::D17
21500 || MI->getOperand(0).getReg() == AArch64::D18
21501 || MI->getOperand(0).getReg() == AArch64::D19
21502 || MI->getOperand(0).getReg() == AArch64::D20
21503 || MI->getOperand(0).getReg() == AArch64::D21
21504 || MI->getOperand(0).getReg() == AArch64::D22
21505 || MI->getOperand(0).getReg() == AArch64::D23
21506 || MI->getOperand(0).getReg() == AArch64::D24
21507 || MI->getOperand(0).getReg() == AArch64::D25
21508 || MI->getOperand(0).getReg() == AArch64::D26
21509 || MI->getOperand(0).getReg() == AArch64::D27
21510 || MI->getOperand(0).getReg() == AArch64::D28
21511 || MI->getOperand(0).getReg() == AArch64::D29
21512 || MI->getOperand(0).getReg() == AArch64::D30
21513 || MI->getOperand(0).getReg() == AArch64::D31
21519 MI->getOperand(0).getReg() == AArch64::Q0
21520 || MI->getOperand(0).getReg() == AArch64::Q1
21521 || MI->getOperand(0).getReg() == AArch64::Q2
21522 || MI->getOperand(0).getReg() == AArch64::Q3
21523 || MI->getOperand(0).getReg() == AArch64::Q4
21524 || MI->getOperand(0).getReg() == AArch64::Q5
21525 || MI->getOperand(0).getReg() == AArch64::Q6
21526 || MI->getOperand(0).getReg() == AArch64::Q7
21527 || MI->getOperand(0).getReg() == AArch64::Q8
21528 || MI->getOperand(0).getReg() == AArch64::Q9
21529 || MI->getOperand(0).getReg() == AArch64::Q10
21530 || MI->getOperand(0).getReg() == AArch64::Q11
21531 || MI->getOperand(0).getReg() == AArch64::Q12
21532 || MI->getOperand(0).getReg() == AArch64::Q13
21533 || MI->getOperand(0).getReg() == AArch64::Q14
21534 || MI->getOperand(0).getReg() == AArch64::Q15
21535 || MI->getOperand(0).getReg() == AArch64::Q16
21536 || MI->getOperand(0).getReg() == AArch64::Q17
21537 || MI->getOperand(0).getReg() == AArch64::Q18
21538 || MI->getOperand(0).getReg() == AArch64::Q19
21539 || MI->getOperand(0).getReg() == AArch64::Q20
21540 || MI->getOperand(0).getReg() == AArch64::Q21
21541 || MI->getOperand(0).getReg() == AArch64::Q22
21542 || MI->getOperand(0).getReg() == AArch64::Q23
21543 || MI->getOperand(0).getReg() == AArch64::Q24
21544 || MI->getOperand(0).getReg() == AArch64::Q25
21545 || MI->getOperand(0).getReg() == AArch64::Q26
21546 || MI->getOperand(0).getReg() == AArch64::Q27
21547 || MI->getOperand(0).getReg() == AArch64::Q28
21548 || MI->getOperand(0).getReg() == AArch64::Q29
21549 || MI->getOperand(0).getReg() == AArch64::Q30
21550 || MI->getOperand(0).getReg() == AArch64::Q31
21558 if (MI->getOperand(1).getReg() == AArch64::WZR ||
21560 MI->getOperand(1).getReg() == AArch64::XZR)
22066 MI->getOperand(0).getReg() == AArch64::D0
22067 || MI->getOperand(0).getReg() == AArch64::D1
22068 || MI->getOperand(0).getReg() == AArch64::D2
22069 || MI->getOperand(0).getReg() == AArch64::D3
22070 || MI->getOperand(0).getReg() == AArch64::D4
22071 || MI->getOperand(0).getReg() == AArch64::D5
22072 || MI->getOperand(0).getReg() == AArch64::D6
22073 || MI->getOperand(0).getReg() == AArch64::D7
22074 || MI->getOperand(0).getReg() == AArch64::D8
22075 || MI->getOperand(0).getReg() == AArch64::D9
22076 || MI->getOperand(0).getReg() == AArch64::D10
22077 || MI->getOperand(0).getReg() == AArch64::D11
22078 || MI->getOperand(0).getReg() == AArch64::D12
22079 || MI->getOperand(0).getReg() == AArch64::D13
22080 || MI->getOperand(0).getReg() == AArch64::D14
22081 || MI->getOperand(0).getReg() == AArch64::D15
22082 || MI->getOperand(0).getReg() == AArch64::D16
22083 || MI->getOperand(0).getReg() == AArch64::D17
22084 || MI->getOperand(0).getReg() == AArch64::D18
22085 || MI->getOperand(0).getReg() == AArch64::D19
22086 || MI->getOperand(0).getReg() == AArch64::D20
22087 || MI->getOperand(0).getReg() == AArch64::D21
22088 || MI->getOperand(0).getReg() == AArch64::D22
22089 || MI->getOperand(0).getReg() == AArch64::D23
22090 || MI->getOperand(0).getReg() == AArch64::D24
22091 || MI->getOperand(0).getReg() == AArch64::D25
22092 || MI->getOperand(0).getReg() == AArch64::D26
22093 || MI->getOperand(0).getReg() == AArch64::D27
22094 || MI->getOperand(0).getReg() == AArch64::D28
22095 || MI->getOperand(0).getReg() == AArch64::D29
22096 || MI->getOperand(0).getReg() == AArch64::D30
22097 || MI->getOperand(0).getReg() == AArch64::D31
22103 MI->getOperand(0).getReg() == AArch64::Q0
22104 || MI->getOperand(0).getReg() == AArch64::Q1
22105 || MI->getOperand(0).getReg() == AArch64::Q2
22106 || MI->getOperand(0).getReg() == AArch64::Q3
22107 || MI->getOperand(0).getReg() == AArch64::Q4
22108 || MI->getOperand(0).getReg() == AArch64::Q5
22109 || MI->getOperand(0).getReg() == AArch64::Q6
22110 || MI->getOperand(0).getReg() == AArch64::Q7
22111 || MI->getOperand(0).getReg() == AArch64::Q8
22112 || MI->getOperand(0).getReg() == AArch64::Q9
22113 || MI->getOperand(0).getReg() == AArch64::Q10
22114 || MI->getOperand(0).getReg() == AArch64::Q11
22115 || MI->getOperand(0).getReg() == AArch64::Q12
22116 || MI->getOperand(0).getReg() == AArch64::Q13
22117 || MI->getOperand(0).getReg() == AArch64::Q14
22118 || MI->getOperand(0).getReg() == AArch64::Q15
22119 || MI->getOperand(0).getReg() == AArch64::Q16
22120 || MI->getOperand(0).getReg() == AArch64::Q17
22121 || MI->getOperand(0).getReg() == AArch64::Q18
22122 || MI->getOperand(0).getReg() == AArch64::Q19
22123 || MI->getOperand(0).getReg() == AArch64::Q20
22124 || MI->getOperand(0).getReg() == AArch64::Q21
22125 || MI->getOperand(0).getReg() == AArch64::Q22
22126 || MI->getOperand(0).getReg() == AArch64::Q23
22127 || MI->getOperand(0).getReg() == AArch64::Q24
22128 || MI->getOperand(0).getReg() == AArch64::Q25
22129 || MI->getOperand(0).getReg() == AArch64::Q26
22130 || MI->getOperand(0).getReg() == AArch64::Q27
22131 || MI->getOperand(0).getReg() == AArch64::Q28
22132 || MI->getOperand(0).getReg() == AArch64::Q29
22133 || MI->getOperand(0).getReg() == AArch64::Q30
22134 || MI->getOperand(0).getReg() == AArch64::Q31
22148 MI->getOperand(0).getReg() == AArch64::D0
22149 || MI->getOperand(0).getReg() == AArch64::D1
22150 || MI->getOperand(0).getReg() == AArch64::D2
22151 || MI->getOperand(0).getReg() == AArch64::D3
22152 || MI->getOperand(0).getReg() == AArch64::D4
22153 || MI->getOperand(0).getReg() == AArch64::D5
22154 || MI->getOperand(0).getReg() == AArch64::D6
22155 || MI->getOperand(0).getReg() == AArch64::D7
22156 || MI->getOperand(0).getReg() == AArch64::D8
22157 || MI->getOperand(0).getReg() == AArch64::D9
22158 || MI->getOperand(0).getReg() == AArch64::D10
22159 || MI->getOperand(0).getReg() == AArch64::D11
22160 || MI->getOperand(0).getReg() == AArch64::D12
22161 || MI->getOperand(0).getReg() == AArch64::D13
22162 || MI->getOperand(0).getReg() == AArch64::D14
22163 || MI->getOperand(0).getReg() == AArch64::D15
22164 || MI->getOperand(0).getReg() == AArch64::D16
22165 || MI->getOperand(0).getReg() == AArch64::D17
22166 || MI->getOperand(0).getReg() == AArch64::D18
22167 || MI->getOperand(0).getReg() == AArch64::D19
22168 || MI->getOperand(0).getReg() == AArch64::D20
22169 || MI->getOperand(0).getReg() == AArch64::D21
22170 || MI->getOperand(0).getReg() == AArch64::D22
22171 || MI->getOperand(0).getReg() == AArch64::D23
22172 || MI->getOperand(0).getReg() == AArch64::D24
22173 || MI->getOperand(0).getReg() == AArch64::D25
22174 || MI->getOperand(0).getReg() == AArch64::D26
22175 || MI->getOperand(0).getReg() == AArch64::D27
22176 || MI->getOperand(0).getReg() == AArch64::D28
22177 || MI->getOperand(0).getReg() == AArch64::D29
22178 || MI->getOperand(0).getReg() == AArch64::D30
22179 || MI->getOperand(0).getReg() == AArch64::D31
22185 MI->getOperand(0).getReg() == AArch64::Q0
22186 || MI->getOperand(0).getReg() == AArch64::Q1
22187 || MI->getOperand(0).getReg() == AArch64::Q2
22188 || MI->getOperand(0).getReg() == AArch64::Q3
22189 || MI->getOperand(0).getReg() == AArch64::Q4
22190 || MI->getOperand(0).getReg() == AArch64::Q5
22191 || MI->getOperand(0).getReg() == AArch64::Q6
22192 || MI->getOperand(0).getReg() == AArch64::Q7
22193 || MI->getOperand(0).getReg() == AArch64::Q8
22194 || MI->getOperand(0).getReg() == AArch64::Q9
22195 || MI->getOperand(0).getReg() == AArch64::Q10
22196 || MI->getOperand(0).getReg() == AArch64::Q11
22197 || MI->getOperand(0).getReg() == AArch64::Q12
22198 || MI->getOperand(0).getReg() == AArch64::Q13
22199 || MI->getOperand(0).getReg() == AArch64::Q14
22200 || MI->getOperand(0).getReg() == AArch64::Q15
22201 || MI->getOperand(0).getReg() == AArch64::Q16
22202 || MI->getOperand(0).getReg() == AArch64::Q17
22203 || MI->getOperand(0).getReg() == AArch64::Q18
22204 || MI->getOperand(0).getReg() == AArch64::Q19
22205 || MI->getOperand(0).getReg() == AArch64::Q20
22206 || MI->getOperand(0).getReg() == AArch64::Q21
22207 || MI->getOperand(0).getReg() == AArch64::Q22
22208 || MI->getOperand(0).getReg() == AArch64::Q23
22209 || MI->getOperand(0).getReg() == AArch64::Q24
22210 || MI->getOperand(0).getReg() == AArch64::Q25
22211 || MI->getOperand(0).getReg() == AArch64::Q26
22212 || MI->getOperand(0).getReg() == AArch64::Q27
22213 || MI->getOperand(0).getReg() == AArch64::Q28
22214 || MI->getOperand(0).getReg() == AArch64::Q29
22215 || MI->getOperand(0).getReg() == AArch64::Q30
22216 || MI->getOperand(0).getReg() == AArch64::Q31
22230 MI->getOperand(0).getReg() == AArch64::D0
22231 || MI->getOperand(0).getReg() == AArch64::D1
22232 || MI->getOperand(0).getReg() == AArch64::D2
22233 || MI->getOperand(0).getReg() == AArch64::D3
22234 || MI->getOperand(0).getReg() == AArch64::D4
22235 || MI->getOperand(0).getReg() == AArch64::D5
22236 || MI->getOperand(0).getReg() == AArch64::D6
22237 || MI->getOperand(0).getReg() == AArch64::D7
22238 || MI->getOperand(0).getReg() == AArch64::D8
22239 || MI->getOperand(0).getReg() == AArch64::D9
22240 || MI->getOperand(0).getReg() == AArch64::D10
22241 || MI->getOperand(0).getReg() == AArch64::D11
22242 || MI->getOperand(0).getReg() == AArch64::D12
22243 || MI->getOperand(0).getReg() == AArch64::D13
22244 || MI->getOperand(0).getReg() == AArch64::D14
22245 || MI->getOperand(0).getReg() == AArch64::D15
22246 || MI->getOperand(0).getReg() == AArch64::D16
22247 || MI->getOperand(0).getReg() == AArch64::D17
22248 || MI->getOperand(0).getReg() == AArch64::D18
22249 || MI->getOperand(0).getReg() == AArch64::D19
22250 || MI->getOperand(0).getReg() == AArch64::D20
22251 || MI->getOperand(0).getReg() == AArch64::D21
22252 || MI->getOperand(0).getReg() == AArch64::D22
22253 || MI->getOperand(0).getReg() == AArch64::D23
22254 || MI->getOperand(0).getReg() == AArch64::D24
22255 || MI->getOperand(0).getReg() == AArch64::D25
22256 || MI->getOperand(0).getReg() == AArch64::D26
22257 || MI->getOperand(0).getReg() == AArch64::D27
22258 || MI->getOperand(0).getReg() == AArch64::D28
22259 || MI->getOperand(0).getReg() == AArch64::D29
22260 || MI->getOperand(0).getReg() == AArch64::D30
22261 || MI->getOperand(0).getReg() == AArch64::D31
22267 MI->getOperand(0).getReg() == AArch64::Q0
22268 || MI->getOperand(0).getReg() == AArch64::Q1
22269 || MI->getOperand(0).getReg() == AArch64::Q2
22270 || MI->getOperand(0).getReg() == AArch64::Q3
22271 || MI->getOperand(0).getReg() == AArch64::Q4
22272 || MI->getOperand(0).getReg() == AArch64::Q5
22273 || MI->getOperand(0).getReg() == AArch64::Q6
22274 || MI->getOperand(0).getReg() == AArch64::Q7
22275 || MI->getOperand(0).getReg() == AArch64::Q8
22276 || MI->getOperand(0).getReg() == AArch64::Q9
22277 || MI->getOperand(0).getReg() == AArch64::Q10
22278 || MI->getOperand(0).getReg() == AArch64::Q11
22279 || MI->getOperand(0).getReg() == AArch64::Q12
22280 || MI->getOperand(0).getReg() == AArch64::Q13
22281 || MI->getOperand(0).getReg() == AArch64::Q14
22282 || MI->getOperand(0).getReg() == AArch64::Q15
22283 || MI->getOperand(0).getReg() == AArch64::Q16
22284 || MI->getOperand(0).getReg() == AArch64::Q17
22285 || MI->getOperand(0).getReg() == AArch64::Q18
22286 || MI->getOperand(0).getReg() == AArch64::Q19
22287 || MI->getOperand(0).getReg() == AArch64::Q20
22288 || MI->getOperand(0).getReg() == AArch64::Q21
22289 || MI->getOperand(0).getReg() == AArch64::Q22
22290 || MI->getOperand(0).getReg() == AArch64::Q23
22291 || MI->getOperand(0).getReg() == AArch64::Q24
22292 || MI->getOperand(0).getReg() == AArch64::Q25
22293 || MI->getOperand(0).getReg() == AArch64::Q26
22294 || MI->getOperand(0).getReg() == AArch64::Q27
22295 || MI->getOperand(0).getReg() == AArch64::Q28
22296 || MI->getOperand(0).getReg() == AArch64::Q29
22297 || MI->getOperand(0).getReg() == AArch64::Q30
22298 || MI->getOperand(0).getReg() == AArch64::Q31
include/llvm/CodeGen/GlobalISel/CallLowering.h 64 assert((Ty->isVoidTy() == (Regs.empty() || Regs[0] == 0)) &&
268 assert(SwiftErrorVReg == 0 && "attempt to use unsupported swifterror");
lib/CodeGen/AggressiveAntiDepBreaker.cpp 236 if (Reg == 0)
369 if (Reg == 0) continue;
379 if (Reg == 0) continue;
422 if (Reg == 0) continue;
475 if (Reg == 0) continue;
510 if (Reg == 0) continue;
lib/CodeGen/CriticalAntiDepBreaker.cpp 191 if (Reg == 0) continue;
276 if (Reg == 0) continue;
307 if (Reg == 0) continue;
617 if (Reg == 0) continue;
lib/CodeGen/GlobalISel/IRTranslator.cpp 1554 assert(SwiftInVReg == 0 && "Expected only one swift error argument");
lib/CodeGen/GlobalISel/MachineIRBuilder.cpp 235 assert(Res == 0 && "Res is a result argument");
lib/CodeGen/GlobalISel/RegisterBankInfo.cpp 700 assert(NewVReg == 0 && "Register has already been created");
721 assert(NewVRegs[OpToNewVRegIdx[OpIdx] + PartialMapIdx] == 0 &&
lib/CodeGen/GlobalISel/Utils.cpp 138 if (Reg == 0)
lib/CodeGen/LiveDebugValues.cpp 697 assert(MI.getOperand(0).isReg() && MI.getOperand(0).getReg() == 0 &&
lib/CodeGen/LiveDebugVariables.cpp 229 if (LocMO.getReg() == 0)
lib/CodeGen/LivePhysRegs.cpp 296 if (Reg == 0)
313 if (Reg == 0)
lib/CodeGen/LiveVariables.cpp 216 if (!MO.isReg() || !MO.isDef() || MO.getReg() == 0)
521 if (!MO.isReg() || MO.getReg() == 0)
lib/CodeGen/MachineBasicBlock.cpp 908 if (!OI->isReg() || OI->getReg() == 0 ||
929 if (!OI->isReg() || OI->getReg() == 0)
lib/CodeGen/MachineLICM.cpp 1013 if (Reg == 0) continue;
1379 assert((!MO.isReg() || MO.getReg() == 0 ||
lib/CodeGen/MachineSink.cpp 443 if (Reg == 0)
642 if (Reg == 0) continue;
882 if (Reg == 0 || !Register::isPhysicalRegister(Reg))
lib/CodeGen/ModuloSchedule.cpp 1500 if (R == 0) {
lib/CodeGen/TargetInstrInfo.cpp 928 if (Reg == 0)
lib/CodeGen/VirtRegMap.cpp 85 assert(Virt2PhysMap[virtReg.id()] == NO_PHYS_REG &&
lib/Target/AArch64/AArch64CondBrTuning.cpp 94 if (MO.isReg() && MO.isDead() && MO.getReg() == AArch64::NZCV)
lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp 115 if (DstReg == AArch64::XZR || DstReg == AArch64::WZR) {
115 if (DstReg == AArch64::XZR || DstReg == AArch64::WZR) {
lib/Target/AArch64/AArch64FalkorHWPFFix.cpp 646 if (BaseReg == AArch64::SP || BaseReg == AArch64::WSP)
646 if (BaseReg == AArch64::SP || BaseReg == AArch64::WSP)
lib/Target/AArch64/AArch64FrameLowering.cpp 518 if (Reg0 == AArch64::FP && Reg1 == AArch64::LR)
518 if (Reg0 == AArch64::FP && Reg1 == AArch64::LR)
567 if (Reg0 == AArch64::FP && Reg1 == AArch64::LR)
567 if (Reg0 == AArch64::FP && Reg1 == AArch64::LR)
705 assert(MBBI->getOperand(OpndIdx - 1).getReg() == AArch64::SP &&
766 assert(MI.getOperand(OffsetIdx - 1).getReg() == AArch64::SP &&
1547 Prev->getOperand(0).getReg() == AArch64::SP)
lib/Target/AArch64/AArch64InstrInfo.cpp 701 (MI.getOperand(1).getReg() == AArch64::WZR ||
702 MI.getOperand(1).getReg() == AArch64::XZR))
1589 return MI.getOperand(1).getReg() == AArch64::WZR;
1591 return MI.getOperand(1).getReg() == AArch64::XZR;
1593 return MI.getOperand(1).getReg() == AArch64::WZR;
1611 if (MI.getOperand(1).getReg() == AArch64::XZR) {
3197 if (SrcReg == AArch64::SP && Register::isVirtualRegister(DstReg)) {
3201 if (DstReg == AArch64::SP && Register::isVirtualRegister(SrcReg)) {
4855 if (!(DefMI->getOperand(1).getReg() == AArch64::WZR &&
4856 DefMI->getOperand(2).getReg() == AArch64::WZR) &&
4857 !(DefMI->getOperand(1).getReg() == AArch64::XZR &&
4858 DefMI->getOperand(2).getReg() == AArch64::XZR))
5411 (MOP.getReg() == AArch64::LR || MOP.getReg() == AArch64::W30))
5411 (MOP.getReg() == AArch64::LR || MOP.getReg() == AArch64::W30))
5712 MI.getOperand(1).getReg() == AArch64::WZR &&
5720 MI.getOperand(1).getReg() == AArch64::XZR &&
lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp 639 getLdStRegOp(MI).getReg() == AArch64::WZR;
lib/Target/AArch64/AArch64RedundantCopyElimination.cpp 386 ((IsCopy && (SrcReg == AArch64::XZR || SrcReg == AArch64::WZR)) ||
386 ((IsCopy && (SrcReg == AArch64::XZR || SrcReg == AArch64::WZR)) ||
lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp 74 return Reg == AMDGPU::SCC;
123 if (SrcReg == AMDGPU::SCC) {
lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp 787 bool First = CondReg == AMDGPU::NoRegister;
882 bool First = CondReg == AMDGPU::NoRegister;
lib/Target/AMDGPU/GCNHazardRecognizer.cpp 999 (MI->getOperand(0).getReg() == AMDGPU::SGPR_NULL);
1093 I->getOperand(0).getReg() == AMDGPU::SGPR_NULL &&
1115 I->getOperand(0).getReg() == AMDGPU::SGPR_NULL &&
lib/Target/AMDGPU/R600EmitClauseMarkers.cpp 79 if (MO.isReg() && MO.getReg() == R600::ALU_LITERAL_X)
lib/Target/AMDGPU/R600InstrInfo.cpp 297 if (Reg == R600::ALU_CONST) {
320 if (Reg == R600::ALU_CONST) {
326 if (Reg == R600::ALU_LITERAL_X) {
352 if (Reg == R600::OQAP) {
618 if (Src.first->getReg() == R600::ALU_LITERAL_X)
622 if (Src.first->getReg() == R600::ALU_CONST)
1041 if (OffsetReg == R600::INDIRECT_BASE_ADDR) {
1055 if (OffsetReg == R600::INDIRECT_BASE_ADDR) {
lib/Target/AMDGPU/R600MachineScheduler.cpp 164 if (MO.isReg() && MO.getReg() == R600::ALU_LITERAL_X)
lib/Target/AMDGPU/R600Packetizer.cpp 103 if (Dst == R600::OQAP) {
lib/Target/AMDGPU/SIFixSGPRCopies.cpp 621 if (DstReg == AMDGPU::M0 && TRI->hasVectorRegisters(SrcRC)) {
lib/Target/AMDGPU/SIFoldOperands.cpp 1485 if (MI.getOperand(0).getReg() == AMDGPU::M0) {
lib/Target/AMDGPU/SIFrameLowering.cpp 446 if (PreloadedScratchWaveOffsetReg == AMDGPU::NoRegister)
lib/Target/AMDGPU/SIISelLowering.cpp 2994 if (Reg == AMDGPU::NoRegister) {
3504 if (Idx->getReg() == AMDGPU::NoRegister) {
lib/Target/AMDGPU/SIInsertWaitcnts.cpp 1080 assert(II->getOperand(0).getReg() == AMDGPU::SGPR_NULL);
1128 assert(II->getOperand(0).getReg() == AMDGPU::SGPR_NULL);
1383 Inst.getOperand(0).getReg() == AMDGPU::SGPR_NULL)) {
lib/Target/AMDGPU/SIInstrInfo.cpp 3050 if (Use.isUse() && Use.getReg() == AMDGPU::VCC) {
3071 assert(((MI.getOperand(0).getReg() == AMDGPU::VCC) ||
3072 (MI.getOperand(0).getReg() == AMDGPU::VCC_LO)) &&
3118 if (MO.getReg() == AMDGPU::SGPR_NULL)
3123 return MO.getReg() == AMDGPU::M0 ||
3124 MO.getReg() == AMDGPU::VCC ||
3125 MO.getReg() == AMDGPU::VCC_LO;
3289 if (Reg == AMDGPU::NoRegister || Register::isVirtualRegister(Reg))
5014 if (Op.isReg() && Op.getReg() == AMDGPU::SCC) {
5120 assert(Inst.getOperand(3).getReg() == AMDGPU::SCC);
5718 assert(Op.isReg() && Op.getReg() == AMDGPU::SCC && Op.isDef() &&
6251 if (Op.isReg() && Op.getReg() == AMDGPU::VCC)
lib/Target/AMDGPU/SILowerControlFlow.cpp 140 assert(ImpDefSCC.getReg() == AMDGPU::SCC && ImpDefSCC.isDef());
207 assert(ImpDefSCC.getReg() == AMDGPU::SCC && ImpDefSCC.isDef());
lib/Target/AMDGPU/SILowerI1Copies.cpp 775 if (MO.isReg() && MO.getReg() == AMDGPU::SCC) {
lib/Target/AMDGPU/SIOptimizeExecMasking.cpp 68 Src.getReg() == (ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC))
84 Dst.getReg() == (ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC) &&
110 if (Src1.isReg() && Src1.getReg() == AMDGPU::EXEC)
113 if (Src2.isReg() && Src2.getReg() == AMDGPU::EXEC)
126 if (Src1.isReg() && Src1.getReg() == AMDGPU::EXEC_LO)
129 if (Src2.isReg() && Src2.getReg() == AMDGPU::EXEC_LO)
lib/Target/AMDGPU/SIWholeQuadMode.cpp 282 if (Reg == AMDGPU::EXEC || Reg == AMDGPU::EXEC_LO)
282 if (Reg == AMDGPU::EXEC || Reg == AMDGPU::EXEC_LO)
lib/Target/ARM/ARMAsmPrinter.cpp 1148 assert(MI->getOperand(2).getReg() == ARM::SP &&
1681 if (Base == ARM::PC) {
lib/Target/ARM/ARMBaseInstrInfo.cpp 185 if (OffReg == 0) {
219 if (OffReg == 0)
551 (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)) {
562 if (MO.isReg() && MO.getReg() == ARM::CPSR && MO.isDef() && !MO.isDead())
1212 MI.getOperand(3).isImm() && MI.getOperand(2).getReg() == 0 &&
1449 MI.getOperand(3).isImm() && MI.getOperand(2).getReg() == 0 &&
2420 assert((IsT1PushPop || (MI->getOperand(0).getReg() == ARM::SP &&
2421 MI->getOperand(1).getReg() == ARM::SP)) &&
3219 if (MO.getReg() == ARM::CPSR && !MO.isDead())
3228 if (UseMI.getOperand(NumOps - 1).getReg() == ARM::CPSR)
3449 if (Rm == 0)
4754 if (!(MI.getOpcode() == ARM::tPUSH && Reg == ARM::LR) &&
4755 !(MI.getOpcode() == ARM::tPOP_RET && Reg == ARM::PC)) {
lib/Target/ARM/ARMConstantIslandPass.cpp 1747 MI->getOperand(2).getReg() == ARM::PC &&
1756 MI->getOperand(2).getReg() == ARM::LR &&
lib/Target/ARM/ARMExpandPseudoInsts.cpp 536 assert(AM6Offset.getReg() == 0 &&
617 assert(AM6Offset.getReg() == 0 &&
1928 assert(Reg == ARM::LR && "expect LR register!");
lib/Target/ARM/ARMFastISel.cpp 257 if (MO.getReg() == ARM::CPSR)
2260 if (CalleeReg == 0) return false;
2401 if (CalleeReg == 0) return false;
lib/Target/ARM/ARMFrameLowering.cpp 160 MI.getOperand(1).getReg() == ARM::SP)
1891 if (FramePtr == ARM::R7)
lib/Target/ARM/ARMISelLowering.cpp 4074 if (VA.getLocReg() == ARM::R0 && Ins[VA.getValNo()].Flags.isReturned()) {
10785 if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR) {
lib/Target/ARM/ARMLoadStoreOptimizer.cpp 207 if (MO.isDef() && MO.getReg() == ARM::CPSR && !MO.isDead())
988 if (getLoadStoreBaseOp(MI).getReg() == ARM::SP &&
1030 if (PReg == ARM::SP || PReg == ARM::PC)
1030 if (PReg == ARM::SP || PReg == ARM::PC)
1056 if (Reg == ARM::SP || Reg == ARM::PC)
1056 if (Reg == ARM::SP || Reg == ARM::PC)
1685 assert((isT2 || MI->getOperand(3).getReg() == ARM::NoRegister) &&
lib/Target/ARM/ARMLowOverheadLoops.cpp 151 MI->getOperand(0).getReg() == ARM::LR &&
190 if (Start->getOperand(0).getReg() == ARM::LR)
295 MO.getReg() == ARM::LR) {
lib/Target/ARM/Thumb1FrameLowering.cpp 464 return ((ARM::tGPRRegClass.contains(Src) || Src == ARM::LR) &&
lib/Target/ARM/Thumb2ITBlockPass.cpp 91 if (!Reg || Reg == ARM::ITSTATE || Reg == ARM::SP)
91 if (!Reg || Reg == ARM::ITSTATE || Reg == ARM::SP)
173 MI->getOperand(MCID.getNumOperands() - 1).getReg() == ARM::CPSR)
lib/Target/ARM/Thumb2InstrInfo.cpp 520 (!HasCCOut || MI.getOperand(MI.getNumOperands()-1).getReg() == 0)) {
lib/Target/ARM/Thumb2SizeReduction.cpp 304 if (Reg == 0 || Reg == ARM::CPSR)
304 if (Reg == 0 || Reg == ARM::CPSR)
384 if (Reg == 0 || Reg == ARM::CPSR)
384 if (Reg == 0 || Reg == ARM::CPSR)
386 if (isPCOk && Reg == ARM::PC)
388 if (isLROk && Reg == ARM::LR)
390 if (Reg == ARM::SP) {
423 if (MI->getOperand(1).getReg() == ARM::SP) {
541 if (BaseReg == ARM::SP &&
647 MI->getOperand(MCID.getNumOperands()-1).getReg() == ARM::CPSR)
808 HasCC = (MI->getOperand(NumOps-1).getReg() == ARM::CPSR);
872 if (!Reg || Reg == ARM::CPSR)
900 HasCC = (MI->getOperand(NumOps-1).getReg() == ARM::CPSR);
952 if (MO.isReg() && MO.isImplicit() && MO.getReg() == ARM::CPSR)
lib/Target/AVR/AVRAsmPrinter.cpp 151 if (MI->getOperand(OpNum).getReg() == AVR::R31R30) {
154 assert(MI->getOperand(OpNum).getReg() == AVR::R29R28 &&
lib/Target/AVR/AVRFrameLowering.cpp 323 assert(MI.getOperand(0).getReg() == AVR::SP &&
lib/Target/AVR/AVRISelLowering.cpp 1572 return (SrcReg == AVR::R0 || SrcReg == AVR::R1);
1572 return (SrcReg == AVR::R0 || SrcReg == AVR::R1);
lib/Target/Hexagon/HexagonInstrInfo.cpp 1031 unsigned CSx = (Mx == Hexagon::M0 ? Hexagon::CS0 : Hexagon::CS1);
2955 if (Op.isReg() && Op.isUse() && Op.getReg() == Hexagon::R29)
3397 return DestReg == Hexagon::P0 ? Hexagon::J4_cmpeqn1_tp0_jump_nt
3401 return DestReg == Hexagon::P0 ? Hexagon::J4_cmpeqi_tp0_jump_nt
lib/Target/Hexagon/RDFGraph.cpp 1272 if (!Op.isReg() || Op.getReg() == 0 || !Op.isUse() || Op.isUndef())
lib/Target/Lanai/LanaiDelaySlotFiller.cpp 109 RI->getOperand(0).getReg() == Lanai::FP &&
111 RI->getOperand(1).getReg() == Lanai::FP &&
116 RI->getOperand(0).getReg() == Lanai::SP &&
118 RI->getOperand(1).getReg() == Lanai::FP);
lib/Target/Lanai/LanaiMemAluCombiner.cpp 185 return ((Op.isReg() && Op.getReg() == Lanai::R0) ||
307 if (Offset.isReg() && Offset.getReg() == Lanai::R0)
lib/Target/MSP430/MSP430AsmPrinter.cpp 115 if (Disp.isImm() && Base.getReg() == MSP430::SR)
lib/Target/Mips/MicroMipsSizeReduction.cpp 287 if (MO.isReg() && ((MO.getReg() == Mips::SP)))
365 if (reg == Mips::RA)
lib/Target/Mips/MipsInstrInfo.cpp 467 (I->getOperand(0).getReg() == Mips::ZERO ||
468 I->getOperand(0).getReg() == Mips::ZERO_64)) &&
470 (I->getOperand(1).getReg() == Mips::ZERO ||
471 I->getOperand(1).getReg() == Mips::ZERO_64)))
lib/Target/Mips/MipsSEFrameLowering.cpp 306 && I->getOperand(3).getReg() == Mips::SP) {
371 && I->getOperand(3).getReg() == Mips::SP) {
lib/Target/Mips/MipsSEISelDAGToDAG.cpp 88 (MI.getOperand(1).getReg() == Mips::ZERO) &&
94 (MI.getOperand(1).getReg() == Mips::ZERO_64) &&
lib/Target/Mips/MipsSEInstrInfo.cpp 192 if (MI.getOperand(2).getReg() == Mips::ZERO)
196 if (MI.getOperand(2).getReg() == Mips::ZERO_64)
lib/Target/NVPTX/NVPTXAsmPrinter.cpp 2214 if (MO.getReg() == NVPTX::VRDepot)
lib/Target/NVPTX/NVPTXPeephole.cpp 97 if (BaseAddrOp.isReg() && BaseAddrOp.getReg() == NVPTX::VRFrame) {
lib/Target/PowerPC/PPCAsmPrinter.cpp 485 ((Subtarget->isPPC64() && MI->getOperand(0).getReg() == PPC::X3) ||
486 (!Subtarget->isPPC64() && MI->getOperand(0).getReg() == PPC::R3)) &&
489 ((Subtarget->isPPC64() && MI->getOperand(1).getReg() == PPC::X3) ||
490 (!Subtarget->isPPC64() && MI->getOperand(1).getReg() == PPC::R3)) &&
lib/Target/PowerPC/PPCCTRLoops.cpp 117 if (MO.isDef() && (MO.getReg() == PPC::CTR || MO.getReg() == PPC::CTR8))
117 if (MO.isDef() && (MO.getReg() == PPC::CTR || MO.getReg() == PPC::CTR8))
lib/Target/PowerPC/PPCFastISel.cpp 525 if (ResultReg == 0)
lib/Target/PowerPC/PPCInstrInfo.cpp 720 else if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
720 else if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
737 if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
737 if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
764 if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
764 if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
1316 if (Cond[1].getReg() == PPC::CTR8 || Cond[1].getReg() == PPC::CTR)
1316 if (Cond[1].getReg() == PPC::CTR8 || Cond[1].getReg() == PPC::CTR)
1441 if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR) {
1441 if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR) {
1460 if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR) {
1460 if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR) {
1494 if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR)
1494 if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR)
1528 if (Pred1[1].getReg() == PPC::CTR8 || Pred1[1].getReg() == PPC::CTR)
1528 if (Pred1[1].getReg() == PPC::CTR8 || Pred1[1].getReg() == PPC::CTR)
1530 if (Pred2[1].getReg() == PPC::CTR8 || Pred2[1].getReg() == PPC::CTR)
1530 if (Pred2[1].getReg() == PPC::CTR8 || Pred2[1].getReg() == PPC::CTR)
3746 if ((NewZeroReg == PPC::R0 || NewZeroReg == PPC::X0) &&
3746 if ((NewZeroReg == PPC::R0 || NewZeroReg == PPC::X0) &&
3749 if ((OrigZeroReg == PPC::R0 || OrigZeroReg == PPC::X0) &&
3749 if ((OrigZeroReg == PPC::R0 || OrigZeroReg == PPC::X0) &&
3983 if (StackReg == PPC::X1 && StackOffset == TOCSaveOffset)
4028 if (SrcReg == PPC::X3) {
lib/Target/PowerPC/PPCReduceCRLogicals.cpp 549 if (CopySrc == PPC::CR0EQ || CopySrc == PPC::CR6EQ)
549 if (CopySrc == PPC::CR0EQ || CopySrc == PPC::CR6EQ)
551 if (CopySrc == PPC::CR0LT || CopySrc == PPC::CR6LT)
551 if (CopySrc == PPC::CR0LT || CopySrc == PPC::CR6LT)
553 if (CopySrc == PPC::CR0GT || CopySrc == PPC::CR6GT)
553 if (CopySrc == PPC::CR0GT || CopySrc == PPC::CR6GT)
555 if (CopySrc == PPC::CR0UN || CopySrc == PPC::CR6UN)
555 if (CopySrc == PPC::CR0UN || CopySrc == PPC::CR6UN)
lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp 957 if (RegNo == RISCV::NoRegister)
961 return RegNo == RISCV::NoRegister;
1007 if (RegNo == RISCV::NoRegister) {
lib/Target/RISCV/RISCVISelLowering.cpp 1792 if (VA.getLocReg() == RISCV::X17) {
2173 if (RegLo == RISCV::X17) {
lib/Target/RISCV/RISCVInstrInfo.cpp 486 return (MI.getOperand(1).isReg() && MI.getOperand(1).getReg() == RISCV::X0);
lib/Target/Sparc/DelaySlotFiller.cpp 328 if (Reg == 0)
489 && MBBI->getOperand(0).getReg() == SP::G0
490 && MBBI->getOperand(1).getReg() == SP::G0
491 && MBBI->getOperand(2).getReg() == SP::G0);
lib/Target/Sparc/SparcAsmPrinter.cpp 394 MI->getOperand(opNum+1).getReg() == SP::G0)
lib/Target/SystemZ/SystemZISelLowering.cpp 1450 if (Reg == SystemZ::R6H || Reg == SystemZ::R6L || Reg == SystemZ::R6D)
1450 if (Reg == SystemZ::R6H || Reg == SystemZ::R6L || Reg == SystemZ::R6D)
1450 if (Reg == SystemZ::R6H || Reg == SystemZ::R6L || Reg == SystemZ::R6D)
lib/Target/SystemZ/SystemZInstrInfo.cpp 313 MI.getOperand(2).getImm() == 0 && MI.getOperand(3).getReg() == 0) {
906 MI->getOperand(3).getReg() == 0);
1616 if (!(MI && MI->getOperand(3).getReg() == 0))
lib/Target/SystemZ/SystemZRegisterInfo.cpp 306 && MI->getOperand(FIOperandNum + 2).getReg() == 0) {
lib/Target/WebAssembly/WebAssemblyRegStackify.cpp 347 if (Reg == WebAssembly::ARGUMENTS)
lib/Target/X86/X86AsmPrinter.cpp 285 BaseReg.getReg() == X86::RIP)
lib/Target/X86/X86AvoidStoreForwardingBlocks.cpp 324 if (!(Index.isReg() && Index.getReg() == X86::NoRegister))
326 if (!(Segment.isReg() && Segment.getReg() == X86::NoRegister))
lib/Target/X86/X86FastISel.cpp 1217 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
1217 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
3566 if ((SrcReg == X86::FP0 || SrcReg == X86::FP1) &&
3566 if ((SrcReg == X86::FP0 || SrcReg == X86::FP1) &&
lib/Target/X86/X86FixupBWInsts.cpp 345 MI->getOperand(0).getReg() == X86::AX &&
346 MI->getOperand(1).getReg() == X86::AL)
lib/Target/X86/X86FixupLEAs.cpp 372 if (UseLEAForSP && (DestReg == X86::ESP || DestReg == X86::RSP))
372 if (UseLEAForSP && (DestReg == X86::ESP || DestReg == X86::RSP))
403 } else if (DestReg == BaseReg && IndexReg == 0) {
498 if ((SrcR1 == 0 || SrcR1 != DstR) && (SrcR2 == 0 || SrcR2 != DstR))
498 if ((SrcR1 == 0 || SrcR1 != DstR) && (SrcR2 == 0 || SrcR2 != DstR))
lib/Target/X86/X86FixupSetCC.cpp 81 if (Op.isReg() && (Op.getReg() == X86::EFLAGS) && Op.isDef())
89 if (Op.isReg() && (Op.getReg() == X86::EFLAGS) && Op.isUse())
lib/Target/X86/X86FlagsCopyLowering.cpp 361 MI.getOperand(0).getReg() == X86::EFLAGS)
404 assert(DOp.getReg() == X86::EFLAGS && "Unexpected copy def register!");
703 (MI.getOperand(0).getReg() == X86::EFLAGS ||
704 MI.getOperand(1).getReg() == X86::EFLAGS)) {
lib/Target/X86/X86FrameLowering.cpp 430 PI->getOperand(3).getReg() == X86::NoRegister &&
431 PI->getOperand(5).getReg() == X86::NoRegister) {
lib/Target/X86/X86ISelLowering.cpp 2526 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
2526 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
2541 if (VA.getLocReg() == X86::FP0 ||
2542 VA.getLocReg() == X86::FP1) {
2556 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
2556 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
2862 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
2862 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
4387 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
4387 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
24263 if (Reg == X86::EBP || Reg == X86::RBP) {
24263 if (Reg == X86::EBP || Reg == X86::RBP) {
24271 assert((FrameReg == X86::EBP || FrameReg == X86::RBP) &&
24271 assert((FrameReg == X86::EBP || FrameReg == X86::RBP) &&
24317 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
24318 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
28315 (BasePtr == X86::RBX || BasePtr == X86::EBX)) {
28315 (BasePtr == X86::RBX || BasePtr == X86::EBX)) {
28322 assert(((Regs64bit == (BasePtr == X86::RBX)) || BasePtr == X86::EBX) &&
28322 assert(((Regs64bit == (BasePtr == X86::RBX)) || BasePtr == X86::EBX) &&
29562 MI.getOperand(MI.getNumOperands() - 1).getReg() == X86::EFLAGS) &&
31223 assert(Push->getOperand(2).getReg() == X86::EFLAGS &&
31226 assert(Push->getOperand(3).getReg() == X86::DF &&
31372 assert(TRI->getBaseRegister() == X86::ESI &&
lib/Target/X86/X86InsertPrefetch.cpp 84 return (BaseReg == 0 ||
87 (IndexReg == 0 ||
lib/Target/X86/X86InstrInfo.cpp 200 MI.getOperand(Op + X86::AddrIndexReg).getReg() == 0 &&
603 MI.getOperand(1 + X86::AddrIndexReg).getReg() == 0 &&
606 if (BaseReg == 0 || BaseReg == X86::RIP)
606 if (BaseReg == 0 || BaseReg == X86::RIP)
622 MI.getOperand(1 + X86::AddrIndexReg).getReg() == 0 &&
628 if (BaseReg == 0)
676 MO.getReg() == X86::EFLAGS && !MO.isDead()) {
7247 Inst.getOperand(3).getReg() == X86::EFLAGS &&
7578 assert(Op2.isReg() && (Op2.getReg() == X86::NoRegister ||
7675 assert(OldOp1.isReg() && OldOp1.getReg() == X86::EFLAGS && OldOp1.isDead() &&
7677 assert(OldOp2.isReg() && OldOp2.getReg() == X86::EFLAGS && OldOp2.isDead() &&
7683 assert(NewOp1.isReg() && NewOp1.getReg() == X86::EFLAGS &&
7685 assert(NewOp2.isReg() && NewOp2.getReg() == X86::EFLAGS &&
lib/Target/X86/X86SpeculativeLoadHardening.cpp 1964 } else if (BaseMO.getReg() == X86::RSP) {
1968 assert(IndexMO.getReg() == X86::NoRegister &&
1972 } else if (BaseMO.getReg() == X86::RIP ||
1973 BaseMO.getReg() == X86::NoRegister) {
1984 << (BaseMO.getReg() == X86::RIP ? "RIP-relative" : "no-base")
unittests/CodeGen/MachineOperandTest.cpp 74 ASSERT_TRUE(MO.getReg() == 1);