reference, declarationdefinition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

include/llvm/CodeGen/MachineInstrBuilder.h
  499          getKillRegState(RegOp.isKill()) | getDeadRegState(RegOp.isDead()) |
lib/CodeGen/BranchFolding.cpp
 1888       if (!MO.isDead())
 2032         if (Defs.count(Reg) && !MO.isDead()) {
 2087       if (!MO.isReg() || !MO.isDef() || MO.isDead())
lib/CodeGen/DetectDeadLanes.cpp
  367     if (Def.isDead())
  409   if (DefMI.isImplicitDef() || Def.isDead())
  544         if (MO.isDef() && !MO.isDead() && RegInfo.UsedLanes.none()) {
lib/CodeGen/InlineSpiller.cpp
  859     assert(MO->isDead() && "Cannot fold physreg def");
 1049         if (!MO.isDead())
 1523         if (MO.isReg() && MO.isImplicit() && MO.isDef() && !MO.isDead())
lib/CodeGen/LivePhysRegs.cpp
  110     if (Reg.second->isReg() && Reg.second->isDead())
lib/CodeGen/LiveRangeShrink.cpp
  145         else if (MO.isDead() && UseMap.count(MO.getReg()))
  173         if (!MO.isReg() || MO.isDead() || MO.isDebug())
lib/CodeGen/LiveVariables.cpp
  379           assert(!MO->isDead());
lib/CodeGen/MIRCanonicalizerPass.cpp
  365       if (MO.isDef() && MO.isDead()) {
lib/CodeGen/MachineCSE.cpp
  315     if (!MO.isDead() && !isPhysDefTriviallyDead(Reg, I, MBB->end()))
  603       if (MO.isImplicit() && !MO.isDead() && CSMI->getOperand(i).isDead())
  603       if (MO.isImplicit() && !MO.isDead() && CSMI->getOperand(i).isDead())
  608       if (MO.isImplicit() && !MO.isDead() && OldReg == NewReg)
  659         if (!MI->getOperand(PhysDef.first).isDead())
lib/CodeGen/MachineCopyPropagation.cpp
  293   if (PrevCopy->getOperand(0).isDead())
lib/CodeGen/MachineInstr.cpp
  637         if (Check == CheckKillDead && MO.isDead() != OMO.isDead())
  637         if (Check == CheckKillDead && MO.isDead() != OMO.isDead())
 1011     if (Found && (!isDead || MO.isDead()))
 1390     if (!MO.isDead())
 1882     } else if (hasAliases && MO.isDead() &&
lib/CodeGen/MachineInstrBundle.cpp
  186         if (MO.isDead()) {
  192         if (!MO.isDead())
  197       if (!MO.isDead() && Register::isPhysicalRegister(Reg)) {
  351       if (!MO.isDead())
lib/CodeGen/MachineLICM.cpp
  443       if (!MO.isDead())
 1028       } else if (!MO.isDead()) {
 1486       if (MO.isReg() && MO.isDef() && !MO.isDead())
lib/CodeGen/MachineOperand.cpp
  759     if (isDead())
lib/CodeGen/MachinePipeliner.cpp
 1566       if (MO.isReg() && MO.isDef() && !MO.isDead()) {
lib/CodeGen/MachineScheduler.cpp
  946         if (MO2.isReg() && MO2.isDef() && MO2.getReg() == Reg && !MO2.isDead()) {
 1698   if (!Register::isVirtualRegister(DstReg) || DstOp.isDead())
lib/CodeGen/MachineSink.cpp
  651       } else if (!MO.isDead()) {
lib/CodeGen/MachineTraceMetrics.cpp
  716       if (MO.isDead())
lib/CodeGen/MachineVerifier.cpp
 1918   if (MO->isDead()) {
 2057     if (MO->isDead())
 2569         if (MOI->isDead())
lib/CodeGen/ModuloSchedule.cpp
  732           used = !MOI->isDead();
lib/CodeGen/PHIElimination.cpp
  252   bool isDead = MPhi->getOperand(0).isDead();
lib/CodeGen/PeepholeOptimizer.cpp
  882     while (CopyLike.getOperand(CurrentSrcIdx).isDead()) {
 1359     if (MO.isImplicit() && MO.isDead())
 1851     if (MO.isImplicit() && MO.isDead())
lib/CodeGen/RegAllocFast.cpp
  830     } else if (MO.isDead()) {
  841   } else if (MO.isDead()) {
  857   bool Dead = MO.isDead();
 1066                     (MO.isImplicit() || MO.isDead()) ? regFree : regReserved);
 1173     definePhysReg(MI, Reg, MO.isDead() ? regFree : regReserved);
lib/CodeGen/RegisterCoalescer.cpp
 1338       assert(MO.isImplicit() && MO.isDead() &&
lib/CodeGen/RegisterPressure.cpp
  512       if (MO.isDead()) {
  544       if (MO.isDead()) {
lib/CodeGen/RegisterScavenging.cpp
  148       if (MO.isDead())
lib/CodeGen/RenameIndependentSubregs.cpp
  358       if (!MO.isDead()) {
lib/CodeGen/ScheduleDAGInstrs.cpp
  307           (Kind != SDep::Output || !MO.isDead() ||
  336       if (!MO.isDead())
  339     if (MO.isDead() && SU->isCall) {
  422   if (MO.isDead()) {
lib/CodeGen/TwoAddressInstructionPass.cpp
  964         if (!MO.isDead() && regOverlapsSet(Defs, MOReg, TRI))
 1109       if (!MO.isDead())
lib/CodeGen/VirtRegMap.cpp
  536               if (MO.isDead())
  548             } else if (!MO.isDead()) {
lib/Target/AArch64/AArch64CondBrTuning.cpp
   94       if (MO.isReg() && MO.isDead() && MO.getReg() == AArch64::NZCV)
lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp
  150           (!MO.isDead() && !MRI->use_nodbg_empty(Reg)))
lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
  144       bool DstIsDead = MI.getOperand(0).isDead();
  154       bool DstIsDead = MI.getOperand(0).isDead();
  178   bool StatusDead = MI.getOperand(1).isDead();
  206       .addReg(Dest.getReg(), getKillRegState(Dest.isDead()))
  258   bool StatusDead = MI.getOperand(2).isDead();
  287       .addReg(DestLo.getReg(), getKillRegState(DestLo.isDead()))
  295       .addReg(DestHi.getReg(), getKillRegState(DestHi.isDead()))
lib/Target/AArch64/AArch64RedundantCopyElimination.cpp
  407                   return !O.isDead() && O.isReg() && O.isDef() &&
lib/Target/AArch64/AArch64SpeculationHardening.cpp
  510         if (Def.isDead())
lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
  230                                      MO.isKill(), MO.isDead(), MO.isUndef(),
lib/Target/AMDGPU/GCNRegPressure.cpp
  331     if (!MO.isReg() || !Register::isVirtualRegister(MO.getReg()) || MO.isDead())
lib/Target/AMDGPU/SIFormMemoryClauses.cpp
  139   if (MO.isDead())
lib/Target/AMDGPU/SIInstrInfo.cpp
 1648   bool IsDead = RegOp.isDead();
 5016         if (Op.isDef() && !Op.isDead())
 5719          !Op.isDead() && Op.getParent() == &SCCDefInst);
lib/Target/AMDGPU/SILowerControlFlow.cpp
  238     setImpSCCDefDead(*Xor, ImpDefSCC.isDead());
lib/Target/AMDGPU/SIPeepholeSDWA.cpp
  283     To.setIsDead(From.isDead());
lib/Target/ARM/ARMBaseInstrInfo.cpp
  269     if (WB.isDead())
  285           if (MO.isDead())
  562     if (MO.isReg() && MO.getReg() == ARM::CPSR && MO.isDef() && !MO.isDead())
  689     if (!MO.isDead())
 1522   if (isThumb1 || !MI->getOperand(1).isDead()) {
 1532   if (isThumb1 || !MI->getOperand(0).isDead()) {
 1610   if (MI.getOperand(0).isDead())
 2203     if (MO.isDef() && !MO.isDead())
 3219     if (MO.getReg() == ARM::CPSR && !MO.isDead())
lib/Target/ARM/ARMExpandPseudoInsts.cpp
  483   bool DstIsDead = MI.getOperand(OpIdx).isDead();
  686     DstIsDead = MI.getOperand(OpIdx).isDead();
  833   bool DstIsDead = MI.getOperand(0).isDead();
  976       .addReg(Dest.getReg(), getKillRegState(Dest.isDead()))
 1091       .addReg(DestLo, getKillRegState(Dest.isDead()))
 1096       .addReg(DestHi, getKillRegState(Dest.isDead()))
 1114   unsigned Flags = getKillRegState(New.isDead());
 1451       bool DstIsDead = MI.getOperand(0).isDead();
 1473       bool DstIsDead = MI.getOperand(0).isDead();
 1531       bool DstIsDead = MI.getOperand(0).isDead();
 1593       bool DstIsDead = MI.getOperand(OpIdx).isDead();
lib/Target/ARM/ARMISelLowering.cpp
10787       if (MO.isDead())
lib/Target/ARM/ARMLoadStoreOptimizer.cpp
  207     if (MO.isDef() && MO.getReg() == ARM::CPSR && !MO.isDead())
  874         if (!MO.isReg() || !MO.isDef() || MO.isDead())
 1678     MI->getOperand(0).isDead() : MI->getOperand(0).isKill();
 1681     MI->getOperand(1).isDead() : MI->getOperand(1).isKill();
lib/Target/ARM/MLxExpansionPass.cpp
  273   bool DstDead = MI->getOperand(0).isDead();
lib/Target/ARM/Thumb2SizeReduction.cpp
  809     if (HasCC && MI->getOperand(NumOps-1).isDead())
  901     if (HasCC && MI->getOperand(NumOps-1).isDead())
  981     if (!MO.isDead())
 1091       if (MO && !MO->isDead())
lib/Target/AVR/AVRExpandPseudoInsts.cpp
  145   bool DstIsDead = MI.getOperand(0).isDead();
  148   bool ImpIsDead = MI.getOperand(3).isDead();
  178   bool DstIsDead = MI.getOperand(0).isDead();
  181   bool ImpIsDead = MI.getOperand(3).isDead();
  224   bool DstIsDead = MI.getOperand(0).isDead();
  226   bool ImpIsDead = MI.getOperand(3).isDead();
  276   bool DstIsDead = MI.getOperand(0).isDead();
  278   bool ImpIsDead = MI.getOperand(3).isDead();
  328   bool DstIsDead = MI.getOperand(0).isDead();
  330   bool ImpIsDead = MI.getOperand(3).isDead();
  391   bool DstIsDead = MI.getOperand(0).isDead();
  393   bool ImpIsDead = MI.getOperand(2).isDead();
  424   bool ImpIsDead = MI.getOperand(2).isDead();
  457   bool ImpIsDead = MI.getOperand(2).isDead();
  489   bool DstIsDead = MI.getOperand(0).isDead();
  538   bool DstIsDead = MI.getOperand(0).isDead();
  632   bool DstIsDead = MI.getOperand(0).isDead();
  663   bool DstIsDead = MI.getOperand(0).isDead();
 1047   bool DstIsDead = MI.getOperand(0).isDead();
 1081   bool DstIsDead = MI.getOperand(0).isDead();
 1148   bool DstIsDead = MI.getOperand(0).isDead();
 1250   bool DstIsDead = MI.getOperand(0).isDead();
 1252   bool ImpIsDead = MI.getOperand(2).isDead();
 1283   bool DstIsDead = MI.getOperand(0).isDead();
 1285   bool ImpIsDead = MI.getOperand(2).isDead();
 1326   bool DstIsDead = MI.getOperand(0).isDead();
 1328   bool ImpIsDead = MI.getOperand(2).isDead();
 1370   bool DstIsDead = MI.getOperand(0).isDead();
 1372   bool ImpIsDead = MI.getOperand(2).isDead();
 1424   bool DstIsDead = MI.getOperand(0).isDead();
 1426   bool ImpIsDead = MI.getOperand(2).isDead();
 1452   bool DstIsDead = MI.getOperand(0).isDead();
lib/Target/BPF/BPFMIChecking.cpp
  119     if (!MO.isDead()) {
lib/Target/Hexagon/HexagonBlockRanges.cpp
  343         if (Op.isDead())
lib/Target/Hexagon/HexagonSplitDouble.cpp
  622           Op.isDead(), Op.isUndef(), Op.isEarlyClobber(), SR, Op.isDebug(),
lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
 1204     if (!MO.isReg() || !MO.isDef() || !MO.isDead())
 1210     if (!MO.isReg() || !MO.isDef() || !MO.isDead())
lib/Target/Hexagon/RDFGraph.cpp
  611     if (Op.isDef() && Op.isDead())
 1308     if (IsCall && Op.isDead())
 1354     if (IsCall && Op.isDead()) {
lib/Target/Lanai/LanaiInstrInfo.cpp
  483     if (MO.isDef() && !MO.isDead())
lib/Target/PowerPC/PPCInstrInfo.cpp
  426     bool Reg0IsDead = MI.getOperand(0).isDead();
 2526   assert((IsKillSet || (MO && MO->isDead())) &&
lib/Target/PowerPC/PPCPreEmitPeephole.cpp
   99         if (BBI->getOperand(0).isDead()) {
lib/Target/SystemZ/SystemZElimCompare.cpp
  176          MI.getOperand(0).isDead();
lib/Target/WebAssembly/WebAssemblyLateEHPrepare.cpp
  244         if (MI.getOperand(0).isDead())
lib/Target/WebAssembly/WebAssemblyOptimizeLiveIntervals.cpp
   98     if (MI->isImplicitDef() && MI->getOperand(0).isDead()) {
lib/Target/WebAssembly/WebAssemblyRegStackify.cpp
  340     if (MO.isDead() && Insert->definesRegister(Reg) &&
  616                           .addReg(DefReg, getUndefRegState(DefMO.isDead()));
lib/Target/X86/X86DomainReassignment.cpp
  145       if (MO.isReg() && MO.isDef() && !MO.isDead() &&
lib/Target/X86/X86FlagsCopyLowering.cpp
  405     if (DOp.isDead())
lib/Target/X86/X86FloatingPoint.cpp
  450       if (MO.isReg() && MO.isDead())
 1553         if (MO.isDead())
lib/Target/X86/X86InstrInfo.cpp
  676         MO.getReg() == X86::EFLAGS && !MO.isDead()) {
  793   bool IsDead = MI.getOperand(0).isDead();
 1321     if (Dest.isDead())
 5543                getDeadRegState(ImpOp.isDead()) |
 7249     if (!Inst.getOperand(3).isDead())
 7675   assert(OldOp1.isReg() && OldOp1.getReg() == X86::EFLAGS && OldOp1.isDead() &&
 7677   assert(OldOp2.isReg() && OldOp2.getReg() == X86::EFLAGS && OldOp2.isDead() &&
lib/Target/X86/X86SpeculativeLoadHardening.cpp
 1348     if (!MI.findRegisterDefOperand(X86::EFLAGS)->isDead()) {
 1517     if (!MI.findRegisterDefOperand(X86::EFLAGS)->isDead()) {
 1595       if (DefOp->isDead())