reference, declarationdefinition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

lib/CodeGen/CalcSpillWeights.cpp
  108         if (MI->getOperand(0).getReg() != Reg)
lib/CodeGen/CriticalAntiDepBreaker.cpp
  368           CheckOper.getReg() != NewReg)
  622         if (MO.isDef() && Reg != AntiDepReg)
lib/CodeGen/ImplicitNullChecks.cpp
  369       !BaseOp->isReg() || BaseOp->getReg() != PointerReg)
lib/CodeGen/LiveDebugValues.cpp
 1301     return Op.isReg() && Op.getReg() != SP && Op.getReg() != FP;
lib/CodeGen/LiveDebugVariables.cpp
 1123     if (!Loc->isReg() || Loc->getReg() != OldReg)
lib/CodeGen/LiveInterval.cpp
  906       if (MOI->getReg() != Reg)
lib/CodeGen/LiveIntervals.cpp
  779           if (!MO.isReg() || MO.getReg() != Reg)
 1514       if (!MO.isReg() || MO.getReg() != Reg)
lib/CodeGen/LiveVariables.cpp
  405       bool NeedEC = MO->isEarlyClobber() && MO->getReg() != Reg;
lib/CodeGen/MachineInstrBundle.cpp
  290     if (!MO.isReg() || MO.getReg() != Reg)
lib/CodeGen/MachineLICM.cpp
 1107       if (MOReg != Reg)
lib/CodeGen/MachineRegisterInfo.cpp
  244     if (MO->getReg() != Reg) {
lib/CodeGen/MachineVerifier.cpp
 2419         if (MOI->getReg() != Reg)
 2556       if (!MOI->isReg() || MOI->getReg() != Reg)
lib/CodeGen/RegisterCoalescer.cpp
  806   if (NewReg != IntB.reg || !IntB.Query(AValNo->def).isKill())
  888     if (UseMI->getOperand(0).getReg() != IntB.reg ||
 1066     if (DefMI->getOperand(0).getReg() != IntA.reg ||
 1067         DefMI->getOperand(1).getReg() != IntB.reg ||
 1194     if (!Op.isReg() || !Op.isDef() || Op.getReg() != Reg)
 2394     if (!MO.isReg() || MO.getReg() != Reg || !MO.isDef())
 2828     if (!MO.isReg() || MO.isDef() || MO.getReg() != Reg)
 3193         if (Register::isVirtualRegister(Reg) && Reg != CP.getSrcReg() &&
 3194             Reg != CP.getDstReg())
lib/CodeGen/SplitKit.cpp
  441       if (R != LI.reg)
lib/CodeGen/TwoAddressInstructionPass.cpp
  236     if (MO.isUse() && MOReg != SavedReg)
  505     if (!MO.isReg() || !MO.isUse() || MO.getReg() != Reg)
  920       if (MOReg != Reg && (MO.isKill() ||
  974         if (MOReg != Reg && ((isKill && regOverlapsSet(Uses, MOReg, TRI)) ||
  982         assert((MOReg != Reg || &OtherMI == KillMI) &&
 1105       if (isKill && MOReg != Reg)
lib/CodeGen/VirtRegMap.cpp
  141     if (Virt2PhysMap[Reg] != (unsigned)VirtRegMap::NO_PHYS_REG) {
lib/Target/AArch64/AArch64InstrInfo.cpp
 3614     if (MI->getOperand(3).getReg() != ZeroReg)
lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
 1459     if (MI.getOperand(0).getReg() != BaseReg ||
 1460         MI.getOperand(1).getReg() != BaseReg)
lib/Target/AMDGPU/SIFixSGPRCopies.cpp
  439       if ((MO.isReg() && ((MO.isDef() && MO.getReg() != Reg) || !MO.isDef())) ||
lib/Target/AMDGPU/SIFoldOperands.cpp
  594     if (!SOff->isReg() || (SOff->getReg() != MFI->getScratchWaveOffsetReg() &&
  595                            SOff->getReg() != MFI->getStackPtrOffsetReg()))
  598     if (TII->getNamedOperand(*UseMI, AMDGPU::OpName::srsrc)->getReg() !=
lib/Target/AMDGPU/SIInsertSkips.cpp
  373   if (Op1.getReg() != ExecReg && Op2.isReg() && Op2.getReg() == ExecReg) {
  377   if (Op1.getReg() != ExecReg)
lib/Target/AMDGPU/SIInstrInfo.cpp
  331       if (RSrc->getReg() != MFI->getScratchRSrcReg())
lib/Target/AMDGPU/SILowerControlFlow.cpp
  459         !(I->isCopy() && I->getOperand(0).getReg() != Exec))
lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp
  112   if (Op->isReg() && Op->getReg() != Exec)
  115   if (Op->isReg() && Op->getReg() != Exec)
  220   } else if (And->getOperand(2).getReg() != ExecReg) {
lib/Target/AMDGPU/SIRegisterInfo.cpp
  768   assert(SpillToVGPR || (SuperReg != MFI->getStackPtrOffsetReg() &&
  769                          SuperReg != MFI->getFrameOffsetReg() &&
  770                          SuperReg != MFI->getScratchWaveOffsetReg()));
lib/Target/AMDGPU/SIShrinkInstructions.cpp
  733         if (DstReg != VCCReg)
  749         if (SReg != VCCReg)
  764         if (SDst->getReg() != VCCReg) {
  772         if (Src2 && Src2->getReg() != VCCReg) {
lib/Target/ARM/ARMBaseInstrInfo.cpp
 3249     Commute = UseMI.getOperand(2).getReg() != Reg;
lib/Target/ARM/ARMConstantIslandPass.cpp
 2007   if (I.getOperand(0).getReg() != EntryReg)
 2010   if (I.getOperand(1).getReg() != BaseReg)
lib/Target/ARM/ARMLoadStoreOptimizer.cpp
  939           if (!MO.isReg() || MO.getReg() != ImpDefReg)
 1198   if (MI.getOperand(0).getReg() != Reg ||
 1199       MI.getOperand(1).getReg() != Reg ||
 2127       if (Reg != Base && !MemRegs.count(Reg))
lib/Target/ARM/ARMLowOverheadLoops.cpp
  123       if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg)
  136       if (!MO.isReg() || !MO.isUse() || MO.getReg() != Reg)
lib/Target/Hexagon/HexagonBitSimplify.cpp
 2281       if (Op1.getReg() != SrcR || Op1.getSubReg() != SrcSR)
lib/Target/Hexagon/HexagonCopyToCombine.cpp
  240     if (!Op.isReg() || Op.getReg() != RegNotKilled || !Op.isKill())
lib/Target/Hexagon/HexagonExpandCondsets.cpp
  320       if (!Op.isReg() || !Op.isUse() || Op.getReg() != Reg ||
  376     if (!Register::isVirtualRegister(DR) || DR != Reg)
lib/Target/Hexagon/HexagonFrameLowering.cpp
 2305           if (DstR != FoundR) {
lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
  651   if (Val.isReg() && Val.getReg() != DepReg)
  833     if (!MO.isReg() || MO.getReg() != DepReg || !MO.isImplicit())
lib/Target/PowerPC/PPCISelLowering.cpp
10502   if (ptrA != ZeroReg) {
lib/Target/SystemZ/SystemZInstrInfo.cpp
  615   if (DefMI.getOperand(0).getReg() != Reg)
lib/Target/X86/X86FastISel.cpp
 3957     if (!MO.isReg() || MO.isDef() || MO.getReg() != AM.IndexReg)
lib/Target/X86/X86InstrInfo.cpp
 3345     if (MI.getOperand(1).getReg() != SrcReg)
 3851     if (Reg != FoldAsLoadDefReg)
lib/Target/X86/X86SpeculativeLoadHardening.cpp
  548       if (!Op.isReg() || Op.getReg() != PS->InitialReg)