|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
include/llvm/CodeGen/LiveVariables.h 217 if (MO.isReg() && MO.isKill() && MO.getReg() == reg) {
253 if (MO.isReg() && MO.isDef() && MO.getReg() == reg) {
lib/CodeGen/AntiDepBreaker.h 61 if (MI.getOperand(0).isReg() && MI.getOperand(0).getReg() == OldReg)
lib/CodeGen/AsmPrinter/DbgEntityHistoryCalculator.cpp 147 if (isDescribedByReg(*Entry.getInstr()) == RegNo) {
274 if (MI.isCall() && MO.getReg() == SP)
lib/CodeGen/AsmPrinter/DwarfDebug.cpp 656 bool IsSPorFP = (RegLoc == SP) || (RegLoc == FP);
lib/CodeGen/CalcSpillWeights.cpp 56 if (mi->getOperand(0).getReg() == reg) {
lib/CodeGen/InlineSpiller.cpp 264 if (MI.getOperand(0).getReg() == Reg)
266 if (MI.getOperand(1).getReg() == Reg)
559 if (MO.isReg() && MO.isUse() && MO.getReg() == VirtReg.reg)
624 if (MO.isReg() && MO.isUse() && MO.getReg() == VirtReg.reg) {
886 if (MO.getReg() == ImpReg)
lib/CodeGen/LiveDebugValues.cpp 817 !(MI.isCall() && MO.getReg() == SP)) {
lib/CodeGen/MachineCopyPropagation.cpp 304 assert(CopyDef == Src || CopyDef == Def);
304 assert(CopyDef == Src || CopyDef == Def);
lib/CodeGen/MachineInstr.cpp 2135 DI->getOperand(0).getReg() == DefReg){
lib/CodeGen/MachineLICM.cpp 580 if (MO.getReg() == Reg || TRI->isSuperRegister(Reg, MO.getReg()))
lib/CodeGen/MachinePipeliner.cpp 824 if (PMI->getOperand(0).getReg() == HasPhiUse)
2632 if (DMO.getReg() == LoopReg)
2769 if (MO.isReg() && MO.isUse() && MO.getReg() == OverlapReg) {
lib/CodeGen/ModuloSchedule.cpp 1152 if (!Phi->isPHI() && UseMI->getOperand(0).getReg() == NewReg)
lib/CodeGen/RegAllocGreedy.cpp 2878 if (OtherReg == Reg) {
2880 if (OtherReg == Reg)
lib/CodeGen/RegisterCoalescer.cpp 521 return TRI.getSubReg(DstReg, SrcSub) == Dst;
1618 if (MO.isReg() && MO.isDef() && MO.getReg() == DstReg)
2944 if (MO.isReg() && MO.isDef() && MO.getReg() == Reg) {
lib/CodeGen/ShrinkWrap.cpp 290 UseOrDefCSR = (!MI.isCall() && PhysReg == SP) ||
lib/CodeGen/TwoAddressInstructionPass.cpp 309 if (&OtherMI == KillMI && MOReg == SavedReg)
978 if (MOReg == Reg && !isKill)
1102 if (MOReg == Reg && !isKill)
1143 if (&OtherMI != MI && MOReg == Reg &&
1529 if (RegA == RegB) {
1592 assert(MO.isReg() && MO.getReg() == RegB && MO.isUse() &&
1617 if (MO.isReg() && MO.getReg() == RegB && MO.isUse()) {
1657 if (MO.isReg() && MO.getReg() == RegB && MO.isUse()) {
lib/Target/AArch64/AArch64SIMDInstrOpt.cpp 326 CurrentMI->getOperand(1).getReg() == SrcReg &&
lib/Target/AArch64/AArch64StackTaggingPreRA.cpp 155 UseI->getOperand(OpIdx).getReg() == TaggedReg) {
lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp 97 return Reg == TRI.getVCC();
lib/Target/AMDGPU/GCNRegBankReassign.cpp 373 if (Bank != -1 && R == Reg && Op.getSubReg()) {
lib/Target/AMDGPU/SIInsertSkips.cpp 373 if (Op1.getReg() != ExecReg && Op2.isReg() && Op2.getReg() == ExecReg) {
lib/Target/AMDGPU/SIInstrInfo.cpp 2373 if (Src0->isReg() && Src0->getReg() == Reg) {
2425 if (Src2->isReg() && Src2->getReg() == Reg) {
lib/Target/AMDGPU/SILowerControlFlow.cpp 464 (Register::isVirtualRegister(SrcOp.getReg()) || SrcOp.getReg() == Exec))
lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp 99 if (MI.isCopy() && MI.getOperand(1).getReg() == Exec) {
216 if (CmpReg == ExecReg) {
271 (CmpReg == CondReg &&
lib/Target/AMDGPU/SIRegisterInfo.cpp 401 assert(TII->getNamedOperand(MI, AMDGPU::OpName::soffset)->getReg() ==
1043 assert(TII->getNamedOperand(*MI, AMDGPU::OpName::soffset)->getReg() ==
1073 assert(TII->getNamedOperand(*MI, AMDGPU::OpName::soffset)->getReg() ==
1206 assert(TII->getNamedOperand(*MI, AMDGPU::OpName::soffset)->getReg() ==
lib/Target/AMDGPU/SIShrinkInstructions.cpp 400 } else if (MO.getReg() == Reg && Register::isVirtualRegister(Reg)) {
lib/Target/ARM/ARMBaseInstrInfo.cpp 2773 ((OI->getOperand(1).getReg() == SrcReg &&
2774 OI->getOperand(2).getReg() == SrcReg2) ||
2775 (OI->getOperand(1).getReg() == SrcReg2 &&
2776 OI->getOperand(2).getReg() == SrcReg))) {
2782 ((OI->getOperand(2).getReg() == SrcReg &&
2783 OI->getOperand(3).getReg() == SrcReg2) ||
2784 (OI->getOperand(2).getReg() == SrcReg2 &&
2785 OI->getOperand(3).getReg() == SrcReg))) {
2792 OI->getOperand(1).getReg() == SrcReg &&
2800 OI->getOperand(2).getReg() == SrcReg &&
2810 OI->getOperand(0).getReg() == SrcReg &&
2811 OI->getOperand(1).getReg() == SrcReg2) {
2819 OI->getOperand(0).getReg() == SrcReg &&
2820 OI->getOperand(2).getReg() == SrcReg2) {
3114 (SrcReg2 != 0 && SubAdd->getOperand(OpI).getReg() == SrcReg2 &&
3115 SubAdd->getOperand(OpI + 1).getReg() == SrcReg)) {
lib/Target/ARM/ARMConstantIslandPass.cpp 2237 if (BaseReg == IdxReg && !jumpTableFollowsTB(MI, User.CPEMI))
lib/Target/ARM/ARMLoadStoreOptimizer.cpp 514 if (Offset >= 0 && !(IsStore && InstrSrcReg == Base))
lib/Target/ARM/ARMLowOverheadLoops.cpp 152 MI->getOperand(1).getReg() == Reg &&
lib/Target/Hexagon/HexagonBitSimplify.cpp 980 if (DR == R)
2535 if (SrcOp.getReg() == R)
3014 if (Op.getReg() == InpR)
lib/Target/Hexagon/HexagonHardwareLoops.cpp 677 if (Op2.isImm() || Op1.getReg() == IVReg)
1769 if (MO.isReg() && MO.getReg() == RB.first) {
1836 if (MO.isReg() && MO.getReg() == RB.first) {
lib/Target/Hexagon/HexagonInstrInfo.cpp 3101 if (MO.isReg() && MO.isDef() && MO.isImplicit() && (MO.getReg() == PredReg))
lib/Target/Hexagon/HexagonNewValueJump.cpp 566 MI.getOperand(0).getReg() == predReg) {
602 (MI.getOperand(0).getReg() == cmpReg1 ||
604 MI.getOperand(0).getReg() == (unsigned)cmpOp2))) {
614 if (feederReg == cmpReg1) {
624 if (!foundFeeder && isSecondOpReg && feederReg == (unsigned)cmpOp2)
633 (feederReg == (unsigned)cmpOp2)) {
642 if (feederReg == (unsigned)cmpOp2)
lib/Target/Hexagon/HexagonOptAddrMode.cpp 133 if (StOp.isReg() && StOp.getReg() == TfrDefR)
170 if (OffsetReg == RR.Reg) {
lib/Target/Hexagon/HexagonSplitDouble.cpp 555 if (T == CmpR1 || T == CmpR2)
555 if (T == CmpR1 || T == CmpR2)
lib/Target/Hexagon/HexagonSubtarget.cpp 427 if (MO.isReg() && MO.isDef() && MO.getReg() == DepR)
435 if (MO.isReg() && MO.isUse() && MO.getReg() == DepR) {
lib/Target/Hexagon/HexagonVExtract.cpp 143 assert(ExtI->getOperand(1).getReg() == VecR);
lib/Target/Hexagon/HexagonVLIWPacketizer.cpp 312 if (MO.isReg() && MO.getReg() == DepReg && !MO.isImplicit())
673 getPostIncrementOperand(MI, HII).getReg() == DepReg) {
678 getPostIncrementOperand(PacketMI, HII).getReg() == DepReg) {
687 if (isLoadAbsSet(PacketMI) && getAbsSetOperand(PacketMI).getReg() == DepReg)
778 if (MO.isReg() && MO.getReg() == DepReg)
793 if (R == DepReg || HRI->isSuperRegister(DepReg, R))
803 if (MO.isReg() && MO.isUse() && MO.isImplicit() && MO.getReg() == DepReg)
1562 if (I.getOperand(0).getReg() == HRI->getStackRegister()) {
lib/Target/Lanai/LanaiInstrInfo.cpp 210 ((OI->getOperand(1).getReg() == SrcReg &&
211 OI->getOperand(2).getReg() == SrcReg2) ||
212 (OI->getOperand(1).getReg() == SrcReg2 &&
213 OI->getOperand(2).getReg() == SrcReg)))
220 OI->getOperand(1).getReg() == SrcReg &&
382 if (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
383 Sub->getOperand(2).getReg() == SrcReg) {
lib/Target/Mips/MipsInstrInfo.cpp 451 if (I->getOperand(1).getReg() == Subtarget.getABI().GetZeroReg())
lib/Target/Mips/MipsOptimizePICCall.cpp 172 if (MO.isReg() && MO.getReg() == Reg) {
lib/Target/PowerPC/PPCInstrInfo.cpp 1349 UseMI.getOperand(UseIdx).getReg() == Reg)
1817 ((Instr.getOperand(1).getReg() == SrcReg &&
1818 Instr.getOperand(2).getReg() == SrcReg2) ||
1819 (Instr.getOperand(1).getReg() == SrcReg2 &&
1820 Instr.getOperand(2).getReg() == SrcReg))) {
1865 ShouldSwap = SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
1866 Sub->getOperand(2).getReg() == SrcReg;
lib/Target/SystemZ/SystemZElimCompare.cpp 129 if (MI.getOperand(1).getReg() == Reg)
140 MI.getOperand(0).isDef() && MI.getOperand(0).getReg() == Reg)
lib/Target/SystemZ/SystemZInstrInfo.cpp 632 if (UseMI.getOperand(2).getReg() == Reg)
634 else if (UseMI.getOperand(1).getReg() == Reg)
646 if (UseMI.getOperand(2).getReg() == Reg)
648 else if (UseMI.getOperand(1).getReg() == Reg)
lib/Target/SystemZ/SystemZRegisterInfo.cpp 124 (TrueMO.getReg() == Reg ? FalseMO.getReg() : TrueMO.getReg());
lib/Target/WebAssembly/WebAssemblyRegStackify.cpp 392 if (MO.isReg() && MO.isDef() && MO.getReg() == Reg)
712 if (MO.isReg() && MO.getReg() == Reg)
lib/Target/X86/X86DomainReassignment.cpp 541 if (Op.isReg() && Op.getReg() == Reg)
lib/Target/X86/X86FrameLowering.cpp 423 PI->getOperand(0).getReg() == StackPtr){
424 assert(PI->getOperand(1).getReg() == StackPtr);
427 PI->getOperand(0).getReg() == StackPtr &&
428 PI->getOperand(1).getReg() == StackPtr &&
436 PI->getOperand(0).getReg() == StackPtr) {
437 assert(PI->getOperand(1).getReg() == StackPtr);
lib/Target/X86/X86InstrInfo.cpp 3370 ((OI.getOperand(1).getReg() == SrcReg &&
3371 OI.getOperand(2).getReg() == SrcReg2) ||
3372 (OI.getOperand(1).getReg() == SrcReg2 &&
3373 OI.getOperand(2).getReg() == SrcReg)))
3388 OI.getOperand(1).getReg() == SrcReg &&
3631 J->getOperand(1).getReg() == SrcReg) {
3694 (SrcReg2 != 0 && Sub && Sub->getOperand(1).getReg() == SrcReg2 &&
3695 Sub->getOperand(2).getReg() == SrcReg);
lib/Target/X86/X86SelectionDAGInfo.cpp 41 if (BaseReg == R)