|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
Derived Classes
include/llvm/CodeGen/GlobalISel/CSEMIRBuilder.h 32 class CSEMIRBuilder : public MachineIRBuilder {
include/llvm/CodeGen/GlobalISel/ConstantFoldingMIRBuilder.h 19 class ConstantFoldingMIRBuilder : public MachineIRBuilder {
Declarations
include/llvm/CodeGen/GlobalISel/CallLowering.h 33 class MachineIRBuilder;
include/llvm/CodeGen/GlobalISel/CombinerHelper.h 26 class MachineIRBuilder;
include/llvm/CodeGen/GlobalISel/CombinerInfo.h 22 class MachineIRBuilder;
include/llvm/CodeGen/GlobalISel/LegalizerInfo.h 38 class MachineIRBuilder;
lib/Target/AArch64/AArch64CallLowering.h 28 class MachineIRBuilder;
lib/Target/AMDGPU/AMDGPUInstructionSelector.h 38 class MachineIRBuilder;
lib/Target/AMDGPU/AMDGPURegisterBankInfo.h 29 class MachineIRBuilder;
lib/Target/ARM/ARMCallLowering.h 28 class MachineIRBuilder;
References
gen/lib/Target/AArch64/AArch64GenGICombiner.inc 28 MachineIRBuilder &B) const;
99 MachineIRBuilder &B) const {
include/llvm/CodeGen/GlobalISel/CSEMIRBuilder.h 32 class CSEMIRBuilder : public MachineIRBuilder {
include/llvm/CodeGen/GlobalISel/CallLowering.h 113 ValueHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
163 MachineIRBuilder &MIRBuilder;
195 MachineIRBuilder &MIRBuilder) const;
203 MachineIRBuilder &MIRBuilder) const;
209 bool handleAssignments(MachineIRBuilder &MIRBuilder,
214 MachineIRBuilder &MIRBuilder,
264 virtual bool lowerReturn(MachineIRBuilder &MIRBuilder, const Value *Val,
276 virtual bool lowerReturn(MachineIRBuilder &MIRBuilder, const Value *Val,
291 virtual bool lowerFormalArguments(MachineIRBuilder &MIRBuilder,
302 virtual bool lowerCall(MachineIRBuilder &MIRBuilder,
331 bool lowerCall(MachineIRBuilder &MIRBuilder, ImmutableCallSite CS,
include/llvm/CodeGen/GlobalISel/Combiner.h 41 std::unique_ptr<MachineIRBuilder> Builder;
include/llvm/CodeGen/GlobalISel/CombinerHelper.h 41 MachineIRBuilder &Builder;
48 CombinerHelper(GISelChangeObserver &Observer, MachineIRBuilder &B,
include/llvm/CodeGen/GlobalISel/CombinerInfo.h 68 MachineIRBuilder &B) const = 0;
include/llvm/CodeGen/GlobalISel/ConstantFoldingMIRBuilder.h 19 class ConstantFoldingMIRBuilder : public MachineIRBuilder {
include/llvm/CodeGen/GlobalISel/IRTranslator.h 207 bool translateBitCast(const User &U, MachineIRBuilder &MIRBuilder);
210 bool translateLoad(const User &U, MachineIRBuilder &MIRBuilder);
213 bool translateStore(const User &U, MachineIRBuilder &MIRBuilder);
216 bool translateMemFunc(const CallInst &CI, MachineIRBuilder &MIRBuilder,
219 void getStackGuard(Register DstReg, MachineIRBuilder &MIRBuilder);
222 MachineIRBuilder &MIRBuilder);
233 MachineIRBuilder &MIRBuilder);
236 MachineIRBuilder &MIRBuilder);
238 bool translateInlineAsm(const CallInst &CI, MachineIRBuilder &MIRBuilder);
248 MachineIRBuilder &MIRBuilder);
252 bool translateCall(const User &U, MachineIRBuilder &MIRBuilder);
254 bool translateInvoke(const User &U, MachineIRBuilder &MIRBuilder);
256 bool translateCallBr(const User &U, MachineIRBuilder &MIRBuilder);
258 bool translateLandingPad(const User &U, MachineIRBuilder &MIRBuilder);
263 MachineIRBuilder &MIRBuilder);
266 bool translatePHI(const User &U, MachineIRBuilder &MIRBuilder);
269 bool translateCompare(const User &U, MachineIRBuilder &MIRBuilder);
272 bool translateICmp(const User &U, MachineIRBuilder &MIRBuilder) {
277 bool translateFCmp(const User &U, MachineIRBuilder &MIRBuilder) {
288 MachineIRBuilder &MIRBuilder);
292 bool translateBr(const User &U, MachineIRBuilder &MIRBuilder);
301 MachineIRBuilder &MIB);
307 MachineIRBuilder &MIB,
320 MachineIRBuilder &MIB,
326 MachineIRBuilder &MIB);
328 bool translateSwitch(const User &U, MachineIRBuilder &MIRBuilder);
331 bool translateIndirectBr(const User &U, MachineIRBuilder &MIRBuilder);
333 bool translateExtractValue(const User &U, MachineIRBuilder &MIRBuilder);
335 bool translateInsertValue(const User &U, MachineIRBuilder &MIRBuilder);
337 bool translateSelect(const User &U, MachineIRBuilder &MIRBuilder);
339 bool translateGetElementPtr(const User &U, MachineIRBuilder &MIRBuilder);
341 bool translateAlloca(const User &U, MachineIRBuilder &MIRBuilder);
347 bool translateRet(const User &U, MachineIRBuilder &MIRBuilder);
349 bool translateFSub(const User &U, MachineIRBuilder &MIRBuilder);
351 bool translateFNeg(const User &U, MachineIRBuilder &MIRBuilder);
353 bool translateAdd(const User &U, MachineIRBuilder &MIRBuilder) {
356 bool translateSub(const User &U, MachineIRBuilder &MIRBuilder) {
359 bool translateAnd(const User &U, MachineIRBuilder &MIRBuilder) {
362 bool translateMul(const User &U, MachineIRBuilder &MIRBuilder) {
365 bool translateOr(const User &U, MachineIRBuilder &MIRBuilder) {
368 bool translateXor(const User &U, MachineIRBuilder &MIRBuilder) {
372 bool translateUDiv(const User &U, MachineIRBuilder &MIRBuilder) {
375 bool translateSDiv(const User &U, MachineIRBuilder &MIRBuilder) {
378 bool translateURem(const User &U, MachineIRBuilder &MIRBuilder) {
381 bool translateSRem(const User &U, MachineIRBuilder &MIRBuilder) {
384 bool translateIntToPtr(const User &U, MachineIRBuilder &MIRBuilder) {
387 bool translatePtrToInt(const User &U, MachineIRBuilder &MIRBuilder) {
390 bool translateTrunc(const User &U, MachineIRBuilder &MIRBuilder) {
393 bool translateFPTrunc(const User &U, MachineIRBuilder &MIRBuilder) {
396 bool translateFPExt(const User &U, MachineIRBuilder &MIRBuilder) {
399 bool translateFPToUI(const User &U, MachineIRBuilder &MIRBuilder) {
402 bool translateFPToSI(const User &U, MachineIRBuilder &MIRBuilder) {
405 bool translateUIToFP(const User &U, MachineIRBuilder &MIRBuilder) {
408 bool translateSIToFP(const User &U, MachineIRBuilder &MIRBuilder) {
411 bool translateUnreachable(const User &U, MachineIRBuilder &MIRBuilder) {
414 bool translateSExt(const User &U, MachineIRBuilder &MIRBuilder) {
418 bool translateZExt(const User &U, MachineIRBuilder &MIRBuilder) {
422 bool translateShl(const User &U, MachineIRBuilder &MIRBuilder) {
425 bool translateLShr(const User &U, MachineIRBuilder &MIRBuilder) {
428 bool translateAShr(const User &U, MachineIRBuilder &MIRBuilder) {
432 bool translateFAdd(const User &U, MachineIRBuilder &MIRBuilder) {
435 bool translateFMul(const User &U, MachineIRBuilder &MIRBuilder) {
438 bool translateFDiv(const User &U, MachineIRBuilder &MIRBuilder) {
441 bool translateFRem(const User &U, MachineIRBuilder &MIRBuilder) {
445 bool translateVAArg(const User &U, MachineIRBuilder &MIRBuilder);
447 bool translateInsertElement(const User &U, MachineIRBuilder &MIRBuilder);
449 bool translateExtractElement(const User &U, MachineIRBuilder &MIRBuilder);
451 bool translateShuffleVector(const User &U, MachineIRBuilder &MIRBuilder);
453 bool translateAtomicCmpXchg(const User &U, MachineIRBuilder &MIRBuilder);
454 bool translateAtomicRMW(const User &U, MachineIRBuilder &MIRBuilder);
455 bool translateFence(const User &U, MachineIRBuilder &MIRBuilder);
459 bool translateResume(const User &U, MachineIRBuilder &MIRBuilder) {
462 bool translateCleanupRet(const User &U, MachineIRBuilder &MIRBuilder) {
465 bool translateCatchRet(const User &U, MachineIRBuilder &MIRBuilder) {
468 bool translateCatchSwitch(const User &U, MachineIRBuilder &MIRBuilder) {
471 bool translateAddrSpaceCast(const User &U, MachineIRBuilder &MIRBuilder) {
474 bool translateCleanupPad(const User &U, MachineIRBuilder &MIRBuilder) {
477 bool translateCatchPad(const User &U, MachineIRBuilder &MIRBuilder) {
480 bool translateUserOp1(const User &U, MachineIRBuilder &MIRBuilder) {
483 bool translateUserOp2(const User &U, MachineIRBuilder &MIRBuilder) {
494 std::unique_ptr<MachineIRBuilder> CurBuilder;
499 std::unique_ptr<MachineIRBuilder> EntryBuilder;
include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h 27 MachineIRBuilder &Builder;
44 LegalizationArtifactCombiner(MachineIRBuilder &B, MachineRegisterInfo &MRI,
include/llvm/CodeGen/GlobalISel/LegalizerHelper.h 52 MachineIRBuilder &B);
54 GISelChangeObserver &Observer, MachineIRBuilder &B);
93 MachineIRBuilder &MIRBuilder;
250 createLibcall(MachineIRBuilder &MIRBuilder, RTLIB::Libcall Libcall,
255 LegalizerHelper::LegalizeResult createMemLibcall(MachineIRBuilder &MIRBuilder,
include/llvm/CodeGen/GlobalISel/LegalizerInfo.h 1151 MachineIRBuilder &MIRBuilder,
1157 MachineIRBuilder &MIRBuilder) const;
include/llvm/CodeGen/GlobalISel/RegBankSelect.h 507 MachineIRBuilder MIRBuilder;
lib/CodeGen/GlobalISel/CallLowering.cpp 32 bool CallLowering::lowerCall(MachineIRBuilder &MIRBuilder, ImmutableCallSite CS,
127 MachineIRBuilder &MIRBuilder) const {
153 MachineIRBuilder &MIRBuilder) const {
167 bool CallLowering::handleAssignments(MachineIRBuilder &MIRBuilder,
179 MachineIRBuilder &MIRBuilder,
lib/CodeGen/GlobalISel/Combiner.cpp 107 CSEInfo ? std::make_unique<CSEMIRBuilder>() : std::make_unique<MachineIRBuilder>();
119 MachineIRBuilder &B = *Builder.get();
lib/CodeGen/GlobalISel/CombinerHelper.cpp 35 MachineIRBuilder &B, GISelKnownBits *KB,
321 MachineIRBuilder &Builder, MachineInstr &DefMI, MachineOperand &UseMO,
715 MachineIRBuilder MIRBuilder(MI);
891 static Register getMemsetValue(Register Val, LLT Ty, MachineIRBuilder &MIB) {
967 MachineIRBuilder MIB(MI);
1097 MachineIRBuilder MIB(MI);
1204 MachineIRBuilder MIB(MI);
lib/CodeGen/GlobalISel/IRTranslator.cpp 288 MachineIRBuilder &MIRBuilder) {
306 bool IRTranslator::translateFSub(const User &U, MachineIRBuilder &MIRBuilder) {
324 bool IRTranslator::translateFNeg(const User &U, MachineIRBuilder &MIRBuilder) {
337 MachineIRBuilder &MIRBuilder) {
362 bool IRTranslator::translateRet(const User &U, MachineIRBuilder &MIRBuilder) {
384 bool IRTranslator::translateBr(const User &U, MachineIRBuilder &MIRBuilder) {
435 bool IRTranslator::translateSwitch(const User &U, MachineIRBuilder &MIB) {
511 MachineIRBuilder MIB(*MBB->getParent());
525 MachineIRBuilder MIB(*HeaderBB->getParent());
568 MachineIRBuilder &MIB) {
646 MachineIRBuilder &MIB,
720 MachineIRBuilder &MIB,
752 MachineIRBuilder &MIB) {
837 MachineIRBuilder &MIRBuilder) {
859 bool IRTranslator::translateLoad(const User &U, MachineIRBuilder &MIRBuilder) {
902 bool IRTranslator::translateStore(const User &U, MachineIRBuilder &MIRBuilder) {
967 MachineIRBuilder &MIRBuilder) {
982 MachineIRBuilder &MIRBuilder) {
1002 MachineIRBuilder &MIRBuilder) {
1022 MachineIRBuilder &MIRBuilder) {
1042 MachineIRBuilder &MIRBuilder) {
1050 MachineIRBuilder &MIRBuilder) {
1119 MachineIRBuilder &MIRBuilder,
1166 MachineIRBuilder &MIRBuilder) {
1187 MachineIRBuilder &MIRBuilder) {
1260 MachineIRBuilder &MIRBuilder) {
1279 MachineIRBuilder &MIRBuilder) {
1526 MachineIRBuilder &MIRBuilder) {
1545 MachineIRBuilder &MIRBuilder) {
1584 bool IRTranslator::translateCall(const User &U, MachineIRBuilder &MIRBuilder) {
1670 MachineIRBuilder &MIRBuilder) {
1721 MachineIRBuilder &MIRBuilder) {
1727 MachineIRBuilder &MIRBuilder) {
1785 MachineIRBuilder &MIRBuilder) {
1844 bool IRTranslator::translateVAArg(const User &U, MachineIRBuilder &MIRBuilder) {
1857 MachineIRBuilder &MIRBuilder) {
1881 MachineIRBuilder &MIRBuilder) {
1918 MachineIRBuilder &MIRBuilder) {
1927 bool IRTranslator::translatePHI(const User &U, MachineIRBuilder &MIRBuilder) {
1941 MachineIRBuilder &MIRBuilder) {
1972 MachineIRBuilder &MIRBuilder) {
2040 MachineIRBuilder &MIRBuilder) {
2234 EntryBuilder = std::make_unique<MachineIRBuilder>();
2235 CurBuilder = std::make_unique<MachineIRBuilder>();
lib/CodeGen/GlobalISel/Legalizer.cpp 180 std::unique_ptr<MachineIRBuilder> MIRBuilder;
191 MIRBuilder = std::make_unique<MachineIRBuilder>();
lib/CodeGen/GlobalISel/LegalizerHelper.cpp 68 MachineIRBuilder &Builder)
77 MachineIRBuilder &B)
360 llvm::createLibcall(MachineIRBuilder &MIRBuilder, RTLIB::Libcall Libcall,
380 simpleLibcall(MachineInstr &MI, MachineIRBuilder &MIRBuilder, unsigned Size,
392 llvm::createMemLibcall(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
482 conversionLibcall(MachineInstr &MI, MachineIRBuilder &MIRBuilder, Type *ToType,
3353 MachineIRBuilder &B = MIRBuilder;
lib/Target/AArch64/AArch64CallLowering.cpp 56 IncomingArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
108 FormalArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
119 CallReturnHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
131 OutgoingArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
256 bool AArch64CallLowering::lowerReturn(MachineIRBuilder &MIRBuilder,
376 static void handleMustTailForwardedRegisters(MachineIRBuilder &MIRBuilder,
417 MachineIRBuilder &MIRBuilder, const Function &F,
661 MachineIRBuilder &MIRBuilder, CallLoweringInfo &Info,
779 MachineIRBuilder &MIRBuilder, CallLoweringInfo &Info,
921 bool AArch64CallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
lib/Target/AArch64/AArch64CallLowering.h 36 bool lowerReturn(MachineIRBuilder &MIRBuilder, const Value *Val,
40 bool lowerFormalArguments(MachineIRBuilder &MIRBuilder, const Function &F,
43 bool lowerCall(MachineIRBuilder &MIRBuilder,
48 isEligibleForTailCallOptimization(MachineIRBuilder &MIRBuilder,
56 using RegHandler = std::function<void(MachineIRBuilder &, Type *, unsigned,
60 std::function<void(MachineIRBuilder &, int, CCValAssign &)>;
67 bool lowerTailCall(MachineIRBuilder &MIRBuilder, CallLoweringInfo &Info,
lib/Target/AArch64/AArch64InstructionSelector.cpp 101 MachineIRBuilder &MIRBuilder) const;
112 MachineIRBuilder &MIRBuilder) const;
135 MachineIRBuilder &MIRBuilder) const;
140 MachineIRBuilder &MIRBuilder) const;
143 MachineIRBuilder &MIRBuilder) const;
145 MachineIRBuilder &MIRBuilder) const;
147 MachineIRBuilder &MIRBuilder) const;
149 MachineIRBuilder &MIRBuilder) const;
153 MachineIRBuilder &MIRBuilder) const;
163 MachineIRBuilder &MIRBuilder) const;
235 MachineIRBuilder &MIB) const;
252 MachineIRBuilder &MIRBuilder) const;
597 MachineIRBuilder MIB(I);
971 MachineIRBuilder MIB(I);
1032 MachineIRBuilder MIB(I);
1074 MachineIRBuilder MIB(I);
1120 MachineIRBuilder MIB(I);
1182 MachineIRBuilder MIB(I);
1215 MachineIRBuilder MIB(I);
1391 MachineIRBuilder MIB(I);
1609 MachineIRBuilder MIB(I);
1720 MachineIRBuilder MIB(I);
1887 MachineIRBuilder MIRBuilder(I);
1911 MachineIRBuilder MIRBuilder(I);
2000 MachineIRBuilder MIB(I);
2075 MachineIRBuilder MIB(I);
2200 MachineIRBuilder MIRBuilder(I);
2338 MachineIRBuilder MIB(I);
2360 MachineIRBuilder MIB(I);
2377 MachineIRBuilder MIB(I);
2666 MachineIRBuilder MIB(I);
2684 MachineIRBuilder &MIRBuilder) const {
2724 MachineIRBuilder MIB(I);
2806 Register VecReg, unsigned LaneIdx, MachineIRBuilder &MIRBuilder) const {
2892 MachineIRBuilder MIRBuilder(I);
2917 MachineIRBuilder MIB(I);
2964 MachineIRBuilder MIB(I);
3056 MachineIRBuilder MIRBuilder(I);
3077 Constant *CPVal, MachineIRBuilder &MIRBuilder) const {
3147 MachineIRBuilder &MIRBuilder) const {
3171 MachineIRBuilder &MIRBuilder) const {
3197 MachineIRBuilder &MIRBuilder) const {
3225 MachineIRBuilder &MIRBuilder) const {
3273 MachineIRBuilder &MIRBuilder) const {
3366 MachineIRBuilder &MIRBuilder) const {
3379 MachineIRBuilder MIB(I);
3477 MachineIRBuilder &MIRBuilder) const {
3581 MachineIRBuilder MIB(I);
3686 MachineIRBuilder MIRBuilder(I);
3745 MachineIRBuilder &MIRBuilder) const {
3800 MachineIRBuilder MIRBuilder(I);
3860 MachineIRBuilder MIRBuilder(I);
3942 MachineIRBuilder MIRBuilder(I);
3967 MachineIRBuilder MIRBuilder(I);
4553 Register ExtReg, MachineIRBuilder &MIB) const {
4626 MachineIRBuilder MIB(*RootDef);
lib/Target/AArch64/AArch64LegalizerInfo.cpp 621 MachineIRBuilder &MIRBuilder,
643 MachineIRBuilder &MIRBuilder) const {
660 MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &MIRBuilder,
684 MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &MIRBuilder,
724 MachineIRBuilder &MIRBuilder) const {
lib/Target/AArch64/AArch64LegalizerInfo.h 31 MachineIRBuilder &MIRBuilder,
35 MachineIRBuilder &MIRBuilder) const override;
39 MachineIRBuilder &MIRBuilder) const;
41 MachineIRBuilder &MIRBuilder,
44 MachineIRBuilder &MIRBuilder,
lib/Target/AArch64/AArch64PreLegalizerCombiner.cpp 56 MachineIRBuilder &B) const override;
61 MachineIRBuilder &B) const {
lib/Target/AMDGPU/AMDGPUCallLowering.cpp 34 OutgoingValueHandler(MachineIRBuilder &B, MachineRegisterInfo &MRI,
78 IncomingArgHandler(MachineIRBuilder &B, MachineRegisterInfo &MRI,
138 FormalArgHandler(MachineIRBuilder &B, MachineRegisterInfo &MRI,
218 static void unpackRegsToOrigType(MachineIRBuilder &B,
261 bool AMDGPUCallLowering::lowerReturnVal(MachineIRBuilder &B,
291 bool AMDGPUCallLowering::lowerReturn(MachineIRBuilder &B,
340 Register AMDGPUCallLowering::lowerParameterPtr(MachineIRBuilder &B,
364 void AMDGPUCallLowering::lowerParameter(MachineIRBuilder &B,
387 MachineIRBuilder &B,
438 MachineIRBuilder &B, const Function &F,
490 static void packSplitRegsToOrigType(MachineIRBuilder &B,
551 MachineIRBuilder &B, const Function &F,
lib/Target/AMDGPU/AMDGPUCallLowering.h 26 Register lowerParameterPtr(MachineIRBuilder &B, Type *ParamTy,
29 void lowerParameter(MachineIRBuilder &B, Type *ParamTy, uint64_t Offset,
41 bool lowerReturnVal(MachineIRBuilder &B, const Value *Val,
47 bool lowerReturn(MachineIRBuilder &B, const Value *Val,
50 bool lowerFormalArgumentsKernel(MachineIRBuilder &B, const Function &F,
53 bool lowerFormalArguments(MachineIRBuilder &B, const Function &F,
lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp 920 AMDGPUInstructionSelector::splitBufferOffsets(MachineIRBuilder &B,
980 MachineIRBuilder B(MI);
lib/Target/AMDGPU/AMDGPUInstructionSelector.h 96 splitBufferOffsets(MachineIRBuilder &B, Register OrigOffset) const;
lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp 1092 MachineIRBuilder &B,
1139 MachineIRBuilder &B) const {
1212 MachineIRBuilder &B) const {
1318 MachineIRBuilder &B) const {
1345 MachineIRBuilder &B) const {
1373 MachineIRBuilder &B) {
1390 MachineIRBuilder &B) const {
1436 MachineIRBuilder &B, bool Signed) const {
1468 MachineIRBuilder &B) const {
1483 MachineIRBuilder HelperBuilder(MI);
1492 MachineIRBuilder &B) const {
1521 MachineIRBuilder &B) const {
1551 MachineIRBuilder &B) const {
1580 MachineIRBuilder &B, const GlobalValue *GV,
1636 MachineIRBuilder &B) const {
1706 MachineIRBuilder &B, GISelChangeObserver &Observer) const {
1718 MachineIRBuilder &B) const {
1730 MachineIRBuilder HelperBuilder(MI);
1738 MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const {
1787 bool AMDGPULegalizerInfo::loadInputValue(Register DstReg, MachineIRBuilder &B,
1837 MachineIRBuilder &B,
1861 MachineIRBuilder &B) const {
1878 MachineIRBuilder &B) const {
1938 MachineIRBuilder &B) const {
1971 MachineIRBuilder &B) const {
2007 MachineIRBuilder &B) const {
2041 MachineIRBuilder &B,
2052 Register AMDGPULegalizerInfo::handleD16VData(MachineIRBuilder &B,
2076 MachineIRBuilder &B,
2109 MachineIRBuilder &B) const {
lib/Target/AMDGPU/AMDGPULegalizerInfo.h 36 MachineIRBuilder &B,
41 MachineIRBuilder &B) const;
44 MachineIRBuilder &B) const;
46 MachineIRBuilder &B) const;
48 MachineIRBuilder &B) const;
50 MachineIRBuilder &B) const;
52 MachineIRBuilder &B, bool Signed) const;
54 MachineIRBuilder &B) const;
56 MachineIRBuilder &B) const;
58 MachineIRBuilder &B) const;
60 MachineIRBuilder &B) const;
63 Register DstReg, LLT PtrTy, MachineIRBuilder &B, const GlobalValue *GV,
67 MachineIRBuilder &B) const;
69 MachineIRBuilder &B,
73 MachineIRBuilder &B) const;
76 MachineIRBuilder &B) const;
81 bool loadInputValue(Register DstReg, MachineIRBuilder &B,
84 MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B,
88 MachineIRBuilder &B) const;
90 MachineIRBuilder &B) const;
92 MachineIRBuilder &B) const;
94 MachineIRBuilder &B) const;
97 MachineIRBuilder &B) const;
99 MachineIRBuilder &B, unsigned AddrSpace) const;
101 Register handleD16VData(MachineIRBuilder &B, MachineRegisterInfo &MRI,
104 MachineIRBuilder &B, bool IsFormat) const;
106 MachineIRBuilder &B) const override;
lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp 603 MachineIRBuilder &B,
662 MachineIRBuilder &B,
977 MachineIRBuilder &B, MachineInstr &MI, MachineRegisterInfo &MRI,
994 MachineIRBuilder B(MI);
1006 MachineIRBuilder B(MI);
1073 MachineIRBuilder B(MI);
1149 Register AMDGPURegisterBankInfo::handleD16VData(MachineIRBuilder &B,
1188 AMDGPURegisterBankInfo::splitBufferOffsets(MachineIRBuilder &B,
1249 AMDGPURegisterBankInfo::selectStoreIntrinsic(MachineIRBuilder &B,
1351 MachineIRBuilder B(MI);
1406 MachineIRBuilder B(MI);
1448 MachineIRBuilder B(MI);
1468 MachineIRBuilder B(MI);
1499 MachineIRBuilder B(MI);
1606 MachineIRBuilder B(MI);
1674 MachineIRBuilder B(MI);
1741 MachineIRBuilder B(MI);
lib/Target/AMDGPU/AMDGPURegisterBankInfo.h 54 MachineIRBuilder &B,
59 bool executeInWaterfallLoop(MachineIRBuilder &B,
77 Register handleD16VData(MachineIRBuilder &B, MachineRegisterInfo &MRI,
81 splitBufferOffsets(MachineIRBuilder &B, Register Offset) const;
83 MachineInstr *selectStoreIntrinsic(MachineIRBuilder &B,
108 void split64BitValueForMapping(MachineIRBuilder &B,
lib/Target/ARM/ARMCallLowering.cpp 89 OutgoingValueHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
237 bool ARMCallLowering::lowerReturnVal(MachineIRBuilder &MIRBuilder,
265 bool ARMCallLowering::lowerReturn(MachineIRBuilder &MIRBuilder,
286 IncomingValueHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
404 FormalArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
417 MachineIRBuilder &MIRBuilder, const Function &F,
474 CallReturnHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
503 bool ARMCallLowering::lowerCall(MachineIRBuilder &MIRBuilder, CallLoweringInfo &Info) const {
lib/Target/ARM/ARMCallLowering.h 35 bool lowerReturn(MachineIRBuilder &MIRBuilder, const Value *Val,
38 bool lowerFormalArguments(MachineIRBuilder &MIRBuilder, const Function &F,
41 bool lowerCall(MachineIRBuilder &MIRBuilder,
45 bool lowerReturnVal(MachineIRBuilder &MIRBuilder, const Value *Val,
lib/Target/ARM/ARMLegalizerInfo.cpp 362 MachineIRBuilder &MIRBuilder,
lib/Target/ARM/ARMLegalizerInfo.h 32 MachineIRBuilder &MIRBuilder,
lib/Target/Mips/MipsCallLowering.cpp 92 IncomingValueHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI)
122 CallReturnHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
227 OutgoingValueHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
413 bool MipsCallLowering::lowerReturn(MachineIRBuilder &MIRBuilder,
454 MachineIRBuilder &MIRBuilder, const Function &F,
537 bool MipsCallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
lib/Target/Mips/MipsCallLowering.h 28 MipsHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI)
42 MachineIRBuilder &MIRBuilder;
65 bool lowerReturn(MachineIRBuilder &MIRBuilder, const Value *Val,
68 bool lowerFormalArguments(MachineIRBuilder &MIRBuilder, const Function &F,
71 bool lowerCall(MachineIRBuilder &MIRBuilder,
lib/Target/Mips/MipsInstructionSelector.cpp 43 MachineIRBuilder &B) const;
130 MachineIRBuilder &B) const {
469 MachineIRBuilder B(I);
484 MachineIRBuilder B(I);
496 MachineIRBuilder B(I);
689 MachineIRBuilder B(I);
lib/Target/Mips/MipsLegalizerInfo.cpp 243 MachineIRBuilder &MIRBuilder,
300 MachineIRBuilder &MIRBuilder,
315 MachineIRBuilder &MIRBuilder,
327 MachineIRBuilder &MIRBuilder,
339 MachineIRBuilder &MIRBuilder) const {
lib/Target/Mips/MipsLegalizerInfo.h 29 MachineIRBuilder &MIRBuilder,
33 MachineIRBuilder &MIRBuilder) const override;
lib/Target/Mips/MipsPreLegalizerCombiner.cpp 33 MachineIRBuilder &B) const override;
38 MachineIRBuilder &B) const {
lib/Target/Mips/MipsRegisterBankInfo.cpp 664 MachineIRBuilder B(MI);
lib/Target/RISCV/RISCVCallLowering.cpp 24 bool RISCVCallLowering::lowerReturn(MachineIRBuilder &MIRBuilder,
38 MachineIRBuilder &MIRBuilder, const Function &F,
47 bool RISCVCallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
lib/Target/RISCV/RISCVCallLowering.h 30 bool lowerReturn(MachineIRBuilder &MIRBuiler, const Value *Val,
33 bool lowerFormalArguments(MachineIRBuilder &MIRBuilder, const Function &F,
36 bool lowerCall(MachineIRBuilder &MIRBuilder,
lib/Target/X86/X86CallLowering.cpp 99 OutgoingValueHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
188 MachineIRBuilder &MIRBuilder, const Value *Val,
230 IncomingValueHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
302 FormalArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
313 CallReturnHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
328 MachineIRBuilder &MIRBuilder, const Function &F,
378 bool X86CallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
lib/Target/X86/X86CallLowering.h 31 bool lowerReturn(MachineIRBuilder &MIRBuilder, const Value *Val,
34 bool lowerFormalArguments(MachineIRBuilder &MIRBuilder, const Function &F,
37 bool lowerCall(MachineIRBuilder &MIRBuilder,
lib/Target/X86/X86LegalizerInfo.cpp 90 MachineIRBuilder &MIRBuilder) const {
lib/Target/X86/X86LegalizerInfo.h 36 MachineIRBuilder &MIRBuilder) const override;
tools/llvm-exegesis/lib/Assembler.cpp 129 MachineIRBuilder MIB(MF);
unittests/CodeGen/GlobalISel/GISelMITest.h 158 MachineIRBuilder B;
usr/include/c++/7.4.0/bits/unique_ptr.h 68 default_delete(const default_delete<_Up>&) noexcept { }
72 operator()(_Tp* __ptr) const
74 static_assert(!is_void<_Tp>::value,
76 static_assert(sizeof(_Tp)>0,
122 using type = _Up*;
137 using pointer = typename _Ptr<_Tp, _Dp>::type;
161 typename __uniq_ptr_impl<_Tp, _Up>::_DeleterConstraint::type;
163 __uniq_ptr_impl<_Tp, _Dp> _M_t;
166 using pointer = typename __uniq_ptr_impl<_Tp, _Dp>::pointer;
167 using element_type = _Tp;
252 unique_ptr(unique_ptr<_Up, _Ep>&& __u) noexcept
297 __safe_conversion_up<_Up, _Ep>,
301 operator=(unique_ptr<_Up, _Ep>&& __u) noexcept
811 { typedef unique_ptr<_Tp> __single_object; };
823 inline typename _MakeUniq<_Tp>::__single_object
825 { return unique_ptr<_Tp>(new _Tp(std::forward<_Args>(__args)...)); }
usr/include/c++/7.4.0/type_traits 215 : public __is_void_helper<typename remove_cv<_Tp>::type>::type
581 : public __or_<is_lvalue_reference<_Tp>,
582 is_rvalue_reference<_Tp>>::type
601 : public __not_<__or_<is_function<_Tp>, is_reference<_Tp>,
601 : public __not_<__or_<is_function<_Tp>, is_reference<_Tp>,
602 is_void<_Tp>>>::type
638 : public __or_<is_object<_Tp>, is_reference<_Tp>>::type
638 : public __or_<is_object<_Tp>, is_reference<_Tp>>::type
1554 { typedef _Tp type; };
1563 { typedef _Tp type; };
1574 remove_const<typename remove_volatile<_Tp>::type>::type type;
1645 { typedef _Tp& type; };
1650 : public __add_lvalue_reference_helper<_Tp>