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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenSubtargetInfo.inc17815 if (Bits[AArch64::FeatureCallSavedX8]) CustomCallSavedXRegs[8] = true;
17816 if (Bits[AArch64::FeatureCallSavedX9]) CustomCallSavedXRegs[9] = true;
17817 if (Bits[AArch64::FeatureCallSavedX10]) CustomCallSavedXRegs[10] = true;
17818 if (Bits[AArch64::FeatureCallSavedX11]) CustomCallSavedXRegs[11] = true;
17819 if (Bits[AArch64::FeatureCallSavedX12]) CustomCallSavedXRegs[12] = true;
17820 if (Bits[AArch64::FeatureCallSavedX13]) CustomCallSavedXRegs[13] = true;
17821 if (Bits[AArch64::FeatureCallSavedX14]) CustomCallSavedXRegs[14] = true;
17822 if (Bits[AArch64::FeatureCallSavedX15]) CustomCallSavedXRegs[15] = true;
17823 if (Bits[AArch64::FeatureCallSavedX18]) CustomCallSavedXRegs[18] = true;
17868 if (Bits[AArch64::FeatureReserveX1]) ReserveXRegister[1] = true;
17869 if (Bits[AArch64::FeatureReserveX2]) ReserveXRegister[2] = true;
17870 if (Bits[AArch64::FeatureReserveX3]) ReserveXRegister[3] = true;
17871 if (Bits[AArch64::FeatureReserveX4]) ReserveXRegister[4] = true;
17872 if (Bits[AArch64::FeatureReserveX5]) ReserveXRegister[5] = true;
17873 if (Bits[AArch64::FeatureReserveX6]) ReserveXRegister[6] = true;
17874 if (Bits[AArch64::FeatureReserveX7]) ReserveXRegister[7] = true;
17875 if (Bits[AArch64::FeatureReserveX9]) ReserveXRegister[9] = true;
17876 if (Bits[AArch64::FeatureReserveX10]) ReserveXRegister[10] = true;
17877 if (Bits[AArch64::FeatureReserveX11]) ReserveXRegister[11] = true;
17878 if (Bits[AArch64::FeatureReserveX12]) ReserveXRegister[12] = true;
17879 if (Bits[AArch64::FeatureReserveX13]) ReserveXRegister[13] = true;
17880 if (Bits[AArch64::FeatureReserveX14]) ReserveXRegister[14] = true;
17881 if (Bits[AArch64::FeatureReserveX15]) ReserveXRegister[15] = true;
17882 if (Bits[AArch64::FeatureReserveX18]) ReserveXRegister[18] = true;
17883 if (Bits[AArch64::FeatureReserveX20]) ReserveXRegister[20] = true;
17884 if (Bits[AArch64::FeatureReserveX21]) ReserveXRegister[21] = true;
17885 if (Bits[AArch64::FeatureReserveX22]) ReserveXRegister[22] = true;
17886 if (Bits[AArch64::FeatureReserveX23]) ReserveXRegister[23] = true;
17887 if (Bits[AArch64::FeatureReserveX24]) ReserveXRegister[24] = true;
17888 if (Bits[AArch64::FeatureReserveX25]) ReserveXRegister[25] = true;
17889 if (Bits[AArch64::FeatureReserveX26]) ReserveXRegister[26] = true;
17890 if (Bits[AArch64::FeatureReserveX27]) ReserveXRegister[27] = true;
17891 if (Bits[AArch64::FeatureReserveX28]) ReserveXRegister[28] = true;
gen/lib/Target/RISCV/RISCVGenSubtargetInfo.inc 221 if (Bits[RISCV::FeatureReserveX1]) UserReservedRegister[RISCV::X1] = true;
222 if (Bits[RISCV::FeatureReserveX2]) UserReservedRegister[RISCV::X2] = true;
223 if (Bits[RISCV::FeatureReserveX3]) UserReservedRegister[RISCV::X3] = true;
224 if (Bits[RISCV::FeatureReserveX4]) UserReservedRegister[RISCV::X4] = true;
225 if (Bits[RISCV::FeatureReserveX5]) UserReservedRegister[RISCV::X5] = true;
226 if (Bits[RISCV::FeatureReserveX6]) UserReservedRegister[RISCV::X6] = true;
227 if (Bits[RISCV::FeatureReserveX7]) UserReservedRegister[RISCV::X7] = true;
228 if (Bits[RISCV::FeatureReserveX8]) UserReservedRegister[RISCV::X8] = true;
229 if (Bits[RISCV::FeatureReserveX9]) UserReservedRegister[RISCV::X9] = true;
230 if (Bits[RISCV::FeatureReserveX10]) UserReservedRegister[RISCV::X10] = true;
231 if (Bits[RISCV::FeatureReserveX11]) UserReservedRegister[RISCV::X11] = true;
232 if (Bits[RISCV::FeatureReserveX12]) UserReservedRegister[RISCV::X12] = true;
233 if (Bits[RISCV::FeatureReserveX13]) UserReservedRegister[RISCV::X13] = true;
234 if (Bits[RISCV::FeatureReserveX14]) UserReservedRegister[RISCV::X14] = true;
235 if (Bits[RISCV::FeatureReserveX15]) UserReservedRegister[RISCV::X15] = true;
236 if (Bits[RISCV::FeatureReserveX16]) UserReservedRegister[RISCV::X16] = true;
237 if (Bits[RISCV::FeatureReserveX17]) UserReservedRegister[RISCV::X17] = true;
238 if (Bits[RISCV::FeatureReserveX18]) UserReservedRegister[RISCV::X18] = true;
239 if (Bits[RISCV::FeatureReserveX19]) UserReservedRegister[RISCV::X19] = true;
240 if (Bits[RISCV::FeatureReserveX20]) UserReservedRegister[RISCV::X20] = true;
241 if (Bits[RISCV::FeatureReserveX21]) UserReservedRegister[RISCV::X21] = true;
242 if (Bits[RISCV::FeatureReserveX22]) UserReservedRegister[RISCV::X22] = true;
243 if (Bits[RISCV::FeatureReserveX23]) UserReservedRegister[RISCV::X23] = true;
244 if (Bits[RISCV::FeatureReserveX24]) UserReservedRegister[RISCV::X24] = true;
245 if (Bits[RISCV::FeatureReserveX25]) UserReservedRegister[RISCV::X25] = true;
246 if (Bits[RISCV::FeatureReserveX26]) UserReservedRegister[RISCV::X26] = true;
247 if (Bits[RISCV::FeatureReserveX27]) UserReservedRegister[RISCV::X27] = true;
248 if (Bits[RISCV::FeatureReserveX28]) UserReservedRegister[RISCV::X28] = true;
249 if (Bits[RISCV::FeatureReserveX29]) UserReservedRegister[RISCV::X29] = true;
250 if (Bits[RISCV::FeatureReserveX30]) UserReservedRegister[RISCV::X30] = true;
251 if (Bits[RISCV::FeatureReserveX31]) UserReservedRegister[RISCV::X31] = true;
include/llvm/ADT/PackedVector.h 40 Bits[(Idx << (BitNum-1)) + i] = val & (T(1) << i);
63 Bits[(Idx << (BitNum-1)) + i] = val & (T(1) << i);
include/llvm/ADT/SmallBitVector.h 340 (*BV)[i] = (OldBits >> i) & 1;
460 return getPointer()->operator[](Idx);
lib/CodeGen/AggressiveAntiDepBreaker.cpp 934 if (!RegAliases[R])
lib/CodeGen/DwarfEHPrepare.cpp 168 if (ResumeReachable[I]) {
lib/CodeGen/LiveRangeCalc.cpp 280 if (DefOnEntry[BN])
282 if (UndefOnEntry[BN])
287 DefOnEntry[S->getNumber()] = true;
288 DefOnEntry[BN] = true;
302 if (Seen[N]) {
330 if (UndefOnEntry[N] || LR.isUndefIn(Undefs, Begin, End)) {
331 UndefOnEntry[N] = true;
334 if (DefOnEntry[N])
342 UndefOnEntry[BN] = true;
599 if (DefBlocks[BN])
lib/CodeGen/ModuloSchedule.cpp 1594 LS[I] = 1;
1622 LS[J] = 1;
lib/CodeGen/SelectionDAG/SelectionDAG.cpp 1615 if (UndefElements[MaskVec[i] - Offset]) {
1621 if (!UndefElements[i])
9443 (*UndefElements)[i] = true;
lib/CodeGen/TargetRegisterInfo.cpp 69 if (Checked[Reg])
lib/DebugInfo/MSF/MSFBuilder.cpp 43 FreeBlocks[kSuperBlockBlock] = false;
44 FreeBlocks[kFreePageMap0Block] = false;
45 FreeBlocks[kFreePageMap1Block] = false;
46 FreeBlocks[BlockMapAddr] = false;
76 FreeBlocks[BlockMapAddr] = true;
77 FreeBlocks[Addr] = false;
88 FreeBlocks[B] = true;
94 FreeBlocks[B] = false;
216 FreeBlocks[P] = true;
277 FreeBlocks[B] = true;
lib/DebugInfo/PDB/Native/PDBFile.cpp 166 ContainerLayout.FreePageMap[BI] = true;
lib/Support/CodeGenCoverage.cpp 37 RuleCoverage[RuleID] = true;
lib/Support/GlobPattern.cpp 41 BV[Start] = true;
53 BV[(uint8_t)C] = true;
58 BV[(uint8_t)C] = true;
102 BV[(uint8_t)S[0]] = true;
lib/Target/AArch64/AArch64RegisterInfo.cpp 223 return getReservedRegs(MF)[Reg];
lib/Target/AArch64/AArch64SpeculationHardening.cpp 445 if (RegsAlreadyMasked[Reg])
632 if (Op.isReg() && RegsNeedingCSDBBeforeUse[Op.getReg()]) {
lib/Target/AMDGPU/SIISelLowering.cpp 2123 if (Arg.isOrigArg() && Skipped[Arg.getOrigArgIndex()]) {
lib/Target/AMDGPU/SIMachineFunctionInfo.cpp 373 !OtherUsedRegs[Reg];
lib/Target/Hexagon/BitTracker.cpp 1075 if (BlockScanned[Edge.second])
1077 BlockScanned[Edge.second] = true;
lib/Target/Hexagon/HexagonBitSimplify.cpp 118 return BitVector::operator[](Idx);
1295 if (Used[i+DB] && DC[DB+i] != SC[SB+i])
lib/Target/Hexagon/HexagonBlockRanges.cpp 228 Reserved[R] = true;
252 if (!Reserved[R.Reg])
255 if (!Reserved[S.Reg])
324 if (Register::isPhysicalRegister(R.Reg) && Reserved[R.Reg])
341 if (Register::isPhysicalRegister(S.Reg) && Reserved[S.Reg])
360 if (Reserved[PR])
478 if (Reserved[S.Reg] || Visited[S.Reg])
478 if (Reserved[S.Reg] || Visited[S.Reg])
481 Visited[S.Reg] = true;
lib/Target/Hexagon/HexagonFrameLowering.cpp 438 CSR[*S] = true;
801 if (Path[BN] || DoneF[BN])
801 if (Path[BN] || DoneF[BN])
803 if (DoneT[BN])
808 Path[BN] = true;
831 DoneT[BN] = true;
834 DoneF[BN] = true;
836 Path[BN] = false;
1444 SRegs[*SR] = true;
1456 SRegs[*SR] = false;
1471 TmpSup[*SR] = true;
1476 if (!Reserved[*SR])
1478 TmpSup[R] = false;
1495 if (!SRegs[*SR])
1497 SRegs[R] = false;
1514 if (!SRegs[S->Reg])
1520 SRegs[S->Reg] = false;
1537 SRegs[R] = false;
2437 Regs[R] = true;
lib/Target/Hexagon/HexagonGenInsert.cpp 134 return BitVector::operator[](Idx);
lib/Target/Hexagon/HexagonGenMux.cpp 148 SRs[*I] = true;
155 Set[Reg] = true;
lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp 1135 if (Picked[M]) {
lib/Target/Hexagon/HexagonSplitDouble.cpp 245 if (FixedRegs[x])
269 if (FixedRegs[u])
288 unsigned ThisP = FixedRegs[x] ? 0 : NextP++;
lib/Target/Hexagon/HexagonVLIWPacketizer.cpp 1206 DeadDefs[MO.getReg()] = true;
1213 if (R != Hexagon::USR_OVF && DeadDefs[R])
lib/Target/Hexagon/RDFLiveness.cpp 906 if (!Live[*AR])
lib/Target/Hexagon/RDFRegisters.cpp 36 if (RI.RegClass != nullptr && !BadRC[R]) {
lib/Target/PowerPC/PPCFrameLowering.cpp 2154 if (BVCalleeSaved[Reg] ||
lib/Target/WebAssembly/WebAssemblyExplicitLocals.cpp 224 UseEmpty[I] = MRI.use_empty(Register::index2VirtReg(I));
283 if (UseEmpty[Register::virtReg2Index(OldReg)]) {
lib/Target/X86/X86ISelLowering.cpp 8289 if (!(UndefElements[0] || (ScalarSize != 32 && ScalarSize != 64)))
tools/clang/lib/Analysis/CFGReachabilityAnalysis.cpp 31 if (!analyzed[DstBlockID]) {
33 analyzed[DstBlockID] = true;
37 return reachable[DstBlockID][Src->getBlockID()];
57 if (visited[block->getBlockID()])
59 visited[block->getBlockID()] = true;
64 DstReachability[block->getBlockID()] = true;
tools/clang/lib/Analysis/LiveVariables.cpp 51 if (block && !enqueuedBlocks[block->getBlockID()]) {
52 enqueuedBlocks[block->getBlockID()] = true;
69 enqueuedBlocks[b->getBlockID()] = false;
601 if (!everAnalyzedBlock[block->getBlockID()])
602 everAnalyzedBlock[block->getBlockID()] = true;
tools/clang/lib/Analysis/ReachableCode.cpp 319 if (!Reachable[Start->getBlockID()]) {
321 Reachable[Start->getBlockID()] = true;
363 if (!Reachable[blockID]) {
419 if (Reachable[blockID] || Visited[blockID])
419 if (Reachable[blockID] || Visited[blockID])
421 Visited[blockID] = true;
432 if (Visited[blockID]) {
436 if (!Reachable[blockID]) {
438 Visited[blockID] = true;
494 if (Reachable[Block->getBlockID()])
535 if (Reachable[Block->getBlockID()])
709 if (reachable[block->getBlockID()])
tools/clang/lib/Analysis/UninitializedValues.cpp 233 enqueuedBlocks[(*PO_I)->getBlockID()] = false;
248 if (!Successor || enqueuedBlocks[Successor->getBlockID()])
251 enqueuedBlocks[Successor->getBlockID()] = true;
272 assert(enqueuedBlocks[B->getBlockID()] == true);
273 enqueuedBlocks[B->getBlockID()] = false;
841 wasAnalyzed[block->getBlockID()] = true;
850 if (wasAnalyzed[pred->getBlockID()]) {
886 hadUse[currentBlock] = true;
894 hadUse[currentBlock] = true;
931 wasAnalyzed[cfg.getEntry().getBlockID()] = true;
941 if (changed || !previouslyVisited[block->getBlockID()])
943 previouslyVisited[block->getBlockID()] = true;
951 if (PBH.hadUse[block->getBlockID()]) {
tools/clang/lib/Basic/SourceManager.cpp 574 assert(!SLocEntryLoaded[Index] && "FileID already loaded");
577 SLocEntryLoaded[Index] = true;
638 assert(!SLocEntryLoaded[Index] && "FileID already loaded");
640 SLocEntryLoaded[Index] = true;
tools/clang/lib/CodeGen/CGStmt.cpp 2331 if ((i < ResultTypeRequiresCast.size()) && ResultTypeRequiresCast[i]) {
tools/clang/lib/Sema/AnalysisBasedWarnings.cpp 287 Queued[ThrowBlock.getBlockID()] = true;
294 if (!Succ.isReachable() || Queued[Succ->getBlockID()])
310 Queued[Succ->getBlockID()] = true;
324 if (!Reachable[B->getBlockID()])
413 if (!live[B->getBlockID()]) {
442 if (!live[B.getBlockID()])
tools/clang/lib/StaticAnalyzer/Checkers/DeadStoresChecker.cpp 91 llvm::BitVector::reference isReachable = reachable[block->getBlockID()];
tools/clang/tools/extra/clang-tidy/bugprone/BranchCloneCheck.cpp 117 if (KnownAsClone[i])
123 if (KnownAsClone[j] ||
129 KnownAsClone[j] = true;
tools/dsymutil/DwarfLinker.cpp 2819 if (!ProcessedFiles[i]) {
2821 LockGuard, [&]() { return ProcessedFiles[i]; });
unittests/ADT/BitVectorTest.cpp 75 EXPECT_TRUE(Vec[i]);
80 EXPECT_FALSE(Vec[0]);
81 EXPECT_TRUE(Vec[32]);
82 EXPECT_FALSE(Vec[56]);
105 EXPECT_TRUE(Vec[i]);
110 EXPECT_FALSE(Vec[0]);
111 EXPECT_TRUE(Vec[32]);
112 EXPECT_FALSE(Vec[60]);
113 EXPECT_FALSE(Vec[129]);
116 EXPECT_TRUE(Vec[60]);
119 EXPECT_FALSE(Vec[60]);
123 EXPECT_FALSE(Vec[32]);
126 EXPECT_TRUE(Vec[32]);
732 Vec[0] = Vec[1] = Vec[2] = true;
732 Vec[0] = Vec[1] = Vec[2] = true;
732 Vec[0] = Vec[1] = Vec[2] = true;
734 Vec[2] = Vec[1] = Vec[0] = false;
734 Vec[2] = Vec[1] = Vec[0] = false;
734 Vec[2] = Vec[1] = Vec[0] = false;
unittests/IR/ConstantRangeTest.cpp 1121 if (Results[Bias]) {
utils/TableGen/CodeGenDAGPatterns.cpp 4621 if (MatchedPatterns[i])
4633 if (!MatchedPatterns[p])
4634 Matches[p] = (Predicates == PatternsToMatch[p].getPredicates());
4660 if (!Matches[p])
4683 P.push_back(P[i]);
utils/TableGen/CodeGenRegisters.cpp 1008 if (SuperRegRCsBV[RC.EnumValue])
utils/TableGen/RegisterInfoEmitter.cpp 606 Values[v] = true;