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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenGlobalISel.inc43347 GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_ASHR,
43384 GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_ASHR,
43432 GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_ASHR,
43469 GIM_CheckOpcode, /*MI*/4, TargetOpcode::G_ASHR,
gen/lib/Target/ARM/ARMGenGlobalISel.inc 1093 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ASHR,
1099 GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_ASHR,
1129 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ASHR,
1135 GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_ASHR,
1166 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ASHR,
1172 GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_ASHR,
1202 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ASHR,
1208 GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_ASHR,
4395 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ASHR,
4401 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ASHR,
4424 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ASHR,
4430 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ASHR,
5725 GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_ASHR,
5765 GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_ASHR,
5794 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ASHR,
5834 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ASHR,
5878 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ASHR,
5919 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ASHR,
6130 GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_ASHR,
6171 GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_ASHR,
6492 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ASHR,
6527 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ASHR,
6696 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ASHR,
6731 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ASHR,
gen/lib/Target/Mips/MipsGenGlobalISel.inc12341 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ASHR,
12480 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ASHR,
include/llvm/CodeGen/GlobalISel/ConstantFoldingMIRBuilder.h 36 case TargetOpcode::G_ASHR:
include/llvm/CodeGen/GlobalISel/IRTranslator.h 429 return translateBinaryOp(TargetOpcode::G_ASHR, U, MIRBuilder);
include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h 1297 return buildInstr(TargetOpcode::G_ASHR, {Dst}, {Src0, Src1}, Flags);
lib/CodeGen/GlobalISel/CSEInfo.cpp 37 case TargetOpcode::G_ASHR:
lib/CodeGen/GlobalISel/CSEMIRBuilder.cpp 146 case TargetOpcode::G_ASHR:
lib/CodeGen/GlobalISel/GISelKnownBits.cpp 308 case TargetOpcode::G_ASHR:
327 case TargetOpcode::G_ASHR:
lib/CodeGen/GlobalISel/LegalizerHelper.cpp 881 case TargetOpcode::G_ASHR:
1055 .buildInstr(TargetOpcode::G_ASHR, {NarrowTy},
1576 case TargetOpcode::G_ASHR:
1581 unsigned CvtOp = MI.getOpcode() == TargetOpcode::G_ASHR ?
1964 MIRBuilder.buildInstr(TargetOpcode::G_ASHR)
2270 MIRBuilder.buildInstr(TargetOpcode::G_ASHR, {DstReg}, {TmpRes, MIBSz->getOperand(0).getReg()});
3001 case G_ASHR:
3203 case TargetOpcode::G_ASHR: {
lib/CodeGen/GlobalISel/MachineIRBuilder.cpp 991 case TargetOpcode::G_ASHR:
lib/CodeGen/GlobalISel/Utils.cpp 354 case TargetOpcode::G_ASHR:
lib/Target/AArch64/AArch64InstructionSelector.cpp 458 case TargetOpcode::G_ASHR:
471 case TargetOpcode::G_ASHR:
1041 assert(I.getOpcode() == TargetOpcode::G_ASHR);
1161 case TargetOpcode::G_ASHR:
1854 case TargetOpcode::G_ASHR:
4447 case TargetOpcode::G_ASHR:
lib/Target/AArch64/AArch64LegalizerInfo.cpp 120 getActionDefinitionsBuilder({G_LSHR, G_ASHR})
633 case TargetOpcode::G_ASHR:
662 assert(MI.getOpcode() == TargetOpcode::G_ASHR ||
lib/Target/AArch64/AArch64RegisterBankInfo.cpp 557 case TargetOpcode::G_ASHR: {
lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp 890 auto &Shifts = getActionDefinitionsBuilder({G_SHL, G_LSHR, G_ASHR})
lib/Target/ARM/ARMInstructionSelector.cpp 1059 case G_ASHR:
lib/Target/ARM/ARMLegalizerInfo.cpp 102 getActionDefinitionsBuilder({G_ASHR, G_LSHR, G_SHL})
lib/Target/ARM/ARMRegisterBankInfo.cpp 245 case G_ASHR:
lib/Target/Mips/MipsLegalizerInfo.cpp 155 getActionDefinitionsBuilder({G_SHL, G_ASHR, G_LSHR})
lib/Target/Mips/MipsRegisterBankInfo.cpp 450 case G_ASHR:
lib/Target/X86/X86LegalizerInfo.cpp 160 {G_SHL, G_LSHR, G_ASHR})
272 {G_SHL, G_LSHR, G_ASHR})
lib/Target/X86/X86RegisterBankInfo.cpp 186 case TargetOpcode::G_ASHR: {
unittests/CodeGen/GlobalISel/ConstantFoldingTest.cpp 108 ConstantFoldBinOp(TargetOpcode::G_ASHR, MIBCst1->getOperand(0).getReg(),
113 ConstantFoldBinOp(TargetOpcode::G_ASHR, MIBFCst2->getOperand(0).getReg(),