reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

gen/lib/Target/AMDGPU/AMDGPUGenGlobalISel.inc

  208   LLT::pointer(0, 64),
  209   LLT::pointer(1, 64),
  210   LLT::pointer(2, 32),
  211   LLT::pointer(3, 32),
  212   LLT::pointer(4, 64),
  213   LLT::pointer(5, 32),
  214   LLT::pointer(6, 32),

include/llvm/Support/LowLevelTypeImpl.h

  168       return pointer(getAddressSpace(), getScalarSizeInBits());

lib/CodeGen/GlobalISel/LegalizerInfo.cpp

  643                                  : LLT::pointer(Aspect.Type.getAddressSpace(),

lib/CodeGen/LowLevelType.cpp

   28     return LLT::pointer(PTy->getAddressSpace(), DL.getTypeSizeInBits(&Ty));

lib/CodeGen/MIRParser/MIParser.cpp

 1540     Ty = LLT::pointer(AS, DL.getPointerSizeInBits(AS));
 1580     Ty = LLT::pointer(AS, DL.getPointerSizeInBits(AS));

lib/Target/AArch64/AArch64CallLowering.cpp

   65     Register AddrReg = MRI.createGenericVirtualRegister(LLT::pointer(0, 64));
  144     LLT p0 = LLT::pointer(0, 64);

lib/Target/AArch64/AArch64InstructionSelector.cpp

  839   else if (Ty == LLT::scalar(64) || Ty == LLT::pointer(0, 64))
 1492     const LLT p0 = LLT::pointer(0, 64);
 1675     if (Ty != LLT::pointer(0, 64)) {
 1677                         << ", expected: " << LLT::pointer(0, 64) << '\n');
 1724     if (PtrTy != LLT::pointer(0, 64)) {
 1726                         << ", expected: " << LLT::pointer(0, 64) << '\n');

lib/Target/AArch64/AArch64LegalizerInfo.cpp

   35   const LLT p0 = LLT::pointer(0, 64);

lib/Target/AMDGPU/AMDGPUCallLowering.cpp

   88       LLT::pointer(AMDGPUAS::PRIVATE_ADDRESS, 32));
  413     const LLT P4 = LLT::pointer(AMDGPUAS::CONSTANT_ADDRESS, 64);

lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

  169     return LLT::pointer(AS, TM.getPointerSizeInBits(AS));
 1178     LLT::pointer(AMDGPUAS::CONSTANT_ADDRESS, 64));
 1254       LLT::pointer(AMDGPUAS::CONSTANT_ADDRESS_32BIT, 32), AddrHiVal);
 1613   LLT ConstPtrTy = LLT::pointer(AMDGPUAS::CONSTANT_ADDRESS, 64);
 1682   LLT PtrTy = LLT::pointer(AMDGPUAS::CONSTANT_ADDRESS, 64);
 1708   LLT ConstPtr = LLT::pointer(AMDGPUAS::CONSTANT_ADDRESS, 64);

lib/Target/AMDGPU/SIISelLowering.cpp

 1792     MRI.setType(VReg, LLT::pointer(AMDGPUAS::CONSTANT_ADDRESS, 64));

lib/Target/ARM/ARMCallLowering.cpp

  100     LLT p0 = LLT::pointer(0, 32);
  303         MRI.createGenericVirtualRegister(LLT::pointer(MPO.getAddrSpace(), 32));

lib/Target/ARM/ARMLegalizerInfo.cpp

   69   const LLT p0 = LLT::pointer(0, 32);

lib/Target/Mips/MipsCallLowering.cpp

  195   Register AddrReg = MRI.createGenericVirtualRegister(LLT::pointer(0, 32));
  292   LLT p0 = LLT::pointer(0, 32);
  526           MIRBuilder.buildFrameIndex(LLT::pointer(MPO.getAddrSpace(), 32), FI);
  574         MF.getRegInfo().createGenericVirtualRegister(LLT::pointer(0, 32));

lib/Target/Mips/MipsLegalizerInfo.cpp

   62   const LLT p0 = LLT::pointer(0, 32);
  362     Register Tmp = MRI.createGenericVirtualRegister(LLT::pointer(0, 32));

lib/Target/X86/X86CallLowering.cpp

  109     LLT p0 = LLT::pointer(0, DL.getPointerSizeInBits(0));
  244         LLT::pointer(0, DL.getPointerSizeInBits(0)));

lib/Target/X86/X86InstructionSelector.cpp

  408   } else if (Ty == LLT::scalar(32) || Ty == LLT::pointer(0, 32)) {
  418   } else if (Ty == LLT::scalar(64) || Ty == LLT::pointer(0, 64)) {
  550   if (Ty == LLT::pointer(0, 64))
  552   else if (Ty == LLT::pointer(0, 32))

lib/Target/X86/X86LegalizerInfo.cpp

  108   const LLT p0 = LLT::pointer(0, TM.getPointerSizeInBits(0));
  204   const LLT p0 = LLT::pointer(0, TM.getPointerSizeInBits(0));

unittests/CodeGen/GlobalISel/LegalizerHelperTest.cpp

 1035   const LLT P0 = LLT::pointer(0, 64);

unittests/CodeGen/GlobalISel/LegalizerInfoTest.cpp

  126   LLT p0 = LLT::pointer(0, 64);
  147       L.getAction({G_PTRTOINT, {s64, LLT::pointer(0, 32)}}),
  148       LegalizeActionStep(Unsupported, 1, LLT::pointer(0, 32)));
  225   const LLT p0 = LLT::pointer(0, 32);
  364   const LLT p0 = LLT::pointer(0, 64);

unittests/CodeGen/GlobalISel/MachineIRBuilderTest.cpp

  302   LLT P0 = LLT::pointer(0, 64);

unittests/CodeGen/GlobalISel/PatternMatchTest.cpp

  266   LLT PtrTy = LLT::pointer(0, 64);
  320   B.buildCast(LLT::pointer(0, 32), MIBAdd);
  321   B.buildCast(LLT::pointer(1, 32), MIBAdd);

unittests/CodeGen/LowLevelTypeTest.cpp

  104   EXPECT_EQ(LLT::pointer(1, 32), LLT::scalarOrVector(1, LLT::pointer(1, 32)));
  104   EXPECT_EQ(LLT::pointer(1, 32), LLT::scalarOrVector(1, LLT::pointer(1, 32)));
  105   EXPECT_EQ(LLT::vector(2, LLT::pointer(1, 32)),
  106             LLT::scalarOrVector(2, LLT::pointer(1, 32)));
  110   const LLT P0 = LLT::pointer(0, 32);
  111   const LLT P1 = LLT::pointer(1, 64);
  146   const LLT P0 = LLT::pointer(0, 32);
  172       const LLT Ty = LLT::pointer(AS, DL.getPointerSizeInBits(AS));

utils/TableGen/GlobalISelEmitter.cpp

 1605     addPredicate<LLTOperandMatcher>(LLT::pointer(VTy.getPtrAddrSpace(),