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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
include/llvm/CodeGen/LivePhysRegs.h 93 LiveRegs.erase(*R);
lib/CodeGen/AggressiveAntiDepBreaker.cpp 165 unsigned Reg = *AI;
183 unsigned AliasReg = *AI;
315 if (TRI->isSuperRegister(Reg, *AI) && State->IsLive(*AI)) {
315 if (TRI->isSuperRegister(Reg, *AI) && State->IsLive(*AI)) {
398 unsigned AliasReg = *AI;
435 if (TRI->isSuperRegister(Reg, *AI) && State->IsLive(*AI))
435 if (TRI->isSuperRegister(Reg, *AI) && State->IsLive(*AI))
438 DefIndices[*AI] = Count;
689 unsigned AliasReg = *AI;
928 RegAliases.set(*AI);
lib/CodeGen/AsmPrinter/DbgEntityHistoryCalculator.cpp 290 clobberRegisterUses(RegVars, *AI, DbgValues, LiveEntries, MI);
lib/CodeGen/BranchFolding.cpp 1856 Set.insert(*AI);
2079 ActiveDefsSet.erase(*AI);
lib/CodeGen/CallingConvLower.cpp 64 UsedRegs[*AI/32] |= 1 << (*AI&31);
64 UsedRegs[*AI/32] |= 1 << (*AI&31);
75 if (*AI == Reg)
lib/CodeGen/CriticalAntiDepBreaker.cpp 75 unsigned Reg = *AI;
93 unsigned Reg = *AI;
209 unsigned AliasReg = *AI;
326 unsigned AliasReg = *AI;
lib/CodeGen/DeadMachineInstructionElim.cpp 165 LivePhysRegs.set(*AI);
lib/CodeGen/ExecutionDomainFix.cpp 448 AliasMap[*AI].push_back(i);
lib/CodeGen/ImplicitNullChecks.cpp 318 if (MBB->isLiveIn(*AR))
lib/CodeGen/LiveDebugValues.cpp 821 if (VarLocIDs[ID].isDescribedByReg() == *RAI)
1008 if (CalleeSavedRegs.test(*RAI))
lib/CodeGen/LivePhysRegs.cpp 150 if (LiveRegs.count(*R))
lib/CodeGen/MachineCSE.cpp 293 PhysRefs.insert(*AI);
323 PhysRefs.insert(*AI);
lib/CodeGen/MachineLICM.cpp 442 PhysRegClobbers.set(*AI);
462 if (PhysRegDefs.test(*AS))
463 PhysRegClobbers.set(*AS);
468 PhysRegDefs.set(*AS);
513 PhysRegDefs.set(*AI);
532 TermRegs.set(*AI);
lib/CodeGen/MachineRegisterInfo.cpp 530 if (!def_empty(*AI) || isAllocatable(*AI))
530 if (!def_empty(*AI) || isAllocatable(*AI))
592 for (const MachineOperand &MO : make_range(def_begin(*AI), def_end())) {
607 if (!reg_nodbg_empty(*AliasReg))
633 UpdatedCSRs.erase(std::remove(UpdatedCSRs.begin(), UpdatedCSRs.end(), *AI),
lib/CodeGen/RegAllocFast.cpp 479 MCPhysReg Alias = *AI;
538 MCPhysReg Alias = *AI;
586 MCPhysReg Alias = *AI;
912 if (ThroughRegs.count(PhysRegState[*AI]))
913 definePhysReg(MI, *AI, regFree);
lib/CodeGen/RegUsageInfoCollector.cpp 150 SetRegAsDefined(*AI);
163 if (!SavedRegs.test(*AI))
164 SetRegAsDefined(*AI);
lib/CodeGen/RegisterClassInfo.cpp 65 CalleeSavedAliases[*AI] = *I;
lib/CodeGen/RegisterScavenging.cpp 340 Candidates.reset(*AI);
547 Candidates.reset(*AI);
lib/CodeGen/ScheduleDAGInstrs.cpp 243 if (!Uses.contains(*Alias))
245 for (Reg2SUnitsMap::iterator I = Uses.find(*Alias); I != Uses.end(); ++I) {
261 Dep = SDep(SU, SDep::Data, *Alias);
268 !UseMIDesc->hasImplicitUseOfPhysReg(*Alias));
300 if (!Defs.contains(*Alias))
302 for (Reg2SUnitsMap::iterator I = Defs.find(*Alias); I != Defs.end(); ++I) {
308 !DefSU->getInstr()->registerDefIsDead(*Alias))) {
310 DefSU->addPred(SDep(SU, Kind, /*Reg=*/*Alias));
312 SDep Dep(SU, Kind, /*Reg=*/*Alias);
lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp 453 if (LiveRegDefs[*AI] && LiveRegDefs[*AI] != SU) {
453 if (LiveRegDefs[*AI] && LiveRegDefs[*AI] != SU) {
454 if (RegAdded.insert(*AI).second) {
455 LRegs.push_back(*AI);
lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp 1305 if (!LiveRegDefs[*AliasI]) continue;
1308 if (LiveRegDefs[*AliasI] == SU) continue;
1311 if (RegAdded.insert(*AliasI).second) {
1312 LRegs.push_back(*AliasI);
lib/Target/AArch64/AArch64SpeculationHardening.cpp 500 RegsAlreadyMasked.reset(*AI);
572 RegsNeedingCSDBBeforeUse.set(*AI);
lib/Target/AMDGPU/AMDGPURegisterInfo.cpp 88 Reserved.set(*R);
lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp 4348 if (*R == RegNo)
4355 if (*R == RegNo)
4404 if (*R == RegNo)
lib/Target/AMDGPU/R600RegisterInfo.cpp 119 Reserved.set(*R);
lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp 966 if (*R == Reg1) return true;
lib/Target/Hexagon/HexagonFrameLowering.cpp 1401 if (MRI.isPhysRegUsed(*AI))
lib/Target/Hexagon/HexagonSubtarget.cpp 249 if (LastVRegUse.count(*AI) &&
250 LastVRegUse[*AI] != &DAG->SUnits[su])
252 DAG->addEdge(&DAG->SUnits[su], SDep(LastVRegUse[*AI], SDep::Barrier));
253 LastVRegUse.erase(*AI);
lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.cpp 81 if (!MCSubRegIterator(*SRI, &RI).isValid())
83 Uses.insert(*SRI);
140 if (MCSubRegIterator(*SRI, &RI).isValid())
144 if (R == *SRI) {
153 if (Hexagon::P3_0 != R && Hexagon::P3_0 == *SRI)
158 SoftDefs.insert(*SRI);
160 isPredicateRegister(*SRI))
162 LatePreds.insert(*SRI);
170 TmpDefs.insert(*SRI);
174 Uses.insert(*SRI);
176 Defs[*SRI].insert(PredSense(PredReg, isTrue));
534 if (*K == Register) {
lib/Target/Hexagon/RDFLiveness.cpp 906 if (!Live[*AR])
lib/Target/Hexagon/RDFRegisters.cpp 122 AS.insert(*AI);
lib/Target/Lanai/LanaiDelaySlotFiller.cpp 258 if (RegSet.count(*AI))
lib/Target/Mips/MipsDelaySlotFiller.cpp 386 CallerSavedRegs.reset(*AI);
396 AllocSet.set(*AI);
446 if (RegSet.test(*AI))
lib/Target/Mips/MipsSEFrameLowering.cpp 858 SavedRegs.set(*AI);
lib/Target/Sparc/DelaySlotFiller.cpp 348 if (RegSet.count(*AI))
lib/Target/Sparc/SparcRegisterInfo.cpp 93 Reserved.set(*AI);
lib/Target/X86/X86FrameLowering.cpp 183 Uses.insert(*AI);
2094 if (MRI.isLiveIn(*AReg)) {
lib/Target/X86/X86RegisterInfo.cpp 589 Reserved.set(*AI);
593 Reserved.set(*AI);
599 Reserved.set(*AI);
tools/llvm-exegesis/lib/RegisterAliasing.cpp 21 AliasedBits.set(*Itr);
54 AliasedBits.set(*Itr);
55 Origins[*Itr] = PhysReg;