|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/AArch64/AArch64GenSubtargetInfo.inc18036 && MI->getOperand(1).getReg() == MI->getOperand(2).getReg()
18047 && MI->getOperand(1).getReg() == MI->getOperand(2).getReg()
18517 && MI->getOperand(1).getReg() == MI->getOperand(2).getReg()
18528 && MI->getOperand(1).getReg() == MI->getOperand(2).getReg()
18541 && MI->getOperand(1).getReg() == MI->getOperand(2).getReg()
18552 && MI->getOperand(1).getReg() == MI->getOperand(2).getReg()
gen/lib/Target/X86/X86GenSubtargetInfo.inc21530 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
21535 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
21924 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
21929 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
21934 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
21939 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
21944 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
21949 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
21954 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
21961 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
21966 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
21971 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
21976 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
21981 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
21986 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
21991 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
21998 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22003 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22008 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22013 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22018 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22023 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22030 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22035 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22040 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22045 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22050 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22055 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22060 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22067 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22072 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22077 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22082 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22087 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22092 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22097 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22104 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22109 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22114 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22119 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22124 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22129 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22134 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22141 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22146 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22151 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22156 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22161 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22166 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22367 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22372 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22377 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22382 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22389 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22394 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22399 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22404 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22411 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22416 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22421 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22426 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22453 MI->getOperand(1).getReg() == MI->getOperand(2).getReg()
22469 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22474 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22481 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22486 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22493 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22498 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22505 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22510 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22742 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22749 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22756 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22776 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22781 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22788 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22793 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22798 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22803 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22808 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22813 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22818 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22825 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22830 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22835 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22840 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22847 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22854 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22861 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22868 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22875 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22882 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22889 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22896 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22903 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22925 return MI->getOperand(1).getReg() == MI->getOperand(2).getReg();
22933 MI->getOperand(1).getReg() == MI->getOperand(2).getReg()
22997 return MI->getOperand(1).getReg() == MI->getOperand(2).getReg();
23017 return MI->getOperand(1).getReg() == MI->getOperand(2).getReg();
23034 return MI->getOperand(1).getReg() == MI->getOperand(2).getReg();
23042 return MI->getOperand(0).getReg() == MI->getOperand(1).getReg();
include/llvm/ADT/SmallSet.h 240 if (*I == V)
include/llvm/CodeGen/MachineInstr.h 1135 return isCopy() && getOperand(0).getReg() == getOperand(1).getReg() &&
include/llvm/CodeGen/TargetRegisterInfo.h 381 if (regA == regB) return true;
lib/CodeGen/AsmPrinter/DwarfDebug.cpp 656 bool IsSPorFP = (RegLoc == SP) || (RegLoc == FP);
lib/CodeGen/ExpandPostRAPseudos.cpp 105 if (DstSubReg == InsReg) {
146 bool IdentityCopy = (SrcMO.getReg() == DstMO.getReg());
lib/CodeGen/GlobalISel/CombinerHelper.cpp 657 if (Base == MI.getOperand(0).getReg()) {
664 if (MI.getOperand(0).getReg() == Addr) {
lib/CodeGen/LiveDebugVariables.cpp 234 locations[i].getReg() == LocMO.getReg() &&
lib/CodeGen/LiveRangeShrink.cpp 237 EndIter->getOperand(0).getReg() == MI.getOperand(0).getReg();
lib/CodeGen/MIRVRegNamerUtils.cpp 111 return TR.isReg() && TR.getReg() == Reg;
lib/CodeGen/MachineCSE.cpp 608 if (MO.isImplicit() && !MO.isDead() && OldReg == NewReg)
611 if (OldReg == NewReg) {
lib/CodeGen/MachineInstr.cpp 934 if (MO.isReg() && MO.isUse() && MO.isImplicit() && MO.getReg() == Reg)
952 if (MOReg == Reg || (TRI && Reg && MOReg && TRI->regsOverlap(MOReg, Reg)))
1004 bool Found = (MOReg == Reg);
1807 if (Reg == IncomingReg) {
1858 if ((RegInfo && RegInfo->regsOverlap(Reg, OpReg)) || Reg == OpReg)
1879 if (MOReg == Reg) {
1940 if (MO.isReg() && MO.getReg() == Reg && MO.isDef() &&
2116 DI->getOperand(0).getReg() == MI.getOperand(0).getReg())
lib/CodeGen/MachineLICM.cpp 1381 MO.getReg() == Dup->getOperand(i).getReg()) &&
lib/CodeGen/MachineOperand.cpp 53 if (getReg() == Reg)
281 return getReg() == Other.getReg() && isDef() == Other.isDef() &&
lib/CodeGen/MachinePipeliner.cpp 2480 if (MI->getOperand(BasePos).getReg() == Reg)
lib/CodeGen/MachineRegisterInfo.cpp 281 assert(MO->getReg() == Head->getReg() && "Different regs on the same list!");
286 assert(MO->getReg() == Last->getReg() && "Different regs on the same list!");
lib/CodeGen/MachineScheduler.cpp 946 if (MO2.isReg() && MO2.isDef() && MO2.getReg() == Reg && !MO2.isDead()) {
lib/CodeGen/MachineSink.cpp 758 MBP.LHS.getReg() == BaseOp->getReg();
lib/CodeGen/OptimizePHIs.cpp 113 if (SrcReg == DstReg)
lib/CodeGen/PeepholeOptimizer.cpp 1469 if (PrevDstReg == SrcReg) {
lib/CodeGen/ScheduleDAGInstrs.cpp 409 if (OtherMO.isReg() && OtherMO.isDef() && OtherMO.getReg() == Reg)
lib/CodeGen/TargetInstrInfo.cpp 195 if (HasDef && Reg0 == Reg1 &&
200 } else if (HasDef && Reg0 == Reg2 &&
lib/CodeGen/TwoAddressInstructionPass.cpp 1477 if (SrcReg == DstReg)
1829 if (MI.getOperand(j).getReg() == SrcReg) {
lib/CodeGen/VirtRegMap.cpp 107 return getPhys(VirtReg) == Hint;
lib/Target/AArch64/AArch64InstrInfo.cpp 1641 if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) {
lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp 962 if (StRt == LdRt && LoadSize == 8) {
1136 BaseReg == getLdStBaseOp(MI).getReg() &&
1278 if (BaseReg == MIBaseReg && ((Offset == MIOffset + OffsetStride) ||
1317 if (MayLoad && Reg == getLdStRegOp(MI).getReg()) {
1513 if (DestReg == BaseReg || TRI->isSubRegister(BaseReg, DestReg))
1567 if (DestReg == BaseReg || TRI->isSubRegister(BaseReg, DestReg))
lib/Target/AMDGPU/GCNDPPCombine.cpp 470 if (OrigMI.getOperand(OpNo).getReg() == DPPMovReg) {
lib/Target/AMDGPU/GCNHazardRecognizer.cpp 1263 if (DstReg == Reg)
lib/Target/AMDGPU/GCNNSAReassign.cpp 199 if (Def && Def->isCopy() && Def->getOperand(1).getReg() == PhysReg)
206 if (UseInst->isCopy() && UseInst->getOperand(0).getReg() == PhysReg)
lib/Target/AMDGPU/GCNRegBankReassign.cpp 430 if (Def && Def->isCopy() && Def->getOperand(1).getReg() == PhysReg)
437 if (UseInst->isCopy() && UseInst->getOperand(0).getReg() == PhysReg)
lib/Target/AMDGPU/R600MachineScheduler.cpp 367 MO.getReg() == DestReg)
lib/Target/AMDGPU/SIFixSGPRCopies.cpp 723 MO->getReg() == Def.getReg() &&
lib/Target/AMDGPU/SIFoldOperands.cpp 1399 if (Src0->isReg() && Src1->isReg() && Src0->getReg() == Src1->getReg() &&
lib/Target/AMDGPU/SIFormMemoryClauses.cpp 127 if (MO.getReg() == ResReg)
lib/Target/AMDGPU/SIInstrInfo.cpp 1485 assert(VecReg == MI.getOperand(1).getReg());
2916 return Op0.getReg() == Op1.getReg();
3187 SubReg.getReg() == SuperVec.getReg();
lib/Target/AMDGPU/SILowerControlFlow.cpp 191 J->getOperand(1).isReg() && J->getOperand(1).getReg() == SaveExecReg) {
lib/Target/AMDGPU/SIOptimizeExecMasking.cpp 393 if (Src0.isReg() && Src0.getReg() == CopyFromExec) {
395 } else if (Src1.isReg() && Src1.getReg() == CopyFromExec) {
lib/Target/AMDGPU/SIPeepholeSDWA.cpp 290 LHS.getReg() == RHS.getReg() &&
326 if (DefMO.isReg() && DefMO.getReg() == Reg->getReg())
lib/Target/AMDGPU/SIShrinkInstructions.cpp 369 if (SrcReg->isReg() && SrcReg->getReg() == Dest->getReg()) {
650 if (Src0->isReg() && Src0->getReg() == Dest->getReg()) {
lib/Target/ARC/ARCOptAddrMode.cpp 296 if (Add->getOperand(0).getReg() == StReg || BaseReg == StReg) {
296 if (Add->getOperand(0).getReg() == StReg || BaseReg == StReg) {
lib/Target/ARM/ARMAsmPrinter.cpp 285 bool Lane0 = TRI->getSubReg(*SR, ARM::ssub_0) == Reg;
lib/Target/ARM/ARMBaseInstrInfo.cpp 284 MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI;
3381 return (Rt == Rm) ? 4 : 3;
3388 if (Rt == Rm)
3420 if (Rt == Rm)
3430 return (Rt == Rm) ? 3 : 2;
3452 if (Rt == Rm)
3472 return (Rt == Rn) ? 3 : 2;
3498 return (Rt == Rn) ? 4 : 3;
3504 return (Rt == Rn) ? 4 : 3;
3541 return (Rt == Rn) ? 3 : 2;
3792 if (Op.isReg() && Op.getReg() == BaseReg)
lib/Target/ARM/ARMCallLowering.cpp 118 assert(VA.getLocReg() == PhysReg && "Assigning to the wrong reg?");
340 assert(VA.getLocReg() == PhysReg && "Assigning to the wrong reg?");
lib/Target/ARM/ARMConstantIslandPass.cpp 2064 if (MO.isDef() && MO.getReg() == BaseReg)
2066 if (MO.isUse() && MO.getReg() == BaseReg) {
2083 if (MO.isDef() && MO.getReg() == BaseReg)
2085 if (MO.isUse() && MO.getReg() == EntryReg)
2093 } else if (BaseReg == EntryReg) {
2130 if (I->getOpcode() == ARM::t2ADDrs && I->getOperand(0).getReg() == EntryReg)
2144 if (MO.isDef() && MO.getReg() == EntryReg)
2146 if (MO.isUse() && MO.getReg() == EntryReg)
lib/Target/ARM/ARMLoadStoreOptimizer.cpp 1019 PReg == getLoadStoreBaseOp(*MI).getReg())
1274 if (MI->getOperand(i).getReg() == Base)
1405 if (MI->getOperand(0).getReg() == Base)
1518 if (Reg0Op.getReg() == Base || Reg1Op.getReg() == Base)
1518 if (Reg0Op.getReg() == Base || Reg1Op.getReg() == Base)
1666 bool Errata602117 = EvenReg == BaseReg &&
1736 if (OddReg == EvenReg && EvenDeadKill) {
1744 if (EvenReg == BaseReg)
1810 Overlap = (Base == Reg);
lib/Target/ARM/Thumb2SizeReduction.cpp 506 if (MI->getOperand(i).getReg() == BaseReg) {
lib/Target/Hexagon/HexagonHardwareLoops.cpp 1344 if (MO.getReg() == PredR) // Found an intervening use of PredR.
lib/Target/Hexagon/HexagonInstrInfo.cpp 1242 .addReg(Pu, (Rd == Rt) ? K1 : 0)
2620 if (MI2.getOperand(I).isReg() && DstReg == MI2.getOperand(I).getReg())
2626 MI1.getOperand(0).getReg() == MI2.getOperand(3).getReg())
2969 if (Op.isReg() && Op.isDef() && Op.getReg() == Stored.getReg())
lib/Target/Hexagon/HexagonOptAddrMode.cpp 201 UseMI.getOperand(2).getReg() == MI.getOperand(0).getReg())
756 if (op.isReg() && op.isUse() && DefR == op.getReg())
lib/Target/Hexagon/HexagonSubtarget.cpp 352 if (MO.isReg() && MO.getReg() && MO.isUse() && MO.getReg() == DReg) {
lib/Target/Hexagon/HexagonVLIWPacketizer.cpp 387 if (MO.isReg() && MO.getReg() == MI->getOperand(0).getReg())
429 if (MO.isReg() && MO.getReg() == DestReg)
1356 if (NOp1.isReg() && I.getOperand(0).getReg() == NOp1.getReg())
lib/Target/Lanai/LanaiMemAluCombiner.cpp 176 return Op1.getReg() == Op2.getReg();
320 if (Offset.isReg() && Op2.getReg() == Offset.getReg())
lib/Target/Mips/MicroMipsSizeReduction.cpp 371 if (ReduceToLwp && (MI->getOperand(0).getReg() == MI->getOperand(1).getReg()))
664 if (!(MI->getOperand(0).getReg() == MI->getOperand(2).getReg()) &&
665 !(MI->getOperand(0).getReg() == MI->getOperand(1).getReg()))
722 if (MI->getOperand(0).getReg() == MI->getOperand(2).getReg()) {
lib/Target/Mips/MipsInstrInfo.cpp 484 else if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
491 else if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
495 if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
499 if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
509 if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
513 if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
519 if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
523 if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
lib/Target/NVPTX/NVPTXProxyRegErasure.cpp 113 if (Op.isReg() && Op.getReg() == From.getReg()) {
lib/Target/PowerPC/PPCExpandISEL.cpp 88 return (Op1.getReg() == Op2.getReg());
lib/Target/PowerPC/PPCInstrInfo.cpp 405 if (Reg0 == Reg1) {
2390 MI.getOperand(1).getReg() == MI.getOperand(2).getReg())
lib/Target/PowerPC/PPCMIPeephole.cpp 488 if (ShiftOp1 == ShiftOp2) {
540 Use.getOperand(i).getReg() == FRSPDefines)
lib/Target/PowerPC/PPCPreEmitPeephole.cpp 180 MI.getOperand(0).getReg() == MI.getOperand(1).getReg() &&
181 MI.getOperand(0).getReg() == MI.getOperand(2).getReg()) {
189 MI.getOperand(0).getReg() == MI.getOperand(1).getReg()) {
234 It->getOperand(0).getReg() == CRBit)
lib/Target/PowerPC/PPCVSXFMAMutate.cpp 240 assert(OldFMAReg == AddendMI->getOperand(0).getReg() &&
263 if (OtherProdReg == AddendMI->getOperand(0).getReg()) {
lib/Target/RISCV/RISCVFrameLowering.cpp 70 if (DestReg == SrcReg && Val == 0)
282 if (DestReg == FPReg) {
lib/Target/RISCV/RISCVMergeBaseOffset.cpp 140 Register Reg = Rs == GAReg ? Rt : Rs;
lib/Target/Sparc/SparcISelLowering.cpp 345 if (i+1 < RVLocs.size() && RVLocs[i+1].getLocReg() == VA.getLocReg()) {
1201 ArgLocs[i+1].getLocReg() == VA.getLocReg()) {
lib/Target/SystemZ/SystemZInstrInfo.cpp 1177 DstPhys == VRM->getPhys(SrcReg))
lib/Target/SystemZ/SystemZPostRewrite.cpp 139 if (DestReg != Src1Reg && DestReg == Src2Reg) {
168 assert(DestReg == MI.getOperand(1).getReg() &&
lib/Target/SystemZ/SystemZShortenInst.cpp 133 MI.getOperand(1).getReg() == MI.getOperand(0).getReg() &&
182 if (MI.getOperand(0).getReg() == MI.getOperand(1).getReg()) {
187 if (MI.getOperand(0).getReg() == MI.getOperand(2).getReg()) {
lib/Target/X86/X86AvoidStoreForwardingBlocks.cpp 623 return LoadBase.getReg() == StoreBase.getReg();
lib/Target/X86/X86CallFrameOptimization.cpp 395 J->getOperand(1).getReg() == StackPtr) {
lib/Target/X86/X86FixupLEAs.cpp 245 if (opnd.isReg() && opnd.getReg() == p.getReg()) {
388 (DestReg == BaseReg || DestReg == IndexReg)) {
388 (DestReg == BaseReg || DestReg == IndexReg)) {
403 } else if (DestReg == BaseReg && IndexReg == 0) {
508 const MachineOperand &Src = SrcR1 == DstR ? Index : Base;
517 const MachineOperand &SrcR = SrcR1 == DstR ? Base : Index;
564 if (IsInefficientBase && DestReg == BaseReg && !IsScale1)
576 if (IsScale1 && (DestReg == BaseReg || DestReg == IndexReg)) {
576 if (IsScale1 && (DestReg == BaseReg || DestReg == IndexReg)) {
lib/Target/X86/X86ISelLowering.cpp29948 NextMIIt->getOperand(2).getReg() == MI.getOperand(2).getReg() &&
29949 NextMIIt->getOperand(1).getReg() == MI.getOperand(0).getReg() &&
lib/Target/X86/X86InstrInfo.cpp 839 if (Src == Src2) {
3887 assert(MIB->getOperand(1).getReg() == Reg &&
3888 MIB->getOperand(2).getReg() == Reg && "Misplaced operand");
4876 MI.getOperand(0).getReg() == MI.getOperand(1).getReg()) {
4953 if ((HasDef && Reg0 == Reg1 && Tied1) ||
4954 (HasDef && Reg0 == Reg2 && Tied2))
6675 if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg() &&
6793 MI.getOperand(1).getReg() == MI.getOperand(2).getReg() &&
7583 if ((Op1.isReg() && Op1.getReg() == MI.getOperand(0).getReg()) ||
7584 Op2.getReg() == MI.getOperand(0).getReg())
7601 if (Op && Op->isReg() && Op->getReg() == Op2.getReg() && Coef > 0) {
7646 if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg())
lib/Target/X86/X86SpeculativeLoadHardening.cpp 2187 if ((BaseMO.isReg() && BaseMO.getReg() == DefReg) ||
2188 (IndexMO.isReg() && IndexMO.getReg() == DefReg))
usr/include/c++/7.4.0/bits/predefined_ops.h 241 { return *__it == _M_value; }
utils/unittest/googletest/include/gtest/gtest.h 1392 if (lhs == rhs) {