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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
lib/CodeGen/AggressiveAntiDepBreaker.cpp 724 if (DefMI->readsRegister(NewReg, TRI)) {
lib/CodeGen/GlobalISel/RegBankSelect.cpp 422 assert(!Next->readsRegister(Reg) && "Need to split between terminators");
lib/CodeGen/ModuloSchedule.cpp 808 if (BBJ.readsRegister(Def)) {
823 if (I.readsRegister(Def))
lib/CodeGen/PHIElimination.cpp 446 if (Term->readsRegister(SrcReg))
460 if (KillInst->readsRegister(SrcReg))
468 assert(KillInst->readsRegister(SrcReg) && "Cannot find kill instruction");
506 if (Term->readsRegister(SrcReg))
520 if (KillInst->readsRegister(SrcReg))
528 assert(KillInst->readsRegister(SrcReg) &&
lib/CodeGen/RegisterCoalescer.cpp 2065 if (MI->readsRegister(DstReg, TRI)) {
lib/CodeGen/RegisterScavenging.cpp 638 if (!MI.readsRegister(VReg, &TRI)) {
657 return !MO.getParent()->readsRegister(VReg, &TRI);
lib/CodeGen/SelectionDAG/InstrEmitter.cpp 1137 if (MIB->readsRegister(Reg, TRI)) {
lib/CodeGen/TargetSchedule.cpp 306 if (!DepMI->readsRegister(Reg, TRI) && TII->isPredicated(*DepMI))
lib/Target/AArch64/AArch64CondBrTuning.cpp 200 I->readsRegister(AArch64::NZCV, TRI))
259 I->readsRegister(AArch64::NZCV, TRI))
lib/Target/AArch64/AArch64ConditionOptimizer.cpp 164 if (I->readsRegister(AArch64::NZCV))
lib/Target/AArch64/AArch64ConditionalCompares.cpp 303 if (!I->readsRegister(AArch64::NZCV)) {
lib/Target/AArch64/AArch64InstrInfo.cpp 1164 ((AccessToCheck & AK_Read) && Instr.readsRegister(AArch64::NZCV, TRI)))
1422 if (Instr.readsRegister(AArch64::NZCV, TRI)) {
5122 !MI.readsRegister(AArch64::SP, &TRI))
5487 if (MI.readsRegister(AArch64::W30, &getRegisterInfo()) ||
lib/Target/AArch64/AArch64SpeculationHardening.cpp 419 if (MI.readsRegister(MisspeculatingTaintReg, TRI) ||
lib/Target/AMDGPU/GCNHazardRecognizer.cpp 982 return SIInstrInfo::isSMRD(*I) && I->readsRegister(SDSTReg, TRI);
1044 return I->readsRegister(AMDGPU::EXEC, TRI);
lib/Target/AMDGPU/GCNRegBankReassign.cpp 714 return C.MI->readsRegister(Reg, TRI);
lib/Target/AMDGPU/R600EmitClauseMarkers.cpp 228 if (UseI->readsRegister(MOI->getReg(), &TRI))
lib/Target/AMDGPU/SIFixSGPRCopies.cpp 572 if (R->readsRegister(Reg, TRI) || R->definesRegister(Reg, TRI) ||
lib/Target/AMDGPU/SIFixVGPRCopies.cpp 58 if (TII->isVGPRCopy(MI) && !MI.readsRegister(AMDGPU::EXEC, TRI)) {
lib/Target/AMDGPU/SIFoldOperands.cpp 1214 if (DefMI->readsRegister(AMDGPU::EXEC, TRI) &&
lib/Target/AMDGPU/SIInsertSkips.cpp 366 ReadsCond |= A->readsRegister(CondReg, TRI);
392 ReadsSreg |= M->readsRegister(SReg, TRI);
lib/Target/AMDGPU/SIInstrInfo.cpp 2796 return MI.readsRegister(AMDGPU::EXEC, &RI);
2807 return !isSALU(MI) || MI.readsRegister(AMDGPU::EXEC, &RI);
4310 if (!RI.isSGPRClass(DstRC) && !Copy->readsRegister(AMDGPU::EXEC, &RI) &&
6516 if (I->readsRegister(VReg))
6531 if (!Cur->isPHI() && Cur->readsRegister(Dst))
lib/Target/AMDGPU/SIOptimizeExecMasking.cpp 332 if (SaveExecInst && J->readsRegister(Exec, TRI)) {
340 bool ReadsCopyFromExec = J->readsRegister(CopyFromExec, TRI);
377 if (SaveExecInst && J->readsRegister(CopyToExec, TRI)) {
lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp 274 return MI.readsRegister(CondReg, TRI);
lib/Target/ARM/ARMBaseInstrInfo.cpp 292 if (!NewMI->readsRegister(Reg))
1606 if (!MI.definesRegister(DstRegD, TRI) || MI.readsRegister(DstRegD, TRI))
2978 if (I != E && !MI->readsRegister(ARM::CPSR, TRI)) {
3014 Instr.readsRegister(ARM::CPSR, TRI))
4906 if (MI.definesRegister(DReg, TRI) || MI.readsRegister(DReg, TRI)) {
5011 .addReg(DReg, getUndefRegState(!MI.readsRegister(DReg, TRI)))
5047 .addReg(DDst, getUndefRegState(!MI.readsRegister(DDst, TRI)))
5080 bool CurUndef = !MI.readsRegister(CurReg, TRI);
5084 CurUndef = !MI.readsRegister(CurReg, TRI);
5098 CurUndef = CurReg == DSrc && !MI.readsRegister(CurReg, TRI);
5102 CurUndef = CurReg == DSrc && !MI.readsRegister(CurReg, TRI);
5373 if (CmpMI->readsRegister(ARM::CPSR, TRI))
lib/Target/ARM/ARMHazardRecognizer.cpp 29 return MI->readsRegister(DefMI->getOperand(0).getReg(), &TRI);
lib/Target/ARM/ARMISelLowering.cpp10373 if (mi.readsRegister(ARM::CPSR))
lib/Target/ARM/ARMLoadStoreOptimizer.cpp 494 if (MBBI->readsRegister(Base)) {
882 if (MI->readsRegister(DefReg))
lib/Target/ARM/MLxExpansionPass.cpp 192 return MI->readsRegister(Reg, TRI);
lib/Target/ARM/MVEVPTBlockPass.cpp 148 if (CmpMI->readsRegister(ARM::VPR, TRI))
lib/Target/Hexagon/HexagonCopyToCombine.cpp 252 MI.modifiesRegister(DestReg, TRI) || MI.readsRegister(DestReg, TRI) ||
312 I->readsRegister(KilledOperand, TRI))
361 if (MI.readsRegister(I1DestReg, TRI)) // Move this instruction after I2.
lib/Target/Hexagon/HexagonExpandCondsets.cpp 758 if (MI->readsRegister(PredR) && (Cond != HII->isPredicatedTrue(*MI)))
917 if (!MI->readsRegister(PredR) || (Cond != HII->isPredicatedTrue(*MI)))
988 if (PredValid && HII->isPredicated(*MI) && MI->readsRegister(PredR))
lib/Target/Hexagon/HexagonInstrInfo.cpp 3387 if (!GB.readsRegister(DestReg))
lib/Target/Hexagon/HexagonNewValueJump.cpp 187 localBegin->readsRegister(Reg, TRI))
315 localII->readsRegister(pReg, TRI))
lib/Target/Hexagon/HexagonVLIWPacketizer.cpp 153 if (SecondI.readsRegister(R, TRI))
438 if (BI->readsRegister(DepReg, MF.getSubtarget().getRegisterInfo()))
1590 if (!J.readsRegister(R, HRI) && !J.modifiesRegister(R, HRI))
lib/Target/Lanai/LanaiInstrInfo.cpp 324 Instr.readsRegister(Lanai::SR, TRI))
lib/Target/PowerPC/PPCInstrInfo.cpp 1805 Instr.readsRegister(PPC::CR0, TRI)))
1988 if (!MI->readsRegister(*ImpUses))
2334 if (It->readsRegister(Reg, TRI))
lib/Target/PowerPC/PPCPreEmitPeephole.cpp 238 if (It->readsRegister(CRBit, TRI))
lib/Target/PowerPC/PPCQPXLoadSplat.cpp 136 MI->readsRegister(SplatReg, TRI))) {
lib/Target/SystemZ/SystemZElimCompare.cpp 617 if (MI.readsRegister(SystemZ::CC) && CompleteCCUsers)
lib/Target/SystemZ/SystemZISelLowering.cpp 6527 if (mi.readsRegister(SystemZ::CC))
lib/Target/WebAssembly/WebAssemblyRegStackify.cpp 90 if (!MI->readsRegister(WebAssembly::VALUE_STACK))
341 !Insert->readsRegister(Reg))
lib/Target/X86/X86CmovConversion.cpp 575 if (I->readsRegister(X86::EFLAGS))
lib/Target/X86/X86ISelLowering.cpp29599 if (mi.readsRegister(X86::EFLAGS))
lib/Target/X86/X86InstrInfo.cpp 2707 if (I->readsRegister(X86::EFLAGS, TRI))
3672 Instr.readsRegister(X86::EFLAGS, TRI)) {
3707 bool UseEFLAGS = Instr.readsRegister(X86::EFLAGS, TRI);
3802 if (!Instr->readsRegister(X86::EFLAGS, TRI) &&
4353 if (MI.readsRegister(Reg, TRI))
8080 if (MI.modifiesRegister(X86::RSP, &RI) || MI.readsRegister(X86::RSP, &RI) ||
8086 if (MI.readsRegister(X86::RIP, &RI) ||