reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

lib/CodeGen/GlobalISel/IRTranslator.cpp

 1768   MBB.addLiveIn(ExceptionReg);
 1776   MBB.addLiveIn(SelectorReg);

lib/CodeGen/ImplicitNullChecks.cpp

  695       MBB->addLiveIn(Reg);
  703           NC.getNotNullSucc()->addLiveIn(MO.getReg());

lib/CodeGen/LivePhysRegs.cpp

  275     MBB.addLiveIn(Reg);

lib/CodeGen/MIRParser/MIParser.cpp

  723     MBB.addLiveIn(Reg, Mask);

lib/CodeGen/MachineBasicBlock.cpp

  520     addLiveIn(PhysReg);

lib/CodeGen/MachineCSE.cpp

  691             MBB->addLiveIn(LiveIn.second);

lib/CodeGen/MachineLICM.cpp

  576       BB->addLiveIn(Reg);

lib/CodeGen/MachineRegisterInfo.cpp

  491         EntryMBB->addLiveIn(LiveIns[i].first);
  495       EntryMBB->addLiveIn(LiveIns[i].first);

lib/CodeGen/MachineSink.cpp

 1174       SuccBB->addLiveIn(Reg);

lib/CodeGen/PrologEpilogInserter.cpp

  512         MBB->addLiveIn(Reg);
  525           MBB.addLiveIn(DstReg);

lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp

 1244         MBB->addLiveIn(EHPhysReg);

lib/CodeGen/VirtRegMap.cpp

  306     MBB->addLiveIn(PhysReg, LaneMask);
  336           MBB->addLiveIn(PhysReg);

lib/Target/AArch64/AArch64CallLowering.cpp

  114     MIRBuilder.getMBB().addLiveIn(PhysReg);
  411     MBB.addLiveIn(F.PReg);

lib/Target/AArch64/AArch64FrameLowering.cpp

  993         MBB.addLiveIn(AArch64::X1);
 1991     MBB.addLiveIn(AArch64::X18);
 2048       MBB.addLiveIn(Reg1);
 2051         MBB.addLiveIn(Reg2);

lib/Target/AArch64/AArch64ISelLowering.cpp

 1367     TrueBB->addLiveIn(AArch64::NZCV);
 1368     EndBB->addLiveIn(AArch64::NZCV);
12403     Entry->addLiveIn(*I);

lib/Target/AArch64/AArch64InstrInfo.cpp

 5564     MBB.addLiveIn(AArch64::LR);

lib/Target/AArch64/AArch64RedundantCopyElimination.cpp

  456       MBB->addLiveIn(KnownReg);

lib/Target/AArch64/AArch64SpeculationHardening.cpp

  236     SplitEdgeBB.addLiveIn(AArch64::NZCV);

lib/Target/AMDGPU/AMDGPUCallLowering.cpp

  143     MIRBuilder.getMBB().addLiveIn(PhysReg);
  416     B.getMBB().addLiveIn(InputPtrReg);
  580     MBB.addLiveIn(ReturnAddrReg);

lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

 1824     EntryMBB.addLiveIn(Arg->getRegister());

lib/Target/AMDGPU/SIFrameLowering.cpp

  214   MBB.addLiveIn(FlatScratchInitReg);
  452   MBB.addLiveIn(PreloadedScratchWaveOffsetReg);
  457     MBB.addLiveIn(PreloadedPrivateBufferReg);
  466       OtherBB.addLiveIn(ScratchWaveOffsetReg);
  469       OtherBB.addLiveIn(ScratchRsrcReg);
  574     MBB.addLiveIn(GitPtrLo);
  644         MBB.addLiveIn(MFI->getImplicitBufferPtrUserSGPR());

lib/Target/AMDGPU/SIISelLowering.cpp

 2005     Entry->addLiveIn(*I);

lib/Target/AMDGPU/SIInstrInfo.cpp

 1261           Entry.addLiveIn(Reg);

lib/Target/AMDGPU/SILowerSGPRSpills.cpp

  305         MBB.addLiveIn(SSpill.VGPR);
  308         MBB.addLiveIn(Reg);
  311         MBB.addLiveIn(Reg);

lib/Target/AMDGPU/SIMachineFunctionInfo.cpp

  310         BB.addLiveIn(LaneVGPR);

lib/Target/ARM/ARMCallLowering.cpp

  410     MIRBuilder.getMBB().addLiveIn(PhysReg);

lib/Target/ARM/ARMConstantIslandPass.cpp

  928       NewBB->addLiveIn(L);

lib/Target/ARM/ARMFrameLowering.cpp

 1001         MBB.addLiveIn(Reg);
 1243     MBB.addLiveIn(SupReg);
 1262     MBB.addLiveIn(SupReg);
 1277     MBB.addLiveIn(SupReg);
 1289     MBB.addLiveIn(NextReg);

lib/Target/ARM/ARMISelLowering.cpp

10501       copy0MBB->addLiveIn(ARM::CPSR);
10502       sinkMBB->addLiveIn(ARM::CPSR);
17124     Entry->addLiveIn(*I);

lib/Target/ARM/Thumb1FrameLowering.cpp

  857           MBB.addLiveIn(Reg);
  901           MBB.addLiveIn(*HiRegToSave);

lib/Target/AVR/AVRFrameLowering.cpp

  121     I->addLiveIn(AVR::R29R28);
  261       MBB.addLiveIn(Reg);

lib/Target/Hexagon/HexagonFrameLowering.cpp

  789         MBB.addLiveIn(R.getReg());
  830         MBB.addLiveIn(R.getReg());
 1259       MBB.addLiveIn(CSI[I].getReg());
 1273       MBB.addLiveIn(Reg);

lib/Target/MSP430/MSP430FrameLowering.cpp

   76       I->addLiveIn(MSP430::FP);
  198     MBB.addLiveIn(Reg);

lib/Target/Mips/Mips16FrameLowering.cpp

  134       MBB.addLiveIn(Reg);

lib/Target/Mips/MipsCallLowering.cpp

  110     MIRBuilder.getMBB().addLiveIn(PhysReg);
  519       MIRBuilder.getMBB().addLiveIn(ArgRegs[I]);

lib/Target/Mips/MipsDelaySlotFiller.cpp

  342       MBB.addLiveIn(R);

lib/Target/Mips/MipsMachineFunction.cpp

   82     MBB.addLiveIn(Mips::T9_64);
  110   MBB.addLiveIn(Mips::T9);
  145   MBB.addLiveIn(Mips::V0);

lib/Target/Mips/MipsSEFrameLowering.cpp

  510         MBB.addLiveIn(ABI.GetEhDataReg(I));
  597     MBB.addLiveIn(Mips::COP013);
  611   MBB.addLiveIn(Mips::COP014);
  622   MBB.addLiveIn(Mips::COP012);
  810       MBB.addLiveIn(Reg);

lib/Target/PowerPC/PPCExpandISEL.cpp

  398       NewSuccessor->addLiveIn(LI);
  465       TrueBlock->addLiveIn(TrueValue.getReg());
  470       FalseBlock->addLiveIn(FalseValue.getReg());
  475       NewSuccessor->addLiveIn(Dest.getReg());
  476       NewSuccessor->addLiveIn(TrueValue.getReg());
  477       NewSuccessor->addLiveIn(FalseValue.getReg());
  478       NewSuccessor->addLiveIn(ConditionRegister.getReg());

lib/Target/PowerPC/PPCFrameLowering.cpp

 2222        MBB.addLiveIn(Reg);

lib/Target/PowerPC/PPCISelLowering.cpp

15056     Entry->addLiveIn(*I);

lib/Target/Sparc/SparcFrameLowering.cpp

  359       MBB->addLiveIn(reg - SP::I0_I1 + SP::O0_O1);
  365       MBB->addLiveIn(reg - SP::I0 + SP::O0);

lib/Target/SystemZ/SystemZFrameLowering.cpp

  126       MBB.addLiveIn(GPR64);
  210       MBB.addLiveIn(Reg);
  215       MBB.addLiveIn(Reg);
  432       I->addLiveIn(SystemZ::R11D);

lib/Target/SystemZ/SystemZISelLowering.cpp

 6676     FalseMBB->addLiveIn(SystemZ::CC);
 6677     JoinMBB->addLiveIn(SystemZ::CC);
 6770     FalseMBB->addLiveIn(SystemZ::CC);
 6771     JoinMBB->addLiveIn(SystemZ::CC);
 7156     DoneMBB->addLiveIn(SystemZ::CC);
 7342       DoneMBB->addLiveIn(SystemZ::CC);
 7393     MBB->addLiveIn(SystemZ::CC);
 7454   DoneMBB->addLiveIn(SystemZ::CC);

lib/Target/SystemZ/SystemZPostRewrite.cpp

  182     RestMBB->addLiveIn(*I);
  187   MoveMBB->addLiveIn(SrcReg);
  189     MoveMBB->addLiveIn(*I);

lib/Target/WebAssembly/WebAssemblyRegStackify.cpp

  905       MBB.addLiveIn(WebAssembly::VALUE_STACK);

lib/Target/X86/X86CallLowering.cpp

  308     MIRBuilder.getMBB().addLiveIn(PhysReg);

lib/Target/X86/X86CmovConversion.cpp

  677     FalseMBB->addLiveIn(X86::EFLAGS);
  678     SinkMBB->addLiveIn(X86::EFLAGS);

lib/Target/X86/X86ExpandPseudo.cpp

   91       MBB->addLiveIn(Selector.getReg());
  108       MBB->addLiveIn(X86::EFLAGS);

lib/Target/X86/X86FrameLowering.cpp

  679   RoundMBB->addLiveIn(FinalReg);
  696   LoopMBB->addLiveIn(JoinReg);
  709   LoopMBB->addLiveIn(RoundedReg);
  731   ContinueMBB->addLiveIn(SizeReg);
 1091     MBB.addLiveIn(Establisher);
 1323       MBB.addLiveIn(Establisher);
 2087       MBB.addLiveIn(Reg);
 2123     MBB.addLiveIn(Reg);
 2345     allocMBB->addLiveIn(IsLP64 ? X86::R10 : X86::R10D);

lib/Target/X86/X86ISelLowering.cpp

29806   FirstInsertedMBB->addLiveIn(X86::EFLAGS);
29813     SecondInsertedMBB->addLiveIn(X86::EFLAGS);
29814     SinkMBB->addLiveIn(X86::EFLAGS);
29968     FalseMBB->addLiveIn(X86::EFLAGS);
29969     SinkMBB->addLiveIn(X86::EFLAGS);
31412       BB->addLiveIn(BasePtr);
46201     Entry->addLiveIn(*I);

lib/Target/X86/X86RetpolineThunks.cpp

  258   Entry->addLiveIn(Reg);
  280   CallTarget->addLiveIn(Reg);

lib/Target/X86/X86SpeculativeLoadHardening.cpp

  737             CheckingMBB.addLiveIn(X86::EFLAGS);

lib/Target/XCore/XCoreFrameLowering.cpp

  263     MBB.addLiveIn(XCore::LR);
  288     MBB.addLiveIn(SpillList[i].Reg);
  439     MBB.addLiveIn(Reg);

tools/llvm-exegesis/lib/Assembler.cpp

  200     Entry.MBB->addLiveIn(Reg);

tools/llvm-exegesis/lib/SnippetRepetitor.cpp

   76       Loop.MBB->addLiveIn(LoopCounter);
   78         Loop.MBB->addLiveIn(Reg);