|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc 6541 static_cast<AArch64Operand&>(*Operands[OpIdx]).addLogicalImmOperands<int16_t>(Inst, 1);
6568 static_cast<AArch64Operand&>(*Operands[OpIdx]).addLogicalImmNotOperands<int16_t>(Inst, 1);
9573 DiagnosticPredicate DP(Operand.isSVEAddSubImm<int16_t>());
9609 DiagnosticPredicate DP(Operand.isSVECpyImm<int16_t>());
11010 DiagnosticPredicate DP(Operand.isLogicalImm<int16_t>());
11028 DiagnosticPredicate DP(Operand.isSVEPreferredLogicalImm<int16_t>());
11058 DiagnosticPredicate DP(Operand.isLogicalImm<int16_t>());
gen/lib/Target/AArch64/AArch64GenAsmWriter.inc12186 printImm8OptLsl<int16_t>(MI, 1, STI, O);
12507 printImm8OptLsl<int16_t>(MI, 3, STI, O);
12927 printImm8OptLsl<int16_t>(MI, 2, STI, O);
26816 printLogicalImm<int16_t>(MI, OpIdx, STI, OS);
26840 printImm8OptLsl<int16_t>(MI, OpIdx, STI, OS);
26849 printSVELogicalImm<int16_t>(MI, OpIdx, STI, OS);
26973 return AArch64_AM::isSVEMaskOfIdenticalElements<int16_t>(Val);
26996 return AArch64_AM::isSVEMaskOfIdenticalElements<int16_t>(Val) &&
gen/lib/Target/AArch64/AArch64GenAsmWriter1.inc13155 printImm8OptLsl<int16_t>(MI, 1, STI, O);
13486 printImm8OptLsl<int16_t>(MI, 3, STI, O);
13806 printImm8OptLsl<int16_t>(MI, 2, STI, O);
27532 printLogicalImm<int16_t>(MI, OpIdx, STI, OS);
27556 printImm8OptLsl<int16_t>(MI, OpIdx, STI, OS);
27565 printSVELogicalImm<int16_t>(MI, OpIdx, STI, OS);
27689 return AArch64_AM::isSVEMaskOfIdenticalElements<int16_t>(Val);
27712 return AArch64_AM::isSVEMaskOfIdenticalElements<int16_t>(Val) &&
gen/lib/Target/AArch64/AArch64GenGlobalISel.inc 379 return AArch64_AM::isSVEAddSubImm<int16_t>(Imm);
407 return AArch64_AM::isSVECpyImm<int16_t>(Imm);
gen/lib/Target/AMDGPU/AMDGPUGenInstrInfo.inc48182 int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx) {
48183 static const int16_t OperandMap [][91] = {
gen/lib/Target/AMDGPU/R600GenInstrInfo.inc 1880 int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx) {
1881 static const int16_t OperandMap [][107] = {
gen/lib/Target/Hexagon/HexagonGenDAGISel.inc72414 int16_t V = N->getSExtValue();
72966 int16_t NV = -N->getSExtValue();
73040 int16_t imm = N->getSExtValue();
gen/lib/Target/PowerPC/PPCGenDAGISel.inc44309 int16_t Imm;
gen/lib/Target/WebAssembly/WebAssemblyGenInstrInfo.inc 4299 int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx) {
4300 static const int16_t OperandMap [][10] = {
gen/tools/clang/include/clang/Basic/DiagnosticGroups.inc 3 static const int16_t DiagArrays[] = {
709 static const int16_t DiagSubGroups[] = {
gen/tools/clang/lib/AST/Opcodes.inc 474 auto V0 = PC.read<int16_t>();
483 OS << "\t" << PC.read<int16_t>() << " "<< "\n";
487 bool emitConstSint16(int16_t, const SourceInfo &);
490 bool ByteCodeEmitter::emitConstSint16(int16_t A0,const SourceInfo &L) {
491 return emitOp<int16_t>(OP_ConstSint16, A0, L);
495 bool EvalEmitter::emitConstSint16(int16_t A0,const SourceInfo &L) {
gen/tools/lldb/scripts/LLDBWrapPython.cpp19031 int16_t result;
include/llvm/BinaryFormat/MachO.h 988 int16_t n_desc;
include/llvm/CodeGen/RegisterPressure.h 105 int16_t UnitInc = 0;
include/llvm/CodeGen/SelectionDAGNodes.h 497 int16_t NodeType;
include/llvm/DebugInfo/PDB/PDBTypes.h 413 explicit Variant(int16_t V) : Type(PDB_VariantType::Int16) {
454 int16_t Int16;
include/llvm/MC/MCInstrDesc.h 76 int16_t RegClass;
include/llvm/MC/MCInstrItineraries.h 96 int16_t NumMicroOps; ///< # of micro-ops, -1 means it's variable
include/llvm/MC/MCSchedule.h 79 int16_t Cycles;
include/llvm/Object/XCOFFObjectFile.h 214 static bool isReservedSectionNumber(int16_t SectionNumber);
324 Expected<DataRefImpl> getSectionByNum(int16_t Num) const;
349 int16_t getSectionNumber() const;
include/llvm/Support/Endian.h 279 detail::packed_endian_specific_integral<int16_t, little, unaligned>;
293 detail::packed_endian_specific_integral<int16_t, little, aligned>;
307 detail::packed_endian_specific_integral<int16_t, big, unaligned>;
321 detail::packed_endian_specific_integral<int16_t, big, aligned>;
335 detail::packed_endian_specific_integral<int16_t, native, unaligned>;
include/llvm/Support/ScaledNumber.h 52 inline std::pair<DigitsT, int16_t> getRounded(DigitsT Digits, int16_t Scale,
52 inline std::pair<DigitsT, int16_t> getRounded(DigitsT Digits, int16_t Scale,
64 inline std::pair<uint32_t, int16_t> getRounded32(uint32_t Digits, int16_t Scale,
64 inline std::pair<uint32_t, int16_t> getRounded32(uint32_t Digits, int16_t Scale,
70 inline std::pair<uint64_t, int16_t> getRounded64(uint64_t Digits, int16_t Scale,
70 inline std::pair<uint64_t, int16_t> getRounded64(uint64_t Digits, int16_t Scale,
79 inline std::pair<DigitsT, int16_t> getAdjusted(uint64_t Digits,
80 int16_t Scale = 0) {
94 inline std::pair<uint32_t, int16_t> getAdjusted32(uint64_t Digits,
95 int16_t Scale = 0) {
100 inline std::pair<uint64_t, int16_t> getAdjusted64(uint64_t Digits,
101 int16_t Scale = 0) {
108 std::pair<uint64_t, int16_t> multiply64(uint64_t LHS, uint64_t RHS);
114 inline std::pair<DigitsT, int16_t> getProduct(DigitsT LHS, DigitsT RHS) {
124 inline std::pair<uint32_t, int16_t> getProduct32(uint32_t LHS, uint32_t RHS) {
129 inline std::pair<uint64_t, int16_t> getProduct64(uint64_t LHS, uint64_t RHS) {
138 std::pair<uint64_t, int16_t> divide64(uint64_t Dividend, uint64_t Divisor);
145 std::pair<uint32_t, int16_t> divide32(uint32_t Dividend, uint32_t Divisor);
153 std::pair<DigitsT, int16_t> getQuotient(DigitsT Dividend, DigitsT Divisor) {
170 inline std::pair<uint32_t, int16_t> getQuotient32(uint32_t Dividend,
176 inline std::pair<uint64_t, int16_t> getQuotient64(uint64_t Dividend,
188 inline std::pair<int32_t, int> getLgImpl(DigitsT Digits, int16_t Scale) {
213 template <class DigitsT> int32_t getLg(DigitsT Digits, int16_t Scale) {
222 template <class DigitsT> int32_t getLgFloor(DigitsT Digits, int16_t Scale) {
232 template <class DigitsT> int32_t getLgCeiling(DigitsT Digits, int16_t Scale) {
251 int compare(DigitsT LDigits, int16_t LScale, DigitsT RDigits, int16_t RScale) {
251 int compare(DigitsT LDigits, int16_t LScale, DigitsT RDigits, int16_t RScale) {
286 int16_t matchScales(DigitsT &LDigits, int16_t &LScale, DigitsT &RDigits,
286 int16_t matchScales(DigitsT &LDigits, int16_t &LScale, DigitsT &RDigits,
287 int16_t &RScale) {
332 std::pair<DigitsT, int16_t> getSum(DigitsT LDigits, int16_t LScale,
332 std::pair<DigitsT, int16_t> getSum(DigitsT LDigits, int16_t LScale,
333 DigitsT RDigits, int16_t RScale) {
342 int16_t Scale = matchScales(LDigits, LScale, RDigits, RScale);
355 inline std::pair<uint32_t, int16_t> getSum32(uint32_t LDigits, int16_t LScale,
355 inline std::pair<uint32_t, int16_t> getSum32(uint32_t LDigits, int16_t LScale,
356 uint32_t RDigits, int16_t RScale) {
361 inline std::pair<uint64_t, int16_t> getSum64(uint64_t LDigits, int16_t LScale,
361 inline std::pair<uint64_t, int16_t> getSum64(uint64_t LDigits, int16_t LScale,
362 uint64_t RDigits, int16_t RScale) {
372 std::pair<DigitsT, int16_t> getDifference(DigitsT LDigits, int16_t LScale,
372 std::pair<DigitsT, int16_t> getDifference(DigitsT LDigits, int16_t LScale,
373 DigitsT RDigits, int16_t RScale) {
378 const int16_t SavedRScale = RScale;
398 inline std::pair<uint32_t, int16_t> getDifference32(uint32_t LDigits,
399 int16_t LScale,
401 int16_t RScale) {
406 inline std::pair<uint64_t, int16_t> getDifference64(uint64_t LDigits,
407 int16_t LScale,
409 int16_t RScale) {
423 static void dump(uint64_t D, int16_t E, int Width);
424 static raw_ostream &print(raw_ostream &OS, uint64_t D, int16_t E, int Width,
426 static std::string toString(uint64_t D, int16_t E, int Width,
507 int16_t Scale = 0;
512 constexpr ScaledNumber(DigitsType Digits, int16_t Scale)
516 ScaledNumber(const std::pair<DigitsT, int16_t> &X)
533 int16_t getScale() const { return Scale; }
623 ScaledNumber &operator<<=(int16_t Shift) {
627 ScaledNumber &operator>>=(int16_t Shift) {
731 int16_t Shift) {
737 int16_t Shift) {
include/llvm/Support/ScopedPrinter.h 186 void printNumber(StringRef Label, int16_t Value) {
include/llvm/Support/YAMLTraits.h 1213 static void output(const int16_t &, void *, raw_ostream &);
1214 static StringRef input(StringRef, void *, int16_t &);
lib/BinaryFormat/MsgPackReader.cpp 51 return readInt<int16_t>(Obj);
lib/CodeGen/AsmPrinter/DIE.cpp 732 case dwarf::DW_FORM_block2: return Size + sizeof(int16_t);
783 case dwarf::DW_FORM_block2: return Size + sizeof(int16_t);
lib/CodeGen/AsmPrinter/DwarfDebug.cpp 2588 sizeof(int16_t) + // DWARF ARange version number
lib/CodeGen/AsmPrinter/DwarfUnit.h 259 return sizeof(int16_t) + // DWARF version number
lib/CodeGen/MachineScheduler.cpp 1079 && NewMaxPressure[ID] <= (unsigned)std::numeric_limits<int16_t>::max())
lib/CodeGen/RegisterPressure.cpp 1205 if (CritInc > 0 && CritInc <= std::numeric_limits<int16_t>::max()) {
lib/DebugInfo/CodeView/CodeViewRecordIO.cpp 282 } else if (Value >= std::numeric_limits<int16_t>::min()) {
331 } else if (Value >= std::numeric_limits<int16_t>::min()) {
334 if (auto EC = Writer->writeInteger<int16_t>(Value))
lib/DebugInfo/CodeView/RecordSerialization.cpp 58 int16_t N;
lib/MC/MCDisassembler/Disassembler.cpp 216 int16_t Latency = 0;
lib/MC/XCOFFObjectWriter.cpp 47 constexpr int16_t MaxSectionIndex = INT16_MAX;
109 int16_t Index;
121 static constexpr int16_t UninitializedIndex =
185 const ControlSection &, int16_t,
187 void writeSymbolTableEntryForControlSection(const ControlSection &, int16_t,
395 int16_t SectionIndex, uint64_t SymbolOffset) {
401 W.write<int16_t>(SectionIndex);
431 const ControlSection &CSectionRef, int16_t SectionIndex,
438 W.write<int16_t>(SectionIndex);
527 const int16_t SectionIndex = Section->Index;
lib/Object/XCOFFObjectFile.cpp 204 int16_t SectNum = SymEntPtr->SectionNumber;
405 Expected<DataRefImpl> XCOFFObjectFile::getSectionByNum(int16_t Num) const {
418 int16_t SectionNum = SymEntPtr->SectionNumber;
436 bool XCOFFObjectFile::isReservedSectionNumber(int16_t SectionNumber) {
728 int16_t XCOFFSymbolRef::getSectionNumber() const {
757 int16_t SectNum = getSectionNumber();
lib/Support/ScaledNumber.cpp 22 std::pair<uint64_t, int16_t> ScaledNumbers::multiply64(uint64_t LHS,
57 std::pair<uint32_t, int16_t> ScaledNumbers::divide32(uint32_t Dividend,
80 std::pair<uint64_t, int16_t> ScaledNumbers::divide64(uint64_t Dividend,
201 std::string ScaledNumberBase::toString(uint64_t D, int16_t E, int Width,
315 raw_ostream &ScaledNumberBase::print(raw_ostream &OS, uint64_t D, int16_t E,
320 void ScaledNumberBase::dump(uint64_t D, int16_t E, int Width) {
lib/Support/YAMLTraits.cpp 969 void ScalarTraits<int16_t>::output(const int16_t &Val, void *,
974 StringRef ScalarTraits<int16_t>::input(StringRef Scalar, void *, int16_t &Val) {
lib/Target/AArch64/AArch64ISelLowering.cpp 2073 int16_t ValueofRHS = cast<ConstantSDNode>(RHS)->getZExtValue();
lib/Target/AArch64/MCTargetDesc/AArch64AddressingModes.h 769 if (std::is_same<int16_t, typename std::make_signed<T>::type>::value)
789 auto H = bit_cast<std::array<int16_t, 4>>(Imm);
794 if (isSVEMaskOfIdenticalElements<int16_t>(Imm) && isSVECpyImm<int16_t>(H[0]))
794 if (isSVEMaskOfIdenticalElements<int16_t>(Imm) && isSVECpyImm<int16_t>(H[0]))
lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp 478 ArrayRef<int16_t> SubRegs = TRI.getRegSplitParts(DstRC, SrcSize / 8);
525 ArrayRef<int16_t> SubRegs = TRI.getRegSplitParts(SrcRC, DstSize / 8);
lib/Target/AMDGPU/AMDGPURegisterBankInfo.h 116 int16_t Cost;
lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp 351 int16_t SImm = static_cast<int16_t>(Imm);
lib/Target/AMDGPU/SIInstrInfo.cpp 704 ArrayRef<int16_t> SubIndices = RI.getRegSplitParts(RC, EltSize);
797 ArrayRef<int16_t> SubIndices = RI.getRegSplitParts(RegClass, EltSize);
2195 static const int16_t Sub0_15[] = {
2202 static const int16_t Sub0_15_64[] = {
2211 const int16_t *SubIndices = Sub0_15;
2870 int16_t Trunc = static_cast<int16_t>(Imm);
lib/Target/AMDGPU/SIRegisterInfo.cpp 779 ArrayRef<int16_t> SplitParts = getRegSplitParts(RC, EltSize);
891 ArrayRef<int16_t> SplitParts = getRegSplitParts(RC, EltSize);
1515 ArrayRef<int16_t> SIRegisterInfo::getRegSplitParts(const TargetRegisterClass *RC,
1518 static const int16_t Sub0_31[] = {
1529 static const int16_t Sub0_15[] = {
1536 static const int16_t Sub0_7[] = {
1541 static const int16_t Sub0_4[] = {
1545 static const int16_t Sub0_3[] = {
1549 static const int16_t Sub0_2[] = {
1553 static const int16_t Sub0_1[] = {
1580 static const int16_t Sub0_31_64[] = {
1591 static const int16_t Sub0_15_64[] = {
1598 static const int16_t Sub0_7_64[] = {
1604 static const int16_t Sub0_3_64[] = {
1626 static const int16_t Sub0_31_128[] = {
1637 static const int16_t Sub0_15_128[] = {
1644 static const int16_t Sub0_7_128[] = {
1665 static const int16_t Sub0_31_256[] = {
1672 static const int16_t Sub0_15_256[] = {
lib/Target/AMDGPU/SIRegisterInfo.h 228 ArrayRef<int16_t> getRegSplitParts(const TargetRegisterClass *RC,
lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp 1182 bool isInlinableLiteral16(int16_t Literal, bool HasInv2Pi) {
1205 int16_t Trunc = static_cast<int16_t>(Literal);
1211 int16_t Lo16 = static_cast<int16_t>(Literal);
1212 int16_t Hi16 = static_cast<int16_t>(Literal >> 16);
lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h 191 int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx);
627 bool isInlinableLiteral16(int16_t Literal, bool HasInv2Pi);
lib/Target/BPF/MCTargetDesc/BPFInstPrinter.cpp 100 int16_t Imm = Op.getImm();
lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.cpp 81 int16_t Imm;
lib/Target/Lanai/LanaiISelDAGToDAG.cpp 130 int16_t Imm = CN->getSExtValue();
143 int16_t Imm = CN->getSExtValue();
lib/Target/MSP430/MCTargetDesc/MSP430AsmBackend.cpp 114 int16_t Offset = Value;
lib/Target/MSP430/MSP430ISelDAGToDAG.cpp 47 int16_t Disp;
lib/Target/Mips/AsmParser/MipsAsmParser.cpp 3609 int16_t DstRegClass = Desc.OpInfo[0].RegClass;
lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp 200 void MipsTargetStreamer::emitII(unsigned Opcode, int16_t Imm1, int16_t Imm2,
200 void MipsTargetStreamer::emitII(unsigned Opcode, int16_t Imm1, int16_t Imm2,
242 int16_t Imm, SMLoc IDLoc,
248 unsigned Reg1, int16_t Imm0, int16_t Imm1,
248 unsigned Reg1, int16_t Imm0, int16_t Imm1,
249 int16_t Imm2, SMLoc IDLoc,
270 int16_t ShiftAmount, SMLoc IDLoc,
lib/Target/Mips/MicroMipsSizeReduction.cpp 53 ImmField(uint8_t Shift, int16_t LBound, int16_t HBound,
53 ImmField(uint8_t Shift, int16_t LBound, int16_t HBound,
59 int16_t LBound; // Low bound of the immediate operand
60 int16_t HBound; // High bound of the immediate operand
103 int16_t LBound() const { return Imm.LBound; }
104 int16_t HBound() const { return Imm.HBound; }
lib/Target/Mips/MipsTargetStreamer.h 121 void emitII(unsigned Opcode, int16_t Imm1, int16_t Imm2, SMLoc IDLoc,
121 void emitII(unsigned Opcode, int16_t Imm1, int16_t Imm2, SMLoc IDLoc,
135 void emitRRI(unsigned Opcode, unsigned Reg0, unsigned Reg1, int16_t Imm,
137 void emitRRIII(unsigned Opcode, unsigned Reg0, unsigned Reg1, int16_t Imm0,
138 int16_t Imm1, int16_t Imm2, SMLoc IDLoc,
138 int16_t Imm1, int16_t Imm2, SMLoc IDLoc,
142 void emitDSLL(unsigned DstReg, unsigned SrcReg, int16_t ShiftAmount,
lib/Target/PowerPC/PPCISelDAGToDAG.cpp 3719 int16_t SImm;
3766 int16_t SImm;
4688 int16_t Imm;
4746 int16_t Imm;
lib/Target/PowerPC/PPCISelLowering.cpp 2242 bool llvm::isIntS16Immediate(SDNode *N, int16_t &Imm) {
2252 bool llvm::isIntS16Immediate(SDValue Op, int16_t &Imm) {
2284 int16_t imm = 0;
2379 int16_t imm = 0;
2403 int16_t imm = 0;
2430 int16_t Imm;
2481 int16_t imm = 0;
lib/Target/PowerPC/PPCISelLowering.h 1237 bool isIntS16Immediate(SDNode *N, int16_t &Imm);
1238 bool isIntS16Immediate(SDValue Op, int16_t &Imm);
lib/Target/PowerPC/PPCInstrInfo.cpp 1771 int16_t Immed = (int16_t)Value;
lib/Target/PowerPC/PPCInstrInfo.h 469 int16_t regClass = Desc.OpInfo[OpNo].RegClass;
lib/Target/PowerPC/PPCMIPeephole.cpp 1127 int16_t Imm1 = 0, NewImm1 = 0, Imm2 = 0, NewImm2 = 0;
1142 int16_t Imm = (int16_t)I->getOperand(2).getImm();
lib/Target/WebAssembly/WebAssemblyInstrInfo.h 31 int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIndex);
lib/Target/WebAssembly/WebAssemblySetP2AlignOperands.cpp 87 int16_t P2AlignOpNum = WebAssembly::getNamedOperandIdx(
lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp 1238 int16_t d16;
lib/Target/X86/X86InsertPrefetch.cpp 122 int16_t max_index = -1;
projects/compiler-rt/lib/builtins/gcc_personality_v0.c 91 p += sizeof(int16_t);
projects/compiler-rt/lib/xray/xray_interface.cpp 44 static const int16_t cSledLength = 12;
tools/clang/include/clang/Analysis/Analyses/ThreadSafetyTIL.h 222 inline ValueType ValueType::getValueType<int16_t>() {
596 return Vs.reduceLiteralT(as<int16_t>());
tools/clang/include/clang/Analysis/Analyses/ThreadSafetyTraverse.h 577 printLiteralT(&E->as<int16_t>(), SS);
tools/clang/lib/AST/Interp/Integral.h 47 template <> struct Repr<16, true> { using Type = int16_t; };
tools/clang/lib/Basic/DiagnosticIDs.cpp 561 const int16_t *Member = DiagArrays + Group->Members;
570 const int16_t *SubGroups = DiagSubGroups + Group->SubGroups;
tools/dsymutil/DwarfStreamer.cpp 336 sizeof(int16_t) + // DWARF ARange version number
tools/lld/COFF/Chunks.cpp 60 static void add16(uint8_t *p, int16_t v) { write16le(p, read16le(p) + v); }
tools/lld/ELF/Arch/MSP430.cpp 81 int16_t offset = ((int16_t)val >> 1) - 1;
tools/lld/ELF/Arch/PPC64.cpp 1035 int16_t hiImm = 0;
1036 int16_t loImm = 0;
tools/lld/lib/ReaderWriter/MachO/ArchHandler.cpp 126 int16_t ArchHandler::readS16(const uint8_t *addr, bool isBig) {
tools/lld/lib/ReaderWriter/MachO/ArchHandler.h 313 static int16_t readS16(const uint8_t *addr, bool isBig);
tools/lld/lib/ReaderWriter/MachO/CompactUnwindPass.cpp 216 const int16_t headerSize = sizeof(uint32_t) + 2 * sizeof(uint16_t);
tools/lldb/include/lldb/API/SBData.h 60 int16_t GetSignedInt16(lldb::SBError &error, lldb::offset_t offset);
tools/lldb/include/lldb/Utility/Stream.h 274 Stream &operator<<(int16_t sval);
tools/lldb/source/API/SBData.cpp 263 int16_t SBData::GetSignedInt16(lldb::SBError &error, lldb::offset_t offset) {
267 int16_t value = 0;
tools/lldb/source/Expression/DWARFExpression.cpp 1795 int16_t skip_offset = (int16_t)opcodes.GetU16(&offset);
1822 int16_t bra_offset = (int16_t)opcodes.GetU16(&offset);
tools/lldb/source/Plugins/LanguageRuntime/RenderScript/RenderScriptRuntime/RenderScriptRuntime.cpp 748 {eFormatDecimal, eFormatVectorOfSInt16, sizeof(int16_t)},
tools/lldb/source/Plugins/Process/elf-core/ThreadElfCore.h 39 int16_t pr_cursig;
tools/lldb/source/Plugins/UnwindAssembly/x86/x86AssemblyInspectionEngine.cpp 799 int16_t rel16 = extract_2_signed (m_cur_insn + opcode_size);
866 int16_t x86AssemblyInspectionEngine::extract_2_signed(uint8_t *b) {
867 int16_t v = 0;
tools/lldb/source/Plugins/UnwindAssembly/x86/x86AssemblyInspectionEngine.h 127 int16_t extract_2_signed(uint8_t *b);
tools/lldb/source/Utility/Stream.cpp 194 Stream &Stream::operator<<(int16_t sval) {
tools/lldb/unittests/Utility/StreamTest.cpp 300 s << std::numeric_limits<int16_t>::max() << " ";
unittests/ADT/StringRefTest.cpp 636 int16_t S16;
822 int16_t S16;
unittests/ExecutionEngine/Orc/RPCUtilsTest.cpp 135 : public Function<AllTheTypes, void(int8_t, uint8_t, int16_t, uint16_t,
unittests/Support/CheckedArithmeticTest.cpp 18 const int16_t Max = std::numeric_limits<int16_t>::max();
18 const int16_t Max = std::numeric_limits<int16_t>::max();
19 const int16_t Min = std::numeric_limits<int16_t>::min();
19 const int16_t Min = std::numeric_limits<int16_t>::min();
45 const int16_t Max = std::numeric_limits<int16_t>::max();
45 const int16_t Max = std::numeric_limits<int16_t>::max();
46 const int16_t Min = std::numeric_limits<int16_t>::min();
46 const int16_t Min = std::numeric_limits<int16_t>::min();
54 const int16_t Max = std::numeric_limits<int16_t>::max();
54 const int16_t Max = std::numeric_limits<int16_t>::max();
55 const int16_t Min = std::numeric_limits<int16_t>::min();
55 const int16_t Min = std::numeric_limits<int16_t>::min();
unittests/Support/ScaledNumberTest.cpp 21 ScaledPair(const std::pair<UIntT, int16_t> &F) : D(F.first), S(F.second) {}
29 bool operator==(const std::pair<UIntT, int16_t> &L,
unittests/Support/SwapByteOrderTest.cpp 56 int16_t original_int16 = static_cast<int16_t>(value);
171 int16_t value = 0x2211;
unittests/Support/YAMLIOTest.cpp 337 int16_t s16;
2046 std::vector<int16_t> seq;
2065 std::vector<int16_t> seq;
usr/include/c++/7.4.0/atomic 923 typedef atomic<int16_t> atomic_int16_t;
usr/include/rpc/xdr.h 298 extern bool_t xdr_int16_t (XDR *__xdrs, int16_t *__ip) __THROW;
utils/TableGen/SubtargetEmitter.cpp 516 int16_t NumUOps = ItinData ? ItinData->getValueAsInt("NumMicroOps") : 0;