reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

Overridden By

lib/Target/AMDGPU/SIInstrInfo.h

 1020   const TargetRegisterClass *getRegClass(const MCInstrDesc &TID, unsigned OpNum,

Declarations

include/llvm/CodeGen/TargetInstrInfo.h

   89   const TargetRegisterClass *getRegClass(const MCInstrDesc &MCID, unsigned OpNum,

References

lib/CodeGen/AggressiveAntiDepBreaker.cpp

  409       RC = TII->getRegClass(MI.getDesc(), i, TRI, MF);
  493       RC = TII->getRegClass(MI.getDesc(), i, TRI, MF);

lib/CodeGen/BreakFalseDeps.cpp

  126     TII->getRegClass(MI->getDesc(), OpIdx, TRI, *MF);

lib/CodeGen/CriticalAntiDepBreaker.cpp

  195       NewRC = TII->getRegClass(MI.getDesc(), i, TRI, MF);
  312       NewRC = TII->getRegClass(MI.getDesc(), i, TRI, MF);

lib/CodeGen/GlobalISel/Utils.cpp

   79   const TargetRegisterClass *RegClass = TII.getRegClass(II, OpIdx, &TRI, MF);

lib/CodeGen/MachineInstr.cpp

  840     return TII->getRegClass(getDesc(), OpIdx, TRI, MF);

lib/CodeGen/MachineLICM.cpp

 1304   const TargetRegisterClass *RC = TII->getRegClass(MID, LoadRegIndex, TRI, MF);

lib/CodeGen/MachineVerifier.cpp

 1692               TII->getRegClass(MCID, MONum, TRI, *MF)) {
 1762             TII->getRegClass(MCID, MONum, TRI, *MF)) {
 1767                         TII->getRegClass(MCID, MONum, TRI, *MF))
 1792               TII->getRegClass(MCID, MONum, TRI, *MF)) {

lib/CodeGen/RegisterCoalescer.cpp

 1255   const TargetRegisterClass *DefRC = TII->getRegClass(MCID, 0, TRI, *MF);

lib/CodeGen/SelectionDAG/FastISel.cpp

 2024         TII.getRegClass(II, OpNum, &TRI, *FuncInfo.MF);

lib/CodeGen/SelectionDAG/InstrEmitter.cpp

  136                 TII->getRegClass(II, i+II.getNumDefs(), TRI, *MF));
  204       TRI->getAllocatableClass(TII->getRegClass(II, i, TRI, *MF));
  314       OpRC = TII->getRegClass(*II, IIOpNum, TRI, *MF);
  379         II ? TRI->getAllocatableClass(TII->getRegClass(*II, IIOpNum, TRI, *MF))

lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp

  342     const TargetRegisterClass *RC = TII->getRegClass(Desc, Idx, TRI, MF);

lib/CodeGen/TwoAddressInstructionPass.cpp

 1363             TII->getRegClass(UnfoldMCID, LoadRegIndex, TRI, *MF));
 1486         if (const TargetRegisterClass *RC = TII->getRegClass(MCID, SrcIdx,

lib/Target/AArch64/AArch64ConditionalCompares.cpp

  635         MRI->createVirtualRegister(TII->getRegClass(MCID, 0, TRI, *MF));
  644                            TII->getRegClass(MCID, 1, TRI, *MF));
  691                          TII->getRegClass(MCID, 0, TRI, *MF));
  694                            TII->getRegClass(MCID, 1, TRI, *MF));

lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp

  160       const TargetRegisterClass *RC = TII->getRegClass(Desc, I, TRI, MF);

lib/Target/AArch64/AArch64RegisterInfo.cpp

  418   MRI.constrainRegClass(BaseReg, TII->getRegClass(MCID, 0, this, MF));

lib/Target/ARM/ARMBaseRegisterInfo.cpp

  646   MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF));
  815       TII.getRegClass(MCID, FIOperandNum, this, *MI.getParent()->getParent());

lib/Target/ARM/ARMFrameLowering.cpp

 1533         const TargetRegisterClass *RegClass = TII.getRegClass(MCID, i, TRI, MF);

lib/Target/ARM/ARMLoadStoreOptimizer.cpp

 2323           const TargetRegisterClass *TRC = TII->getRegClass(MCID, 0, TRI, *MF);

lib/Target/ARM/MLxExpansionPass.cpp

  288       MRI->createVirtualRegister(TII->getRegClass(MCID1, 0, TRI, MF));

lib/Target/ARM/Thumb2InstrInfo.cpp

  475       TII.getRegClass(Desc, FrameRegIdx, TRI, MF);

lib/Target/Hexagon/HexagonBitSimplify.cpp

 1875   auto *OpRC = HII.getRegClass(HII.get(Opc), OpNum, &HRI, MF);

lib/Target/Hexagon/HexagonFrameLowering.cpp

 2087           auto *RC = HII.getRegClass(In.getDesc(), OpNum, &HRI, MF);
 2255         auto *RC = HII.getRegClass(SI.getDesc(), 2, &HRI, MF);

lib/Target/Hexagon/HexagonStoreWidening.cpp

  443     const TargetRegisterClass *RC = TII->getRegClass(TfrD, 0, TRI, *MF);

lib/Target/Hexagon/HexagonVLIWPacketizer.cpp

  657   const TargetRegisterClass *PacketRC = HII->getRegClass(MCID, 0, HRI, MF);
  870   const TargetRegisterClass *VecRC = HII->getRegClass(MCID, 0, HRI, MF);

lib/Target/Mips/MipsSEInstrInfo.cpp

  706   unsigned DstRegSize = RI->getRegSizeInBits(*getRegClass(Desc, 0, RI, MF));
  707   unsigned SrcRegSize = RI->getRegSizeInBits(*getRegClass(Desc, 1, RI, MF));

lib/Target/PowerPC/PPCRegisterInfo.cpp

 1235   MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF));
 1262                         TII.getRegClass(MCID, FIOperandNum, this, MF));

lib/Target/SystemZ/SystemZHazardRecognizer.cpp

  123     const TargetRegisterClass *RC = TII->getRegClass(MID, OpIdx, TRI, MF);

lib/Target/X86/X86AvoidStoreForwardingBlocks.cpp

  395       TII->getRegClass(TII->get(NLoadOpcode), 0, TRI, *(MBB->getParent())));
  565   auto TRC = TII->getRegClass(TII->get(LoadInst->getOpcode()), 0, TRI,

lib/Target/X86/X86DomainReassignment.cpp

  186         TII->getRegClass(TII->get(DstOpcode), 0, MRI->getTargetRegisterInfo(),

lib/Target/X86/X86InstrInfo.cpp

 4648         Reg, TII.getRegClass(NewMI.getDesc(), Idx, &TRI, MF));
 4744       const TargetRegisterClass *RC = getRegClass(MI.getDesc(), OpNum, &RI, MF);
 4768       const TargetRegisterClass *RC = getRegClass(MI.getDesc(), OpNum, &RI, MF);
 4787       const TargetRegisterClass *RC = getRegClass(MI.getDesc(), OpNum, &RI, MF);
 4900       const TargetRegisterClass *RC = getRegClass(MI.getDesc(), OpNum,
 5471   const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
 5579     const TargetRegisterClass *DstRC = getRegClass(MCID, 0, &RI, MF);
 5613   const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
 5664     DstRC = getRegClass(MCID, 0, &RI, MF);

lib/Target/X86/X86OptimizeLEAs.cpp

  356     if (TII->getRegClass(Desc, MemOpNo + X86::AddrBaseReg, TRI, *MF) !=

lib/Target/X86/X86SpeculativeLoadHardening.cpp

  846   return TII.getRegClass(MCID, Index, &TII.getRegisterInfo(), MF);