reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

Declarations

include/llvm/CodeGen/MachineRegisterInfo.h

  601   MachineInstr *getUniqueVRegDef(unsigned Reg) const;

References

lib/CodeGen/GlobalISel/CombinerHelper.cpp

  567   MachineInstr *BaseDef = MRI.getUniqueVRegDef(Base);
  588     MachineInstr *OffsetDef = MRI.getUniqueVRegDef(Offset);
  714   MachineInstr &AddrDef = *MRI.getUniqueVRegDef(Addr);

lib/CodeGen/MachineCSE.cpp

  646         MachineInstr *Def = MRI->getUniqueVRegDef(NewReg);

lib/CodeGen/MachineCombiner.cpp

  141     DefInstr = MRI->getUniqueVRegDef(MO.getReg());

lib/CodeGen/MachinePipeliner.cpp

  797         MachineInstr *DefMI = MRI.getUniqueVRegDef(Reg);
  852     MachineInstr *DefMI = MRI.getUniqueVRegDef(OrigBase);
  859     MachineInstr *LastMI = MRI.getUniqueVRegDef(NewBase);

lib/CodeGen/ModuloSchedule.cpp

 1351   MachineInstr *Producer = MRI.getUniqueVRegDef(Reg);
 1381     LoopProducer = MRI.getUniqueVRegDef(LoopReg);
 1640       MachineInstr *Use = MRI.getUniqueVRegDef(Reg);
 1714   MachineInstr *MI = MRI.getUniqueVRegDef(Reg);
 1725     int RMIStage = getStage(MRI.getUniqueVRegDef(R));

lib/CodeGen/RegAllocFast.cpp

  632     MachineInstr *VRegDef = MRI->getUniqueVRegDef(Reg);

lib/CodeGen/RegAllocGreedy.cpp

 1822   MachineInstr *MI = MRI->getUniqueVRegDef(VirtReg.reg);

lib/CodeGen/TargetInstrInfo.cpp

  678     MI1 = MRI.getUniqueVRegDef(Op1.getReg());
  680     MI2 = MRI.getUniqueVRegDef(Op2.getReg());
  690   MachineInstr *MI1 = MRI.getUniqueVRegDef(Inst.getOperand(1).getReg());
  691   MachineInstr *MI2 = MRI.getUniqueVRegDef(Inst.getOperand(2).getReg());
  867     Prev = MRI.getUniqueVRegDef(Root.getOperand(1).getReg());
  871     Prev = MRI.getUniqueVRegDef(Root.getOperand(2).getReg());

lib/Target/AArch64/AArch64CondBrTuning.cpp

   83   return MRI->getUniqueVRegDef(MO.getReg());

lib/Target/AArch64/AArch64FastISel.cpp

 2047     auto *MI = MRI.getUniqueVRegDef(Reg);
 2079         MI = MRI.getUniqueVRegDef(Reg);
 4535   MachineInstr *MI = MRI.getUniqueVRegDef(Reg);
 4546     LoadMI = MRI.getUniqueVRegDef(LoadReg);

lib/Target/AArch64/AArch64InstrInfo.cpp

 1445   MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
 3601     MI = MRI.getUniqueVRegDef(MO.getReg());
 3992   MachineInstr *MUL = MRI.getUniqueVRegDef(Root.getOperand(IdxMulOpd).getReg());
 4069   MachineInstr *MUL = MRI.getUniqueVRegDef(Root.getOperand(IdxMulOpd).getReg());

lib/Target/AArch64/AArch64SIMDInstrOpt.cpp

  519       DefiningMI = MRI->getUniqueVRegDef(SeqReg);

lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp

 1477   const MachineInstr *PtrMI = MRI.getUniqueVRegDef(Load.getOperand(1).getReg());
 1488     const MachineInstr *OpDef = MRI.getUniqueVRegDef(GEPOp.getReg());

lib/Target/AMDGPU/GCNNSAReassign.cpp

  197       const MachineInstr *Def = MRI->getUniqueVRegDef(Reg);

lib/Target/AMDGPU/GCNRegBankReassign.cpp

  426   const MachineInstr *Def = MRI->getUniqueVRegDef(Reg);

lib/Target/AMDGPU/R600OptimizeVectorRegisters.cpp

   63   const MachineInstr *MI = MRI.getUniqueVRegDef(Reg);

lib/Target/AMDGPU/SIFixupVectorISel.cpp

   96     MachineInstr *DefInst = MRI.getUniqueVRegDef(WOp->getReg());
  120       MachineInstr *MI = MRI.getUniqueVRegDef(IndexReg);
  132       MI = MRI.getUniqueVRegDef(BaseReg);

lib/Target/AMDGPU/SIFoldOperands.cpp

  452   MachineInstr *Def = MRI.getUniqueVRegDef(UseReg);
  460     for (MachineInstr *SubDef = MRI.getUniqueVRegDef(Sub->getReg());
  463          SubDef = MRI.getUniqueVRegDef(Sub->getReg())) {

lib/Target/AMDGPU/SIISelLowering.cpp

10412         auto *Src = MRI.getUniqueVRegDef(Op.getReg());

lib/Target/AMDGPU/SIInstrInfo.cpp

 2433         MachineInstr *Def = MRI->getUniqueVRegDef(Src0->getReg());
 2451         MachineInstr *Def = MRI->getUniqueVRegDef(Src1->getReg());
 2598   auto Def = MRI.getUniqueVRegDef(MO->getReg());
 4307     Def = MRI.getUniqueVRegDef(Def->getOperand(1).getReg());

lib/Target/AMDGPU/SILoadStoreOptimizer.cpp

 1444   MachineInstr *Def = MRI->getUniqueVRegDef(Op.getReg());
 1467   MachineInstr *Def = MRI->getUniqueVRegDef(Base.getReg());
 1477   MachineInstr *BaseLoDef = MRI->getUniqueVRegDef(BaseLo.getReg());
 1478   MachineInstr *BaseHiDef = MRI->getUniqueVRegDef(BaseHi.getReg());

lib/Target/AMDGPU/SILowerControlFlow.cpp

  365     if (MachineInstr *Def = MRI->getUniqueVRegDef(MI.getOperand(1).getReg())) {
  420   MachineInstr *Def = MRI.getUniqueVRegDef(CFMask);
  449   MachineInstr *Def = MRI->getUniqueVRegDef(Op.getReg());
  491     MRI->getUniqueVRegDef(Reg)->eraseFromParent();

lib/Target/AMDGPU/SILowerI1Copies.cpp

  578       MachineInstr *IncomingDef = MRI->getUniqueVRegDef(IncomingReg);
  740     MI = MRI->getUniqueVRegDef(Reg);

lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp

  127   auto SaveExecInst = MRI.getUniqueVRegDef(SavedExec);

lib/Target/AMDGPU/SIPeepholeSDWA.cpp

  321   MachineInstr *DefInstr = MRI->getUniqueVRegDef(Reg->getReg());

lib/Target/AMDGPU/SIShrinkInstructions.cpp

   82       MachineInstr *Def = MRI.getUniqueVRegDef(Reg);

lib/Target/ARM/ARMBaseInstrInfo.cpp

 2907   MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);

lib/Target/BPF/BPFMISimplifyPatchable.cpp

  103       MachineInstr *DefInst = MRI->getUniqueVRegDef(SrcReg);

lib/Target/Lanai/LanaiInstrInfo.cpp

  287   MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);

lib/Target/NVPTX/NVPTXPeephole.cpp

   85     GenericAddrDef = MRI.getUniqueVRegDef(Op.getReg());
  109   auto &Prev = *MRI.getUniqueVRegDef(Root.getOperand(1).getReg());
  148     if (auto MI = MRI.getUniqueVRegDef(NVPTX::VRFrame)) {

lib/Target/PowerPC/PPCInstrInfo.cpp

 1670   MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
 4241       MachineInstr *LoopCount = MRI.getUniqueVRegDef(LoopCountReg);

lib/Target/WebAssembly/WebAssemblyCFGStackify.cpp

  718       if (MachineInstr *Def = MRI.getUniqueVRegDef(MO.getReg()))

lib/Target/WebAssembly/WebAssemblyMachineFunctionInfo.h

   98     assert(MF.getRegInfo().getUniqueVRegDef(VReg));

lib/Target/WebAssembly/WebAssemblyRegStackify.cpp

  273   if (MachineInstr *Def = MRI.getUniqueVRegDef(Reg))

lib/Target/WebAssembly/WebAssemblyRegisterInfo.cpp

   96         MachineInstr *Def = MF.getRegInfo().getUniqueVRegDef(OtherMOReg);

lib/Target/X86/X86InstrInfo.cpp

 3606   MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
 4817   MachineInstr *VRegDef = RegInfo.getUniqueVRegDef(MI.getOperand(1).getReg());

lib/Target/X86/X86WinAllocaExpander.cpp

   85   MachineInstr *Def = MRI->getUniqueVRegDef(AmountReg);
  269     if (MachineInstr *AmountDef = MRI->getUniqueVRegDef(AmountReg))