reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

gen/lib/Target/AArch64/AArch64GenGlobalISel.inc

42157         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FSUB,
42189         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FSUB,
42221         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FSUB,
42254         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FSUB,
42287         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FSUB,
42320         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FSUB,
42353         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FSUB,
42386         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FSUB,

gen/lib/Target/Mips/MipsGenGlobalISel.inc

20828         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FSUB,
20854         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FSUB,
21076         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FSUB,
21103         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FSUB,
21130         GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FSUB,

include/llvm/CodeGen/GlobalISel/MIPatternMatch.h

  224 inline BinaryOp_match<LHS, RHS, TargetOpcode::G_FSUB, false>
  226   return BinaryOp_match<LHS, RHS, TargetOpcode::G_FSUB, false>(L, R);

include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h

 1380     return buildInstr(TargetOpcode::G_FSUB, {Dst}, {Src0, Src1});

lib/CodeGen/GlobalISel/IRTranslator.cpp

  321   return translateBinaryOp(TargetOpcode::G_FSUB, U, MIRBuilder);

lib/CodeGen/GlobalISel/LegalizerHelper.cpp

  278   case TargetOpcode::G_FSUB:
  512   case TargetOpcode::G_FSUB:
 1823   case TargetOpcode::G_FSUB:
 2004     MIRBuilder.buildInstr(TargetOpcode::G_FSUB, {Res}, {ZeroReg, SubByReg},
 2009   case TargetOpcode::G_FSUB: {
 2962   case G_FSUB:

lib/Target/AArch64/AArch64InstructionSelector.cpp

  484       case TargetOpcode::G_FSUB:
  497       case TargetOpcode::G_FSUB:
 1850   case TargetOpcode::G_FSUB:

lib/Target/AArch64/AArch64LegalizerInfo.cpp

  148   getActionDefinitionsBuilder({G_FADD, G_FSUB, G_FMUL, G_FDIV, G_FNEG})

lib/Target/AArch64/AArch64RegisterBankInfo.cpp

  390   case TargetOpcode::G_FSUB:
  542   case TargetOpcode::G_FSUB:

lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

  418   getActionDefinitionsBuilder(G_FSUB)

lib/Target/ARM/ARMLegalizerInfo.cpp

  173         {G_FADD, G_FSUB, G_FMUL, G_FDIV, G_FCONSTANT, G_FNEG})
  195     getActionDefinitionsBuilder({G_FADD, G_FSUB, G_FMUL, G_FDIV})

lib/Target/ARM/ARMRegisterBankInfo.cpp

  288   case G_FSUB:

lib/Target/Mips/MipsLegalizerInfo.cpp

  191   getActionDefinitionsBuilder({G_FADD, G_FSUB, G_FMUL, G_FDIV, G_FABS, G_FSQRT})
  429     return MSA3OpIntrinsicToGeneric(MI, TargetOpcode::G_FSUB, MIRBuilder, ST);

lib/Target/Mips/MipsRegisterBankInfo.cpp

  112   case TargetOpcode::G_FSUB:
  543   case G_FSUB:

lib/Target/X86/X86LegalizerInfo.cpp

  293   for (unsigned BinOp : {G_FADD, G_FSUB, G_FMUL, G_FDIV})
  329   for (unsigned BinOp : {G_FADD, G_FSUB, G_FMUL, G_FDIV})

lib/Target/X86/X86RegisterBankInfo.cpp

  180   case TargetOpcode::G_FSUB:

unittests/CodeGen/GlobalISel/LegalizerHelperTest.cpp

  758     getActionDefinitionsBuilder(G_FSUB).legalFor({s64});

unittests/CodeGen/GlobalISel/PatternMatchTest.cpp

  106   auto MIBFSub = B.buildInstr(TargetOpcode::G_FSUB, {s64},