|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
Declarations
include/llvm/CodeGen/TargetInstrInfo.h 51 struct MCSchedModel;
References
gen/lib/Target/AArch64/AArch64GenSubtargetInfo.inc12439 static const llvm::MCSchedModel NoSchedModel = {
12440 MCSchedModel::DefaultIssueWidth,
12441 MCSchedModel::DefaultMicroOpBufferSize,
12442 MCSchedModel::DefaultLoopMicroOpBufferSize,
12443 MCSchedModel::DefaultLoadLatency,
12444 MCSchedModel::DefaultHighLatency,
12445 MCSchedModel::DefaultMispredictPenalty,
12476 static const llvm::MCSchedModel CycloneModel = {
12479 MCSchedModel::DefaultLoopMicroOpBufferSize,
12481 MCSchedModel::DefaultHighLatency,
12510 static const llvm::MCSchedModel CortexA53Model = {
12513 MCSchedModel::DefaultLoopMicroOpBufferSize,
12515 MCSchedModel::DefaultHighLatency,
12546 static const llvm::MCSchedModel CortexA57Model = {
12551 MCSchedModel::DefaultHighLatency,
12594 static const llvm::MCSchedModel ExynosM1Model = {
12599 MCSchedModel::DefaultHighLatency,
12676 static const llvm::MCSchedModel ExynosM3Model = {
12681 MCSchedModel::DefaultHighLatency,
12786 static const llvm::MCSchedModel ExynosM4Model = {
12791 MCSchedModel::DefaultHighLatency,
12835 static const llvm::MCSchedModel FalkorModel = {
12840 MCSchedModel::DefaultHighLatency,
12876 static const llvm::MCSchedModel KryoModel = {
12881 MCSchedModel::DefaultHighLatency,
12910 static const llvm::MCSchedModel ThunderXT8XModel = {
12913 MCSchedModel::DefaultLoopMicroOpBufferSize,
12915 MCSchedModel::DefaultHighLatency,
12959 static const llvm::MCSchedModel ThunderX2T99Model = {
12964 MCSchedModel::DefaultHighLatency,
gen/lib/Target/AMDGPU/AMDGPUGenSubtargetInfo.inc 433 static const llvm::MCSchedModel NoSchedModel = {
434 MCSchedModel::DefaultIssueWidth,
435 MCSchedModel::DefaultMicroOpBufferSize,
436 MCSchedModel::DefaultLoopMicroOpBufferSize,
437 MCSchedModel::DefaultLoadLatency,
438 MCSchedModel::DefaultHighLatency,
439 MCSchedModel::DefaultMispredictPenalty,
463 static const llvm::MCSchedModel SIQuarterSpeedModel = {
466 MCSchedModel::DefaultLoopMicroOpBufferSize,
467 MCSchedModel::DefaultLoadLatency,
468 MCSchedModel::DefaultHighLatency,
497 static const llvm::MCSchedModel GFX10SpeedModel = {
500 MCSchedModel::DefaultLoopMicroOpBufferSize,
501 MCSchedModel::DefaultLoadLatency,
502 MCSchedModel::DefaultHighLatency,
530 static const llvm::MCSchedModel SIFullSpeedModel = {
533 MCSchedModel::DefaultLoopMicroOpBufferSize,
534 MCSchedModel::DefaultLoadLatency,
535 MCSchedModel::DefaultHighLatency,
gen/lib/Target/AMDGPU/R600GenSubtargetInfo.inc 160 static const llvm::MCSchedModel NoSchedModel = {
161 MCSchedModel::DefaultIssueWidth,
162 MCSchedModel::DefaultMicroOpBufferSize,
163 MCSchedModel::DefaultLoopMicroOpBufferSize,
164 MCSchedModel::DefaultLoadLatency,
165 MCSchedModel::DefaultHighLatency,
166 MCSchedModel::DefaultMispredictPenalty,
175 static const llvm::MCSchedModel R600_VLIW5_ItinModel = {
176 MCSchedModel::DefaultIssueWidth,
177 MCSchedModel::DefaultMicroOpBufferSize,
178 MCSchedModel::DefaultLoopMicroOpBufferSize,
179 MCSchedModel::DefaultLoadLatency,
180 MCSchedModel::DefaultHighLatency,
181 MCSchedModel::DefaultMispredictPenalty,
190 static const llvm::MCSchedModel R600_VLIW4_ItinModel = {
191 MCSchedModel::DefaultIssueWidth,
192 MCSchedModel::DefaultMicroOpBufferSize,
193 MCSchedModel::DefaultLoopMicroOpBufferSize,
194 MCSchedModel::DefaultLoadLatency,
195 MCSchedModel::DefaultHighLatency,
196 MCSchedModel::DefaultMispredictPenalty,
gen/lib/Target/ARC/ARCGenSubtargetInfo.inc 53 static const llvm::MCSchedModel NoSchedModel = {
54 MCSchedModel::DefaultIssueWidth,
55 MCSchedModel::DefaultMicroOpBufferSize,
56 MCSchedModel::DefaultLoopMicroOpBufferSize,
57 MCSchedModel::DefaultLoadLatency,
58 MCSchedModel::DefaultHighLatency,
59 MCSchedModel::DefaultMispredictPenalty,
gen/lib/Target/ARM/ARMGenSubtargetInfo.inc18005 static const llvm::MCSchedModel NoSchedModel = {
18006 MCSchedModel::DefaultIssueWidth,
18007 MCSchedModel::DefaultMicroOpBufferSize,
18008 MCSchedModel::DefaultLoopMicroOpBufferSize,
18009 MCSchedModel::DefaultLoadLatency,
18010 MCSchedModel::DefaultHighLatency,
18011 MCSchedModel::DefaultMispredictPenalty,
18020 static const llvm::MCSchedModel ARMV6ItinerariesModel = {
18021 MCSchedModel::DefaultIssueWidth,
18022 MCSchedModel::DefaultMicroOpBufferSize,
18023 MCSchedModel::DefaultLoopMicroOpBufferSize,
18024 MCSchedModel::DefaultLoadLatency,
18025 MCSchedModel::DefaultHighLatency,
18026 MCSchedModel::DefaultMispredictPenalty,
18050 static const llvm::MCSchedModel CortexA9Model = {
18053 MCSchedModel::DefaultLoopMicroOpBufferSize,
18055 MCSchedModel::DefaultHighLatency,
18068 static const llvm::MCSchedModel CortexA8Model = {
18070 MCSchedModel::DefaultMicroOpBufferSize,
18071 MCSchedModel::DefaultLoopMicroOpBufferSize,
18073 MCSchedModel::DefaultHighLatency,
18101 static const llvm::MCSchedModel CortexA57Model = {
18106 MCSchedModel::DefaultHighLatency,
18129 static const llvm::MCSchedModel CortexM4Model = {
18132 MCSchedModel::DefaultLoopMicroOpBufferSize,
18134 MCSchedModel::DefaultHighLatency,
18163 static const llvm::MCSchedModel CortexR52Model = {
18166 MCSchedModel::DefaultLoopMicroOpBufferSize,
18168 MCSchedModel::DefaultHighLatency,
18195 static const llvm::MCSchedModel SwiftModel = {
18198 MCSchedModel::DefaultLoopMicroOpBufferSize,
18200 MCSchedModel::DefaultHighLatency,
gen/lib/Target/AVR/AVRGenSubtargetInfo.inc 145 static const llvm::MCSchedModel NoSchedModel = {
146 MCSchedModel::DefaultIssueWidth,
147 MCSchedModel::DefaultMicroOpBufferSize,
148 MCSchedModel::DefaultLoopMicroOpBufferSize,
149 MCSchedModel::DefaultLoadLatency,
150 MCSchedModel::DefaultHighLatency,
151 MCSchedModel::DefaultMispredictPenalty,
gen/lib/Target/BPF/BPFGenSubtargetInfo.inc 67 static const llvm::MCSchedModel NoSchedModel = {
68 MCSchedModel::DefaultIssueWidth,
69 MCSchedModel::DefaultMicroOpBufferSize,
70 MCSchedModel::DefaultLoopMicroOpBufferSize,
71 MCSchedModel::DefaultLoadLatency,
72 MCSchedModel::DefaultHighLatency,
73 MCSchedModel::DefaultMispredictPenalty,
gen/lib/Target/Hexagon/HexagonGenSubtargetInfo.inc 4472 static const llvm::MCSchedModel NoSchedModel = {
4473 MCSchedModel::DefaultIssueWidth,
4474 MCSchedModel::DefaultMicroOpBufferSize,
4475 MCSchedModel::DefaultLoopMicroOpBufferSize,
4476 MCSchedModel::DefaultLoadLatency,
4477 MCSchedModel::DefaultHighLatency,
4478 MCSchedModel::DefaultMispredictPenalty,
4487 static const llvm::MCSchedModel HexagonModelV60 = {
4489 MCSchedModel::DefaultMicroOpBufferSize,
4490 MCSchedModel::DefaultLoopMicroOpBufferSize,
4492 MCSchedModel::DefaultHighLatency,
4493 MCSchedModel::DefaultMispredictPenalty,
4502 static const llvm::MCSchedModel HexagonModelV5 = {
4504 MCSchedModel::DefaultMicroOpBufferSize,
4505 MCSchedModel::DefaultLoopMicroOpBufferSize,
4507 MCSchedModel::DefaultHighLatency,
4508 MCSchedModel::DefaultMispredictPenalty,
4517 static const llvm::MCSchedModel HexagonModelV55 = {
4519 MCSchedModel::DefaultMicroOpBufferSize,
4520 MCSchedModel::DefaultLoopMicroOpBufferSize,
4522 MCSchedModel::DefaultHighLatency,
4523 MCSchedModel::DefaultMispredictPenalty,
4532 static const llvm::MCSchedModel HexagonModelV62 = {
4534 MCSchedModel::DefaultMicroOpBufferSize,
4535 MCSchedModel::DefaultLoopMicroOpBufferSize,
4537 MCSchedModel::DefaultHighLatency,
4538 MCSchedModel::DefaultMispredictPenalty,
4547 static const llvm::MCSchedModel HexagonModelV65 = {
4549 MCSchedModel::DefaultMicroOpBufferSize,
4550 MCSchedModel::DefaultLoopMicroOpBufferSize,
4552 MCSchedModel::DefaultHighLatency,
4553 MCSchedModel::DefaultMispredictPenalty,
4562 static const llvm::MCSchedModel HexagonModelV66 = {
4564 MCSchedModel::DefaultMicroOpBufferSize,
4565 MCSchedModel::DefaultLoopMicroOpBufferSize,
4567 MCSchedModel::DefaultHighLatency,
4568 MCSchedModel::DefaultMispredictPenalty,
gen/lib/Target/Lanai/LanaiGenSubtargetInfo.inc 104 static const llvm::MCSchedModel NoSchedModel = {
105 MCSchedModel::DefaultIssueWidth,
106 MCSchedModel::DefaultMicroOpBufferSize,
107 MCSchedModel::DefaultLoopMicroOpBufferSize,
108 MCSchedModel::DefaultLoadLatency,
109 MCSchedModel::DefaultHighLatency,
110 MCSchedModel::DefaultMispredictPenalty,
130 static const llvm::MCSchedModel LanaiSchedModel = {
135 MCSchedModel::DefaultHighLatency,
gen/lib/Target/MSP430/MSP430GenSubtargetInfo.inc 69 static const llvm::MCSchedModel NoSchedModel = {
70 MCSchedModel::DefaultIssueWidth,
71 MCSchedModel::DefaultMicroOpBufferSize,
72 MCSchedModel::DefaultLoopMicroOpBufferSize,
73 MCSchedModel::DefaultLoadLatency,
74 MCSchedModel::DefaultHighLatency,
75 MCSchedModel::DefaultMispredictPenalty,
gen/lib/Target/Mips/MipsGenSubtargetInfo.inc 3624 static const llvm::MCSchedModel NoSchedModel = {
3625 MCSchedModel::DefaultIssueWidth,
3626 MCSchedModel::DefaultMicroOpBufferSize,
3627 MCSchedModel::DefaultLoopMicroOpBufferSize,
3628 MCSchedModel::DefaultLoadLatency,
3629 MCSchedModel::DefaultHighLatency,
3630 MCSchedModel::DefaultMispredictPenalty,
3668 static const llvm::MCSchedModel MipsGenericModel = {
3671 MCSchedModel::DefaultLoopMicroOpBufferSize,
3709 static const llvm::MCSchedModel MipsP5600Model = {
3712 MCSchedModel::DefaultLoopMicroOpBufferSize,
3714 MCSchedModel::DefaultHighLatency,
gen/lib/Target/NVPTX/NVPTXGenSubtargetInfo.inc 111 static const llvm::MCSchedModel NoSchedModel = {
112 MCSchedModel::DefaultIssueWidth,
113 MCSchedModel::DefaultMicroOpBufferSize,
114 MCSchedModel::DefaultLoopMicroOpBufferSize,
115 MCSchedModel::DefaultLoadLatency,
116 MCSchedModel::DefaultHighLatency,
117 MCSchedModel::DefaultMispredictPenalty,
gen/lib/Target/PowerPC/PPCGenSubtargetInfo.inc 7798 static const llvm::MCSchedModel NoSchedModel = {
7799 MCSchedModel::DefaultIssueWidth,
7800 MCSchedModel::DefaultMicroOpBufferSize,
7801 MCSchedModel::DefaultLoopMicroOpBufferSize,
7802 MCSchedModel::DefaultLoadLatency,
7803 MCSchedModel::DefaultHighLatency,
7804 MCSchedModel::DefaultMispredictPenalty,
7813 static const llvm::MCSchedModel PPC440Model = {
7815 MCSchedModel::DefaultMicroOpBufferSize,
7816 MCSchedModel::DefaultLoopMicroOpBufferSize,
7818 MCSchedModel::DefaultHighLatency,
7819 MCSchedModel::DefaultMispredictPenalty,
7828 static const llvm::MCSchedModel G3ItinerariesModel = {
7829 MCSchedModel::DefaultIssueWidth,
7830 MCSchedModel::DefaultMicroOpBufferSize,
7831 MCSchedModel::DefaultLoopMicroOpBufferSize,
7832 MCSchedModel::DefaultLoadLatency,
7833 MCSchedModel::DefaultHighLatency,
7834 MCSchedModel::DefaultMispredictPenalty,
7843 static const llvm::MCSchedModel G4ItinerariesModel = {
7844 MCSchedModel::DefaultIssueWidth,
7845 MCSchedModel::DefaultMicroOpBufferSize,
7846 MCSchedModel::DefaultLoopMicroOpBufferSize,
7847 MCSchedModel::DefaultLoadLatency,
7848 MCSchedModel::DefaultHighLatency,
7849 MCSchedModel::DefaultMispredictPenalty,
7858 static const llvm::MCSchedModel G4PlusItinerariesModel = {
7859 MCSchedModel::DefaultIssueWidth,
7860 MCSchedModel::DefaultMicroOpBufferSize,
7861 MCSchedModel::DefaultLoopMicroOpBufferSize,
7862 MCSchedModel::DefaultLoadLatency,
7863 MCSchedModel::DefaultHighLatency,
7864 MCSchedModel::DefaultMispredictPenalty,
7873 static const llvm::MCSchedModel G5Model = {
7875 MCSchedModel::DefaultMicroOpBufferSize,
7876 MCSchedModel::DefaultLoopMicroOpBufferSize,
7878 MCSchedModel::DefaultHighLatency,
7888 static const llvm::MCSchedModel PPCA2Model = {
7890 MCSchedModel::DefaultMicroOpBufferSize,
7891 MCSchedModel::DefaultLoopMicroOpBufferSize,
7893 MCSchedModel::DefaultHighLatency,
7903 static const llvm::MCSchedModel PPCE500Model = {
7905 MCSchedModel::DefaultMicroOpBufferSize,
7906 MCSchedModel::DefaultLoopMicroOpBufferSize,
7908 MCSchedModel::DefaultHighLatency,
7909 MCSchedModel::DefaultMispredictPenalty,
7918 static const llvm::MCSchedModel PPCE500mcModel = {
7920 MCSchedModel::DefaultMicroOpBufferSize,
7921 MCSchedModel::DefaultLoopMicroOpBufferSize,
7923 MCSchedModel::DefaultHighLatency,
7924 MCSchedModel::DefaultMispredictPenalty,
7933 static const llvm::MCSchedModel PPCE5500Model = {
7935 MCSchedModel::DefaultMicroOpBufferSize,
7936 MCSchedModel::DefaultLoopMicroOpBufferSize,
7938 MCSchedModel::DefaultHighLatency,
7939 MCSchedModel::DefaultMispredictPenalty,
7948 static const llvm::MCSchedModel P8Model = {
7950 MCSchedModel::DefaultMicroOpBufferSize,
7953 MCSchedModel::DefaultHighLatency,
7963 static const llvm::MCSchedModel P7Model = {
7965 MCSchedModel::DefaultMicroOpBufferSize,
7968 MCSchedModel::DefaultHighLatency,
8011 static const llvm::MCSchedModel P9Model = {
8016 MCSchedModel::DefaultHighLatency,
gen/lib/Target/RISCV/RISCVGenSubtargetInfo.inc 141 static const llvm::MCSchedModel NoSchedModel = {
142 MCSchedModel::DefaultIssueWidth,
143 MCSchedModel::DefaultMicroOpBufferSize,
144 MCSchedModel::DefaultLoopMicroOpBufferSize,
145 MCSchedModel::DefaultLoadLatency,
146 MCSchedModel::DefaultHighLatency,
147 MCSchedModel::DefaultMispredictPenalty,
gen/lib/Target/Sparc/SparcGenSubtargetInfo.inc 341 static const llvm::MCSchedModel NoSchedModel = {
342 MCSchedModel::DefaultIssueWidth,
343 MCSchedModel::DefaultMicroOpBufferSize,
344 MCSchedModel::DefaultLoopMicroOpBufferSize,
345 MCSchedModel::DefaultLoadLatency,
346 MCSchedModel::DefaultHighLatency,
347 MCSchedModel::DefaultMispredictPenalty,
356 static const llvm::MCSchedModel LEON2ItinerariesModel = {
357 MCSchedModel::DefaultIssueWidth,
358 MCSchedModel::DefaultMicroOpBufferSize,
359 MCSchedModel::DefaultLoopMicroOpBufferSize,
360 MCSchedModel::DefaultLoadLatency,
361 MCSchedModel::DefaultHighLatency,
362 MCSchedModel::DefaultMispredictPenalty,
371 static const llvm::MCSchedModel LEON3ItinerariesModel = {
372 MCSchedModel::DefaultIssueWidth,
373 MCSchedModel::DefaultMicroOpBufferSize,
374 MCSchedModel::DefaultLoopMicroOpBufferSize,
375 MCSchedModel::DefaultLoadLatency,
376 MCSchedModel::DefaultHighLatency,
377 MCSchedModel::DefaultMispredictPenalty,
386 static const llvm::MCSchedModel LEON4ItinerariesModel = {
387 MCSchedModel::DefaultIssueWidth,
388 MCSchedModel::DefaultMicroOpBufferSize,
389 MCSchedModel::DefaultLoopMicroOpBufferSize,
390 MCSchedModel::DefaultLoadLatency,
391 MCSchedModel::DefaultHighLatency,
392 MCSchedModel::DefaultMispredictPenalty,
gen/lib/Target/SystemZ/SystemZGenSubtargetInfo.inc 4875 static const llvm::MCSchedModel NoSchedModel = {
4876 MCSchedModel::DefaultIssueWidth,
4877 MCSchedModel::DefaultMicroOpBufferSize,
4878 MCSchedModel::DefaultLoopMicroOpBufferSize,
4879 MCSchedModel::DefaultLoadLatency,
4880 MCSchedModel::DefaultHighLatency,
4881 MCSchedModel::DefaultMispredictPenalty,
4905 static const llvm::MCSchedModel ZEC12Model = {
4908 MCSchedModel::DefaultLoopMicroOpBufferSize,
4910 MCSchedModel::DefaultHighLatency,
4939 static const llvm::MCSchedModel Z13Model = {
4942 MCSchedModel::DefaultLoopMicroOpBufferSize,
4944 MCSchedModel::DefaultHighLatency,
4973 static const llvm::MCSchedModel Z14Model = {
4976 MCSchedModel::DefaultLoopMicroOpBufferSize,
4978 MCSchedModel::DefaultHighLatency,
5007 static const llvm::MCSchedModel Z15Model = {
5010 MCSchedModel::DefaultLoopMicroOpBufferSize,
5012 MCSchedModel::DefaultHighLatency,
5039 static const llvm::MCSchedModel Z196Model = {
5042 MCSchedModel::DefaultLoopMicroOpBufferSize,
5044 MCSchedModel::DefaultHighLatency,
gen/lib/Target/WebAssembly/WebAssemblyGenSubtargetInfo.inc 81 static const llvm::MCSchedModel NoSchedModel = {
82 MCSchedModel::DefaultIssueWidth,
83 MCSchedModel::DefaultMicroOpBufferSize,
84 MCSchedModel::DefaultLoopMicroOpBufferSize,
85 MCSchedModel::DefaultLoadLatency,
86 MCSchedModel::DefaultHighLatency,
87 MCSchedModel::DefaultMispredictPenalty,
gen/lib/Target/X86/X86GenSubtargetInfo.inc19175 static const llvm::MCSchedModel NoSchedModel = {
19176 MCSchedModel::DefaultIssueWidth,
19177 MCSchedModel::DefaultMicroOpBufferSize,
19178 MCSchedModel::DefaultLoopMicroOpBufferSize,
19179 MCSchedModel::DefaultLoadLatency,
19180 MCSchedModel::DefaultHighLatency,
19181 MCSchedModel::DefaultMispredictPenalty,
19190 static const llvm::MCSchedModel GenericModel = {
19193 MCSchedModel::DefaultLoopMicroOpBufferSize,
19196 MCSchedModel::DefaultMispredictPenalty,
19218 static const llvm::MCSchedModel AtomModel = {
19224 MCSchedModel::DefaultMispredictPenalty,
19301 static const llvm::MCSchedModel BdVer2Model = {
19304 MCSchedModel::DefaultLoopMicroOpBufferSize,
19364 static const llvm::MCSchedModel BroadwellModel = {
19369 MCSchedModel::DefaultHighLatency,
19442 static const llvm::MCSchedModel BtVer2Model = {
19445 MCSchedModel::DefaultLoopMicroOpBufferSize,
19505 static const llvm::MCSchedModel SkylakeServerModel = {
19510 MCSchedModel::DefaultHighLatency,
19549 static const llvm::MCSchedModel SandyBridgeModel = {
19554 MCSchedModel::DefaultHighLatency,
19612 static const llvm::MCSchedModel HaswellModel = {
19617 MCSchedModel::DefaultHighLatency,
19651 static const llvm::MCSchedModel SLMModel = {
19656 MCSchedModel::DefaultHighLatency,
19669 static const llvm::MCSchedModel GenericPostRAModel = {
19672 MCSchedModel::DefaultLoopMicroOpBufferSize,
19675 MCSchedModel::DefaultMispredictPenalty,
19729 static const llvm::MCSchedModel SkylakeClientModel = {
19734 MCSchedModel::DefaultHighLatency,
19817 static const llvm::MCSchedModel Znver1Model = {
19820 MCSchedModel::DefaultLoopMicroOpBufferSize,
gen/lib/Target/XCore/XCoreGenSubtargetInfo.inc 53 static const llvm::MCSchedModel NoSchedModel = {
54 MCSchedModel::DefaultIssueWidth,
55 MCSchedModel::DefaultMicroOpBufferSize,
56 MCSchedModel::DefaultLoopMicroOpBufferSize,
57 MCSchedModel::DefaultLoadLatency,
58 MCSchedModel::DefaultHighLatency,
59 MCSchedModel::DefaultMispredictPenalty,
include/llvm/CodeGen/MachinePipeliner.h 430 const MCSchedModel &SM;
451 void initProcResourceVectors(const MCSchedModel &SM,
include/llvm/CodeGen/TargetInstrInfo.h 1454 unsigned defaultDefLatency(const MCSchedModel &SchedModel,
include/llvm/CodeGen/TargetSchedule.h 34 MCSchedModel SchedModel;
46 TargetSchedModel() : SchedModel(MCSchedModel::GetDefaultSchedModel()) {}
71 const MCSchedModel *getMCSchedModel() const { return &SchedModel; }
include/llvm/MC/MCInstrItineraries.h 108 MCSchedModel SchedModel =
109 MCSchedModel::GetDefaultSchedModel(); ///< Basic machine properties.
117 InstrItineraryData(const MCSchedModel &SM, const InstrStage *S,
include/llvm/MC/MCSchedule.h 379 static const MCSchedModel &GetDefaultSchedModel() { return Default; }
380 static const MCSchedModel Default;
include/llvm/MC/MCSubtargetInfo.h 57 const MCSchedModel *SchedModel;
84 const MCSchedModel *CPUSchedModel;
153 const MCSchedModel &getSchedModelForCPU(StringRef CPU) const;
156 const MCSchedModel &getSchedModel() const { return *CPUSchedModel; }
include/llvm/MCA/HardwareUnits/LSUnit.h 199 LSUnitBase(const MCSchedModel &SM, unsigned LoadQueueSize,
419 LSUnit(const MCSchedModel &SM)
421 LSUnit(const MCSchedModel &SM, unsigned LQ, unsigned SQ)
423 LSUnit(const MCSchedModel &SM, unsigned LQ, unsigned SQ, bool AssumeNoAlias)
include/llvm/MCA/HardwareUnits/RegisterFile.h 185 void initialize(const MCSchedModel &SM, unsigned NumRegs);
188 RegisterFile(const MCSchedModel &SM, const MCRegisterInfo &mri,
include/llvm/MCA/HardwareUnits/ResourceManager.h 387 ResourceManager(const MCSchedModel &SM);
include/llvm/MCA/HardwareUnits/RetireControlUnit.h 80 RetireControlUnit(const MCSchedModel &SM);
include/llvm/MCA/HardwareUnits/Scheduler.h 157 Scheduler(const MCSchedModel &Model, LSUnitBase &Lsu)
160 Scheduler(const MCSchedModel &Model, LSUnitBase &Lsu,
include/llvm/MCA/Stages/InstructionTables.h 29 const MCSchedModel &SM;
34 InstructionTables(const MCSchedModel &Model)
include/llvm/MCA/Support.h 94 void computeProcResourceMasks(const MCSchedModel &SM,
108 double computeBlockRThroughput(const MCSchedModel &SM, unsigned DispatchWidth,
lib/CodeGen/EarlyIfConversion.cpp 703 MCSchedModel SchedModel;
lib/CodeGen/MachineCombiner.cpp 64 MCSchedModel SchedModel;
lib/CodeGen/MachinePipeliner.cpp 2891 const MCSchedModel &SM, SmallVectorImpl<uint64_t> &Masks) {
lib/CodeGen/TargetInstrInfo.cpp 1085 unsigned TargetInstrInfo::defaultDefLatency(const MCSchedModel &SchedModel,
lib/CodeGen/TargetSchedule.cpp 257 return capLatency(MCSchedModel::computeInstrLatency(*STI, SCDesc));
328 return MCSchedModel::getReciprocalThroughput(SchedClass,
333 return MCSchedModel::getReciprocalThroughput(*STI, *resolveSchedClass(MI));
342 return MCSchedModel::getReciprocalThroughput(SchedClass,
347 return MCSchedModel::getReciprocalThroughput(*STI, SCDesc);
lib/MC/MCDisassembler/Disassembler.cpp 197 const MCSchedModel SCModel = STI->getSchedModel();
lib/MC/MCSchedule.cpp 22 static_assert(std::is_pod<MCSchedModel>::value,
24 const MCSchedModel MCSchedModel::Default = {DefaultIssueWidth,
62 return MCSchedModel::computeInstrLatency(STI, SCDesc);
82 return MCSchedModel::computeInstrLatency(STI, *SCDesc);
91 const MCSchedModel &SM = STI.getSchedModel();
128 return MCSchedModel::getReciprocalThroughput(STI, *SCDesc);
lib/MC/MCSubtargetInfo.cpp 202 CPUSchedModel = &MCSchedModel::GetDefaultSchedModel();
290 const MCSchedModel &MCSubtargetInfo::getSchedModelForCPU(StringRef CPU) const {
302 return MCSchedModel::GetDefaultSchedModel();
310 const MCSchedModel &SchedModel = getSchedModelForCPU(CPU);
lib/MCA/Context.cpp 32 const MCSchedModel &SM = STI.getSchedModel();
lib/MCA/HardwareUnits/LSUnit.cpp 24 LSUnitBase::LSUnitBase(const MCSchedModel &SM, unsigned LQ, unsigned SQ,
lib/MCA/HardwareUnits/RegisterFile.cpp 25 RegisterFile::RegisterFile(const MCSchedModel &SM, const MCRegisterInfo &mri,
33 void RegisterFile::initialize(const MCSchedModel &SM, unsigned NumRegs) {
417 const MCSchedModel &SM = STI.getSchedModel();
lib/MCA/HardwareUnits/ResourceManager.cpp 111 ResourceManager::ResourceManager(const MCSchedModel &SM)
lib/MCA/HardwareUnits/RetireControlUnit.cpp 22 RetireControlUnit::RetireControlUnit(const MCSchedModel &SM)
lib/MCA/InstrBuilder.cpp 33 const MCSchedModel &SM = STI.getSchedModel();
42 const MCSchedModel &SM = STI.getSchedModel();
213 int Latency = MCSchedModel::computeInstrLatency(STI, SCDesc);
250 const MCSchedModel &SM = STI.getSchedModel();
516 const MCSchedModel &SM = STI.getSchedModel();
lib/MCA/Support.cpp 39 void computeProcResourceMasks(const MCSchedModel &SM,
82 double computeBlockRThroughput(const MCSchedModel &SM, unsigned DispatchWidth,
lib/Target/AArch64/AArch64ConditionalCompares.cpp 765 MCSchedModel SchedModel;
lib/Target/ARM/ARMSubtarget.h 489 MCSchedModel SchedModel;
tools/llvm-exegesis/lib/Analysis.cpp 380 const auto &SM = SubtargetInfo_->getSchedModel();
401 MCSchedModel::getReciprocalThroughput(*SubtargetInfo_, *RSC.SCDesc));
tools/llvm-exegesis/lib/SchedClassResolution.cpp 53 const auto &SM = STI.getSchedModel();
175 computeIdealizedProcResPressure(const MCSchedModel &SM,
222 const auto &SM = STI.getSchedModel();
249 const auto &SchedModel = STI.getSchedModel();
309 MCSchedModel::getReciprocalThroughput(STI, *SCDesc);
tools/llvm-exegesis/lib/SchedClassResolution.h 35 computeIdealizedProcResPressure(const MCSchedModel &SM,
tools/llvm-mca/Views/BottleneckAnalysis.cpp 26 PressureTracker::PressureTracker(const MCSchedModel &Model)
620 const MCSchedModel &SM = STI.getSchedModel();
tools/llvm-mca/Views/BottleneckAnalysis.h 95 const MCSchedModel &SM;
137 PressureTracker(const MCSchedModel &Model);
tools/llvm-mca/Views/InstructionInfoView.cpp 23 const MCSchedModel &SM = STI.getSchedModel();
53 unsigned Latency = MCSchedModel::computeInstrLatency(STI, SCDesc);
55 Latency += MCSchedModel::getForwardingDelayCycles(
58 MCSchedModel::getReciprocalThroughput(STI, SCDesc);
tools/llvm-mca/Views/RegisterFileStatistics.cpp 22 const MCSchedModel &SM = STI.getSchedModel();
tools/llvm-mca/Views/ResourcePressureView.cpp 27 const MCSchedModel &SM = STI.getSchedModel();
68 const MCSchedModel &SM) {
108 const MCSchedModel &SM = STI.getSchedModel();
tools/llvm-mca/Views/RetireControlUnitStatistics.cpp 20 RetireControlUnitStatistics::RetireControlUnitStatistics(const MCSchedModel &SM)
tools/llvm-mca/Views/RetireControlUnitStatistics.h 50 RetireControlUnitStatistics(const MCSchedModel &SM);
tools/llvm-mca/Views/SchedulerStatistics.h 48 const llvm::MCSchedModel &SM;
tools/llvm-mca/Views/SummaryView.cpp 25 SummaryView::SummaryView(const MCSchedModel &Model, ArrayRef<MCInst> S,
tools/llvm-mca/Views/SummaryView.h 41 const llvm::MCSchedModel &SM;
69 SummaryView(const llvm::MCSchedModel &Model, llvm::ArrayRef<llvm::MCInst> S,
tools/llvm-mca/Views/TimelineView.cpp 46 const MCSchedModel &SM = STI.getSchedModel();
tools/llvm-mca/llvm-mca.cpp 427 const MCSchedModel &SM = STI->getSchedModel();
unittests/tools/llvm-exegesis/PowerPC/AnalysisTest.cpp 39 const auto &SM = STI->getSchedModel();
unittests/tools/llvm-exegesis/X86/SchedClassResolutionTest.cpp 31 const auto &SM = STI.getSchedModel();
usr/include/c++/7.4.0/bits/move.h 72 constexpr _Tp&&
83 constexpr _Tp&&
usr/include/c++/7.4.0/bits/unique_ptr.h 824 make_unique(_Args&&... __args)