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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenRegisterInfo.inc 9121 for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any(); ++Ops) {
9135 for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any(); ++Ops) {
gen/lib/Target/AMDGPU/AMDGPUGenRegisterInfo.inc25771 for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any(); ++Ops) {
25785 for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any(); ++Ops) {
gen/lib/Target/AMDGPU/R600GenRegisterInfo.inc11483 for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any(); ++Ops) {
11497 for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any(); ++Ops) {
gen/lib/Target/ARM/ARMGenRegisterInfo.inc 8541 for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any(); ++Ops) {
8555 for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any(); ++Ops) {
gen/lib/Target/AVR/AVRGenRegisterInfo.inc 1461 for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any(); ++Ops) {
1475 for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any(); ++Ops) {
gen/lib/Target/BPF/BPFGenRegisterInfo.inc 552 for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any(); ++Ops) {
566 for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any(); ++Ops) {
gen/lib/Target/Hexagon/HexagonGenRegisterInfo.inc 3219 for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any(); ++Ops) {
3233 for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any(); ++Ops) {
gen/lib/Target/Lanai/LanaiGenRegisterInfo.inc 772 for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any(); ++Ops) {
786 for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any(); ++Ops) {
gen/lib/Target/MSP430/MSP430GenRegisterInfo.inc 485 for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any(); ++Ops) {
499 for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any(); ++Ops) {
gen/lib/Target/Mips/MipsGenRegisterInfo.inc 6200 for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any(); ++Ops) {
6214 for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any(); ++Ops) {
gen/lib/Target/PowerPC/PPCGenRegisterInfo.inc 5198 for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any(); ++Ops) {
5212 for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any(); ++Ops) {
gen/lib/Target/RISCV/RISCVGenRegisterInfo.inc 1626 for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any(); ++Ops) {
1640 for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any(); ++Ops) {
gen/lib/Target/Sparc/SparcGenRegisterInfo.inc 2525 for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any(); ++Ops) {
2539 for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any(); ++Ops) {
gen/lib/Target/SystemZ/SystemZGenRegisterInfo.inc 2612 for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any(); ++Ops) {
2626 for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any(); ++Ops) {
gen/lib/Target/X86/X86GenRegisterInfo.inc 8147 for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any(); ++Ops) {
8161 for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any(); ++Ops) {
include/llvm/CodeGen/LiveRegUnits.h 97 if (UnitMask.none() || (UnitMask & Mask).any())
include/llvm/CodeGen/RegisterPressure.h 336 if (P.LaneMask.any())
lib/CodeGen/DetectDeadLanes.cpp 482 if (UsedLanes.any())
lib/CodeGen/LiveInterval.cpp 954 if (ToApply.any()) {
973 assert((VRegMask & LaneMask).any());
982 if ((UndefMask & LaneMask).any()) {
lib/CodeGen/LiveIntervals.cpp 373 if ((SR.LaneMask & M).any()) {
429 assert(LaneMask.any() &&
784 if ((UseMask & ~DefinedLanesMask).any())
1028 if (LaneMask.any())
1408 if (SubReg != 0 && LaneMask.any()
lib/CodeGen/LivePhysRegs.cpp 162 assert(Mask.any() && "Invalid livein mask");
169 if ((Mask & TRI->getSubRegIndexLaneMask(SI)).any())
lib/CodeGen/LiveRangeEdit.cpp 253 if ((S.LaneMask & LaneMask).any() && S.Query(Idx).isKill())
lib/CodeGen/LiveRegMatrix.cpp 87 if ((S.LaneMask & Mask).any()) {
lib/CodeGen/MachineBasicBlock.cpp 469 return I != livein_end() && (I->LaneMask & LaneMask).any();
lib/CodeGen/MachineScheduler.cpp 1108 bool Decrement = P.LaneMask.any();
1124 assert(P.LaneMask.any());
lib/CodeGen/MachineVerifier.cpp 530 if (LaneMask.any())
1889 if (LaneMask.any())
1904 if (LaneMask.any())
1913 if (LaneMask.any())
1932 if (LaneMask.any())
2426 if (LaneMask.any() &&
2572 if (LaneMask.any() && (LaneMask & SLM).none())
2591 if (!MRI->shouldTrackSubRegLiveness(Reg) || LaneMask.any() ||
2614 if (LaneMask.any()) {
2688 if ((Mask & SR.LaneMask).any()) {
2692 if ((SR.LaneMask & ~MaxMask).any()) {
lib/CodeGen/RegisterCoalescer.cpp 958 if ((SB.LaneMask & MaskA).any())
1394 if (MaxMask.any()) {
1933 if (ShrinkMask.any()) {
2274 bool isAnalyzed() const { return WriteLanes.any(); }
2580 if ((V.ValidLanes & OtherV.ValidLanes).any())
2750 (OtherV.WriteLanes & ~V.ValidLanes).any()) {
2819 } while (TaintedLanes.any());
2833 if ((Lanes & TRI->getSubRegIndexLaneMask(S)).any())
3337 assert(Mask.any());
lib/CodeGen/RegisterPressure.cpp 54 if (PrevMask.any() || NewMask.none())
68 if (NewMask.any() || PrevMask.none())
158 if (PreviousMask.any() || NewMask.none())
384 assert(Pair.LaneMask.any());
410 assert(Pair.LaneMask.any());
715 assert(Pair.LaneMask.any());
779 if (LiveOut.any()) {
804 assert(Use.LaneMask.any());
834 if (LiveOut.any())
917 if (LiveIn.any()) {
925 if (LastUseMask.any()) {
lib/CodeGen/ScheduleDAGInstrs.cpp 436 if ((LaneMask & DefLaneMask).any()) {
448 if (LaneMask.any()) {
494 if (NonOverlapMask.any())
498 if (LaneMask.any())
lib/CodeGen/SplitKit.cpp 451 if ((S.LaneMask & LM).any())
574 if ((SubRegMask & ~LaneMask).any())
595 while (LanesLeft.any()) {
lib/CodeGen/VirtRegMap.cpp 368 if ((SR.LaneMask & UseMask).any() && SR.liveAt(BaseIndex))
lib/Target/AMDGPU/GCNRegPressure.cpp 130 assert(NewMask.any());
284 if (LiveMask.any())
503 if (It != LiveRegs.end() && It->second.any())
lib/Target/AMDGPU/SIFormMemoryClauses.cpp 175 if ((SubRegMask & ~LaneMask).any() || (SubRegMask & LaneMask).none())
193 if ((SubRegMask & ~LaneMask).any() || (SubRegMask & LaneMask).none())
234 if ((Conflict->second.second & Mask).any())
lib/Target/AMDGPU/SIShrinkInstructions.cpp 403 if (Overlap.any())
lib/Target/Hexagon/HexagonBlockRanges.cpp 240 if (I.LaneMask.all() || (I.LaneMask.any() && !S.isValid())) {
246 if ((I.LaneMask & TRI.getSubRegIndexLaneMask(SI)).any())
lib/Target/Hexagon/HexagonExpandCondsets.cpp 380 return { A.any(), A == SLM };
lib/Target/Hexagon/RDFGraph.cpp 983 return M.any() ? RegisterRef(AR.Reg, M) : RegisterRef();
lib/Target/Hexagon/RDFGraph.h 439 assert(LM.any());
444 assert(LM.any());
lib/Target/Hexagon/RDFLiveness.cpp 867 if ((M & I.LaneMask).any())
lib/Target/Hexagon/RDFRegisters.cpp 63 if (P.second.any()) {
141 if (PA.second.any() && (PA.second & RA.Mask).none()) {
147 if (PB.second.any() && (PB.second & RB.Mask).none()) {
246 if (P.second.none() || (P.second & RR.Mask).any())
261 if (P.second.none() || (P.second & RR.Mask).any())
276 if (P.second.none() || (P.second & RR.Mask).any())
lib/Target/Hexagon/RDFRegisters.h 80 return Reg != 0 && Mask.any();
utils/TableGen/CodeGenRegisters.cpp 107 if (LaneMask.any())
117 assert(M.any() && "Missing lane mask, sub-register cycle?");
1499 if (SrcMask.any()) {