reference, declarationdefinition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
    1
    2
    3
    4
    5
    6
    7
    8
    9
   10
   11
   12
   13
   14
   15
   16
   17
   18
   19
   20
   21
   22
   23
   24
   25
   26
   27
   28
   29
   30
   31
   32
   33
   34
   35
   36
   37
   38
   39
   40
   41
   42
   43
   44
   45
   46
   47
   48
   49
   50
   51
   52
   53
   54
   55
   56
   57
   58
   59
   60
   61
   62
   63
   64
   65
   66
   67
   68
   69
   70
   71
   72
   73
   74
   75
   76
   77
   78
   79
   80
   81
   82
   83
   84
   85
   86
   87
   88
   89
   90
   91
   92
   93
   94
   95
   96
   97
   98
   99
  100
  101
  102
  103
  104
  105
  106
  107
  108
  109
  110
  111
  112
  113
  114
  115
  116
  117
  118
  119
  120
  121
  122
  123
  124
  125
  126
  127
  128
  129
  130
  131
  132
  133
  134
  135
  136
  137
  138
  139
  140
  141
  142
  143
  144
  145
  146
  147
  148
  149
  150
  151
  152
  153
  154
  155
  156
  157
  158
  159
  160
  161
  162
  163
  164
  165
  166
  167
  168
  169
  170
  171
  172
  173
  174
  175
  176
  177
  178
  179
  180
  181
  182
  183
  184
  185
  186
  187
  188
  189
  190
  191
  192
  193
  194
  195
  196
  197
  198
  199
  200
  201
  202
  203
  204
  205
  206
  207
  208
  209
  210
  211
  212
  213
  214
  215
  216
  217
  218
  219
  220
  221
  222
  223
  224
  225
  226
  227
  228
  229
  230
  231
  232
  233
  234
  235
  236
  237
  238
  239
  240
  241
  242
  243
  244
  245
  246
  247
  248
  249
  250
  251
  252
  253
  254
  255
  256
  257
  258
  259
  260
  261
  262
  263
  264
  265
  266
  267
  268
  269
  270
  271
  272
  273
  274
  275
  276
  277
  278
  279
  280
  281
  282
  283
  284
  285
  286
  287
  288
  289
  290
  291
  292
  293
  294
  295
  296
  297
  298
  299
  300
  301
  302
  303
  304
  305
  306
  307
  308
  309
  310
  311
  312
  313
  314
  315
  316
  317
  318
  319
  320
  321
  322
  323
  324
  325
  326
  327
  328
  329
  330
  331
  332
  333
  334
  335
  336
  337
  338
  339
  340
  341
  342
  343
  344
  345
  346
  347
  348
  349
  350
  351
  352
  353
  354
  355
  356
  357
  358
  359
  360
  361
  362
  363
  364
  365
  366
  367
  368
  369
  370
  371
  372
  373
  374
  375
  376
  377
  378
  379
  380
  381
  382
  383
  384
  385
  386
  387
  388
  389
  390
  391
  392
  393
  394
  395
  396
  397
  398
  399
  400
  401
  402
  403
  404
  405
  406
  407
  408
  409
  410
  411
  412
  413
  414
  415
  416
  417
  418
  419
  420
  421
  422
  423
  424
  425
  426
  427
  428
  429
  430
  431
  432
  433
  434
  435
  436
  437
  438
  439
  440
  441
  442
  443
  444
  445
  446
  447
  448
  449
  450
  451
  452
  453
  454
  455
  456
  457
  458
  459
  460
  461
  462
  463
  464
  465
  466
  467
  468
  469
  470
  471
  472
  473
  474
  475
  476
  477
  478
  479
  480
  481
  482
  483
  484
  485
  486
  487
  488
  489
  490
  491
  492
  493
  494
  495
  496
  497
  498
  499
  500
  501
  502
  503
  504
  505
  506
  507
  508
  509
  510
  511
  512
  513
  514
  515
  516
  517
  518
  519
  520
  521
  522
  523
  524
  525
  526
  527
  528
  529
  530
  531
  532
  533
  534
  535
  536
  537
  538
  539
  540
  541
  542
  543
  544
  545
  546
  547
  548
  549
  550
  551
  552
  553
  554
  555
  556
  557
  558
  559
  560
  561
  562
  563
  564
  565
  566
  567
  568
  569
  570
  571
  572
  573
  574
  575
  576
  577
  578
  579
  580
  581
  582
  583
  584
  585
  586
  587
  588
  589
  590
  591
  592
  593
  594
  595
  596
  597
  598
  599
  600
  601
  602
  603
  604
  605
  606
  607
  608
  609
  610
  611
  612
  613
  614
  615
  616
  617
  618
  619
  620
  621
  622
  623
  624
  625
  626
  627
  628
  629
  630
  631
  632
  633
  634
  635
  636
  637
  638
  639
  640
  641
  642
  643
  644
  645
  646
  647
  648
  649
  650
  651
  652
  653
  654
  655
  656
  657
  658
  659
  660
  661
  662
  663
  664
  665
  666
  667
  668
  669
  670
  671
  672
  673
  674
  675
  676
  677
  678
  679
  680
  681
  682
  683
  684
  685
  686
  687
  688
  689
  690
  691
  692
  693
  694
  695
  696
  697
  698
  699
  700
  701
  702
  703
  704
  705
  706
  707
  708
  709
  710
  711
  712
  713
  714
  715
  716
  717
  718
  719
  720
  721
  722
  723
  724
  725
  726
  727
  728
  729
  730
  731
  732
  733
  734
  735
  736
  737
  738
  739
  740
  741
  742
  743
  744
  745
  746
  747
  748
  749
  750
  751
  752
  753
  754
  755
  756
  757
  758
  759
  760
  761
  762
  763
  764
  765
  766
  767
  768
  769
  770
  771
  772
  773
  774
  775
  776
  777
  778
  779
  780
  781
  782
  783
  784
  785
  786
  787
  788
  789
  790
  791
  792
  793
  794
  795
  796
  797
  798
  799
  800
  801
  802
  803
  804
  805
  806
  807
  808
  809
  810
  811
  812
  813
  814
  815
  816
  817
  818
  819
  820
  821
  822
  823
  824
  825
  826
  827
  828
  829
  830
  831
  832
  833
  834
  835
  836
  837
  838
  839
  840
  841
  842
  843
  844
  845
  846
  847
  848
  849
  850
  851
  852
  853
  854
  855
  856
  857
  858
  859
  860
  861
  862
  863
  864
  865
  866
  867
  868
  869
  870
  871
  872
  873
  874
  875
  876
  877
  878
  879
  880
  881
  882
  883
  884
  885
  886
  887
  888
  889
  890
  891
  892
  893
  894
  895
  896
  897
  898
  899
  900
  901
  902
  903
  904
  905
  906
  907
  908
  909
  910
  911
  912
  913
  914
  915
  916
  917
  918
  919
  920
  921
  922
  923
  924
  925
  926
  927
  928
  929
  930
  931
  932
  933
  934
  935
  936
  937
  938
  939
  940
  941
  942
  943
  944
  945
  946
  947
  948
  949
  950
  951
  952
  953
  954
  955
  956
  957
  958
  959
  960
  961
  962
  963
  964
  965
  966
  967
  968
  969
  970
  971
  972
  973
  974
  975
  976
  977
  978
  979
  980
  981
  982
  983
  984
  985
  986
  987
  988
  989
  990
  991
  992
  993
  994
  995
  996
  997
  998
  999
 1000
 1001
 1002
 1003
 1004
 1005
 1006
 1007
 1008
 1009
 1010
 1011
 1012
 1013
 1014
 1015
 1016
 1017
 1018
 1019
 1020
 1021
 1022
 1023
 1024
 1025
 1026
 1027
 1028
 1029
 1030
 1031
 1032
 1033
 1034
 1035
 1036
 1037
 1038
 1039
 1040
 1041
 1042
 1043
 1044
 1045
 1046
 1047
 1048
 1049
 1050
 1051
 1052
 1053
 1054
 1055
 1056
 1057
 1058
 1059
 1060
 1061
 1062
 1063
 1064
 1065
 1066
 1067
 1068
 1069
 1070
 1071
 1072
 1073
 1074
 1075
 1076
 1077
 1078
 1079
 1080
 1081
 1082
 1083
 1084
 1085
 1086
 1087
 1088
 1089
 1090
 1091
 1092
 1093
 1094
 1095
 1096
 1097
 1098
 1099
 1100
 1101
 1102
 1103
 1104
 1105
 1106
 1107
 1108
 1109
 1110
 1111
 1112
 1113
 1114
 1115
 1116
 1117
 1118
 1119
 1120
 1121
 1122
 1123
 1124
 1125
 1126
 1127
 1128
 1129
 1130
 1131
 1132
 1133
 1134
 1135
 1136
 1137
 1138
 1139
 1140
 1141
 1142
 1143
 1144
 1145
 1146
 1147
 1148
 1149
 1150
 1151
 1152
 1153
 1154
 1155
 1156
 1157
 1158
 1159
 1160
 1161
 1162
 1163
 1164
 1165
 1166
 1167
 1168
 1169
 1170
 1171
 1172
 1173
 1174
 1175
 1176
 1177
 1178
 1179
 1180
 1181
 1182
 1183
 1184
 1185
 1186
 1187
 1188
 1189
 1190
 1191
 1192
 1193
 1194
 1195
 1196
 1197
 1198
 1199
 1200
 1201
 1202
 1203
 1204
 1205
 1206
 1207
 1208
 1209
 1210
 1211
 1212
 1213
 1214
 1215
 1216
 1217
 1218
 1219
 1220
 1221
 1222
 1223
 1224
 1225
 1226
 1227
 1228
 1229
 1230
 1231
 1232
 1233
 1234
 1235
 1236
 1237
 1238
 1239
 1240
 1241
 1242
 1243
 1244
 1245
 1246
 1247
 1248
 1249
 1250
 1251
 1252
 1253
 1254
 1255
 1256
 1257
 1258
 1259
 1260
 1261
 1262
 1263
 1264
 1265
 1266
 1267
 1268
 1269
 1270
 1271
 1272
 1273
 1274
 1275
 1276
 1277
 1278
 1279
 1280
 1281
 1282
 1283
 1284
 1285
 1286
 1287
 1288
 1289
 1290
 1291
 1292
 1293
 1294
 1295
 1296
 1297
 1298
 1299
 1300
 1301
 1302
 1303
 1304
 1305
 1306
 1307
 1308
 1309
 1310
 1311
 1312
 1313
 1314
 1315
 1316
 1317
 1318
 1319
 1320
 1321
 1322
 1323
 1324
 1325
 1326
 1327
 1328
 1329
 1330
 1331
 1332
 1333
 1334
 1335
 1336
 1337
 1338
 1339
 1340
 1341
 1342
 1343
 1344
 1345
 1346
 1347
 1348
 1349
 1350
 1351
 1352
 1353
 1354
 1355
 1356
 1357
 1358
 1359
 1360
 1361
 1362
 1363
 1364
 1365
 1366
 1367
 1368
 1369
 1370
 1371
 1372
 1373
 1374
 1375
 1376
 1377
 1378
 1379
 1380
 1381
 1382
 1383
 1384
 1385
 1386
 1387
 1388
 1389
 1390
 1391
 1392
 1393
 1394
 1395
 1396
 1397
 1398
 1399
 1400
 1401
 1402
 1403
 1404
 1405
 1406
 1407
 1408
 1409
 1410
 1411
 1412
 1413
 1414
 1415
 1416
 1417
 1418
 1419
 1420
 1421
 1422
 1423
 1424
 1425
 1426
 1427
 1428
 1429
 1430
 1431
 1432
 1433
 1434
 1435
 1436
 1437
 1438
 1439
 1440
 1441
 1442
 1443
 1444
 1445
 1446
 1447
 1448
 1449
 1450
 1451
 1452
 1453
 1454
 1455
 1456
 1457
 1458
 1459
 1460
 1461
 1462
 1463
 1464
 1465
 1466
 1467
 1468
 1469
 1470
 1471
 1472
 1473
 1474
 1475
 1476
 1477
 1478
 1479
 1480
 1481
 1482
 1483
 1484
 1485
 1486
 1487
 1488
 1489
 1490
 1491
 1492
 1493
 1494
 1495
 1496
 1497
 1498
 1499
 1500
 1501
 1502
 1503
 1504
 1505
 1506
 1507
 1508
 1509
 1510
 1511
 1512
 1513
 1514
 1515
 1516
 1517
 1518
 1519
 1520
 1521
 1522
 1523
 1524
 1525
 1526
 1527
 1528
 1529
 1530
 1531
 1532
 1533
 1534
 1535
 1536
 1537
 1538
 1539
 1540
 1541
 1542
 1543
 1544
 1545
 1546
 1547
 1548
 1549
 1550
 1551
 1552
 1553
 1554
 1555
 1556
 1557
 1558
 1559
 1560
 1561
 1562
 1563
 1564
 1565
 1566
 1567
 1568
 1569
 1570
 1571
 1572
 1573
 1574
 1575
 1576
 1577
 1578
 1579
 1580
 1581
 1582
 1583
 1584
 1585
 1586
 1587
 1588
 1589
 1590
 1591
 1592
 1593
 1594
 1595
 1596
 1597
 1598
 1599
 1600
 1601
 1602
 1603
 1604
 1605
 1606
 1607
 1608
 1609
 1610
 1611
 1612
 1613
 1614
 1615
 1616
 1617
 1618
 1619
 1620
 1621
 1622
 1623
 1624
 1625
 1626
 1627
 1628
 1629
 1630
 1631
 1632
 1633
 1634
 1635
 1636
 1637
 1638
 1639
 1640
 1641
 1642
 1643
 1644
 1645
 1646
 1647
 1648
 1649
 1650
 1651
 1652
 1653
 1654
 1655
 1656
 1657
 1658
 1659
 1660
 1661
 1662
 1663
 1664
 1665
 1666
 1667
 1668
 1669
 1670
 1671
 1672
 1673
 1674
 1675
 1676
 1677
 1678
 1679
 1680
 1681
 1682
 1683
 1684
 1685
 1686
 1687
 1688
 1689
 1690
 1691
 1692
 1693
 1694
 1695
 1696
 1697
 1698
 1699
 1700
 1701
 1702
 1703
 1704
 1705
 1706
 1707
 1708
 1709
 1710
 1711
 1712
 1713
 1714
 1715
 1716
 1717
 1718
 1719
 1720
 1721
 1722
 1723
 1724
 1725
 1726
 1727
 1728
 1729
 1730
 1731
 1732
 1733
 1734
 1735
 1736
 1737
 1738
 1739
 1740
 1741
 1742
 1743
 1744
 1745
 1746
 1747
 1748
 1749
 1750
 1751
 1752
 1753
 1754
 1755
 1756
 1757
 1758
 1759
 1760
 1761
 1762
 1763
 1764
 1765
 1766
 1767
 1768
 1769
 1770
 1771
 1772
 1773
 1774
 1775
 1776
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|*                                                                            *|
|* Target Register Enum Values                                                *|
|*                                                                            *|
|* Automatically generated file, do not edit!                                 *|
|*                                                                            *|
\*===----------------------------------------------------------------------===*/


#ifdef GET_REGINFO_ENUM
#undef GET_REGINFO_ENUM

namespace llvm {

class MCRegisterClass;
extern const MCRegisterClass AVRMCRegisterClasses[];

namespace AVR {
enum {
  NoRegister,
  SP = 1,
  SPH = 2,
  SPL = 3,
  SREG = 4,
  R0 = 5,
  R1 = 6,
  R2 = 7,
  R3 = 8,
  R4 = 9,
  R5 = 10,
  R6 = 11,
  R7 = 12,
  R8 = 13,
  R9 = 14,
  R10 = 15,
  R11 = 16,
  R12 = 17,
  R13 = 18,
  R14 = 19,
  R15 = 20,
  R16 = 21,
  R17 = 22,
  R18 = 23,
  R19 = 24,
  R20 = 25,
  R21 = 26,
  R22 = 27,
  R23 = 28,
  R24 = 29,
  R25 = 30,
  R26 = 31,
  R27 = 32,
  R28 = 33,
  R29 = 34,
  R30 = 35,
  R31 = 36,
  R1R0 = 37,
  R3R2 = 38,
  R5R4 = 39,
  R7R6 = 40,
  R9R8 = 41,
  R11R10 = 42,
  R13R12 = 43,
  R15R14 = 44,
  R17R16 = 45,
  R19R18 = 46,
  R21R20 = 47,
  R23R22 = 48,
  R25R24 = 49,
  R27R26 = 50,
  R29R28 = 51,
  R31R30 = 52,
  NUM_TARGET_REGS 	// 53
};
} // end namespace AVR

// Register classes

namespace AVR {
enum {
  GPR8RegClassID = 0,
  GPR8loRegClassID = 1,
  LD8RegClassID = 2,
  LD8loRegClassID = 3,
  CCRRegClassID = 4,
  DREGSRegClassID = 5,
  DREGS_WITHOUT_YZ_WORKAROUNDRegClassID = 6,
  DLDREGSRegClassID = 7,
  DREGS_with_sub_hi_in_GPR8loRegClassID = 8,
  DLDREGS_and_DREGS_WITHOUT_YZ_WORKAROUNDRegClassID = 9,
  DLDREGS_with_sub_hi_in_LD8loRegClassID = 10,
  IWREGSRegClassID = 11,
  PTRREGSRegClassID = 12,
  DREGS_WITHOUT_YZ_WORKAROUND_and_IWREGSRegClassID = 13,
  PTRDISPREGSRegClassID = 14,
  DREGS_WITHOUT_YZ_WORKAROUND_and_PTRREGSRegClassID = 15,
  GPRSPRegClassID = 16,
  ZREGRegClassID = 17,

  };
} // end namespace AVR


// Register alternate name indices

namespace AVR {
enum {
  NoRegAltName,	// 0
  ptr,	// 1
  NUM_TARGET_REG_ALT_NAMES = 2
};
} // end namespace AVR


// Subregister indices

namespace AVR {
enum {
  NoSubRegister,
  sub_hi,	// 1
  sub_lo,	// 2
  NUM_TARGET_SUBREGS
};
} // end namespace AVR

} // end namespace llvm

#endif // GET_REGINFO_ENUM

/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|*                                                                            *|
|* MC Register Information                                                    *|
|*                                                                            *|
|* Automatically generated file, do not edit!                                 *|
|*                                                                            *|
\*===----------------------------------------------------------------------===*/


#ifdef GET_REGINFO_MC_DESC
#undef GET_REGINFO_MC_DESC

namespace llvm {

extern const MCPhysReg AVRRegDiffLists[] = {
  /* 0 */ 0, 1, 0,
  /* 3 */ 65465, 1, 0,
  /* 6 */ 65504, 1, 0,
  /* 9 */ 65505, 1, 0,
  /* 12 */ 65506, 1, 0,
  /* 15 */ 65507, 1, 0,
  /* 18 */ 65508, 1, 0,
  /* 21 */ 65509, 1, 0,
  /* 24 */ 65510, 1, 0,
  /* 27 */ 65511, 1, 0,
  /* 30 */ 65512, 1, 0,
  /* 33 */ 65513, 1, 0,
  /* 36 */ 65514, 1, 0,
  /* 39 */ 65515, 1, 0,
  /* 42 */ 65516, 1, 0,
  /* 45 */ 65517, 1, 0,
  /* 48 */ 65518, 1, 0,
  /* 51 */ 65519, 1, 0,
  /* 54 */ 16, 0,
  /* 56 */ 17, 0,
  /* 58 */ 18, 0,
  /* 60 */ 19, 0,
  /* 62 */ 20, 0,
  /* 64 */ 21, 0,
  /* 66 */ 22, 0,
  /* 68 */ 23, 0,
  /* 70 */ 24, 0,
  /* 72 */ 25, 0,
  /* 74 */ 26, 0,
  /* 76 */ 27, 0,
  /* 78 */ 28, 0,
  /* 80 */ 29, 0,
  /* 82 */ 30, 0,
  /* 84 */ 31, 0,
  /* 86 */ 32, 0,
  /* 88 */ 65530, 0,
  /* 90 */ 65534, 0,
  /* 92 */ 2, 65535, 0,
};

extern const LaneBitmask AVRLaneMaskLists[] = {
  /* 0 */ LaneBitmask(0x00000000), LaneBitmask::getAll(),
  /* 2 */ LaneBitmask(0x00000002), LaneBitmask(0x00000001), LaneBitmask::getAll(),
};

extern const uint16_t AVRSubRegIdxLists[] = {
  /* 0 */ 2, 1, 0,
};

extern const MCRegisterInfo::SubRegCoveredBits AVRSubRegIdxRanges[] = {
  { 65535, 65535 },
  { 8, 8 },	// sub_hi
  { 0, 8 },	// sub_lo
};

extern const char AVRRegStrings[] = {
  /* 0 */ 'R', '1', '1', 'R', '1', '0', 0,
  /* 7 */ 'R', '2', '1', 'R', '2', '0', 0,
  /* 14 */ 'R', '3', '1', 'R', '3', '0', 0,
  /* 21 */ 'R', '1', 'R', '0', 0,
  /* 26 */ 'R', '1', '1', 0,
  /* 30 */ 'R', '2', '1', 0,
  /* 34 */ 'R', '3', '1', 0,
  /* 38 */ 'R', '1', 0,
  /* 41 */ 'R', '1', '3', 'R', '1', '2', 0,
  /* 48 */ 'R', '2', '3', 'R', '2', '2', 0,
  /* 55 */ 'R', '3', 'R', '2', 0,
  /* 60 */ 'R', '1', '3', 0,
  /* 64 */ 'R', '2', '3', 0,
  /* 68 */ 'R', '3', 0,
  /* 71 */ 'R', '1', '5', 'R', '1', '4', 0,
  /* 78 */ 'R', '2', '5', 'R', '2', '4', 0,
  /* 85 */ 'R', '5', 'R', '4', 0,
  /* 90 */ 'R', '1', '5', 0,
  /* 94 */ 'R', '2', '5', 0,
  /* 98 */ 'R', '5', 0,
  /* 101 */ 'R', '1', '7', 'R', '1', '6', 0,
  /* 108 */ 'R', '2', '7', 'R', '2', '6', 0,
  /* 115 */ 'R', '7', 'R', '6', 0,
  /* 120 */ 'R', '1', '7', 0,
  /* 124 */ 'R', '2', '7', 0,
  /* 128 */ 'R', '7', 0,
  /* 131 */ 'R', '1', '9', 'R', '1', '8', 0,
  /* 138 */ 'R', '2', '9', 'R', '2', '8', 0,
  /* 145 */ 'R', '9', 'R', '8', 0,
  /* 150 */ 'R', '1', '9', 0,
  /* 154 */ 'R', '2', '9', 0,
  /* 158 */ 'R', '9', 0,
  /* 161 */ 'S', 'R', 'E', 'G', 0,
  /* 166 */ 'S', 'P', 'H', 0,
  /* 170 */ 'S', 'P', 'L', 0,
  /* 174 */ 'S', 'P', 0,
};

extern const MCRegisterDesc AVRRegDesc[] = { // Descriptors
  { 6, 0, 0, 0, 0, 0 },
  { 174, 92, 2, 0, 0, 2 },
  { 166, 2, 93, 2, 16, 0 },
  { 170, 2, 90, 2, 1410, 0 },
  { 161, 2, 2, 2, 1441, 0 },
  { 23, 2, 86, 2, 1441, 0 },
  { 38, 2, 84, 2, 1441, 0 },
  { 57, 2, 84, 2, 1441, 0 },
  { 68, 2, 82, 2, 1441, 0 },
  { 87, 2, 82, 2, 1441, 0 },
  { 98, 2, 80, 2, 1441, 0 },
  { 117, 2, 80, 2, 1441, 0 },
  { 128, 2, 78, 2, 1441, 0 },
  { 147, 2, 78, 2, 1441, 0 },
  { 158, 2, 76, 2, 1441, 0 },
  { 3, 2, 76, 2, 1441, 0 },
  { 26, 2, 74, 2, 1441, 0 },
  { 44, 2, 74, 2, 1441, 0 },
  { 60, 2, 72, 2, 1441, 0 },
  { 74, 2, 72, 2, 1441, 0 },
  { 90, 2, 70, 2, 1441, 0 },
  { 104, 2, 70, 2, 1441, 0 },
  { 120, 2, 68, 2, 1441, 0 },
  { 134, 2, 68, 2, 1441, 0 },
  { 150, 2, 66, 2, 1441, 0 },
  { 10, 2, 66, 2, 1441, 0 },
  { 30, 2, 64, 2, 1441, 0 },
  { 51, 2, 64, 2, 1441, 0 },
  { 64, 2, 62, 2, 1441, 0 },
  { 81, 2, 62, 2, 1441, 0 },
  { 94, 2, 60, 2, 1441, 0 },
  { 111, 2, 60, 2, 1441, 0 },
  { 124, 2, 58, 2, 1441, 0 },
  { 141, 2, 58, 2, 1441, 0 },
  { 154, 2, 56, 2, 1441, 0 },
  { 17, 2, 56, 2, 1441, 0 },
  { 34, 2, 54, 2, 1441, 0 },
  { 21, 6, 2, 0, 50, 2 },
  { 55, 9, 2, 0, 50, 2 },
  { 85, 12, 2, 0, 50, 2 },
  { 115, 15, 2, 0, 50, 2 },
  { 145, 18, 2, 0, 50, 2 },
  { 0, 21, 2, 0, 50, 2 },
  { 41, 24, 2, 0, 50, 2 },
  { 71, 27, 2, 0, 50, 2 },
  { 101, 30, 2, 0, 50, 2 },
  { 131, 33, 2, 0, 50, 2 },
  { 7, 36, 2, 0, 50, 2 },
  { 48, 39, 2, 0, 50, 2 },
  { 78, 42, 2, 0, 50, 2 },
  { 108, 45, 2, 0, 50, 2 },
  { 138, 48, 2, 0, 50, 2 },
  { 14, 51, 2, 0, 50, 2 },
};

extern const MCPhysReg AVRRegUnitRoots[][2] = {
  { AVR::SPL },
  { AVR::SPH },
  { AVR::SREG },
  { AVR::R0 },
  { AVR::R1 },
  { AVR::R2 },
  { AVR::R3 },
  { AVR::R4 },
  { AVR::R5 },
  { AVR::R6 },
  { AVR::R7 },
  { AVR::R8 },
  { AVR::R9 },
  { AVR::R10 },
  { AVR::R11 },
  { AVR::R12 },
  { AVR::R13 },
  { AVR::R14 },
  { AVR::R15 },
  { AVR::R16 },
  { AVR::R17 },
  { AVR::R18 },
  { AVR::R19 },
  { AVR::R20 },
  { AVR::R21 },
  { AVR::R22 },
  { AVR::R23 },
  { AVR::R24 },
  { AVR::R25 },
  { AVR::R26 },
  { AVR::R27 },
  { AVR::R28 },
  { AVR::R29 },
  { AVR::R30 },
  { AVR::R31 },
};

namespace {     // Register classes...
  // GPR8 Register Class...
  const MCPhysReg GPR8[] = {
    AVR::R24, AVR::R25, AVR::R18, AVR::R19, AVR::R20, AVR::R21, AVR::R22, AVR::R23, AVR::R30, AVR::R31, AVR::R26, AVR::R27, AVR::R28, AVR::R29, AVR::R17, AVR::R16, AVR::R15, AVR::R14, AVR::R13, AVR::R12, AVR::R11, AVR::R10, AVR::R9, AVR::R8, AVR::R7, AVR::R6, AVR::R5, AVR::R4, AVR::R3, AVR::R2, AVR::R0, AVR::R1, 
  };

  // GPR8 Bit set.
  const uint8_t GPR8Bits[] = {
    0xe0, 0xff, 0xff, 0xff, 0x1f, 
  };

  // GPR8lo Register Class...
  const MCPhysReg GPR8lo[] = {
    AVR::R15, AVR::R14, AVR::R13, AVR::R12, AVR::R11, AVR::R10, AVR::R9, AVR::R8, AVR::R7, AVR::R6, AVR::R5, AVR::R4, AVR::R3, AVR::R2, AVR::R0, AVR::R1, 
  };

  // GPR8lo Bit set.
  const uint8_t GPR8loBits[] = {
    0xe0, 0xff, 0x1f, 
  };

  // LD8 Register Class...
  const MCPhysReg LD8[] = {
    AVR::R24, AVR::R25, AVR::R18, AVR::R19, AVR::R20, AVR::R21, AVR::R22, AVR::R23, AVR::R30, AVR::R31, AVR::R26, AVR::R27, AVR::R28, AVR::R29, AVR::R17, AVR::R16, 
  };

  // LD8 Bit set.
  const uint8_t LD8Bits[] = {
    0x00, 0x00, 0xe0, 0xff, 0x1f, 
  };

  // LD8lo Register Class...
  const MCPhysReg LD8lo[] = {
    AVR::R23, AVR::R22, AVR::R21, AVR::R20, AVR::R19, AVR::R18, AVR::R17, AVR::R16, 
  };

  // LD8lo Bit set.
  const uint8_t LD8loBits[] = {
    0x00, 0x00, 0xe0, 0x1f, 
  };

  // CCR Register Class...
  const MCPhysReg CCR[] = {
    AVR::SREG, 
  };

  // CCR Bit set.
  const uint8_t CCRBits[] = {
    0x10, 
  };

  // DREGS Register Class...
  const MCPhysReg DREGS[] = {
    AVR::R25R24, AVR::R19R18, AVR::R21R20, AVR::R23R22, AVR::R31R30, AVR::R27R26, AVR::R29R28, AVR::R17R16, AVR::R15R14, AVR::R13R12, AVR::R11R10, AVR::R9R8, AVR::R7R6, AVR::R5R4, AVR::R3R2, AVR::R1R0, 
  };

  // DREGS Bit set.
  const uint8_t DREGSBits[] = {
    0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f, 
  };

  // DREGS_WITHOUT_YZ_WORKAROUND Register Class...
  const MCPhysReg DREGS_WITHOUT_YZ_WORKAROUND[] = {
    AVR::R25R24, AVR::R19R18, AVR::R21R20, AVR::R23R22, AVR::R27R26, AVR::R17R16, AVR::R15R14, AVR::R13R12, AVR::R11R10, AVR::R9R8, AVR::R7R6, AVR::R5R4, AVR::R3R2, AVR::R1R0, 
  };

  // DREGS_WITHOUT_YZ_WORKAROUND Bit set.
  const uint8_t DREGS_WITHOUT_YZ_WORKAROUNDBits[] = {
    0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07, 
  };

  // DLDREGS Register Class...
  const MCPhysReg DLDREGS[] = {
    AVR::R25R24, AVR::R19R18, AVR::R21R20, AVR::R23R22, AVR::R31R30, AVR::R27R26, AVR::R29R28, AVR::R17R16, 
  };

  // DLDREGS Bit set.
  const uint8_t DLDREGSBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 
  };

  // DREGS_with_sub_hi_in_GPR8lo Register Class...
  const MCPhysReg DREGS_with_sub_hi_in_GPR8lo[] = {
    AVR::R15R14, AVR::R13R12, AVR::R11R10, AVR::R9R8, AVR::R7R6, AVR::R5R4, AVR::R3R2, AVR::R1R0, 
  };

  // DREGS_with_sub_hi_in_GPR8lo Bit set.
  const uint8_t DREGS_with_sub_hi_in_GPR8loBits[] = {
    0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 
  };

  // DLDREGS_and_DREGS_WITHOUT_YZ_WORKAROUND Register Class...
  const MCPhysReg DLDREGS_and_DREGS_WITHOUT_YZ_WORKAROUND[] = {
    AVR::R25R24, AVR::R19R18, AVR::R21R20, AVR::R23R22, AVR::R27R26, AVR::R17R16, 
  };

  // DLDREGS_and_DREGS_WITHOUT_YZ_WORKAROUND Bit set.
  const uint8_t DLDREGS_and_DREGS_WITHOUT_YZ_WORKAROUNDBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x07, 
  };

  // DLDREGS_with_sub_hi_in_LD8lo Register Class...
  const MCPhysReg DLDREGS_with_sub_hi_in_LD8lo[] = {
    AVR::R19R18, AVR::R21R20, AVR::R23R22, AVR::R17R16, 
  };

  // DLDREGS_with_sub_hi_in_LD8lo Bit set.
  const uint8_t DLDREGS_with_sub_hi_in_LD8loBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x01, 
  };

  // IWREGS Register Class...
  const MCPhysReg IWREGS[] = {
    AVR::R25R24, AVR::R31R30, AVR::R27R26, AVR::R29R28, 
  };

  // IWREGS Bit set.
  const uint8_t IWREGSBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1e, 
  };

  // PTRREGS Register Class...
  const MCPhysReg PTRREGS[] = {
    AVR::R27R26, AVR::R29R28, AVR::R31R30, 
  };

  // PTRREGS Bit set.
  const uint8_t PTRREGSBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1c, 
  };

  // DREGS_WITHOUT_YZ_WORKAROUND_and_IWREGS Register Class...
  const MCPhysReg DREGS_WITHOUT_YZ_WORKAROUND_and_IWREGS[] = {
    AVR::R25R24, AVR::R27R26, 
  };

  // DREGS_WITHOUT_YZ_WORKAROUND_and_IWREGS Bit set.
  const uint8_t DREGS_WITHOUT_YZ_WORKAROUND_and_IWREGSBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 
  };

  // PTRDISPREGS Register Class...
  const MCPhysReg PTRDISPREGS[] = {
    AVR::R31R30, AVR::R29R28, 
  };

  // PTRDISPREGS Bit set.
  const uint8_t PTRDISPREGSBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 
  };

  // DREGS_WITHOUT_YZ_WORKAROUND_and_PTRREGS Register Class...
  const MCPhysReg DREGS_WITHOUT_YZ_WORKAROUND_and_PTRREGS[] = {
    AVR::R27R26, 
  };

  // DREGS_WITHOUT_YZ_WORKAROUND_and_PTRREGS Bit set.
  const uint8_t DREGS_WITHOUT_YZ_WORKAROUND_and_PTRREGSBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 
  };

  // GPRSP Register Class...
  const MCPhysReg GPRSP[] = {
    AVR::SP, 
  };

  // GPRSP Bit set.
  const uint8_t GPRSPBits[] = {
    0x02, 
  };

  // ZREG Register Class...
  const MCPhysReg ZREG[] = {
    AVR::R31R30, 
  };

  // ZREG Bit set.
  const uint8_t ZREGBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 
  };

} // end anonymous namespace

extern const char AVRRegClassStrings[] = {
  /* 0 */ 'L', 'D', '8', 0,
  /* 4 */ 'G', 'P', 'R', '8', 0,
  /* 9 */ 'D', 'L', 'D', 'R', 'E', 'G', 'S', '_', 'a', 'n', 'd', '_', 'D', 'R', 'E', 'G', 'S', '_', 'W', 'I', 'T', 'H', 'O', 'U', 'T', '_', 'Y', 'Z', '_', 'W', 'O', 'R', 'K', 'A', 'R', 'O', 'U', 'N', 'D', 0,
  /* 49 */ 'Z', 'R', 'E', 'G', 0,
  /* 54 */ 'G', 'P', 'R', 'S', 'P', 0,
  /* 60 */ 'C', 'C', 'R', 0,
  /* 64 */ 'D', 'L', 'D', 'R', 'E', 'G', 'S', 0,
  /* 72 */ 'P', 'T', 'R', 'D', 'I', 'S', 'P', 'R', 'E', 'G', 'S', 0,
  /* 84 */ 'D', 'R', 'E', 'G', 'S', '_', 'W', 'I', 'T', 'H', 'O', 'U', 'T', '_', 'Y', 'Z', '_', 'W', 'O', 'R', 'K', 'A', 'R', 'O', 'U', 'N', 'D', '_', 'a', 'n', 'd', '_', 'P', 'T', 'R', 'R', 'E', 'G', 'S', 0,
  /* 124 */ 'D', 'R', 'E', 'G', 'S', '_', 'W', 'I', 'T', 'H', 'O', 'U', 'T', '_', 'Y', 'Z', '_', 'W', 'O', 'R', 'K', 'A', 'R', 'O', 'U', 'N', 'D', '_', 'a', 'n', 'd', '_', 'I', 'W', 'R', 'E', 'G', 'S', 0,
  /* 163 */ 'D', 'L', 'D', 'R', 'E', 'G', 'S', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', 'h', 'i', '_', 'i', 'n', '_', 'L', 'D', '8', 'l', 'o', 0,
  /* 192 */ 'D', 'R', 'E', 'G', 'S', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', 'h', 'i', '_', 'i', 'n', '_', 'G', 'P', 'R', '8', 'l', 'o', 0,
};

extern const MCRegisterClass AVRMCRegisterClasses[] = {
  { GPR8, GPR8Bits, 4, 32, sizeof(GPR8Bits), AVR::GPR8RegClassID, 1, true },
  { GPR8lo, GPR8loBits, 213, 16, sizeof(GPR8loBits), AVR::GPR8loRegClassID, 1, true },
  { LD8, LD8Bits, 0, 16, sizeof(LD8Bits), AVR::LD8RegClassID, 1, true },
  { LD8lo, LD8loBits, 186, 8, sizeof(LD8loBits), AVR::LD8loRegClassID, 1, true },
  { CCR, CCRBits, 60, 1, sizeof(CCRBits), AVR::CCRRegClassID, -1, true },
  { DREGS, DREGSBits, 66, 16, sizeof(DREGSBits), AVR::DREGSRegClassID, 1, true },
  { DREGS_WITHOUT_YZ_WORKAROUND, DREGS_WITHOUT_YZ_WORKAROUNDBits, 21, 14, sizeof(DREGS_WITHOUT_YZ_WORKAROUNDBits), AVR::DREGS_WITHOUT_YZ_WORKAROUNDRegClassID, 1, true },
  { DLDREGS, DLDREGSBits, 64, 8, sizeof(DLDREGSBits), AVR::DLDREGSRegClassID, 1, true },
  { DREGS_with_sub_hi_in_GPR8lo, DREGS_with_sub_hi_in_GPR8loBits, 192, 8, sizeof(DREGS_with_sub_hi_in_GPR8loBits), AVR::DREGS_with_sub_hi_in_GPR8loRegClassID, 1, true },
  { DLDREGS_and_DREGS_WITHOUT_YZ_WORKAROUND, DLDREGS_and_DREGS_WITHOUT_YZ_WORKAROUNDBits, 9, 6, sizeof(DLDREGS_and_DREGS_WITHOUT_YZ_WORKAROUNDBits), AVR::DLDREGS_and_DREGS_WITHOUT_YZ_WORKAROUNDRegClassID, 1, true },
  { DLDREGS_with_sub_hi_in_LD8lo, DLDREGS_with_sub_hi_in_LD8loBits, 163, 4, sizeof(DLDREGS_with_sub_hi_in_LD8loBits), AVR::DLDREGS_with_sub_hi_in_LD8loRegClassID, 1, true },
  { IWREGS, IWREGSBits, 156, 4, sizeof(IWREGSBits), AVR::IWREGSRegClassID, 1, true },
  { PTRREGS, PTRREGSBits, 116, 3, sizeof(PTRREGSBits), AVR::PTRREGSRegClassID, 1, true },
  { DREGS_WITHOUT_YZ_WORKAROUND_and_IWREGS, DREGS_WITHOUT_YZ_WORKAROUND_and_IWREGSBits, 124, 2, sizeof(DREGS_WITHOUT_YZ_WORKAROUND_and_IWREGSBits), AVR::DREGS_WITHOUT_YZ_WORKAROUND_and_IWREGSRegClassID, 1, true },
  { PTRDISPREGS, PTRDISPREGSBits, 72, 2, sizeof(PTRDISPREGSBits), AVR::PTRDISPREGSRegClassID, 1, true },
  { DREGS_WITHOUT_YZ_WORKAROUND_and_PTRREGS, DREGS_WITHOUT_YZ_WORKAROUND_and_PTRREGSBits, 84, 1, sizeof(DREGS_WITHOUT_YZ_WORKAROUND_and_PTRREGSBits), AVR::DREGS_WITHOUT_YZ_WORKAROUND_and_PTRREGSRegClassID, 1, true },
  { GPRSP, GPRSPBits, 54, 1, sizeof(GPRSPBits), AVR::GPRSPRegClassID, 1, true },
  { ZREG, ZREGBits, 49, 1, sizeof(ZREGBits), AVR::ZREGRegClassID, 1, true },
};

// AVR Dwarf<->LLVM register mappings.
extern const MCRegisterInfo::DwarfLLVMRegPair AVRDwarfFlavour0Dwarf2L[] = {
  { 0U, AVR::R1R0 },
  { 1U, AVR::R1 },
  { 2U, AVR::R3R2 },
  { 3U, AVR::R3 },
  { 4U, AVR::R5R4 },
  { 5U, AVR::R5 },
  { 6U, AVR::R7R6 },
  { 7U, AVR::R7 },
  { 8U, AVR::R9R8 },
  { 9U, AVR::R9 },
  { 10U, AVR::R11R10 },
  { 11U, AVR::R11 },
  { 12U, AVR::R13R12 },
  { 13U, AVR::R13 },
  { 14U, AVR::R15R14 },
  { 15U, AVR::R15 },
  { 16U, AVR::R17R16 },
  { 17U, AVR::R17 },
  { 18U, AVR::R19R18 },
  { 19U, AVR::R19 },
  { 20U, AVR::R21R20 },
  { 21U, AVR::R21 },
  { 22U, AVR::R23R22 },
  { 23U, AVR::R23 },
  { 24U, AVR::R25R24 },
  { 25U, AVR::R25 },
  { 26U, AVR::R27R26 },
  { 27U, AVR::R27 },
  { 28U, AVR::R29R28 },
  { 29U, AVR::R29 },
  { 30U, AVR::R31R30 },
  { 31U, AVR::R31 },
  { 32U, AVR::SPL },
  { 33U, AVR::SPH },
  { 88U, AVR::SREG },
};
extern const unsigned AVRDwarfFlavour0Dwarf2LSize = array_lengthof(AVRDwarfFlavour0Dwarf2L);

extern const MCRegisterInfo::DwarfLLVMRegPair AVREHFlavour0Dwarf2L[] = {
  { 0U, AVR::R1R0 },
  { 1U, AVR::R1 },
  { 2U, AVR::R3R2 },
  { 3U, AVR::R3 },
  { 4U, AVR::R5R4 },
  { 5U, AVR::R5 },
  { 6U, AVR::R7R6 },
  { 7U, AVR::R7 },
  { 8U, AVR::R9R8 },
  { 9U, AVR::R9 },
  { 10U, AVR::R11R10 },
  { 11U, AVR::R11 },
  { 12U, AVR::R13R12 },
  { 13U, AVR::R13 },
  { 14U, AVR::R15R14 },
  { 15U, AVR::R15 },
  { 16U, AVR::R17R16 },
  { 17U, AVR::R17 },
  { 18U, AVR::R19R18 },
  { 19U, AVR::R19 },
  { 20U, AVR::R21R20 },
  { 21U, AVR::R21 },
  { 22U, AVR::R23R22 },
  { 23U, AVR::R23 },
  { 24U, AVR::R25R24 },
  { 25U, AVR::R25 },
  { 26U, AVR::R27R26 },
  { 27U, AVR::R27 },
  { 28U, AVR::R29R28 },
  { 29U, AVR::R29 },
  { 30U, AVR::R31R30 },
  { 31U, AVR::R31 },
  { 32U, AVR::SPL },
  { 33U, AVR::SPH },
  { 88U, AVR::SREG },
};
extern const unsigned AVREHFlavour0Dwarf2LSize = array_lengthof(AVREHFlavour0Dwarf2L);

extern const MCRegisterInfo::DwarfLLVMRegPair AVRDwarfFlavour0L2Dwarf[] = {
  { AVR::SP, 32U },
  { AVR::SPH, 33U },
  { AVR::SPL, 32U },
  { AVR::SREG, 88U },
  { AVR::R0, 0U },
  { AVR::R1, 1U },
  { AVR::R2, 2U },
  { AVR::R3, 3U },
  { AVR::R4, 4U },
  { AVR::R5, 5U },
  { AVR::R6, 6U },
  { AVR::R7, 7U },
  { AVR::R8, 8U },
  { AVR::R9, 9U },
  { AVR::R10, 10U },
  { AVR::R11, 11U },
  { AVR::R12, 12U },
  { AVR::R13, 13U },
  { AVR::R14, 14U },
  { AVR::R15, 15U },
  { AVR::R16, 16U },
  { AVR::R17, 17U },
  { AVR::R18, 18U },
  { AVR::R19, 19U },
  { AVR::R20, 20U },
  { AVR::R21, 21U },
  { AVR::R22, 22U },
  { AVR::R23, 23U },
  { AVR::R24, 24U },
  { AVR::R25, 25U },
  { AVR::R26, 26U },
  { AVR::R27, 27U },
  { AVR::R28, 28U },
  { AVR::R29, 29U },
  { AVR::R30, 30U },
  { AVR::R31, 31U },
  { AVR::R1R0, 0U },
  { AVR::R3R2, 2U },
  { AVR::R5R4, 4U },
  { AVR::R7R6, 6U },
  { AVR::R9R8, 8U },
  { AVR::R11R10, 10U },
  { AVR::R13R12, 12U },
  { AVR::R15R14, 14U },
  { AVR::R17R16, 16U },
  { AVR::R19R18, 18U },
  { AVR::R21R20, 20U },
  { AVR::R23R22, 22U },
  { AVR::R25R24, 24U },
  { AVR::R27R26, 26U },
  { AVR::R29R28, 28U },
  { AVR::R31R30, 30U },
};
extern const unsigned AVRDwarfFlavour0L2DwarfSize = array_lengthof(AVRDwarfFlavour0L2Dwarf);

extern const MCRegisterInfo::DwarfLLVMRegPair AVREHFlavour0L2Dwarf[] = {
  { AVR::SP, 32U },
  { AVR::SPH, 33U },
  { AVR::SPL, 32U },
  { AVR::SREG, 88U },
  { AVR::R0, 0U },
  { AVR::R1, 1U },
  { AVR::R2, 2U },
  { AVR::R3, 3U },
  { AVR::R4, 4U },
  { AVR::R5, 5U },
  { AVR::R6, 6U },
  { AVR::R7, 7U },
  { AVR::R8, 8U },
  { AVR::R9, 9U },
  { AVR::R10, 10U },
  { AVR::R11, 11U },
  { AVR::R12, 12U },
  { AVR::R13, 13U },
  { AVR::R14, 14U },
  { AVR::R15, 15U },
  { AVR::R16, 16U },
  { AVR::R17, 17U },
  { AVR::R18, 18U },
  { AVR::R19, 19U },
  { AVR::R20, 20U },
  { AVR::R21, 21U },
  { AVR::R22, 22U },
  { AVR::R23, 23U },
  { AVR::R24, 24U },
  { AVR::R25, 25U },
  { AVR::R26, 26U },
  { AVR::R27, 27U },
  { AVR::R28, 28U },
  { AVR::R29, 29U },
  { AVR::R30, 30U },
  { AVR::R31, 31U },
  { AVR::R1R0, 0U },
  { AVR::R3R2, 2U },
  { AVR::R5R4, 4U },
  { AVR::R7R6, 6U },
  { AVR::R9R8, 8U },
  { AVR::R11R10, 10U },
  { AVR::R13R12, 12U },
  { AVR::R15R14, 14U },
  { AVR::R17R16, 16U },
  { AVR::R19R18, 18U },
  { AVR::R21R20, 20U },
  { AVR::R23R22, 22U },
  { AVR::R25R24, 24U },
  { AVR::R27R26, 26U },
  { AVR::R29R28, 28U },
  { AVR::R31R30, 30U },
};
extern const unsigned AVREHFlavour0L2DwarfSize = array_lengthof(AVREHFlavour0L2Dwarf);

extern const uint16_t AVRRegEncodingTable[] = {
  0,
  32,
  33,
  32,
  14,
  0,
  1,
  2,
  3,
  4,
  5,
  6,
  7,
  8,
  9,
  10,
  11,
  12,
  13,
  14,
  15,
  16,
  17,
  18,
  19,
  20,
  21,
  22,
  23,
  24,
  25,
  26,
  27,
  28,
  29,
  30,
  31,
  0,
  2,
  4,
  6,
  8,
  10,
  12,
  14,
  16,
  18,
  20,
  22,
  24,
  26,
  28,
  30,
};
static inline void InitAVRMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
  RI->InitMCRegisterInfo(AVRRegDesc, 53, RA, PC, AVRMCRegisterClasses, 18, AVRRegUnitRoots, 35, AVRRegDiffLists, AVRLaneMaskLists, AVRRegStrings, AVRRegClassStrings, AVRSubRegIdxLists, 3,
AVRSubRegIdxRanges, AVRRegEncodingTable);

  switch (DwarfFlavour) {
  default:
    llvm_unreachable("Unknown DWARF flavour");
  case 0:
    RI->mapDwarfRegsToLLVMRegs(AVRDwarfFlavour0Dwarf2L, AVRDwarfFlavour0Dwarf2LSize, false);
    break;
  }
  switch (EHFlavour) {
  default:
    llvm_unreachable("Unknown DWARF flavour");
  case 0:
    RI->mapDwarfRegsToLLVMRegs(AVREHFlavour0Dwarf2L, AVREHFlavour0Dwarf2LSize, true);
    break;
  }
  switch (DwarfFlavour) {
  default:
    llvm_unreachable("Unknown DWARF flavour");
  case 0:
    RI->mapLLVMRegsToDwarfRegs(AVRDwarfFlavour0L2Dwarf, AVRDwarfFlavour0L2DwarfSize, false);
    break;
  }
  switch (EHFlavour) {
  default:
    llvm_unreachable("Unknown DWARF flavour");
  case 0:
    RI->mapLLVMRegsToDwarfRegs(AVREHFlavour0L2Dwarf, AVREHFlavour0L2DwarfSize, true);
    break;
  }
}

} // end namespace llvm

#endif // GET_REGINFO_MC_DESC

/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|*                                                                            *|
|* Register Information Header Fragment                                       *|
|*                                                                            *|
|* Automatically generated file, do not edit!                                 *|
|*                                                                            *|
\*===----------------------------------------------------------------------===*/


#ifdef GET_REGINFO_HEADER
#undef GET_REGINFO_HEADER

#include "llvm/CodeGen/TargetRegisterInfo.h"

namespace llvm {

class AVRFrameLowering;

struct AVRGenRegisterInfo : public TargetRegisterInfo {
  explicit AVRGenRegisterInfo(unsigned RA, unsigned D = 0, unsigned E = 0,
      unsigned PC = 0, unsigned HwMode = 0);
  unsigned composeSubRegIndicesImpl(unsigned, unsigned) const override;
  LaneBitmask composeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
  LaneBitmask reverseComposeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
  const TargetRegisterClass *getSubClassWithSubReg(const TargetRegisterClass*, unsigned) const override;
  const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override;
  unsigned getRegUnitWeight(unsigned RegUnit) const override;
  unsigned getNumRegPressureSets() const override;
  const char *getRegPressureSetName(unsigned Idx) const override;
  unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override;
  const int *getRegClassPressureSets(const TargetRegisterClass *RC) const override;
  const int *getRegUnitPressureSets(unsigned RegUnit) const override;
  ArrayRef<const char *> getRegMaskNames() const override;
  ArrayRef<const uint32_t *> getRegMasks() const override;
  /// Devirtualized TargetFrameLowering.
  static const AVRFrameLowering *getFrameLowering(
      const MachineFunction &MF);
};

namespace AVR { // Register classes
  extern const TargetRegisterClass GPR8RegClass;
  extern const TargetRegisterClass GPR8loRegClass;
  extern const TargetRegisterClass LD8RegClass;
  extern const TargetRegisterClass LD8loRegClass;
  extern const TargetRegisterClass CCRRegClass;
  extern const TargetRegisterClass DREGSRegClass;
  extern const TargetRegisterClass DREGS_WITHOUT_YZ_WORKAROUNDRegClass;
  extern const TargetRegisterClass DLDREGSRegClass;
  extern const TargetRegisterClass DREGS_with_sub_hi_in_GPR8loRegClass;
  extern const TargetRegisterClass DLDREGS_and_DREGS_WITHOUT_YZ_WORKAROUNDRegClass;
  extern const TargetRegisterClass DLDREGS_with_sub_hi_in_LD8loRegClass;
  extern const TargetRegisterClass IWREGSRegClass;
  extern const TargetRegisterClass PTRREGSRegClass;
  extern const TargetRegisterClass DREGS_WITHOUT_YZ_WORKAROUND_and_IWREGSRegClass;
  extern const TargetRegisterClass PTRDISPREGSRegClass;
  extern const TargetRegisterClass DREGS_WITHOUT_YZ_WORKAROUND_and_PTRREGSRegClass;
  extern const TargetRegisterClass GPRSPRegClass;
  extern const TargetRegisterClass ZREGRegClass;
} // end namespace AVR

} // end namespace llvm

#endif // GET_REGINFO_HEADER

/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|*                                                                            *|
|* Target Register and Register Classes Information                           *|
|*                                                                            *|
|* Automatically generated file, do not edit!                                 *|
|*                                                                            *|
\*===----------------------------------------------------------------------===*/


#ifdef GET_REGINFO_TARGET_DESC
#undef GET_REGINFO_TARGET_DESC

namespace llvm {

extern const MCRegisterClass AVRMCRegisterClasses[];

static const MVT::SimpleValueType VTLists[] = {
  /* 0 */ MVT::i8, MVT::Other,
  /* 2 */ MVT::i16, MVT::Other,
};

static const char *const SubRegIndexNameTable[] = { "sub_hi", "sub_lo", "" };


static const LaneBitmask SubRegIndexLaneMaskTable[] = {
  LaneBitmask::getAll(),
  LaneBitmask(0x00000001), // sub_hi
  LaneBitmask(0x00000002), // sub_lo
 };



static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
  // Mode = 0 (Default)
  { 8, 8, 8, VTLists+0 },    // GPR8
  { 8, 8, 8, VTLists+0 },    // GPR8lo
  { 8, 8, 8, VTLists+0 },    // LD8
  { 8, 8, 8, VTLists+0 },    // LD8lo
  { 8, 8, 8, VTLists+0 },    // CCR
  { 16, 16, 8, VTLists+2 },    // DREGS
  { 16, 16, 8, VTLists+2 },    // DREGS_WITHOUT_YZ_WORKAROUND
  { 16, 16, 8, VTLists+2 },    // DLDREGS
  { 16, 16, 8, VTLists+2 },    // DREGS_with_sub_hi_in_GPR8lo
  { 16, 16, 8, VTLists+2 },    // DLDREGS_and_DREGS_WITHOUT_YZ_WORKAROUND
  { 16, 16, 8, VTLists+2 },    // DLDREGS_with_sub_hi_in_LD8lo
  { 16, 16, 8, VTLists+2 },    // IWREGS
  { 16, 16, 8, VTLists+2 },    // PTRREGS
  { 16, 16, 8, VTLists+2 },    // DREGS_WITHOUT_YZ_WORKAROUND_and_IWREGS
  { 16, 16, 8, VTLists+2 },    // PTRDISPREGS
  { 16, 16, 8, VTLists+2 },    // DREGS_WITHOUT_YZ_WORKAROUND_and_PTRREGS
  { 16, 16, 8, VTLists+2 },    // GPRSP
  { 16, 16, 8, VTLists+2 },    // ZREG
};

static const TargetRegisterClass *const NullRegClasses[] = { nullptr };

static const uint32_t GPR8SubClassMask[] = {
  0x0000000f, 
  0x0002ffe0, // sub_hi
  0x0002ffe0, // sub_lo
};

static const uint32_t GPR8loSubClassMask[] = {
  0x00000002, 
  0x00000100, // sub_hi
  0x00000100, // sub_lo
};

static const uint32_t LD8SubClassMask[] = {
  0x0000000c, 
  0x0002fe80, // sub_hi
  0x0002fe80, // sub_lo
};

static const uint32_t LD8loSubClassMask[] = {
  0x00000008, 
  0x00000400, // sub_hi
  0x00000400, // sub_lo
};

static const uint32_t CCRSubClassMask[] = {
  0x00000010, 
};

static const uint32_t DREGSSubClassMask[] = {
  0x0002ffe0, 
};

static const uint32_t DREGS_WITHOUT_YZ_WORKAROUNDSubClassMask[] = {
  0x0000a740, 
};

static const uint32_t DLDREGSSubClassMask[] = {
  0x0002fe80, 
};

static const uint32_t DREGS_with_sub_hi_in_GPR8loSubClassMask[] = {
  0x00000100, 
};

static const uint32_t DLDREGS_and_DREGS_WITHOUT_YZ_WORKAROUNDSubClassMask[] = {
  0x0000a600, 
};

static const uint32_t DLDREGS_with_sub_hi_in_LD8loSubClassMask[] = {
  0x00000400, 
};

static const uint32_t IWREGSSubClassMask[] = {
  0x0002f800, 
};

static const uint32_t PTRREGSSubClassMask[] = {
  0x0002d000, 
};

static const uint32_t DREGS_WITHOUT_YZ_WORKAROUND_and_IWREGSSubClassMask[] = {
  0x0000a000, 
};

static const uint32_t PTRDISPREGSSubClassMask[] = {
  0x00024000, 
};

static const uint32_t DREGS_WITHOUT_YZ_WORKAROUND_and_PTRREGSSubClassMask[] = {
  0x00008000, 
};

static const uint32_t GPRSPSubClassMask[] = {
  0x00010000, 
};

static const uint32_t ZREGSubClassMask[] = {
  0x00020000, 
};

static const uint16_t SuperRegIdxSeqs[] = {
  /* 0 */ 1, 2, 0,
};

static const TargetRegisterClass *const GPR8loSuperclasses[] = {
  &AVR::GPR8RegClass,
  nullptr
};

static const TargetRegisterClass *const LD8Superclasses[] = {
  &AVR::GPR8RegClass,
  nullptr
};

static const TargetRegisterClass *const LD8loSuperclasses[] = {
  &AVR::GPR8RegClass,
  &AVR::LD8RegClass,
  nullptr
};

static const TargetRegisterClass *const DREGS_WITHOUT_YZ_WORKAROUNDSuperclasses[] = {
  &AVR::DREGSRegClass,
  nullptr
};

static const TargetRegisterClass *const DLDREGSSuperclasses[] = {
  &AVR::DREGSRegClass,
  nullptr
};

static const TargetRegisterClass *const DREGS_with_sub_hi_in_GPR8loSuperclasses[] = {
  &AVR::DREGSRegClass,
  &AVR::DREGS_WITHOUT_YZ_WORKAROUNDRegClass,
  nullptr
};

static const TargetRegisterClass *const DLDREGS_and_DREGS_WITHOUT_YZ_WORKAROUNDSuperclasses[] = {
  &AVR::DREGSRegClass,
  &AVR::DREGS_WITHOUT_YZ_WORKAROUNDRegClass,
  &AVR::DLDREGSRegClass,
  nullptr
};

static const TargetRegisterClass *const DLDREGS_with_sub_hi_in_LD8loSuperclasses[] = {
  &AVR::DREGSRegClass,
  &AVR::DREGS_WITHOUT_YZ_WORKAROUNDRegClass,
  &AVR::DLDREGSRegClass,
  &AVR::DLDREGS_and_DREGS_WITHOUT_YZ_WORKAROUNDRegClass,
  nullptr
};

static const TargetRegisterClass *const IWREGSSuperclasses[] = {
  &AVR::DREGSRegClass,
  &AVR::DLDREGSRegClass,
  nullptr
};

static const TargetRegisterClass *const PTRREGSSuperclasses[] = {
  &AVR::DREGSRegClass,
  &AVR::DLDREGSRegClass,
  &AVR::IWREGSRegClass,
  nullptr
};

static const TargetRegisterClass *const DREGS_WITHOUT_YZ_WORKAROUND_and_IWREGSSuperclasses[] = {
  &AVR::DREGSRegClass,
  &AVR::DREGS_WITHOUT_YZ_WORKAROUNDRegClass,
  &AVR::DLDREGSRegClass,
  &AVR::DLDREGS_and_DREGS_WITHOUT_YZ_WORKAROUNDRegClass,
  &AVR::IWREGSRegClass,
  nullptr
};

static const TargetRegisterClass *const PTRDISPREGSSuperclasses[] = {
  &AVR::DREGSRegClass,
  &AVR::DLDREGSRegClass,
  &AVR::IWREGSRegClass,
  &AVR::PTRREGSRegClass,
  nullptr
};

static const TargetRegisterClass *const DREGS_WITHOUT_YZ_WORKAROUND_and_PTRREGSSuperclasses[] = {
  &AVR::DREGSRegClass,
  &AVR::DREGS_WITHOUT_YZ_WORKAROUNDRegClass,
  &AVR::DLDREGSRegClass,
  &AVR::DLDREGS_and_DREGS_WITHOUT_YZ_WORKAROUNDRegClass,
  &AVR::IWREGSRegClass,
  &AVR::PTRREGSRegClass,
  &AVR::DREGS_WITHOUT_YZ_WORKAROUND_and_IWREGSRegClass,
  nullptr
};

static const TargetRegisterClass *const ZREGSuperclasses[] = {
  &AVR::DREGSRegClass,
  &AVR::DLDREGSRegClass,
  &AVR::IWREGSRegClass,
  &AVR::PTRREGSRegClass,
  &AVR::PTRDISPREGSRegClass,
  nullptr
};


namespace AVR {   // Register class instances
  extern const TargetRegisterClass GPR8RegClass = {
    &AVRMCRegisterClasses[GPR8RegClassID],
    GPR8SubClassMask,
    SuperRegIdxSeqs + 0,
    LaneBitmask(0x00000001),
    0,
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass GPR8loRegClass = {
    &AVRMCRegisterClasses[GPR8loRegClassID],
    GPR8loSubClassMask,
    SuperRegIdxSeqs + 0,
    LaneBitmask(0x00000001),
    0,
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    GPR8loSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass LD8RegClass = {
    &AVRMCRegisterClasses[LD8RegClassID],
    LD8SubClassMask,
    SuperRegIdxSeqs + 0,
    LaneBitmask(0x00000001),
    0,
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    LD8Superclasses,
    nullptr
  };

  extern const TargetRegisterClass LD8loRegClass = {
    &AVRMCRegisterClasses[LD8loRegClassID],
    LD8loSubClassMask,
    SuperRegIdxSeqs + 0,
    LaneBitmask(0x00000001),
    0,
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    LD8loSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass CCRRegClass = {
    &AVRMCRegisterClasses[CCRRegClassID],
    CCRSubClassMask,
    SuperRegIdxSeqs + 2,
    LaneBitmask(0x00000001),
    0,
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass DREGSRegClass = {
    &AVRMCRegisterClasses[DREGSRegClassID],
    DREGSSubClassMask,
    SuperRegIdxSeqs + 2,
    LaneBitmask(0x00000003),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass DREGS_WITHOUT_YZ_WORKAROUNDRegClass = {
    &AVRMCRegisterClasses[DREGS_WITHOUT_YZ_WORKAROUNDRegClassID],
    DREGS_WITHOUT_YZ_WORKAROUNDSubClassMask,
    SuperRegIdxSeqs + 2,
    LaneBitmask(0x00000003),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    DREGS_WITHOUT_YZ_WORKAROUNDSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass DLDREGSRegClass = {
    &AVRMCRegisterClasses[DLDREGSRegClassID],
    DLDREGSSubClassMask,
    SuperRegIdxSeqs + 2,
    LaneBitmask(0x00000003),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    DLDREGSSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass DREGS_with_sub_hi_in_GPR8loRegClass = {
    &AVRMCRegisterClasses[DREGS_with_sub_hi_in_GPR8loRegClassID],
    DREGS_with_sub_hi_in_GPR8loSubClassMask,
    SuperRegIdxSeqs + 2,
    LaneBitmask(0x00000003),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    DREGS_with_sub_hi_in_GPR8loSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass DLDREGS_and_DREGS_WITHOUT_YZ_WORKAROUNDRegClass = {
    &AVRMCRegisterClasses[DLDREGS_and_DREGS_WITHOUT_YZ_WORKAROUNDRegClassID],
    DLDREGS_and_DREGS_WITHOUT_YZ_WORKAROUNDSubClassMask,
    SuperRegIdxSeqs + 2,
    LaneBitmask(0x00000003),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    DLDREGS_and_DREGS_WITHOUT_YZ_WORKAROUNDSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass DLDREGS_with_sub_hi_in_LD8loRegClass = {
    &AVRMCRegisterClasses[DLDREGS_with_sub_hi_in_LD8loRegClassID],
    DLDREGS_with_sub_hi_in_LD8loSubClassMask,
    SuperRegIdxSeqs + 2,
    LaneBitmask(0x00000003),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    DLDREGS_with_sub_hi_in_LD8loSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass IWREGSRegClass = {
    &AVRMCRegisterClasses[IWREGSRegClassID],
    IWREGSSubClassMask,
    SuperRegIdxSeqs + 2,
    LaneBitmask(0x00000003),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    IWREGSSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass PTRREGSRegClass = {
    &AVRMCRegisterClasses[PTRREGSRegClassID],
    PTRREGSSubClassMask,
    SuperRegIdxSeqs + 2,
    LaneBitmask(0x00000003),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    PTRREGSSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass DREGS_WITHOUT_YZ_WORKAROUND_and_IWREGSRegClass = {
    &AVRMCRegisterClasses[DREGS_WITHOUT_YZ_WORKAROUND_and_IWREGSRegClassID],
    DREGS_WITHOUT_YZ_WORKAROUND_and_IWREGSSubClassMask,
    SuperRegIdxSeqs + 2,
    LaneBitmask(0x00000003),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    DREGS_WITHOUT_YZ_WORKAROUND_and_IWREGSSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass PTRDISPREGSRegClass = {
    &AVRMCRegisterClasses[PTRDISPREGSRegClassID],
    PTRDISPREGSSubClassMask,
    SuperRegIdxSeqs + 2,
    LaneBitmask(0x00000003),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    PTRDISPREGSSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass DREGS_WITHOUT_YZ_WORKAROUND_and_PTRREGSRegClass = {
    &AVRMCRegisterClasses[DREGS_WITHOUT_YZ_WORKAROUND_and_PTRREGSRegClassID],
    DREGS_WITHOUT_YZ_WORKAROUND_and_PTRREGSSubClassMask,
    SuperRegIdxSeqs + 2,
    LaneBitmask(0x00000003),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    DREGS_WITHOUT_YZ_WORKAROUND_and_PTRREGSSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass GPRSPRegClass = {
    &AVRMCRegisterClasses[GPRSPRegClassID],
    GPRSPSubClassMask,
    SuperRegIdxSeqs + 2,
    LaneBitmask(0x00000003),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass ZREGRegClass = {
    &AVRMCRegisterClasses[ZREGRegClassID],
    ZREGSubClassMask,
    SuperRegIdxSeqs + 2,
    LaneBitmask(0x00000003),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    ZREGSuperclasses,
    nullptr
  };

} // end namespace AVR

namespace {
  const TargetRegisterClass* const RegisterClasses[] = {
    &AVR::GPR8RegClass,
    &AVR::GPR8loRegClass,
    &AVR::LD8RegClass,
    &AVR::LD8loRegClass,
    &AVR::CCRRegClass,
    &AVR::DREGSRegClass,
    &AVR::DREGS_WITHOUT_YZ_WORKAROUNDRegClass,
    &AVR::DLDREGSRegClass,
    &AVR::DREGS_with_sub_hi_in_GPR8loRegClass,
    &AVR::DLDREGS_and_DREGS_WITHOUT_YZ_WORKAROUNDRegClass,
    &AVR::DLDREGS_with_sub_hi_in_LD8loRegClass,
    &AVR::IWREGSRegClass,
    &AVR::PTRREGSRegClass,
    &AVR::DREGS_WITHOUT_YZ_WORKAROUND_and_IWREGSRegClass,
    &AVR::PTRDISPREGSRegClass,
    &AVR::DREGS_WITHOUT_YZ_WORKAROUND_and_PTRREGSRegClass,
    &AVR::GPRSPRegClass,
    &AVR::ZREGRegClass,
  };
} // end anonymous namespace

static const TargetRegisterInfoDesc AVRRegInfoDesc[] = { // Extra Descriptors
  { 0, false },
  { 0, true },
  { 0, false },
  { 0, false },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
};
unsigned AVRGenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
  static const uint8_t Rows[1][2] = {
    { 0, 0, },
  };

  --IdxA; assert(IdxA < 2);
  --IdxB; assert(IdxB < 2);
  return Rows[0][IdxB];
}

  struct MaskRolOp {
    LaneBitmask Mask;
    uint8_t  RotateLeft;
  };
  static const MaskRolOp LaneMaskComposeSequences[] = {
    { LaneBitmask(0xFFFFFFFF),  0 }, { LaneBitmask::getNone(), 0 },   // Sequence 0
    { LaneBitmask(0xFFFFFFFF),  1 }, { LaneBitmask::getNone(), 0 }  // Sequence 2
  };
  static const MaskRolOp *const CompositeSequences[] = {
    &LaneMaskComposeSequences[0], // to sub_hi
    &LaneMaskComposeSequences[2] // to sub_lo
  };

LaneBitmask AVRGenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
  --IdxA; assert(IdxA < 2 && "Subregister index out of bounds");
  LaneBitmask Result;
  for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any(); ++Ops) {
    LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();
    if (unsigned S = Ops->RotateLeft)
      Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S)));
    else
      Result |= LaneBitmask(M);
  }
  return Result;
}

LaneBitmask AVRGenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA,  LaneBitmask LaneMask) const {
  LaneMask &= getSubRegIndexLaneMask(IdxA);
  --IdxA; assert(IdxA < 2 && "Subregister index out of bounds");
  LaneBitmask Result;
  for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any(); ++Ops) {
    LaneBitmask::Type M = LaneMask.getAsInteger();
    if (unsigned S = Ops->RotateLeft)
      Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S)));
    else
      Result |= LaneBitmask(M);
  }
  return Result;
}

const TargetRegisterClass *AVRGenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
  static const uint8_t Table[18][2] = {
    {	// GPR8
      0,	// sub_hi
      0,	// sub_lo
    },
    {	// GPR8lo
      0,	// sub_hi
      0,	// sub_lo
    },
    {	// LD8
      0,	// sub_hi
      0,	// sub_lo
    },
    {	// LD8lo
      0,	// sub_hi
      0,	// sub_lo
    },
    {	// CCR
      0,	// sub_hi
      0,	// sub_lo
    },
    {	// DREGS
      6,	// sub_hi -> DREGS
      6,	// sub_lo -> DREGS
    },
    {	// DREGS_WITHOUT_YZ_WORKAROUND
      7,	// sub_hi -> DREGS_WITHOUT_YZ_WORKAROUND
      7,	// sub_lo -> DREGS_WITHOUT_YZ_WORKAROUND
    },
    {	// DLDREGS
      8,	// sub_hi -> DLDREGS
      8,	// sub_lo -> DLDREGS
    },
    {	// DREGS_with_sub_hi_in_GPR8lo
      9,	// sub_hi -> DREGS_with_sub_hi_in_GPR8lo
      9,	// sub_lo -> DREGS_with_sub_hi_in_GPR8lo
    },
    {	// DLDREGS_and_DREGS_WITHOUT_YZ_WORKAROUND
      10,	// sub_hi -> DLDREGS_and_DREGS_WITHOUT_YZ_WORKAROUND
      10,	// sub_lo -> DLDREGS_and_DREGS_WITHOUT_YZ_WORKAROUND
    },
    {	// DLDREGS_with_sub_hi_in_LD8lo
      11,	// sub_hi -> DLDREGS_with_sub_hi_in_LD8lo
      11,	// sub_lo -> DLDREGS_with_sub_hi_in_LD8lo
    },
    {	// IWREGS
      12,	// sub_hi -> IWREGS
      12,	// sub_lo -> IWREGS
    },
    {	// PTRREGS
      13,	// sub_hi -> PTRREGS
      13,	// sub_lo -> PTRREGS
    },
    {	// DREGS_WITHOUT_YZ_WORKAROUND_and_IWREGS
      14,	// sub_hi -> DREGS_WITHOUT_YZ_WORKAROUND_and_IWREGS
      14,	// sub_lo -> DREGS_WITHOUT_YZ_WORKAROUND_and_IWREGS
    },
    {	// PTRDISPREGS
      15,	// sub_hi -> PTRDISPREGS
      15,	// sub_lo -> PTRDISPREGS
    },
    {	// DREGS_WITHOUT_YZ_WORKAROUND_and_PTRREGS
      16,	// sub_hi -> DREGS_WITHOUT_YZ_WORKAROUND_and_PTRREGS
      16,	// sub_lo -> DREGS_WITHOUT_YZ_WORKAROUND_and_PTRREGS
    },
    {	// GPRSP
      17,	// sub_hi -> GPRSP
      17,	// sub_lo -> GPRSP
    },
    {	// ZREG
      18,	// sub_hi -> ZREG
      18,	// sub_lo -> ZREG
    },
  };
  assert(RC && "Missing regclass");
  if (!Idx) return RC;
  --Idx;
  assert(Idx < 2 && "Bad subreg");
  unsigned TV = Table[RC->getID()][Idx];
  return TV ? getRegClass(TV - 1) : nullptr;
}

/// Get the weight in units of pressure for this register class.
const RegClassWeight &AVRGenRegisterInfo::
getRegClassWeight(const TargetRegisterClass *RC) const {
  static const RegClassWeight RCWeightTable[] = {
    {1, 32},  	// GPR8
    {1, 16},  	// GPR8lo
    {1, 16},  	// LD8
    {1, 8},  	// LD8lo
    {1, 1},  	// CCR
    {2, 32},  	// DREGS
    {2, 28},  	// DREGS_WITHOUT_YZ_WORKAROUND
    {2, 16},  	// DLDREGS
    {2, 16},  	// DREGS_with_sub_hi_in_GPR8lo
    {2, 12},  	// DLDREGS_and_DREGS_WITHOUT_YZ_WORKAROUND
    {2, 8},  	// DLDREGS_with_sub_hi_in_LD8lo
    {2, 8},  	// IWREGS
    {2, 6},  	// PTRREGS
    {2, 4},  	// DREGS_WITHOUT_YZ_WORKAROUND_and_IWREGS
    {2, 4},  	// PTRDISPREGS
    {2, 2},  	// DREGS_WITHOUT_YZ_WORKAROUND_and_PTRREGS
    {2, 2},  	// GPRSP
    {2, 2},  	// ZREG
  };
  return RCWeightTable[RC->getID()];
}

/// Get the weight in units of pressure for this register unit.
unsigned AVRGenRegisterInfo::
getRegUnitWeight(unsigned RegUnit) const {
  assert(RegUnit < 35 && "invalid register unit");
  // All register units have unit weight.
  return 1;
}


// Get the number of dimensions of register pressure.
unsigned AVRGenRegisterInfo::getNumRegPressureSets() const {
  return 10;
}

// Get the name of this register unit pressure set.
const char *AVRGenRegisterInfo::
getRegPressureSetName(unsigned Idx) const {
  static const char *const PressureNameTable[] = {
    "CCR",
    "GPRSP",
    "DREGS_WITHOUT_YZ_WORKAROUND_and_IWREGS",
    "LD8lo",
    "IWREGS",
    "DLDREGS_and_DREGS_WITHOUT_YZ_WORKAROUND",
    "GPR8lo",
    "LD8",
    "DREGS_WITHOUT_YZ_WORKAROUND",
    "GPR8",
  };
  return PressureNameTable[Idx];
}

// Get the register unit pressure limit for this dimension.
// This limit must be adjusted dynamically for reserved registers.
unsigned AVRGenRegisterInfo::
getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
  static const uint8_t PressureLimitTable[] = {
    1,  	// 0: CCR
    2,  	// 1: GPRSP
    4,  	// 2: DREGS_WITHOUT_YZ_WORKAROUND_and_IWREGS
    8,  	// 3: LD8lo
    8,  	// 4: IWREGS
    12,  	// 5: DLDREGS_and_DREGS_WITHOUT_YZ_WORKAROUND
    16,  	// 6: GPR8lo
    16,  	// 7: LD8
    28,  	// 8: DREGS_WITHOUT_YZ_WORKAROUND
    32,  	// 9: GPR8
  };
  return PressureLimitTable[Idx];
}

/// Table of pressure sets per register class or unit.
static const int RCSetsTable[] = {
  /* 0 */ 0, -1,
  /* 2 */ 1, -1,
  /* 4 */ 4, 7, 9, -1,
  /* 8 */ 6, 8, 9, -1,
  /* 12 */ 3, 5, 7, 8, 9, -1,
  /* 18 */ 2, 4, 5, 7, 8, 9, -1,
};

/// Get the dimensions of register pressure impacted by this register class.
/// Returns a -1 terminated array of pressure set IDs
const int* AVRGenRegisterInfo::
getRegClassPressureSets(const TargetRegisterClass *RC) const {
  static const uint8_t RCSetStartTable[] = {
    6,8,5,12,0,6,9,5,8,13,12,4,4,18,4,18,2,4,};
  return &RCSetsTable[RCSetStartTable[RC->getID()]];
}

/// Get the dimensions of register pressure impacted by this register unit.
/// Returns a -1 terminated array of pressure set IDs
const int* AVRGenRegisterInfo::
getRegUnitPressureSets(unsigned RegUnit) const {
  assert(RegUnit < 35 && "invalid register unit");
  static const uint8_t RUSetStartTable[] = {
    2,2,0,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,12,12,12,12,12,12,12,12,18,18,18,18,4,4,4,4,};
  return &RCSetsTable[RUSetStartTable[RegUnit]];
}

extern const MCRegisterDesc AVRRegDesc[];
extern const MCPhysReg AVRRegDiffLists[];
extern const LaneBitmask AVRLaneMaskLists[];
extern const char AVRRegStrings[];
extern const char AVRRegClassStrings[];
extern const MCPhysReg AVRRegUnitRoots[][2];
extern const uint16_t AVRSubRegIdxLists[];
extern const MCRegisterInfo::SubRegCoveredBits AVRSubRegIdxRanges[];
extern const uint16_t AVRRegEncodingTable[];
// AVR Dwarf<->LLVM register mappings.
extern const MCRegisterInfo::DwarfLLVMRegPair AVRDwarfFlavour0Dwarf2L[];
extern const unsigned AVRDwarfFlavour0Dwarf2LSize;

extern const MCRegisterInfo::DwarfLLVMRegPair AVREHFlavour0Dwarf2L[];
extern const unsigned AVREHFlavour0Dwarf2LSize;

extern const MCRegisterInfo::DwarfLLVMRegPair AVRDwarfFlavour0L2Dwarf[];
extern const unsigned AVRDwarfFlavour0L2DwarfSize;

extern const MCRegisterInfo::DwarfLLVMRegPair AVREHFlavour0L2Dwarf[];
extern const unsigned AVREHFlavour0L2DwarfSize;

AVRGenRegisterInfo::
AVRGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
      unsigned PC, unsigned HwMode)
  : TargetRegisterInfo(AVRRegInfoDesc, RegisterClasses, RegisterClasses+18,
             SubRegIndexNameTable, SubRegIndexLaneMaskTable,
             LaneBitmask(0xFFFFFFFF), RegClassInfos, HwMode) {
  InitMCRegisterInfo(AVRRegDesc, 53, RA, PC,
                     AVRMCRegisterClasses, 18,
                     AVRRegUnitRoots,
                     35,
                     AVRRegDiffLists,
                     AVRLaneMaskLists,
                     AVRRegStrings,
                     AVRRegClassStrings,
                     AVRSubRegIdxLists,
                     3,
                     AVRSubRegIdxRanges,
                     AVRRegEncodingTable);

  switch (DwarfFlavour) {
  default:
    llvm_unreachable("Unknown DWARF flavour");
  case 0:
    mapDwarfRegsToLLVMRegs(AVRDwarfFlavour0Dwarf2L, AVRDwarfFlavour0Dwarf2LSize, false);
    break;
  }
  switch (EHFlavour) {
  default:
    llvm_unreachable("Unknown DWARF flavour");
  case 0:
    mapDwarfRegsToLLVMRegs(AVREHFlavour0Dwarf2L, AVREHFlavour0Dwarf2LSize, true);
    break;
  }
  switch (DwarfFlavour) {
  default:
    llvm_unreachable("Unknown DWARF flavour");
  case 0:
    mapLLVMRegsToDwarfRegs(AVRDwarfFlavour0L2Dwarf, AVRDwarfFlavour0L2DwarfSize, false);
    break;
  }
  switch (EHFlavour) {
  default:
    llvm_unreachable("Unknown DWARF flavour");
  case 0:
    mapLLVMRegsToDwarfRegs(AVREHFlavour0L2Dwarf, AVREHFlavour0L2DwarfSize, true);
    break;
  }
}

static const MCPhysReg CSR_Interrupts_SaveList[] = { AVR::R31, AVR::R30, AVR::R29, AVR::R28, AVR::R27, AVR::R26, AVR::R25, AVR::R24, AVR::R23, AVR::R22, AVR::R21, AVR::R20, AVR::R19, AVR::R18, AVR::R17, AVR::R16, AVR::R15, AVR::R14, AVR::R13, AVR::R12, AVR::R11, AVR::R10, AVR::R9, AVR::R8, AVR::R7, AVR::R6, AVR::R5, AVR::R4, AVR::R3, AVR::R2, AVR::R1, AVR::R0, 0 };
static const uint32_t CSR_Interrupts_RegMask[] = { 0xffffffe0, 0x001fffff, };
static const MCPhysReg CSR_Normal_SaveList[] = { AVR::R29, AVR::R28, AVR::R17, AVR::R16, AVR::R15, AVR::R14, AVR::R13, AVR::R12, AVR::R11, AVR::R10, AVR::R9, AVR::R8, AVR::R7, AVR::R6, AVR::R5, AVR::R4, AVR::R3, AVR::R2, 0 };
static const uint32_t CSR_Normal_RegMask[] = { 0x007fff80, 0x00083fc6, };


ArrayRef<const uint32_t *> AVRGenRegisterInfo::getRegMasks() const {
  static const uint32_t *const Masks[] = {
    CSR_Interrupts_RegMask,
    CSR_Normal_RegMask,
  };
  return makeArrayRef(Masks);
}

ArrayRef<const char *> AVRGenRegisterInfo::getRegMaskNames() const {
  static const char *const Names[] = {
    "CSR_Interrupts",
    "CSR_Normal",
  };
  return makeArrayRef(Names);
}

const AVRFrameLowering *
AVRGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
  return static_cast<const AVRFrameLowering *>(
      MF.getSubtarget().getFrameLowering());
}

} // end namespace llvm

#endif // GET_REGINFO_TARGET_DESC