reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

gen/lib/Target/AArch64/AArch64GenRegisterInfo.inc

 9132   LaneMask &= getSubRegIndexLaneMask(IdxA);

gen/lib/Target/AMDGPU/AMDGPUGenRegisterInfo.inc

25782   LaneMask &= getSubRegIndexLaneMask(IdxA);

gen/lib/Target/AMDGPU/R600GenRegisterInfo.inc

11494   LaneMask &= getSubRegIndexLaneMask(IdxA);

gen/lib/Target/ARM/ARMGenRegisterInfo.inc

 8552   LaneMask &= getSubRegIndexLaneMask(IdxA);

gen/lib/Target/AVR/AVRGenRegisterInfo.inc

 1472   LaneMask &= getSubRegIndexLaneMask(IdxA);

gen/lib/Target/BPF/BPFGenRegisterInfo.inc

  563   LaneMask &= getSubRegIndexLaneMask(IdxA);

gen/lib/Target/Hexagon/HexagonGenRegisterInfo.inc

 3230   LaneMask &= getSubRegIndexLaneMask(IdxA);

gen/lib/Target/Lanai/LanaiGenRegisterInfo.inc

  783   LaneMask &= getSubRegIndexLaneMask(IdxA);

gen/lib/Target/MSP430/MSP430GenRegisterInfo.inc

  496   LaneMask &= getSubRegIndexLaneMask(IdxA);

gen/lib/Target/Mips/MipsGenRegisterInfo.inc

 6211   LaneMask &= getSubRegIndexLaneMask(IdxA);

gen/lib/Target/PowerPC/PPCGenRegisterInfo.inc

 5209   LaneMask &= getSubRegIndexLaneMask(IdxA);

gen/lib/Target/RISCV/RISCVGenRegisterInfo.inc

 1637   LaneMask &= getSubRegIndexLaneMask(IdxA);

gen/lib/Target/Sparc/SparcGenRegisterInfo.inc

 2536   LaneMask &= getSubRegIndexLaneMask(IdxA);

gen/lib/Target/SystemZ/SystemZGenRegisterInfo.inc

 2623   LaneMask &= getSubRegIndexLaneMask(IdxA);

gen/lib/Target/X86/X86GenRegisterInfo.inc

 8158   LaneMask &= getSubRegIndexLaneMask(IdxA);

lib/CodeGen/DetectDeadLanes.cpp

  257       MO1UsedLanes = UsedLanes & ~TRI->getSubRegIndexLaneMask(SubIdx);
  318     DefinedLanes &= TRI->getSubRegIndexLaneMask(SubIdx);
  325       DefinedLanes &= TRI->getSubRegIndexLaneMask(SubIdx);
  329       DefinedLanes &= ~TRI->getSubRegIndexLaneMask(SubIdx);
  453     UsedLanes |= TRI->getSubRegIndexLaneMask(SubReg);
  461   LaneBitmask Mask = TRI->getSubRegIndexLaneMask(SubReg);

lib/CodeGen/LiveInterval.cpp

  908       if ((TRI.getSubRegIndexLaneMask(MOI->getSubReg()) & LaneMask).none())
  980     LaneBitmask DefMask = TRI.getSubRegIndexLaneMask(SubReg);

lib/CodeGen/LiveIntervals.cpp

  558       LaneBitmask LaneMask = TRI->getSubRegIndexLaneMask(SubReg);
  783             LaneBitmask UseMask = TRI->getSubRegIndexLaneMask(MO.getSubReg());
  996           LaneBitmask LaneMask = SubReg ? TRI.getSubRegIndexLaneMask(SubReg)
 1409             && (TRI.getSubRegIndexLaneMask(SubReg) & LaneMask).none())
 1518       LaneBitmask Mask = TRI->getSubRegIndexLaneMask(SubReg);

lib/CodeGen/LivePhysRegs.cpp

  169       if ((Mask & TRI->getSubRegIndexLaneMask(SI)).any())

lib/CodeGen/LiveRangeCalc.cpp

   88       LaneBitmask SubMask = SubReg != 0 ? TRI.getSubRegIndexLaneMask(SubReg)
  179       LaneBitmask SLM = TRI.getSubRegIndexLaneMask(SubReg);

lib/CodeGen/LiveRangeEdit.cpp

  251   LaneBitmask LaneMask = TRI.getSubRegIndexLaneMask(SubReg);

lib/CodeGen/MachineVerifier.cpp

 1977                                ? TRI->getSubRegIndexLaneMask(SubRegIdx)
 2080               ? TRI->getSubRegIndexLaneMask(SubRegIdx)
 2427           (TRI->getSubRegIndexLaneMask(MOI->getSubReg()) & LaneMask).none())
 2559       LaneBitmask SLM = Sub != 0 ? TRI->getSubRegIndexLaneMask(Sub)

lib/CodeGen/PeepholeOptimizer.cpp

 1967       !(TRI->getSubRegIndexLaneMask(DefSubReg) &
 1968         TRI->getSubRegIndexLaneMask(InsertedReg.SubIdx)).none())

lib/CodeGen/RegisterCoalescer.cpp

 1411       LaneBitmask DstMask = TRI->getSubRegIndexLaneMask(NewIdx);
 1534     LaneBitmask SrcMask = TRI->getSubRegIndexLaneMask(SrcSubIdx);
 1573     LaneBitmask DstMask = TRI->getSubRegIndexLaneMask(DstSubIdx);
 1592     LaneBitmask UseMask = TRI->getSubRegIndexLaneMask(MO.getSubReg());
 1627   LaneBitmask Mask = TRI->getSubRegIndexLaneMask(SubRegIdx);
 2396     L |= TRI->getSubRegIndexLaneMask(
 2496                                      : TRI->getSubRegIndexLaneMask(SubIdx);
 2700   if ((TRI->getSubRegIndexLaneMask(Other.SubIdx) & ~V.WriteLanes).none())
 2833     if ((Lanes & TRI->getSubRegIndexLaneMask(S)).any())
 3335                                      : TRI->getSubRegIndexLaneMask(DstIdx);
 3353                                      : TRI->getSubRegIndexLaneMask(SrcIdx);

lib/CodeGen/RegisterPressure.cpp

  556                              ? TRI.getSubRegIndexLaneMask(SubRegIdx)
 1234       LaneBitmask UseMask = TRI.getSubRegIndexLaneMask(SubRegIdx);

lib/CodeGen/RenameIndependentSubregs.cpp

  182     LaneBitmask LaneMask = TRI.getSubRegIndexLaneMask(SubRegIdx);
  226     LaneBitmask LaneMask = TRI.getSubRegIndexLaneMask(SubRegIdx);

lib/CodeGen/ScheduleDAGInstrs.cpp

  372   return TRI->getSubRegIndexLaneMask(SubReg);

lib/CodeGen/SplitKit.cpp

  444         LM |= TRI.getSubRegIndexLaneMask(SR);
  529   LaneBitmask LaneMask = TRI.getSubRegIndexLaneMask(SubIdx);
  566     LaneBitmask SubRegMask = TRI.getSubRegIndexLaneMask(Idx);
  594   LaneBitmask LanesLeft = LaneMask & ~(TRI.getSubRegIndexLaneMask(BestIdx));
  599       LaneBitmask SubRegMask = TRI.getSubRegIndexLaneMask(Idx);
  621     LanesLeft &= ~TRI.getSubRegIndexLaneMask(BestIdx);
 1377     LaneBitmask LM = Sub != 0 ? TRI.getSubRegIndexLaneMask(Sub)

lib/CodeGen/VirtRegMap.cpp

  365   LaneBitmask UseMask = TRI->getSubRegIndexLaneMask(SubRegIdx);

lib/Target/AMDGPU/GCNRegBankReassign.cpp

  374       unsigned LM = TRI->getSubRegIndexLaneMask(Op.getSubReg()).getAsInteger();
  498   unsigned LM = TRI->getSubRegIndexLaneMask(SubReg).getAsInteger();

lib/Target/AMDGPU/GCNRegPressure.cpp

  207     MRI.getTargetRegisterInfo()->getSubRegIndexLaneMask(MO.getSubReg());
  216     return MRI.getTargetRegisterInfo()->getSubRegIndexLaneMask(SubReg);

lib/Target/AMDGPU/SIFormMemoryClauses.cpp

  168     LaneBitmask SubRegMask = TRI->getSubRegIndexLaneMask(Idx);
  182     LaneBitmask MaskA = TRI->getSubRegIndexLaneMask(A);
  183     LaneBitmask MaskB = TRI->getSubRegIndexLaneMask(B);
  192     LaneBitmask SubRegMask = TRI->getSubRegIndexLaneMask(Idx);
  233     LaneBitmask Mask = TRI->getSubRegIndexLaneMask(MO.getSubReg());
  273                            ? TRI->getSubRegIndexLaneMask(MO.getSubReg())

lib/Target/AMDGPU/SIInstrInfo.h

  825         return RI.getSubRegIndexLaneMask(SubReg).getNumLanes() * 4;

lib/Target/AMDGPU/SIRegisterInfo.cpp

 1410   unsigned Count = getSubRegIndexLaneMask(SubIdx).getNumLanes();
 1876     LaneBitmask SubLanes = SubReg ? getSubRegIndexLaneMask(SubReg)

lib/Target/AMDGPU/SIShrinkInstructions.cpp

  401       LaneBitmask Overlap = TRI.getSubRegIndexLaneMask(SubReg) &
  402                             TRI.getSubRegIndexLaneMask(MO.getSubReg());
  429       LaneBitmask LM = TRI.getSubRegIndexLaneMask(Sub);

lib/Target/Hexagon/HexagonBlockRanges.cpp

  246       if ((I.LaneMask & TRI.getSubRegIndexLaneMask(SI)).any())

lib/Target/Hexagon/HexagonExpandCondsets.cpp

  289   return Sub != 0 ? TRI->getSubRegIndexLaneMask(Sub)

lib/Target/Hexagon/RDFCopy.cpp

  127       if (RR.Mask == TRI.getSubRegIndexLaneMask(S.getSubRegIndex()))

lib/Target/Hexagon/RDFLiveness.cpp

  866         LaneBitmask M = TRI.getSubRegIndexLaneMask(S.getSubRegIndex());

lib/Target/Hexagon/RDFRegisters.cpp

  182     LaneBitmask SM = TRI.getSubRegIndexLaneMask(SI.getSubRegIndex());