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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
lib/CodeGen/InlineSpiller.cpp 375 VNInfo *VNI = SpillLI.getVNInfoAt(Idx.getRegSlot());
376 assert(VNI && VNI->def == Idx.getRegSlot() && "Not defined by copy");
461 VNInfo *DstVNI = DstLI.getVNInfoAt(Idx.getRegSlot());
463 assert(DstVNI->def == Idx.getRegSlot() && "Wrong copy def slot");
514 VNInfo *SnipVNI = SnipLI.getVNInfoAt(VNI->def.getRegSlot(true));
552 SlotIndex UseIdx = LIS.getInstructionIndex(MI).getRegSlot(true);
766 SlotIndex Idx = LIS.getInstructionIndex(*I).getRegSlot();
774 Idx = Idx.getRegSlot(true);
860 SlotIndex Idx = LIS.getInstructionIndex(*MI).getRegSlot();
1000 SlotIndex Idx = LIS.getInstructionIndex(*MI).getRegSlot();
1001 if (VNInfo *VNI = OldLI.getVNInfoAt(Idx.getRegSlot(true)))
1153 VNInfo *OrigVNI = StackSlotToOrigLI[StackSlot]->getVNInfoAt(Idx.getRegSlot());
1166 VNInfo *OrigVNI = It->second->getVNInfoAt(Idx.getRegSlot());
lib/CodeGen/LiveDebugVariables.cpp 699 : LIS->getInstructionIndex(*std::prev(MBBI)).getRegSlot();
790 LocMap::iterator I = locInts.find(Idx.getRegSlot(true));
797 const VNInfo *DstVNI = DstLI->getVNInfoAt(Idx.getRegSlot());
798 assert(DstVNI && DstVNI->def == Idx.getRegSlot() && "Bad copy value");
lib/CodeGen/LiveInterval.cpp 985 SlotIndex Pos = Indexes.getInstructionIndex(MI).getRegSlot(EarlyClobber);
lib/CodeGen/LiveIntervals.cpp 229 RegMaskSlots.push_back(Indexes->getInstructionIndex(MI).getRegSlot());
240 Indexes->getInstructionIndex(MBB.back()).getRegSlot());
465 SlotIndex Idx = getInstructionIndex(UseMI).getRegSlot();
564 SlotIndex Idx = getInstructionIndex(*UseMI).getRegSlot();
871 SlotIndex(getInstructionIndex(startInst).getRegSlot()),
873 LiveRange::Segment S(SlotIndex(getInstructionIndex(startInst).getRegSlot()),
1080 Prev->end = NewIdx.getRegSlot();
1090 OldIdxIn->end = NewIdx.getRegSlot(OldIdxIn->end.isEarlyClobber());
1112 SlotIndex NewIdxDef = NewIdx.getRegSlot(OldIdxOut->start.isEarlyClobber());
1124 = LR.advanceTo(OldIdxOut, NewIdx.getRegSlot());
1241 NewIdx.getRegSlot(OldIdxIn->end.isEarlyClobber()));
1262 SlotIndex NewIdxDef = NewIdx.getRegSlot(OldIdxOut->start.isEarlyClobber());
1263 LiveRange::iterator NewIdxOut = LR.find(NewIdx.getRegSlot());
1336 OldIdxIn->end = NewIdx.getRegSlot();
1354 NewIdxOut->start, NewIdxDef.getRegSlot(), NewIdxOut->valno);
1356 NewIdxDef.getRegSlot(), (NewIdxOut + 1)->end, OldIdxVNI);
1388 assert(RI != LIS.RegMaskSlots.end() && *RI == OldIdx.getRegSlot() &&
1390 *RI = NewIdx.getRegSlot();
1415 LastUse = InstSlot.getRegSlot();
1449 return Idx.getRegSlot();
1537 LII->start = instrIdx.getRegSlot();
1538 LII->valno->def = instrIdx.getRegSlot();
1540 lastUseIdx = instrIdx.getRegSlot();
1548 VNInfo *VNI = LR.getNextValue(instrIdx.getRegSlot(), VNInfoAllocator);
1549 LiveRange::Segment S(instrIdx.getRegSlot(),
1552 } else if (LII->start != instrIdx.getRegSlot()) {
1553 VNInfo *VNI = LR.getNextValue(instrIdx.getRegSlot(), VNInfoAllocator);
1554 LiveRange::Segment S(instrIdx.getRegSlot(), lastUseIdx, VNI);
1559 lastUseIdx = instrIdx.getRegSlot();
1567 LII->end = instrIdx.getRegSlot();
1569 lastUseIdx = instrIdx.getRegSlot();
lib/CodeGen/LiveRangeCalc.cpp 68 Indexes.getInstructionIndex(MI).getRegSlot(MO.isEarlyClobber());
207 UseIdx = Indexes->getInstructionIndex(*MI).getRegSlot(isEarlyClobber);
lib/CodeGen/LiveRangeEdit.cpp 109 OrigIdx = OrigIdx.getRegSlot(true);
110 UseIdx = UseIdx.getRegSlot(true);
177 return LIS.getSlotIndexes()->insertMachineInstrInMaps(*MI, Late).getRegSlot();
246 SlotIndex Idx = LIS.getInstructionIndex(MI).getRegSlot();
263 SlotIndex Idx = LIS.getInstructionIndex(*MI).getRegSlot();
lib/CodeGen/MachineScheduler.cpp 1405 SlotIndex SlotIdx = LIS->getInstructionIndex(*MI).getRegSlot();
1439 SlotIndex SlotIdx = LIS->getInstructionIndex(*MI).getRegSlot();
lib/CodeGen/MachineVerifier.cpp 1857 if (loads && !LI.liveAt(Idx.getRegSlot(true))) {
1861 if (stores && !LI.liveAt(Idx.getRegSlot())) {
2070 DefIdx = DefIdx.getRegSlot(MO->isEarlyClobber());
lib/CodeGen/PHIElimination.cpp 340 DestCopyIndex.getRegSlot(),
354 DestLI.createDeadDef(DestCopyIndex.getRegSlot(),
360 DestLI.removeSegment(MBBStartIndex, DestCopyIndex.getRegSlot());
361 VNInfo *DestVNI = DestLI.getVNInfoAt(DestCopyIndex.getRegSlot());
363 DestVNI->def = DestCopyIndex.getRegSlot();
532 SrcLI.removeSegment(LastUseIndex.getRegSlot(),
lib/CodeGen/RegAllocGreedy.cpp 2266 llvm::lower_bound(RMS, Uses.front().getRegSlot()) - RMS.begin();
lib/CodeGen/RegisterCoalescer.cpp 564 SlotIndex CopyIdx = LIS->getInstructionIndex(*CopyMI).getRegSlot();
592 SlotIndex CopyUseIdx = CopyIdx.getRegSlot(true);
769 SlotIndex CopyIdx = LIS->getInstructionIndex(*CopyMI).getRegSlot();
774 VNInfo *AValNo = IntA.getVNInfoAt(CopyIdx.getRegSlot(true));
873 SlotIndex UseIdx = LIS->getInstructionIndex(*UseMI).getRegSlot(true);
894 SlotIndex DefIdx = UseIdx.getRegSlot();
925 SlotIndex AIdx = CopyIdx.getRegSlot(true);
1044 SlotIndex CopyIdx = LIS->getInstructionIndex(CopyMI).getRegSlot(true);
1114 SlotIndex InsPosIdx = LIS->getInstructionIndex(*InsPos).getRegSlot(true);
1127 LIS->InsertMachineInstrInMaps(*NewCopyMI).getRegSlot();
1151 LIS->pruneValue(*static_cast<LiveRange *>(&IntB), CopyIdx.getRegSlot(),
1162 LIS->pruneValue(SR, CopyIdx.getRegSlot(), &EndPoints);
1386 CurrIdx.getRegSlot(NewMI.getOperand(0).isEarlyClobber());
1419 if (VNInfo *RmValNo = SR.getVNInfoAt(CurrIdx.getRegSlot())) {
1456 LR->createDeadDef(NewMIIdx.getRegSlot(), LIS->getVNInfoAllocator());
1471 LR->createDeadDef(NewMIIdx.getRegSlot(), LIS->getVNInfoAllocator());
1547 SlotIndex RegIndex = Idx.getRegSlot();
1665 SlotIndex UseIdx = LIS->getInstructionIndex(MI).getRegSlot(true);
1714 SlotIndex UseIdx = MIIdx.getRegSlot(true);
2054 SlotIndex CopyRegIdx = LIS->getInstructionIndex(*CopyMI).getRegSlot();
2055 SlotIndex DestRegIdx = LIS->getInstructionIndex(DestMI).getRegSlot();
lib/CodeGen/RegisterPressure.cpp 315 return LIS->getInstructionIndex(*IdxPos).getRegSlot();
799 SlotIdx = LIS->getInstructionIndex(*CurrPos).getRegSlot();
865 SlotIdx = LIS->getInstructionIndex(*CurrPos).getRegSlot();
885 SlotIndex SlotIdx = LIS->getInstructionIndex(*CurrPos).getRegSlot();
1046 SlotIdx = LIS->getInstructionIndex(*MI).getRegSlot();
1231 SlotIndex InstSlot = LIS->getInstructionIndex(*MI).getRegSlot();
1260 return S != nullptr && S->end == Pos.getRegSlot();
1271 return S != nullptr && S->start < Pos.getRegSlot(true) &&
1287 SlotIdx = LIS->getInstructionIndex(*MI).getRegSlot();
lib/CodeGen/RenameIndependentSubregs.cpp 189 Pos = MO.isDef() ? Pos.getRegSlot(MO.isEarlyClobber())
223 Pos = MO.isDef() ? Pos.getRegSlot(MO.isEarlyClobber())
335 SlotIndex RegDefIdx = DefIdx.getRegSlot();
lib/CodeGen/SplitKit.cpp 178 UseSlots.push_back(LIS.getInstructionIndex(*MO.getParent()).getRegSlot());
525 Def = Indexes.insertMachineInstrInMaps(*CopyMI, Late).getRegSlot();
547 return Indexes.insertMachineInstrInMaps(*CopyMI, Late).getRegSlot();
883 SlotIndex Kill = LIS.getInstructionIndex(*MBBI).getRegSlot();
1332 Idx = Idx.getRegSlot(MO.isEarlyClobber());
1355 Idx = Idx.getRegSlot(true);
lib/CodeGen/TwoAddressInstructionPass.cpp 1578 LastCopyIdx = LIS->InsertMachineInstrInMaps(*PrevMI).getRegSlot();
1584 LIS->getInstructionIndex(*MI).getRegSlot(IsEarlyClobber);
1647 SlotIndex UseIdx = MIIdx.getRegSlot(IsEarlyClobber);
lib/Target/AMDGPU/GCNIterativeScheduler.cpp 399 auto SlotIdx = LIS->getInstructionIndex(*MI).getRegSlot();
lib/Target/AMDGPU/GCNSchedStrategy.cpp 417 SlotIndex SlotIdx = LIS->getInstructionIndex(*MI).getRegSlot();
lib/Target/AMDGPU/SIMachineScheduler.cpp 318 SlotIndex InstSlot = LIS->getInstructionIndex(*MI).getRegSlot();
380 isDefBetween(Reg, LIS->getInstructionIndex(*BeginBlock).getRegSlot(),
381 LIS->getInstructionIndex(*EndBlock).getRegSlot(), MRI,
lib/Target/PowerPC/PPCVSXFMAMutate.cpp 281 VNInfo *FMAValNo = FMAInt.getVNInfoAt(FMAIdx.getRegSlot());
324 FMAIdx.getRegSlot());
lib/Target/SystemZ/SystemZInstrInfo.cpp 1017 LIS->getSlotIndexes()->getInstructionIndex(MI).getRegSlot();
lib/Target/WebAssembly/WebAssemblyMemIntrinsicResults.cpp 94 SlotIndex FromIdx = LIS.getInstructionIndex(MI).getRegSlot();
128 Indices.push_back(WhereIdx.getRegSlot());
lib/Target/WebAssembly/WebAssemblyOptimizeLiveIntervals.cpp 100 LIS.removeVRegDefAt(LI, LIS.getInstructionIndex(*MI).getRegSlot());
lib/Target/WebAssembly/WebAssemblyRegStackify.cpp 296 LI.getVNInfoAt(LIS.getInstructionIndex(*Def).getRegSlot());
511 LI.removeSegment(LIS.getInstructionIndex(*Def).getRegSlot(),
512 LIS.getInstructionIndex(*Op.getParent()).getRegSlot(),
561 SlotIndex Idx = LIS.getInstructionIndex(Def).getRegSlot();
619 SlotIndex TeeIdx = LIS.InsertMachineInstrInMaps(*Tee).getRegSlot();
620 SlotIndex DefIdx = LIS.getInstructionIndex(*Def).getRegSlot();