|
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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
include/llvm/CodeGen/LiveRegUnits.h 52 if (O->isRegMask())
include/llvm/CodeGen/MachineOperand.h 624 assert(isRegMask() && "Wrong MachineOperand accessor");
692 assert(isRegMask() && "Wrong MachineOperand mutator");
lib/CodeGen/AsmPrinter/DbgEntityHistoryCalculator.cpp 292 } else if (MO.isRegMask()) {
lib/CodeGen/BranchFolding.cpp 1916 if (MO.isRegMask())
2015 if (MO.isRegMask()) {
lib/CodeGen/CriticalAntiDepBreaker.cpp 264 if (MO.isRegMask())
364 if (CheckOper.isRegMask() && CheckOper.clobbersPhysReg(NewReg))
lib/CodeGen/DeadMachineInstructionElim.cpp 152 } else if (MO.isRegMask()) {
lib/CodeGen/EarlyIfConversion.cpp 256 if (MO.isRegMask()) {
lib/CodeGen/IfConversion.cpp 1496 if (Op.isRegMask()) {
lib/CodeGen/ImplicitNullChecks.cpp 235 auto IsRegMask = [](const MachineOperand &MO) { return MO.isRegMask(); };
lib/CodeGen/LiveDebugValues.cpp 823 } else if (MO.isRegMask()) {
lib/CodeGen/LiveIntervals.cpp 227 if (!MO.isRegMask())
977 if (MO.isRegMask())
lib/CodeGen/LivePhysRegs.cpp 53 } else if (O->isRegMask())
102 } else if (O->isRegMask())
112 if (Reg.second->isRegMask() &&
lib/CodeGen/LiveRegUnits.cpp 54 } else if (O->isRegMask())
79 } else if (O->isRegMask())
lib/CodeGen/LiveVariables.cpp 517 if (MO.isRegMask()) {
lib/CodeGen/MIRParser/MIRParser.cpp 616 if (!MO.isRegMask())
lib/CodeGen/MachineCSE.cpp 235 if (MO.isRegMask() && MO.clobbersPhysReg(Reg))
377 if (MO.isRegMask())
lib/CodeGen/MachineCopyPropagation.cpp 171 if (MO.isRegMask())
559 if (MO.isRegMask())
lib/CodeGen/MachineInstr.cpp 233 assert((isImpReg || Op.isRegMask() || MCID->isVariadic() ||
999 if (isPhys && Overlap && MO.isRegMask() && MO.clobbersPhysReg(Reg))
1403 if ((MO.isReg() && MO.isImplicit()) || MO.isRegMask())
1954 if (MO.isRegMask()) {
lib/CodeGen/MachineInstrBundle.cpp 324 if (MO.isRegMask() && MO.clobbersPhysReg(Reg)) {
lib/CodeGen/MachineLICM.cpp 419 if (MO.isRegMask()) {
lib/CodeGen/PeepholeOptimizer.cpp 1674 } else if (MO.isRegMask()) {
lib/CodeGen/RegAllocFast.cpp 1041 if (MO.isRegMask()) {
lib/CodeGen/RegUsageInfoPropagate.cpp 71 if (MO.isRegMask())
lib/CodeGen/RegisterScavenging.cpp 120 if (MO.isRegMask()) {
328 if (MO.isRegMask())
lib/CodeGen/ScheduleDAGInstrs.cpp 1126 } else if (MO.isRegMask()) {
lib/CodeGen/ShrinkWrap.cpp 292 } else if (MO.isRegMask()) {
lib/CodeGen/VirtRegMap.cpp 512 if (MO.isRegMask())
lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp 561 } else if (U.isRegMask()) {
697 } else if (MO.isRegMask()) {
lib/Target/AArch64/AArch64CollectLOH.cpp 466 if (MO.isRegMask()) {
lib/Target/AMDGPU/SIShrinkInstructions.cpp 177 if ((MO.isReg() && MO.isImplicit()) || MO.isRegMask())
lib/Target/ARM/ARMBaseInstrInfo.cpp 550 if ((MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR)) ||
3059 if (MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR)) {
lib/Target/Hexagon/HexagonBlockRanges.cpp 351 if (!Op.isRegMask())
lib/Target/Hexagon/HexagonCopyToCombine.cpp 451 } else if (Op.isRegMask()) {
lib/Target/Hexagon/HexagonFrameLowering.cpp 316 if (MO.isRegMask()) {
lib/Target/Hexagon/HexagonInstrInfo.cpp 1632 } else if (MO.isRegMask()) {
3099 if (MO.isRegMask() && MO.clobbersPhysReg(PredReg))
lib/Target/Hexagon/HexagonVLIWPacketizer.cpp 788 if (MO.isRegMask() && MO.clobbersPhysReg(DepReg))
831 if (CheckDef && MO.isRegMask() && MO.clobbersPhysReg(DepReg))
1269 if (!OpJ.isRegMask())
1276 } else if (OpI.isRegMask()) {
1592 } else if (!Op.isRegMask()) {
lib/Target/Hexagon/RDFDeadCode.cpp 69 if (Op.isRegMask()) {
lib/Target/Hexagon/RDFGraph.cpp 607 if (Op.isRegMask())
974 assert(Op.isReg() || Op.isRegMask());
1320 if (!Op.isRegMask())
lib/Target/Hexagon/RDFRegisters.cpp 80 if (Op.isRegMask())
lib/Target/Lanai/LanaiInstrInfo.cpp 360 if (MO.isRegMask() && MO.clobbersPhysReg(Lanai::SR)) {
lib/Target/PowerPC/PPCCTRLoops.cpp 119 } else if (MO.isRegMask()) {
lib/Target/PowerPC/PPCInstrInfo.cpp 1576 } else if (MO.isRegMask()) {
lib/Target/X86/X86FrameLowering.cpp 2737 if (!Prev->isCall() || !Prev->getOperand(1).isRegMask())
lib/Target/X86/X86VZeroUpper.cpp 155 if (MI.isCall() && MO.isRegMask() && !clobbersAllYmmAndZmmRegs(MO))
171 if (MO.isRegMask())
unittests/CodeGen/MachineOperandTest.cpp 53 ASSERT_TRUE(MO.isRegMask());