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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
lib/CodeGen/GlobalISel/RegBankSelect.cpp 764 if (It->modifiesRegister(Reg, &TRI)) {
789 assert(!It->modifiesRegister(MO.getReg(), &TRI) &&
807 assert(It->modifiesRegister(MO.getReg(), &TRI) &&
lib/CodeGen/ImplicitNullChecks.cpp 525 if (I->modifiesRegister(PointerReg, TRI))
lib/CodeGen/TargetInstrInfo.cpp 1000 return MI.modifiesRegister(TLI.getStackPointerRegisterToSaveRestore(), TRI);
lib/Target/AArch64/AArch64CondBrTuning.cpp 199 if (I->modifiesRegister(AArch64::NZCV, TRI) ||
258 if (I->modifiesRegister(AArch64::NZCV, TRI) ||
lib/Target/AArch64/AArch64ConditionalCompares.cpp 427 if (&I != CmpMI && I.modifiesRegister(AArch64::NZCV, TRI)) {
lib/Target/AArch64/AArch64InstrInfo.cpp 1163 Instr.modifiesRegister(AArch64::NZCV, TRI)) ||
1429 if (Instr.modifiesRegister(AArch64::NZCV, TRI))
1944 if (MI.modifiesRegister(BaseReg, TRI))
5121 if (!MI.modifiesRegister(AArch64::SP, &TRI) &&
5128 if (MI.modifiesRegister(AArch64::SP, &TRI))
5488 MI.modifiesRegister(AArch64::W30, &getRegisterInfo()))
lib/Target/AArch64/AArch64RedundantCopyElimination.cpp 435 if (MI->modifiesRegister(KnownRegs[RI].Reg, TRI)) {
lib/Target/AArch64/AArch64SpeculationHardening.cpp 420 MI.modifiesRegister(MisspeculatingTaintReg, TRI))
lib/Target/AMDGPU/GCNHazardRecognizer.cpp 449 return IsHazardDef(MI) && MI->modifiesRegister(Reg, TRI);
1038 if (!MI->modifiesRegister(AMDGPU::EXEC, TRI))
lib/Target/AMDGPU/GCNRegBankReassign.cpp 414 if (Def->modifiesRegister(Reg1, TRI))
416 if (Def->modifiesRegister(Reg2, TRI))
lib/Target/AMDGPU/SIFoldOperands.cpp 1471 if (CurrentKnownM0Val && MI.modifiesRegister(AMDGPU::M0, TRI))
lib/Target/AMDGPU/SIInsertSkips.cpp 359 if (A->modifiesRegister(ExecReg, TRI))
361 if (A->modifiesRegister(CondReg, TRI)) {
390 if (M->modifiesRegister(SReg, TRI))
lib/Target/AMDGPU/SIInsertWaitcnts.cpp 930 if (MI.modifiesRegister(AMDGPU::EXEC, TRI)) {
lib/Target/AMDGPU/SIInstrInfo.cpp 630 if (I->modifiesRegister(DefOp.getReg(), &RI))
2732 MI.modifiesRegister(AMDGPU::EXEC, &RI) ||
6185 MI.modifiesRegister(AMDGPU::EXEC, &RI);
6477 if (I->modifiesRegister(AMDGPU::EXEC, TRI))
6520 if (I->modifiesRegister(AMDGPU::EXEC, TRI))
lib/Target/AMDGPU/SILowerControlFlow.cpp 458 if (I->modifiesRegister(AMDGPU::EXEC, TRI) &&
lib/Target/AMDGPU/SIOptimizeExecMasking.cpp 342 if (J->modifiesRegister(CopyToExec, TRI)) {
lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp 89 MI.modifiesRegister(AMDGPU::EXEC_LO, TRI);
93 MI.modifiesRegister(AMDGPU::EXEC, TRI);
lib/Target/AMDGPU/SIPeepholeSDWA.cpp 919 if (I->modifiesRegister(AMDGPU::VCC, TRI))
lib/Target/AMDGPU/SIRegisterInfo.cpp 1912 assert(Def->modifiesRegister(Reg, this));
lib/Target/ARM/ARMBaseInstrInfo.cpp 3013 if (Instr.modifiesRegister(ARM::CPSR, TRI) ||
5358 if (I->modifiesRegister(Reg, TRI))
5371 if (CmpMI->modifiesRegister(ARM::CPSR, TRI))
lib/Target/ARM/MVEVPTBlockPass.cpp 146 if (CmpMI->modifiesRegister(ARM::VPR, TRI))
lib/Target/Hexagon/HexagonCopyToCombine.cpp 251 return (UseReg && (MI.modifiesRegister(UseReg, TRI))) ||
252 MI.modifiesRegister(DestReg, TRI) || MI.readsRegister(DestReg, TRI) ||
272 if (I2UseReg && I1.modifiesRegister(I2UseReg, TRI))
536 if (I2->modifiesRegister(I1DestReg, TRI))
lib/Target/Hexagon/HexagonExpandCondsets.cpp 975 if (!I->modifiesRegister(PredR, nullptr))
lib/Target/Hexagon/HexagonHardwareLoops.cpp 1003 if (MI->modifiesRegister(R, TRI))
lib/Target/Hexagon/HexagonInstrInfo.cpp 1634 if (!MI.modifiesRegister(PR, &HRI))
lib/Target/Hexagon/HexagonNewValueJump.cpp 186 if (localBegin->modifiesRegister(Reg, TRI) ||
314 if (localII->modifiesRegister(pReg, TRI) ||
325 if (localII->modifiesRegister(cmpReg1, TRI) ||
326 (secondReg && localII->modifiesRegister(cmpOp2, TRI)))
lib/Target/Hexagon/HexagonVLIWPacketizer.cpp 345 if (MI.modifiesRegister(*CSR, TRI))
765 if (MO.isReg() && TempSU->getInstr()->modifiesRegister(MO.getReg(), HRI))
1380 if (OpR.isReg() && PI->modifiesRegister(OpR.getReg(), HRI)) {
1590 if (!J.readsRegister(R, HRI) && !J.modifiesRegister(R, HRI))
lib/Target/Lanai/LanaiInstrInfo.cpp 323 if (Instr.modifiesRegister(Lanai::SR, TRI) ||
lib/Target/Mips/MipsDelaySlotFiller.cpp 711 CurrI->modifiesRegister(Mips::SP, STI.getRegisterInfo()))
lib/Target/PowerPC/PPCInstrInfo.cpp 1804 if (&*I != &CmpInstr && (Instr.modifiesRegister(PPC::CR0, TRI) ||
2332 if (It->modifiesRegister(Reg, TRI))
2605 if (It->modifiesRegister(Reg, &getRegisterInfo()))
3525 if (It->modifiesRegister(Reg, &getRegisterInfo()) && (&*It) != &DefMI)
3537 if (DefMI.modifiesRegister(Reg, &getRegisterInfo()))
lib/Target/PowerPC/PPCPreEmitPeephole.cpp 120 if (!AfterBBI->modifiesRegister(Reg, TRI))
231 if (It->modifiesRegister(CRBit, TRI)) {
lib/Target/PowerPC/PPCQPXLoadSplat.cpp 85 if (MI->modifiesRegister(SrcReg, TRI)) {
134 if (MI->modifiesRegister(SplatReg, TRI) ||
lib/Target/PowerPC/PPCReduceCRLogicals.cpp 560 if ((--Me)->modifiesRegister(CopySrc, TRI))
lib/Target/PowerPC/PPCRegisterInfo.cpp 754 if (Ins->modifiesRegister(SrcReg, TRI))
lib/Target/PowerPC/PPCVSXFMAMutate.cpp 167 if (J->modifiesRegister(AddendSrcReg, TRI) ||
lib/Target/SystemZ/SystemZElimCompare.cpp 530 if (MBBI->modifiesRegister(SrcReg, TRI) ||
531 (SrcReg2 && MBBI->modifiesRegister(SrcReg2, TRI)))
lib/Target/X86/X86InstrInfo.cpp 645 bool ClobbersEFLAGS = Orig.modifiesRegister(X86::EFLAGS, &TRI);
2702 if (I->modifiesRegister(X86::EFLAGS, TRI)) {
3671 if (Instr.modifiesRegister(X86::EFLAGS, TRI) ||
3706 bool ModifyEFLAGS = Instr.modifiesRegister(X86::EFLAGS, TRI);
3803 Instr->modifiesRegister(X86::EFLAGS, TRI)) {
8080 if (MI.modifiesRegister(X86::RSP, &RI) || MI.readsRegister(X86::RSP, &RI) ||
lib/Target/X86/X86WinAllocaExpander.cpp 181 } else if (MI.modifiesRegister(StackPtr, TRI)) {